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drivers/net: Remove unnecessary returns from void function()s
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / e1000e / ich8lan.c
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 */
56
57 #include "e1000.h"
58
59 #define ICH_FLASH_GFPREG 0x0000
60 #define ICH_FLASH_HSFSTS 0x0004
61 #define ICH_FLASH_HSFCTL 0x0006
62 #define ICH_FLASH_FADDR 0x0008
63 #define ICH_FLASH_FDATA0 0x0010
64 #define ICH_FLASH_PR0 0x0074
65
66 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
67 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
68 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
69 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
70 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
71
72 #define ICH_CYCLE_READ 0
73 #define ICH_CYCLE_WRITE 2
74 #define ICH_CYCLE_ERASE 3
75
76 #define FLASH_GFPREG_BASE_MASK 0x1FFF
77 #define FLASH_SECTOR_ADDR_SHIFT 12
78
79 #define ICH_FLASH_SEG_SIZE_256 256
80 #define ICH_FLASH_SEG_SIZE_4K 4096
81 #define ICH_FLASH_SEG_SIZE_8K 8192
82 #define ICH_FLASH_SEG_SIZE_64K 65536
83
84
85 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
86 /* FW established a valid mode */
87 #define E1000_ICH_FWSM_FW_VALID 0x00008000
88
89 #define E1000_ICH_MNG_IAMT_MODE 0x2
90
91 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
92 (ID_LED_DEF1_OFF2 << 8) | \
93 (ID_LED_DEF1_ON2 << 4) | \
94 (ID_LED_DEF1_DEF2))
95
96 #define E1000_ICH_NVM_SIG_WORD 0x13
97 #define E1000_ICH_NVM_SIG_MASK 0xC000
98 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
99 #define E1000_ICH_NVM_SIG_VALUE 0x80
100
101 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
102
103 #define E1000_FEXTNVM_SW_CONFIG 1
104 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
105
106 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
107
108 #define E1000_ICH_RAR_ENTRIES 7
109
110 #define PHY_PAGE_SHIFT 5
111 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
112 ((reg) & MAX_PHY_REG_ADDRESS))
113 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
114 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
115
116 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
117 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
118 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
119
120 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
121
122 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
123
124 /* SMBus Address Phy Register */
125 #define HV_SMB_ADDR PHY_REG(768, 26)
126 #define HV_SMB_ADDR_PEC_EN 0x0200
127 #define HV_SMB_ADDR_VALID 0x0080
128
129 /* Strapping Option Register - RO */
130 #define E1000_STRAP 0x0000C
131 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
132 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
133
134 /* OEM Bits Phy Register */
135 #define HV_OEM_BITS PHY_REG(768, 25)
136 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
137 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
138 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
139
140 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
141 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
142
143 /* KMRN Mode Control */
144 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
145 #define HV_KMRN_MDIO_SLOW 0x0400
146
147 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
148 /* Offset 04h HSFSTS */
149 union ich8_hws_flash_status {
150 struct ich8_hsfsts {
151 u16 flcdone :1; /* bit 0 Flash Cycle Done */
152 u16 flcerr :1; /* bit 1 Flash Cycle Error */
153 u16 dael :1; /* bit 2 Direct Access error Log */
154 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
155 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
156 u16 reserved1 :2; /* bit 13:6 Reserved */
157 u16 reserved2 :6; /* bit 13:6 Reserved */
158 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
159 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
160 } hsf_status;
161 u16 regval;
162 };
163
164 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
165 /* Offset 06h FLCTL */
166 union ich8_hws_flash_ctrl {
167 struct ich8_hsflctl {
168 u16 flcgo :1; /* 0 Flash Cycle Go */
169 u16 flcycle :2; /* 2:1 Flash Cycle */
170 u16 reserved :5; /* 7:3 Reserved */
171 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
172 u16 flockdn :6; /* 15:10 Reserved */
173 } hsf_ctrl;
174 u16 regval;
175 };
176
177 /* ICH Flash Region Access Permissions */
178 union ich8_hws_flash_regacc {
179 struct ich8_flracc {
180 u32 grra :8; /* 0:7 GbE region Read Access */
181 u32 grwa :8; /* 8:15 GbE region Write Access */
182 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
183 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
184 } hsf_flregacc;
185 u16 regval;
186 };
187
188 /* ICH Flash Protected Region */
189 union ich8_flash_protected_range {
190 struct ich8_pr {
191 u32 base:13; /* 0:12 Protected Range Base */
192 u32 reserved1:2; /* 13:14 Reserved */
193 u32 rpe:1; /* 15 Read Protection Enable */
194 u32 limit:13; /* 16:28 Protected Range Limit */
195 u32 reserved2:2; /* 29:30 Reserved */
196 u32 wpe:1; /* 31 Write Protection Enable */
197 } range;
198 u32 regval;
199 };
200
201 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
202 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
203 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
204 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
205 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
206 u32 offset, u8 byte);
207 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
208 u8 *data);
209 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
210 u16 *data);
211 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
212 u8 size, u16 *data);
213 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
214 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
215 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
216 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
217 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
218 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
219 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
220 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
221 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
222 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
223 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
224 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
225 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
226 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
227 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
228 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
229
230 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
231 {
232 return readw(hw->flash_address + reg);
233 }
234
235 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
236 {
237 return readl(hw->flash_address + reg);
238 }
239
240 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
241 {
242 writew(val, hw->flash_address + reg);
243 }
244
245 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
246 {
247 writel(val, hw->flash_address + reg);
248 }
249
250 #define er16flash(reg) __er16flash(hw, (reg))
251 #define er32flash(reg) __er32flash(hw, (reg))
252 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
253 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
254
255 /**
256 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
257 * @hw: pointer to the HW structure
258 *
259 * Initialize family-specific PHY parameters and function pointers.
260 **/
261 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
262 {
263 struct e1000_phy_info *phy = &hw->phy;
264 u32 ctrl;
265 s32 ret_val = 0;
266
267 phy->addr = 1;
268 phy->reset_delay_us = 100;
269
270 phy->ops.read_reg = e1000_read_phy_reg_hv;
271 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
272 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
273 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
274 phy->ops.write_reg = e1000_write_phy_reg_hv;
275 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
276 phy->ops.power_up = e1000_power_up_phy_copper;
277 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
278 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
279
280 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
281 /*
282 * The MAC-PHY interconnect may still be in SMBus mode
283 * after Sx->S0. Toggle the LANPHYPC Value bit to force
284 * the interconnect to PCIe mode, but only if there is no
285 * firmware present otherwise firmware will have done it.
286 */
287 ctrl = er32(CTRL);
288 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
289 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
290 ew32(CTRL, ctrl);
291 udelay(10);
292 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
293 ew32(CTRL, ctrl);
294 msleep(50);
295 }
296
297 /*
298 * Reset the PHY before any acccess to it. Doing so, ensures that
299 * the PHY is in a known good state before we read/write PHY registers.
300 * The generic reset is sufficient here, because we haven't determined
301 * the PHY type yet.
302 */
303 ret_val = e1000e_phy_hw_reset_generic(hw);
304 if (ret_val)
305 goto out;
306
307 phy->id = e1000_phy_unknown;
308 ret_val = e1000e_get_phy_id(hw);
309 if (ret_val)
310 goto out;
311 if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
312 /*
313 * In case the PHY needs to be in mdio slow mode (eg. 82577),
314 * set slow mode and try to get the PHY id again.
315 */
316 ret_val = e1000_set_mdio_slow_mode_hv(hw);
317 if (ret_val)
318 goto out;
319 ret_val = e1000e_get_phy_id(hw);
320 if (ret_val)
321 goto out;
322 }
323 phy->type = e1000e_get_phy_type_from_id(phy->id);
324
325 switch (phy->type) {
326 case e1000_phy_82577:
327 phy->ops.check_polarity = e1000_check_polarity_82577;
328 phy->ops.force_speed_duplex =
329 e1000_phy_force_speed_duplex_82577;
330 phy->ops.get_cable_length = e1000_get_cable_length_82577;
331 phy->ops.get_info = e1000_get_phy_info_82577;
332 phy->ops.commit = e1000e_phy_sw_reset;
333 break;
334 case e1000_phy_82578:
335 phy->ops.check_polarity = e1000_check_polarity_m88;
336 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
337 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
338 phy->ops.get_info = e1000e_get_phy_info_m88;
339 break;
340 default:
341 ret_val = -E1000_ERR_PHY;
342 break;
343 }
344
345 out:
346 return ret_val;
347 }
348
349 /**
350 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
351 * @hw: pointer to the HW structure
352 *
353 * Initialize family-specific PHY parameters and function pointers.
354 **/
355 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
356 {
357 struct e1000_phy_info *phy = &hw->phy;
358 s32 ret_val;
359 u16 i = 0;
360
361 phy->addr = 1;
362 phy->reset_delay_us = 100;
363
364 phy->ops.power_up = e1000_power_up_phy_copper;
365 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
366
367 /*
368 * We may need to do this twice - once for IGP and if that fails,
369 * we'll set BM func pointers and try again
370 */
371 ret_val = e1000e_determine_phy_address(hw);
372 if (ret_val) {
373 phy->ops.write_reg = e1000e_write_phy_reg_bm;
374 phy->ops.read_reg = e1000e_read_phy_reg_bm;
375 ret_val = e1000e_determine_phy_address(hw);
376 if (ret_val) {
377 e_dbg("Cannot determine PHY addr. Erroring out\n");
378 return ret_val;
379 }
380 }
381
382 phy->id = 0;
383 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
384 (i++ < 100)) {
385 msleep(1);
386 ret_val = e1000e_get_phy_id(hw);
387 if (ret_val)
388 return ret_val;
389 }
390
391 /* Verify phy id */
392 switch (phy->id) {
393 case IGP03E1000_E_PHY_ID:
394 phy->type = e1000_phy_igp_3;
395 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
396 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
397 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
398 phy->ops.get_info = e1000e_get_phy_info_igp;
399 phy->ops.check_polarity = e1000_check_polarity_igp;
400 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
401 break;
402 case IFE_E_PHY_ID:
403 case IFE_PLUS_E_PHY_ID:
404 case IFE_C_E_PHY_ID:
405 phy->type = e1000_phy_ife;
406 phy->autoneg_mask = E1000_ALL_NOT_GIG;
407 phy->ops.get_info = e1000_get_phy_info_ife;
408 phy->ops.check_polarity = e1000_check_polarity_ife;
409 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
410 break;
411 case BME1000_E_PHY_ID:
412 phy->type = e1000_phy_bm;
413 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
414 phy->ops.read_reg = e1000e_read_phy_reg_bm;
415 phy->ops.write_reg = e1000e_write_phy_reg_bm;
416 phy->ops.commit = e1000e_phy_sw_reset;
417 phy->ops.get_info = e1000e_get_phy_info_m88;
418 phy->ops.check_polarity = e1000_check_polarity_m88;
419 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
420 break;
421 default:
422 return -E1000_ERR_PHY;
423 break;
424 }
425
426 return 0;
427 }
428
429 /**
430 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
431 * @hw: pointer to the HW structure
432 *
433 * Initialize family-specific NVM parameters and function
434 * pointers.
435 **/
436 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
437 {
438 struct e1000_nvm_info *nvm = &hw->nvm;
439 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
440 u32 gfpreg, sector_base_addr, sector_end_addr;
441 u16 i;
442
443 /* Can't read flash registers if the register set isn't mapped. */
444 if (!hw->flash_address) {
445 e_dbg("ERROR: Flash registers not mapped\n");
446 return -E1000_ERR_CONFIG;
447 }
448
449 nvm->type = e1000_nvm_flash_sw;
450
451 gfpreg = er32flash(ICH_FLASH_GFPREG);
452
453 /*
454 * sector_X_addr is a "sector"-aligned address (4096 bytes)
455 * Add 1 to sector_end_addr since this sector is included in
456 * the overall size.
457 */
458 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
459 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
460
461 /* flash_base_addr is byte-aligned */
462 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
463
464 /*
465 * find total size of the NVM, then cut in half since the total
466 * size represents two separate NVM banks.
467 */
468 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
469 << FLASH_SECTOR_ADDR_SHIFT;
470 nvm->flash_bank_size /= 2;
471 /* Adjust to word count */
472 nvm->flash_bank_size /= sizeof(u16);
473
474 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
475
476 /* Clear shadow ram */
477 for (i = 0; i < nvm->word_size; i++) {
478 dev_spec->shadow_ram[i].modified = false;
479 dev_spec->shadow_ram[i].value = 0xFFFF;
480 }
481
482 return 0;
483 }
484
485 /**
486 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
487 * @hw: pointer to the HW structure
488 *
489 * Initialize family-specific MAC parameters and function
490 * pointers.
491 **/
492 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
493 {
494 struct e1000_hw *hw = &adapter->hw;
495 struct e1000_mac_info *mac = &hw->mac;
496
497 /* Set media type function pointer */
498 hw->phy.media_type = e1000_media_type_copper;
499
500 /* Set mta register count */
501 mac->mta_reg_count = 32;
502 /* Set rar entry count */
503 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
504 if (mac->type == e1000_ich8lan)
505 mac->rar_entry_count--;
506 /* FWSM register */
507 mac->has_fwsm = true;
508 /* ARC subsystem not supported */
509 mac->arc_subsystem_valid = false;
510 /* Adaptive IFS supported */
511 mac->adaptive_ifs = true;
512
513 /* LED operations */
514 switch (mac->type) {
515 case e1000_ich8lan:
516 case e1000_ich9lan:
517 case e1000_ich10lan:
518 /* ID LED init */
519 mac->ops.id_led_init = e1000e_id_led_init;
520 /* setup LED */
521 mac->ops.setup_led = e1000e_setup_led_generic;
522 /* cleanup LED */
523 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
524 /* turn on/off LED */
525 mac->ops.led_on = e1000_led_on_ich8lan;
526 mac->ops.led_off = e1000_led_off_ich8lan;
527 break;
528 case e1000_pchlan:
529 /* ID LED init */
530 mac->ops.id_led_init = e1000_id_led_init_pchlan;
531 /* setup LED */
532 mac->ops.setup_led = e1000_setup_led_pchlan;
533 /* cleanup LED */
534 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
535 /* turn on/off LED */
536 mac->ops.led_on = e1000_led_on_pchlan;
537 mac->ops.led_off = e1000_led_off_pchlan;
538 break;
539 default:
540 break;
541 }
542
543 /* Enable PCS Lock-loss workaround for ICH8 */
544 if (mac->type == e1000_ich8lan)
545 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
546
547 return 0;
548 }
549
550 /**
551 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
552 * @hw: pointer to the HW structure
553 *
554 * Checks to see of the link status of the hardware has changed. If a
555 * change in link status has been detected, then we read the PHY registers
556 * to get the current speed/duplex if link exists.
557 **/
558 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
559 {
560 struct e1000_mac_info *mac = &hw->mac;
561 s32 ret_val;
562 bool link;
563
564 /*
565 * We only want to go out to the PHY registers to see if Auto-Neg
566 * has completed and/or if our link status has changed. The
567 * get_link_status flag is set upon receiving a Link Status
568 * Change or Rx Sequence Error interrupt.
569 */
570 if (!mac->get_link_status) {
571 ret_val = 0;
572 goto out;
573 }
574
575 /*
576 * First we want to see if the MII Status Register reports
577 * link. If so, then we want to get the current speed/duplex
578 * of the PHY.
579 */
580 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
581 if (ret_val)
582 goto out;
583
584 if (hw->mac.type == e1000_pchlan) {
585 ret_val = e1000_k1_gig_workaround_hv(hw, link);
586 if (ret_val)
587 goto out;
588 }
589
590 if (!link)
591 goto out; /* No link detected */
592
593 mac->get_link_status = false;
594
595 if (hw->phy.type == e1000_phy_82578) {
596 ret_val = e1000_link_stall_workaround_hv(hw);
597 if (ret_val)
598 goto out;
599 }
600
601 /*
602 * Check if there was DownShift, must be checked
603 * immediately after link-up
604 */
605 e1000e_check_downshift(hw);
606
607 /*
608 * If we are forcing speed/duplex, then we simply return since
609 * we have already determined whether we have link or not.
610 */
611 if (!mac->autoneg) {
612 ret_val = -E1000_ERR_CONFIG;
613 goto out;
614 }
615
616 /*
617 * Auto-Neg is enabled. Auto Speed Detection takes care
618 * of MAC speed/duplex configuration. So we only need to
619 * configure Collision Distance in the MAC.
620 */
621 e1000e_config_collision_dist(hw);
622
623 /*
624 * Configure Flow Control now that Auto-Neg has completed.
625 * First, we need to restore the desired flow control
626 * settings because we may have had to re-autoneg with a
627 * different link partner.
628 */
629 ret_val = e1000e_config_fc_after_link_up(hw);
630 if (ret_val)
631 e_dbg("Error configuring flow control\n");
632
633 out:
634 return ret_val;
635 }
636
637 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
638 {
639 struct e1000_hw *hw = &adapter->hw;
640 s32 rc;
641
642 rc = e1000_init_mac_params_ich8lan(adapter);
643 if (rc)
644 return rc;
645
646 rc = e1000_init_nvm_params_ich8lan(hw);
647 if (rc)
648 return rc;
649
650 if (hw->mac.type == e1000_pchlan)
651 rc = e1000_init_phy_params_pchlan(hw);
652 else
653 rc = e1000_init_phy_params_ich8lan(hw);
654 if (rc)
655 return rc;
656
657 if (adapter->hw.phy.type == e1000_phy_ife) {
658 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
659 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
660 }
661
662 if ((adapter->hw.mac.type == e1000_ich8lan) &&
663 (adapter->hw.phy.type == e1000_phy_igp_3))
664 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
665
666 return 0;
667 }
668
669 static DEFINE_MUTEX(nvm_mutex);
670
671 /**
672 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
673 * @hw: pointer to the HW structure
674 *
675 * Acquires the mutex for performing NVM operations.
676 **/
677 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
678 {
679 mutex_lock(&nvm_mutex);
680
681 return 0;
682 }
683
684 /**
685 * e1000_release_nvm_ich8lan - Release NVM mutex
686 * @hw: pointer to the HW structure
687 *
688 * Releases the mutex used while performing NVM operations.
689 **/
690 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
691 {
692 mutex_unlock(&nvm_mutex);
693 }
694
695 static DEFINE_MUTEX(swflag_mutex);
696
697 /**
698 * e1000_acquire_swflag_ich8lan - Acquire software control flag
699 * @hw: pointer to the HW structure
700 *
701 * Acquires the software control flag for performing PHY and select
702 * MAC CSR accesses.
703 **/
704 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
705 {
706 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
707 s32 ret_val = 0;
708
709 mutex_lock(&swflag_mutex);
710
711 while (timeout) {
712 extcnf_ctrl = er32(EXTCNF_CTRL);
713 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
714 break;
715
716 mdelay(1);
717 timeout--;
718 }
719
720 if (!timeout) {
721 e_dbg("SW/FW/HW has locked the resource for too long.\n");
722 ret_val = -E1000_ERR_CONFIG;
723 goto out;
724 }
725
726 timeout = SW_FLAG_TIMEOUT;
727
728 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
729 ew32(EXTCNF_CTRL, extcnf_ctrl);
730
731 while (timeout) {
732 extcnf_ctrl = er32(EXTCNF_CTRL);
733 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
734 break;
735
736 mdelay(1);
737 timeout--;
738 }
739
740 if (!timeout) {
741 e_dbg("Failed to acquire the semaphore.\n");
742 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
743 ew32(EXTCNF_CTRL, extcnf_ctrl);
744 ret_val = -E1000_ERR_CONFIG;
745 goto out;
746 }
747
748 out:
749 if (ret_val)
750 mutex_unlock(&swflag_mutex);
751
752 return ret_val;
753 }
754
755 /**
756 * e1000_release_swflag_ich8lan - Release software control flag
757 * @hw: pointer to the HW structure
758 *
759 * Releases the software control flag for performing PHY and select
760 * MAC CSR accesses.
761 **/
762 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
763 {
764 u32 extcnf_ctrl;
765
766 extcnf_ctrl = er32(EXTCNF_CTRL);
767 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
768 ew32(EXTCNF_CTRL, extcnf_ctrl);
769
770 mutex_unlock(&swflag_mutex);
771 }
772
773 /**
774 * e1000_check_mng_mode_ich8lan - Checks management mode
775 * @hw: pointer to the HW structure
776 *
777 * This checks if the adapter has manageability enabled.
778 * This is a function pointer entry point only called by read/write
779 * routines for the PHY and NVM parts.
780 **/
781 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
782 {
783 u32 fwsm;
784
785 fwsm = er32(FWSM);
786
787 return (fwsm & E1000_FWSM_MODE_MASK) ==
788 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
789 }
790
791 /**
792 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
793 * @hw: pointer to the HW structure
794 *
795 * Checks if firmware is blocking the reset of the PHY.
796 * This is a function pointer entry point only called by
797 * reset routines.
798 **/
799 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
800 {
801 u32 fwsm;
802
803 fwsm = er32(FWSM);
804
805 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
806 }
807
808 /**
809 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
810 * @hw: pointer to the HW structure
811 *
812 * SW should configure the LCD from the NVM extended configuration region
813 * as a workaround for certain parts.
814 **/
815 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
816 {
817 struct e1000_adapter *adapter = hw->adapter;
818 struct e1000_phy_info *phy = &hw->phy;
819 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
820 s32 ret_val = 0;
821 u16 word_addr, reg_data, reg_addr, phy_page = 0;
822
823 if (!(hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) &&
824 !(hw->mac.type == e1000_pchlan))
825 return ret_val;
826
827 ret_val = hw->phy.ops.acquire(hw);
828 if (ret_val)
829 return ret_val;
830
831 /*
832 * Initialize the PHY from the NVM on ICH platforms. This
833 * is needed due to an issue where the NVM configuration is
834 * not properly autoloaded after power transitions.
835 * Therefore, after each PHY reset, we will load the
836 * configuration data out of the NVM manually.
837 */
838 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
839 (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M) ||
840 (hw->mac.type == e1000_pchlan))
841 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
842 else
843 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
844
845 data = er32(FEXTNVM);
846 if (!(data & sw_cfg_mask))
847 goto out;
848
849 /*
850 * Make sure HW does not configure LCD from PHY
851 * extended configuration before SW configuration
852 */
853 data = er32(EXTCNF_CTRL);
854 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
855 goto out;
856
857 cnf_size = er32(EXTCNF_SIZE);
858 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
859 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
860 if (!cnf_size)
861 goto out;
862
863 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
864 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
865
866 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
867 (hw->mac.type == e1000_pchlan)) {
868 /*
869 * HW configures the SMBus address and LEDs when the
870 * OEM and LCD Write Enable bits are set in the NVM.
871 * When both NVM bits are cleared, SW will configure
872 * them instead.
873 */
874 data = er32(STRAP);
875 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
876 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
877 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
878 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
879 reg_data);
880 if (ret_val)
881 goto out;
882
883 data = er32(LEDCTL);
884 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
885 (u16)data);
886 if (ret_val)
887 goto out;
888 }
889
890 /* Configure LCD from extended configuration region. */
891
892 /* cnf_base_addr is in DWORD */
893 word_addr = (u16)(cnf_base_addr << 1);
894
895 for (i = 0; i < cnf_size; i++) {
896 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
897 &reg_data);
898 if (ret_val)
899 goto out;
900
901 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
902 1, &reg_addr);
903 if (ret_val)
904 goto out;
905
906 /* Save off the PHY page for future writes. */
907 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
908 phy_page = reg_data;
909 continue;
910 }
911
912 reg_addr &= PHY_REG_MASK;
913 reg_addr |= phy_page;
914
915 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
916 reg_data);
917 if (ret_val)
918 goto out;
919 }
920
921 out:
922 hw->phy.ops.release(hw);
923 return ret_val;
924 }
925
926 /**
927 * e1000_k1_gig_workaround_hv - K1 Si workaround
928 * @hw: pointer to the HW structure
929 * @link: link up bool flag
930 *
931 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
932 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
933 * If link is down, the function will restore the default K1 setting located
934 * in the NVM.
935 **/
936 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
937 {
938 s32 ret_val = 0;
939 u16 status_reg = 0;
940 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
941
942 if (hw->mac.type != e1000_pchlan)
943 goto out;
944
945 /* Wrap the whole flow with the sw flag */
946 ret_val = hw->phy.ops.acquire(hw);
947 if (ret_val)
948 goto out;
949
950 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
951 if (link) {
952 if (hw->phy.type == e1000_phy_82578) {
953 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
954 &status_reg);
955 if (ret_val)
956 goto release;
957
958 status_reg &= BM_CS_STATUS_LINK_UP |
959 BM_CS_STATUS_RESOLVED |
960 BM_CS_STATUS_SPEED_MASK;
961
962 if (status_reg == (BM_CS_STATUS_LINK_UP |
963 BM_CS_STATUS_RESOLVED |
964 BM_CS_STATUS_SPEED_1000))
965 k1_enable = false;
966 }
967
968 if (hw->phy.type == e1000_phy_82577) {
969 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
970 &status_reg);
971 if (ret_val)
972 goto release;
973
974 status_reg &= HV_M_STATUS_LINK_UP |
975 HV_M_STATUS_AUTONEG_COMPLETE |
976 HV_M_STATUS_SPEED_MASK;
977
978 if (status_reg == (HV_M_STATUS_LINK_UP |
979 HV_M_STATUS_AUTONEG_COMPLETE |
980 HV_M_STATUS_SPEED_1000))
981 k1_enable = false;
982 }
983
984 /* Link stall fix for link up */
985 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
986 0x0100);
987 if (ret_val)
988 goto release;
989
990 } else {
991 /* Link stall fix for link down */
992 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
993 0x4100);
994 if (ret_val)
995 goto release;
996 }
997
998 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
999
1000 release:
1001 hw->phy.ops.release(hw);
1002 out:
1003 return ret_val;
1004 }
1005
1006 /**
1007 * e1000_configure_k1_ich8lan - Configure K1 power state
1008 * @hw: pointer to the HW structure
1009 * @enable: K1 state to configure
1010 *
1011 * Configure the K1 power state based on the provided parameter.
1012 * Assumes semaphore already acquired.
1013 *
1014 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1015 **/
1016 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1017 {
1018 s32 ret_val = 0;
1019 u32 ctrl_reg = 0;
1020 u32 ctrl_ext = 0;
1021 u32 reg = 0;
1022 u16 kmrn_reg = 0;
1023
1024 ret_val = e1000e_read_kmrn_reg_locked(hw,
1025 E1000_KMRNCTRLSTA_K1_CONFIG,
1026 &kmrn_reg);
1027 if (ret_val)
1028 goto out;
1029
1030 if (k1_enable)
1031 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1032 else
1033 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1034
1035 ret_val = e1000e_write_kmrn_reg_locked(hw,
1036 E1000_KMRNCTRLSTA_K1_CONFIG,
1037 kmrn_reg);
1038 if (ret_val)
1039 goto out;
1040
1041 udelay(20);
1042 ctrl_ext = er32(CTRL_EXT);
1043 ctrl_reg = er32(CTRL);
1044
1045 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1046 reg |= E1000_CTRL_FRCSPD;
1047 ew32(CTRL, reg);
1048
1049 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1050 udelay(20);
1051 ew32(CTRL, ctrl_reg);
1052 ew32(CTRL_EXT, ctrl_ext);
1053 udelay(20);
1054
1055 out:
1056 return ret_val;
1057 }
1058
1059 /**
1060 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1061 * @hw: pointer to the HW structure
1062 * @d0_state: boolean if entering d0 or d3 device state
1063 *
1064 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1065 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1066 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1067 **/
1068 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1069 {
1070 s32 ret_val = 0;
1071 u32 mac_reg;
1072 u16 oem_reg;
1073
1074 if (hw->mac.type != e1000_pchlan)
1075 return ret_val;
1076
1077 ret_val = hw->phy.ops.acquire(hw);
1078 if (ret_val)
1079 return ret_val;
1080
1081 mac_reg = er32(EXTCNF_CTRL);
1082 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1083 goto out;
1084
1085 mac_reg = er32(FEXTNVM);
1086 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1087 goto out;
1088
1089 mac_reg = er32(PHY_CTRL);
1090
1091 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1092 if (ret_val)
1093 goto out;
1094
1095 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1096
1097 if (d0_state) {
1098 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1099 oem_reg |= HV_OEM_BITS_GBE_DIS;
1100
1101 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1102 oem_reg |= HV_OEM_BITS_LPLU;
1103 } else {
1104 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1105 oem_reg |= HV_OEM_BITS_GBE_DIS;
1106
1107 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1108 oem_reg |= HV_OEM_BITS_LPLU;
1109 }
1110 /* Restart auto-neg to activate the bits */
1111 if (!e1000_check_reset_block(hw))
1112 oem_reg |= HV_OEM_BITS_RESTART_AN;
1113 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1114
1115 out:
1116 hw->phy.ops.release(hw);
1117
1118 return ret_val;
1119 }
1120
1121
1122 /**
1123 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1124 * @hw: pointer to the HW structure
1125 **/
1126 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1127 {
1128 s32 ret_val;
1129 u16 data;
1130
1131 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1132 if (ret_val)
1133 return ret_val;
1134
1135 data |= HV_KMRN_MDIO_SLOW;
1136
1137 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1138
1139 return ret_val;
1140 }
1141
1142 /**
1143 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1144 * done after every PHY reset.
1145 **/
1146 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1147 {
1148 s32 ret_val = 0;
1149 u16 phy_data;
1150
1151 if (hw->mac.type != e1000_pchlan)
1152 return ret_val;
1153
1154 /* Set MDIO slow mode before any other MDIO access */
1155 if (hw->phy.type == e1000_phy_82577) {
1156 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1157 if (ret_val)
1158 goto out;
1159 }
1160
1161 if (((hw->phy.type == e1000_phy_82577) &&
1162 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1163 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1164 /* Disable generation of early preamble */
1165 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1166 if (ret_val)
1167 return ret_val;
1168
1169 /* Preamble tuning for SSC */
1170 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1171 if (ret_val)
1172 return ret_val;
1173 }
1174
1175 if (hw->phy.type == e1000_phy_82578) {
1176 /*
1177 * Return registers to default by doing a soft reset then
1178 * writing 0x3140 to the control register.
1179 */
1180 if (hw->phy.revision < 2) {
1181 e1000e_phy_sw_reset(hw);
1182 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1183 }
1184 }
1185
1186 /* Select page 0 */
1187 ret_val = hw->phy.ops.acquire(hw);
1188 if (ret_val)
1189 return ret_val;
1190
1191 hw->phy.addr = 1;
1192 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1193 hw->phy.ops.release(hw);
1194 if (ret_val)
1195 goto out;
1196
1197 /*
1198 * Configure the K1 Si workaround during phy reset assuming there is
1199 * link so that it disables K1 if link is in 1Gbps.
1200 */
1201 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1202 if (ret_val)
1203 goto out;
1204
1205 /* Workaround for link disconnects on a busy hub in half duplex */
1206 ret_val = hw->phy.ops.acquire(hw);
1207 if (ret_val)
1208 goto out;
1209 ret_val = hw->phy.ops.read_reg_locked(hw,
1210 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1211 &phy_data);
1212 if (ret_val)
1213 goto release;
1214 ret_val = hw->phy.ops.write_reg_locked(hw,
1215 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1216 phy_data & 0x00FF);
1217 release:
1218 hw->phy.ops.release(hw);
1219 out:
1220 return ret_val;
1221 }
1222
1223 /**
1224 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1225 * @hw: pointer to the HW structure
1226 *
1227 * Check the appropriate indication the MAC has finished configuring the
1228 * PHY after a software reset.
1229 **/
1230 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1231 {
1232 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1233
1234 /* Wait for basic configuration completes before proceeding */
1235 do {
1236 data = er32(STATUS);
1237 data &= E1000_STATUS_LAN_INIT_DONE;
1238 udelay(100);
1239 } while ((!data) && --loop);
1240
1241 /*
1242 * If basic configuration is incomplete before the above loop
1243 * count reaches 0, loading the configuration from NVM will
1244 * leave the PHY in a bad state possibly resulting in no link.
1245 */
1246 if (loop == 0)
1247 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1248
1249 /* Clear the Init Done bit for the next init event */
1250 data = er32(STATUS);
1251 data &= ~E1000_STATUS_LAN_INIT_DONE;
1252 ew32(STATUS, data);
1253 }
1254
1255 /**
1256 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1257 * @hw: pointer to the HW structure
1258 **/
1259 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1260 {
1261 s32 ret_val = 0;
1262 u16 reg;
1263
1264 if (e1000_check_reset_block(hw))
1265 goto out;
1266
1267 /* Perform any necessary post-reset workarounds */
1268 switch (hw->mac.type) {
1269 case e1000_pchlan:
1270 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1271 if (ret_val)
1272 goto out;
1273 break;
1274 default:
1275 break;
1276 }
1277
1278 /* Dummy read to clear the phy wakeup bit after lcd reset */
1279 if (hw->mac.type == e1000_pchlan)
1280 e1e_rphy(hw, BM_WUC, &reg);
1281
1282 /* Configure the LCD with the extended configuration region in NVM */
1283 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1284 if (ret_val)
1285 goto out;
1286
1287 /* Configure the LCD with the OEM bits in NVM */
1288 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1289
1290 out:
1291 return ret_val;
1292 }
1293
1294 /**
1295 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1296 * @hw: pointer to the HW structure
1297 *
1298 * Resets the PHY
1299 * This is a function pointer entry point called by drivers
1300 * or other shared routines.
1301 **/
1302 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1303 {
1304 s32 ret_val = 0;
1305
1306 ret_val = e1000e_phy_hw_reset_generic(hw);
1307 if (ret_val)
1308 goto out;
1309
1310 ret_val = e1000_post_phy_reset_ich8lan(hw);
1311
1312 out:
1313 return ret_val;
1314 }
1315
1316 /**
1317 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1318 * @hw: pointer to the HW structure
1319 * @active: true to enable LPLU, false to disable
1320 *
1321 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1322 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1323 * the phy speed. This function will manually set the LPLU bit and restart
1324 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1325 * since it configures the same bit.
1326 **/
1327 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1328 {
1329 s32 ret_val = 0;
1330 u16 oem_reg;
1331
1332 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1333 if (ret_val)
1334 goto out;
1335
1336 if (active)
1337 oem_reg |= HV_OEM_BITS_LPLU;
1338 else
1339 oem_reg &= ~HV_OEM_BITS_LPLU;
1340
1341 oem_reg |= HV_OEM_BITS_RESTART_AN;
1342 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1343
1344 out:
1345 return ret_val;
1346 }
1347
1348 /**
1349 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1350 * @hw: pointer to the HW structure
1351 * @active: true to enable LPLU, false to disable
1352 *
1353 * Sets the LPLU D0 state according to the active flag. When
1354 * activating LPLU this function also disables smart speed
1355 * and vice versa. LPLU will not be activated unless the
1356 * device autonegotiation advertisement meets standards of
1357 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1358 * This is a function pointer entry point only called by
1359 * PHY setup routines.
1360 **/
1361 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1362 {
1363 struct e1000_phy_info *phy = &hw->phy;
1364 u32 phy_ctrl;
1365 s32 ret_val = 0;
1366 u16 data;
1367
1368 if (phy->type == e1000_phy_ife)
1369 return ret_val;
1370
1371 phy_ctrl = er32(PHY_CTRL);
1372
1373 if (active) {
1374 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1375 ew32(PHY_CTRL, phy_ctrl);
1376
1377 if (phy->type != e1000_phy_igp_3)
1378 return 0;
1379
1380 /*
1381 * Call gig speed drop workaround on LPLU before accessing
1382 * any PHY registers
1383 */
1384 if (hw->mac.type == e1000_ich8lan)
1385 e1000e_gig_downshift_workaround_ich8lan(hw);
1386
1387 /* When LPLU is enabled, we should disable SmartSpeed */
1388 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1389 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1390 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1391 if (ret_val)
1392 return ret_val;
1393 } else {
1394 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1395 ew32(PHY_CTRL, phy_ctrl);
1396
1397 if (phy->type != e1000_phy_igp_3)
1398 return 0;
1399
1400 /*
1401 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1402 * during Dx states where the power conservation is most
1403 * important. During driver activity we should enable
1404 * SmartSpeed, so performance is maintained.
1405 */
1406 if (phy->smart_speed == e1000_smart_speed_on) {
1407 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1408 &data);
1409 if (ret_val)
1410 return ret_val;
1411
1412 data |= IGP01E1000_PSCFR_SMART_SPEED;
1413 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1414 data);
1415 if (ret_val)
1416 return ret_val;
1417 } else if (phy->smart_speed == e1000_smart_speed_off) {
1418 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1419 &data);
1420 if (ret_val)
1421 return ret_val;
1422
1423 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1424 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1425 data);
1426 if (ret_val)
1427 return ret_val;
1428 }
1429 }
1430
1431 return 0;
1432 }
1433
1434 /**
1435 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1436 * @hw: pointer to the HW structure
1437 * @active: true to enable LPLU, false to disable
1438 *
1439 * Sets the LPLU D3 state according to the active flag. When
1440 * activating LPLU this function also disables smart speed
1441 * and vice versa. LPLU will not be activated unless the
1442 * device autonegotiation advertisement meets standards of
1443 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1444 * This is a function pointer entry point only called by
1445 * PHY setup routines.
1446 **/
1447 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1448 {
1449 struct e1000_phy_info *phy = &hw->phy;
1450 u32 phy_ctrl;
1451 s32 ret_val;
1452 u16 data;
1453
1454 phy_ctrl = er32(PHY_CTRL);
1455
1456 if (!active) {
1457 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1458 ew32(PHY_CTRL, phy_ctrl);
1459
1460 if (phy->type != e1000_phy_igp_3)
1461 return 0;
1462
1463 /*
1464 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1465 * during Dx states where the power conservation is most
1466 * important. During driver activity we should enable
1467 * SmartSpeed, so performance is maintained.
1468 */
1469 if (phy->smart_speed == e1000_smart_speed_on) {
1470 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1471 &data);
1472 if (ret_val)
1473 return ret_val;
1474
1475 data |= IGP01E1000_PSCFR_SMART_SPEED;
1476 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1477 data);
1478 if (ret_val)
1479 return ret_val;
1480 } else if (phy->smart_speed == e1000_smart_speed_off) {
1481 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1482 &data);
1483 if (ret_val)
1484 return ret_val;
1485
1486 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1487 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1488 data);
1489 if (ret_val)
1490 return ret_val;
1491 }
1492 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1493 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1494 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1495 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1496 ew32(PHY_CTRL, phy_ctrl);
1497
1498 if (phy->type != e1000_phy_igp_3)
1499 return 0;
1500
1501 /*
1502 * Call gig speed drop workaround on LPLU before accessing
1503 * any PHY registers
1504 */
1505 if (hw->mac.type == e1000_ich8lan)
1506 e1000e_gig_downshift_workaround_ich8lan(hw);
1507
1508 /* When LPLU is enabled, we should disable SmartSpeed */
1509 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1510 if (ret_val)
1511 return ret_val;
1512
1513 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1514 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1515 }
1516
1517 return 0;
1518 }
1519
1520 /**
1521 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1522 * @hw: pointer to the HW structure
1523 * @bank: pointer to the variable that returns the active bank
1524 *
1525 * Reads signature byte from the NVM using the flash access registers.
1526 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1527 **/
1528 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1529 {
1530 u32 eecd;
1531 struct e1000_nvm_info *nvm = &hw->nvm;
1532 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1533 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1534 u8 sig_byte = 0;
1535 s32 ret_val = 0;
1536
1537 switch (hw->mac.type) {
1538 case e1000_ich8lan:
1539 case e1000_ich9lan:
1540 eecd = er32(EECD);
1541 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1542 E1000_EECD_SEC1VAL_VALID_MASK) {
1543 if (eecd & E1000_EECD_SEC1VAL)
1544 *bank = 1;
1545 else
1546 *bank = 0;
1547
1548 return 0;
1549 }
1550 e_dbg("Unable to determine valid NVM bank via EEC - "
1551 "reading flash signature\n");
1552 /* fall-thru */
1553 default:
1554 /* set bank to 0 in case flash read fails */
1555 *bank = 0;
1556
1557 /* Check bank 0 */
1558 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1559 &sig_byte);
1560 if (ret_val)
1561 return ret_val;
1562 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1563 E1000_ICH_NVM_SIG_VALUE) {
1564 *bank = 0;
1565 return 0;
1566 }
1567
1568 /* Check bank 1 */
1569 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1570 bank1_offset,
1571 &sig_byte);
1572 if (ret_val)
1573 return ret_val;
1574 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1575 E1000_ICH_NVM_SIG_VALUE) {
1576 *bank = 1;
1577 return 0;
1578 }
1579
1580 e_dbg("ERROR: No valid NVM bank present\n");
1581 return -E1000_ERR_NVM;
1582 }
1583
1584 return 0;
1585 }
1586
1587 /**
1588 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1589 * @hw: pointer to the HW structure
1590 * @offset: The offset (in bytes) of the word(s) to read.
1591 * @words: Size of data to read in words
1592 * @data: Pointer to the word(s) to read at offset.
1593 *
1594 * Reads a word(s) from the NVM using the flash access registers.
1595 **/
1596 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1597 u16 *data)
1598 {
1599 struct e1000_nvm_info *nvm = &hw->nvm;
1600 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1601 u32 act_offset;
1602 s32 ret_val = 0;
1603 u32 bank = 0;
1604 u16 i, word;
1605
1606 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1607 (words == 0)) {
1608 e_dbg("nvm parameter(s) out of bounds\n");
1609 ret_val = -E1000_ERR_NVM;
1610 goto out;
1611 }
1612
1613 nvm->ops.acquire(hw);
1614
1615 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1616 if (ret_val) {
1617 e_dbg("Could not detect valid bank, assuming bank 0\n");
1618 bank = 0;
1619 }
1620
1621 act_offset = (bank) ? nvm->flash_bank_size : 0;
1622 act_offset += offset;
1623
1624 ret_val = 0;
1625 for (i = 0; i < words; i++) {
1626 if ((dev_spec->shadow_ram) &&
1627 (dev_spec->shadow_ram[offset+i].modified)) {
1628 data[i] = dev_spec->shadow_ram[offset+i].value;
1629 } else {
1630 ret_val = e1000_read_flash_word_ich8lan(hw,
1631 act_offset + i,
1632 &word);
1633 if (ret_val)
1634 break;
1635 data[i] = word;
1636 }
1637 }
1638
1639 nvm->ops.release(hw);
1640
1641 out:
1642 if (ret_val)
1643 e_dbg("NVM read error: %d\n", ret_val);
1644
1645 return ret_val;
1646 }
1647
1648 /**
1649 * e1000_flash_cycle_init_ich8lan - Initialize flash
1650 * @hw: pointer to the HW structure
1651 *
1652 * This function does initial flash setup so that a new read/write/erase cycle
1653 * can be started.
1654 **/
1655 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1656 {
1657 union ich8_hws_flash_status hsfsts;
1658 s32 ret_val = -E1000_ERR_NVM;
1659 s32 i = 0;
1660
1661 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1662
1663 /* Check if the flash descriptor is valid */
1664 if (hsfsts.hsf_status.fldesvalid == 0) {
1665 e_dbg("Flash descriptor invalid. "
1666 "SW Sequencing must be used.\n");
1667 return -E1000_ERR_NVM;
1668 }
1669
1670 /* Clear FCERR and DAEL in hw status by writing 1 */
1671 hsfsts.hsf_status.flcerr = 1;
1672 hsfsts.hsf_status.dael = 1;
1673
1674 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1675
1676 /*
1677 * Either we should have a hardware SPI cycle in progress
1678 * bit to check against, in order to start a new cycle or
1679 * FDONE bit should be changed in the hardware so that it
1680 * is 1 after hardware reset, which can then be used as an
1681 * indication whether a cycle is in progress or has been
1682 * completed.
1683 */
1684
1685 if (hsfsts.hsf_status.flcinprog == 0) {
1686 /*
1687 * There is no cycle running at present,
1688 * so we can start a cycle.
1689 * Begin by setting Flash Cycle Done.
1690 */
1691 hsfsts.hsf_status.flcdone = 1;
1692 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1693 ret_val = 0;
1694 } else {
1695 /*
1696 * Otherwise poll for sometime so the current
1697 * cycle has a chance to end before giving up.
1698 */
1699 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1700 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1701 if (hsfsts.hsf_status.flcinprog == 0) {
1702 ret_val = 0;
1703 break;
1704 }
1705 udelay(1);
1706 }
1707 if (ret_val == 0) {
1708 /*
1709 * Successful in waiting for previous cycle to timeout,
1710 * now set the Flash Cycle Done.
1711 */
1712 hsfsts.hsf_status.flcdone = 1;
1713 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1714 } else {
1715 e_dbg("Flash controller busy, cannot get access\n");
1716 }
1717 }
1718
1719 return ret_val;
1720 }
1721
1722 /**
1723 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1724 * @hw: pointer to the HW structure
1725 * @timeout: maximum time to wait for completion
1726 *
1727 * This function starts a flash cycle and waits for its completion.
1728 **/
1729 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1730 {
1731 union ich8_hws_flash_ctrl hsflctl;
1732 union ich8_hws_flash_status hsfsts;
1733 s32 ret_val = -E1000_ERR_NVM;
1734 u32 i = 0;
1735
1736 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1737 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1738 hsflctl.hsf_ctrl.flcgo = 1;
1739 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1740
1741 /* wait till FDONE bit is set to 1 */
1742 do {
1743 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1744 if (hsfsts.hsf_status.flcdone == 1)
1745 break;
1746 udelay(1);
1747 } while (i++ < timeout);
1748
1749 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1750 return 0;
1751
1752 return ret_val;
1753 }
1754
1755 /**
1756 * e1000_read_flash_word_ich8lan - Read word from flash
1757 * @hw: pointer to the HW structure
1758 * @offset: offset to data location
1759 * @data: pointer to the location for storing the data
1760 *
1761 * Reads the flash word at offset into data. Offset is converted
1762 * to bytes before read.
1763 **/
1764 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1765 u16 *data)
1766 {
1767 /* Must convert offset into bytes. */
1768 offset <<= 1;
1769
1770 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1771 }
1772
1773 /**
1774 * e1000_read_flash_byte_ich8lan - Read byte from flash
1775 * @hw: pointer to the HW structure
1776 * @offset: The offset of the byte to read.
1777 * @data: Pointer to a byte to store the value read.
1778 *
1779 * Reads a single byte from the NVM using the flash access registers.
1780 **/
1781 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1782 u8 *data)
1783 {
1784 s32 ret_val;
1785 u16 word = 0;
1786
1787 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1788 if (ret_val)
1789 return ret_val;
1790
1791 *data = (u8)word;
1792
1793 return 0;
1794 }
1795
1796 /**
1797 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1798 * @hw: pointer to the HW structure
1799 * @offset: The offset (in bytes) of the byte or word to read.
1800 * @size: Size of data to read, 1=byte 2=word
1801 * @data: Pointer to the word to store the value read.
1802 *
1803 * Reads a byte or word from the NVM using the flash access registers.
1804 **/
1805 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1806 u8 size, u16 *data)
1807 {
1808 union ich8_hws_flash_status hsfsts;
1809 union ich8_hws_flash_ctrl hsflctl;
1810 u32 flash_linear_addr;
1811 u32 flash_data = 0;
1812 s32 ret_val = -E1000_ERR_NVM;
1813 u8 count = 0;
1814
1815 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1816 return -E1000_ERR_NVM;
1817
1818 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1819 hw->nvm.flash_base_addr;
1820
1821 do {
1822 udelay(1);
1823 /* Steps */
1824 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1825 if (ret_val != 0)
1826 break;
1827
1828 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1829 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1830 hsflctl.hsf_ctrl.fldbcount = size - 1;
1831 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1832 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1833
1834 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1835
1836 ret_val = e1000_flash_cycle_ich8lan(hw,
1837 ICH_FLASH_READ_COMMAND_TIMEOUT);
1838
1839 /*
1840 * Check if FCERR is set to 1, if set to 1, clear it
1841 * and try the whole sequence a few more times, else
1842 * read in (shift in) the Flash Data0, the order is
1843 * least significant byte first msb to lsb
1844 */
1845 if (ret_val == 0) {
1846 flash_data = er32flash(ICH_FLASH_FDATA0);
1847 if (size == 1) {
1848 *data = (u8)(flash_data & 0x000000FF);
1849 } else if (size == 2) {
1850 *data = (u16)(flash_data & 0x0000FFFF);
1851 }
1852 break;
1853 } else {
1854 /*
1855 * If we've gotten here, then things are probably
1856 * completely hosed, but if the error condition is
1857 * detected, it won't hurt to give it another try...
1858 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1859 */
1860 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1861 if (hsfsts.hsf_status.flcerr == 1) {
1862 /* Repeat for some time before giving up. */
1863 continue;
1864 } else if (hsfsts.hsf_status.flcdone == 0) {
1865 e_dbg("Timeout error - flash cycle "
1866 "did not complete.\n");
1867 break;
1868 }
1869 }
1870 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1871
1872 return ret_val;
1873 }
1874
1875 /**
1876 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1877 * @hw: pointer to the HW structure
1878 * @offset: The offset (in bytes) of the word(s) to write.
1879 * @words: Size of data to write in words
1880 * @data: Pointer to the word(s) to write at offset.
1881 *
1882 * Writes a byte or word to the NVM using the flash access registers.
1883 **/
1884 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1885 u16 *data)
1886 {
1887 struct e1000_nvm_info *nvm = &hw->nvm;
1888 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1889 u16 i;
1890
1891 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1892 (words == 0)) {
1893 e_dbg("nvm parameter(s) out of bounds\n");
1894 return -E1000_ERR_NVM;
1895 }
1896
1897 nvm->ops.acquire(hw);
1898
1899 for (i = 0; i < words; i++) {
1900 dev_spec->shadow_ram[offset+i].modified = true;
1901 dev_spec->shadow_ram[offset+i].value = data[i];
1902 }
1903
1904 nvm->ops.release(hw);
1905
1906 return 0;
1907 }
1908
1909 /**
1910 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1911 * @hw: pointer to the HW structure
1912 *
1913 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1914 * which writes the checksum to the shadow ram. The changes in the shadow
1915 * ram are then committed to the EEPROM by processing each bank at a time
1916 * checking for the modified bit and writing only the pending changes.
1917 * After a successful commit, the shadow ram is cleared and is ready for
1918 * future writes.
1919 **/
1920 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1921 {
1922 struct e1000_nvm_info *nvm = &hw->nvm;
1923 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1924 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1925 s32 ret_val;
1926 u16 data;
1927
1928 ret_val = e1000e_update_nvm_checksum_generic(hw);
1929 if (ret_val)
1930 goto out;
1931
1932 if (nvm->type != e1000_nvm_flash_sw)
1933 goto out;
1934
1935 nvm->ops.acquire(hw);
1936
1937 /*
1938 * We're writing to the opposite bank so if we're on bank 1,
1939 * write to bank 0 etc. We also need to erase the segment that
1940 * is going to be written
1941 */
1942 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1943 if (ret_val) {
1944 e_dbg("Could not detect valid bank, assuming bank 0\n");
1945 bank = 0;
1946 }
1947
1948 if (bank == 0) {
1949 new_bank_offset = nvm->flash_bank_size;
1950 old_bank_offset = 0;
1951 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1952 if (ret_val)
1953 goto release;
1954 } else {
1955 old_bank_offset = nvm->flash_bank_size;
1956 new_bank_offset = 0;
1957 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1958 if (ret_val)
1959 goto release;
1960 }
1961
1962 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1963 /*
1964 * Determine whether to write the value stored
1965 * in the other NVM bank or a modified value stored
1966 * in the shadow RAM
1967 */
1968 if (dev_spec->shadow_ram[i].modified) {
1969 data = dev_spec->shadow_ram[i].value;
1970 } else {
1971 ret_val = e1000_read_flash_word_ich8lan(hw, i +
1972 old_bank_offset,
1973 &data);
1974 if (ret_val)
1975 break;
1976 }
1977
1978 /*
1979 * If the word is 0x13, then make sure the signature bits
1980 * (15:14) are 11b until the commit has completed.
1981 * This will allow us to write 10b which indicates the
1982 * signature is valid. We want to do this after the write
1983 * has completed so that we don't mark the segment valid
1984 * while the write is still in progress
1985 */
1986 if (i == E1000_ICH_NVM_SIG_WORD)
1987 data |= E1000_ICH_NVM_SIG_MASK;
1988
1989 /* Convert offset to bytes. */
1990 act_offset = (i + new_bank_offset) << 1;
1991
1992 udelay(100);
1993 /* Write the bytes to the new bank. */
1994 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1995 act_offset,
1996 (u8)data);
1997 if (ret_val)
1998 break;
1999
2000 udelay(100);
2001 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2002 act_offset + 1,
2003 (u8)(data >> 8));
2004 if (ret_val)
2005 break;
2006 }
2007
2008 /*
2009 * Don't bother writing the segment valid bits if sector
2010 * programming failed.
2011 */
2012 if (ret_val) {
2013 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2014 e_dbg("Flash commit failed.\n");
2015 goto release;
2016 }
2017
2018 /*
2019 * Finally validate the new segment by setting bit 15:14
2020 * to 10b in word 0x13 , this can be done without an
2021 * erase as well since these bits are 11 to start with
2022 * and we need to change bit 14 to 0b
2023 */
2024 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2025 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2026 if (ret_val)
2027 goto release;
2028
2029 data &= 0xBFFF;
2030 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2031 act_offset * 2 + 1,
2032 (u8)(data >> 8));
2033 if (ret_val)
2034 goto release;
2035
2036 /*
2037 * And invalidate the previously valid segment by setting
2038 * its signature word (0x13) high_byte to 0b. This can be
2039 * done without an erase because flash erase sets all bits
2040 * to 1's. We can write 1's to 0's without an erase
2041 */
2042 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2043 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2044 if (ret_val)
2045 goto release;
2046
2047 /* Great! Everything worked, we can now clear the cached entries. */
2048 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2049 dev_spec->shadow_ram[i].modified = false;
2050 dev_spec->shadow_ram[i].value = 0xFFFF;
2051 }
2052
2053 release:
2054 nvm->ops.release(hw);
2055
2056 /*
2057 * Reload the EEPROM, or else modifications will not appear
2058 * until after the next adapter reset.
2059 */
2060 if (!ret_val) {
2061 e1000e_reload_nvm(hw);
2062 msleep(10);
2063 }
2064
2065 out:
2066 if (ret_val)
2067 e_dbg("NVM update error: %d\n", ret_val);
2068
2069 return ret_val;
2070 }
2071
2072 /**
2073 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2074 * @hw: pointer to the HW structure
2075 *
2076 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2077 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2078 * calculated, in which case we need to calculate the checksum and set bit 6.
2079 **/
2080 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2081 {
2082 s32 ret_val;
2083 u16 data;
2084
2085 /*
2086 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2087 * needs to be fixed. This bit is an indication that the NVM
2088 * was prepared by OEM software and did not calculate the
2089 * checksum...a likely scenario.
2090 */
2091 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2092 if (ret_val)
2093 return ret_val;
2094
2095 if ((data & 0x40) == 0) {
2096 data |= 0x40;
2097 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2098 if (ret_val)
2099 return ret_val;
2100 ret_val = e1000e_update_nvm_checksum(hw);
2101 if (ret_val)
2102 return ret_val;
2103 }
2104
2105 return e1000e_validate_nvm_checksum_generic(hw);
2106 }
2107
2108 /**
2109 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2110 * @hw: pointer to the HW structure
2111 *
2112 * To prevent malicious write/erase of the NVM, set it to be read-only
2113 * so that the hardware ignores all write/erase cycles of the NVM via
2114 * the flash control registers. The shadow-ram copy of the NVM will
2115 * still be updated, however any updates to this copy will not stick
2116 * across driver reloads.
2117 **/
2118 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2119 {
2120 struct e1000_nvm_info *nvm = &hw->nvm;
2121 union ich8_flash_protected_range pr0;
2122 union ich8_hws_flash_status hsfsts;
2123 u32 gfpreg;
2124
2125 nvm->ops.acquire(hw);
2126
2127 gfpreg = er32flash(ICH_FLASH_GFPREG);
2128
2129 /* Write-protect GbE Sector of NVM */
2130 pr0.regval = er32flash(ICH_FLASH_PR0);
2131 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2132 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2133 pr0.range.wpe = true;
2134 ew32flash(ICH_FLASH_PR0, pr0.regval);
2135
2136 /*
2137 * Lock down a subset of GbE Flash Control Registers, e.g.
2138 * PR0 to prevent the write-protection from being lifted.
2139 * Once FLOCKDN is set, the registers protected by it cannot
2140 * be written until FLOCKDN is cleared by a hardware reset.
2141 */
2142 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2143 hsfsts.hsf_status.flockdn = true;
2144 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2145
2146 nvm->ops.release(hw);
2147 }
2148
2149 /**
2150 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2151 * @hw: pointer to the HW structure
2152 * @offset: The offset (in bytes) of the byte/word to read.
2153 * @size: Size of data to read, 1=byte 2=word
2154 * @data: The byte(s) to write to the NVM.
2155 *
2156 * Writes one/two bytes to the NVM using the flash access registers.
2157 **/
2158 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2159 u8 size, u16 data)
2160 {
2161 union ich8_hws_flash_status hsfsts;
2162 union ich8_hws_flash_ctrl hsflctl;
2163 u32 flash_linear_addr;
2164 u32 flash_data = 0;
2165 s32 ret_val;
2166 u8 count = 0;
2167
2168 if (size < 1 || size > 2 || data > size * 0xff ||
2169 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2170 return -E1000_ERR_NVM;
2171
2172 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2173 hw->nvm.flash_base_addr;
2174
2175 do {
2176 udelay(1);
2177 /* Steps */
2178 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2179 if (ret_val)
2180 break;
2181
2182 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2183 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2184 hsflctl.hsf_ctrl.fldbcount = size -1;
2185 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2186 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2187
2188 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2189
2190 if (size == 1)
2191 flash_data = (u32)data & 0x00FF;
2192 else
2193 flash_data = (u32)data;
2194
2195 ew32flash(ICH_FLASH_FDATA0, flash_data);
2196
2197 /*
2198 * check if FCERR is set to 1 , if set to 1, clear it
2199 * and try the whole sequence a few more times else done
2200 */
2201 ret_val = e1000_flash_cycle_ich8lan(hw,
2202 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2203 if (!ret_val)
2204 break;
2205
2206 /*
2207 * If we're here, then things are most likely
2208 * completely hosed, but if the error condition
2209 * is detected, it won't hurt to give it another
2210 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2211 */
2212 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2213 if (hsfsts.hsf_status.flcerr == 1)
2214 /* Repeat for some time before giving up. */
2215 continue;
2216 if (hsfsts.hsf_status.flcdone == 0) {
2217 e_dbg("Timeout error - flash cycle "
2218 "did not complete.");
2219 break;
2220 }
2221 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2222
2223 return ret_val;
2224 }
2225
2226 /**
2227 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2228 * @hw: pointer to the HW structure
2229 * @offset: The index of the byte to read.
2230 * @data: The byte to write to the NVM.
2231 *
2232 * Writes a single byte to the NVM using the flash access registers.
2233 **/
2234 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2235 u8 data)
2236 {
2237 u16 word = (u16)data;
2238
2239 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2240 }
2241
2242 /**
2243 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2244 * @hw: pointer to the HW structure
2245 * @offset: The offset of the byte to write.
2246 * @byte: The byte to write to the NVM.
2247 *
2248 * Writes a single byte to the NVM using the flash access registers.
2249 * Goes through a retry algorithm before giving up.
2250 **/
2251 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2252 u32 offset, u8 byte)
2253 {
2254 s32 ret_val;
2255 u16 program_retries;
2256
2257 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2258 if (!ret_val)
2259 return ret_val;
2260
2261 for (program_retries = 0; program_retries < 100; program_retries++) {
2262 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2263 udelay(100);
2264 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2265 if (!ret_val)
2266 break;
2267 }
2268 if (program_retries == 100)
2269 return -E1000_ERR_NVM;
2270
2271 return 0;
2272 }
2273
2274 /**
2275 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2276 * @hw: pointer to the HW structure
2277 * @bank: 0 for first bank, 1 for second bank, etc.
2278 *
2279 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2280 * bank N is 4096 * N + flash_reg_addr.
2281 **/
2282 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2283 {
2284 struct e1000_nvm_info *nvm = &hw->nvm;
2285 union ich8_hws_flash_status hsfsts;
2286 union ich8_hws_flash_ctrl hsflctl;
2287 u32 flash_linear_addr;
2288 /* bank size is in 16bit words - adjust to bytes */
2289 u32 flash_bank_size = nvm->flash_bank_size * 2;
2290 s32 ret_val;
2291 s32 count = 0;
2292 s32 j, iteration, sector_size;
2293
2294 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2295
2296 /*
2297 * Determine HW Sector size: Read BERASE bits of hw flash status
2298 * register
2299 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2300 * consecutive sectors. The start index for the nth Hw sector
2301 * can be calculated as = bank * 4096 + n * 256
2302 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2303 * The start index for the nth Hw sector can be calculated
2304 * as = bank * 4096
2305 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2306 * (ich9 only, otherwise error condition)
2307 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2308 */
2309 switch (hsfsts.hsf_status.berasesz) {
2310 case 0:
2311 /* Hw sector size 256 */
2312 sector_size = ICH_FLASH_SEG_SIZE_256;
2313 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2314 break;
2315 case 1:
2316 sector_size = ICH_FLASH_SEG_SIZE_4K;
2317 iteration = 1;
2318 break;
2319 case 2:
2320 sector_size = ICH_FLASH_SEG_SIZE_8K;
2321 iteration = 1;
2322 break;
2323 case 3:
2324 sector_size = ICH_FLASH_SEG_SIZE_64K;
2325 iteration = 1;
2326 break;
2327 default:
2328 return -E1000_ERR_NVM;
2329 }
2330
2331 /* Start with the base address, then add the sector offset. */
2332 flash_linear_addr = hw->nvm.flash_base_addr;
2333 flash_linear_addr += (bank) ? flash_bank_size : 0;
2334
2335 for (j = 0; j < iteration ; j++) {
2336 do {
2337 /* Steps */
2338 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2339 if (ret_val)
2340 return ret_val;
2341
2342 /*
2343 * Write a value 11 (block Erase) in Flash
2344 * Cycle field in hw flash control
2345 */
2346 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2347 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2348 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2349
2350 /*
2351 * Write the last 24 bits of an index within the
2352 * block into Flash Linear address field in Flash
2353 * Address.
2354 */
2355 flash_linear_addr += (j * sector_size);
2356 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2357
2358 ret_val = e1000_flash_cycle_ich8lan(hw,
2359 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2360 if (ret_val == 0)
2361 break;
2362
2363 /*
2364 * Check if FCERR is set to 1. If 1,
2365 * clear it and try the whole sequence
2366 * a few more times else Done
2367 */
2368 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2369 if (hsfsts.hsf_status.flcerr == 1)
2370 /* repeat for some time before giving up */
2371 continue;
2372 else if (hsfsts.hsf_status.flcdone == 0)
2373 return ret_val;
2374 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2375 }
2376
2377 return 0;
2378 }
2379
2380 /**
2381 * e1000_valid_led_default_ich8lan - Set the default LED settings
2382 * @hw: pointer to the HW structure
2383 * @data: Pointer to the LED settings
2384 *
2385 * Reads the LED default settings from the NVM to data. If the NVM LED
2386 * settings is all 0's or F's, set the LED default to a valid LED default
2387 * setting.
2388 **/
2389 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2390 {
2391 s32 ret_val;
2392
2393 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2394 if (ret_val) {
2395 e_dbg("NVM Read Error\n");
2396 return ret_val;
2397 }
2398
2399 if (*data == ID_LED_RESERVED_0000 ||
2400 *data == ID_LED_RESERVED_FFFF)
2401 *data = ID_LED_DEFAULT_ICH8LAN;
2402
2403 return 0;
2404 }
2405
2406 /**
2407 * e1000_id_led_init_pchlan - store LED configurations
2408 * @hw: pointer to the HW structure
2409 *
2410 * PCH does not control LEDs via the LEDCTL register, rather it uses
2411 * the PHY LED configuration register.
2412 *
2413 * PCH also does not have an "always on" or "always off" mode which
2414 * complicates the ID feature. Instead of using the "on" mode to indicate
2415 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2416 * use "link_up" mode. The LEDs will still ID on request if there is no
2417 * link based on logic in e1000_led_[on|off]_pchlan().
2418 **/
2419 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2420 {
2421 struct e1000_mac_info *mac = &hw->mac;
2422 s32 ret_val;
2423 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2424 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2425 u16 data, i, temp, shift;
2426
2427 /* Get default ID LED modes */
2428 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2429 if (ret_val)
2430 goto out;
2431
2432 mac->ledctl_default = er32(LEDCTL);
2433 mac->ledctl_mode1 = mac->ledctl_default;
2434 mac->ledctl_mode2 = mac->ledctl_default;
2435
2436 for (i = 0; i < 4; i++) {
2437 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2438 shift = (i * 5);
2439 switch (temp) {
2440 case ID_LED_ON1_DEF2:
2441 case ID_LED_ON1_ON2:
2442 case ID_LED_ON1_OFF2:
2443 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2444 mac->ledctl_mode1 |= (ledctl_on << shift);
2445 break;
2446 case ID_LED_OFF1_DEF2:
2447 case ID_LED_OFF1_ON2:
2448 case ID_LED_OFF1_OFF2:
2449 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2450 mac->ledctl_mode1 |= (ledctl_off << shift);
2451 break;
2452 default:
2453 /* Do nothing */
2454 break;
2455 }
2456 switch (temp) {
2457 case ID_LED_DEF1_ON2:
2458 case ID_LED_ON1_ON2:
2459 case ID_LED_OFF1_ON2:
2460 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2461 mac->ledctl_mode2 |= (ledctl_on << shift);
2462 break;
2463 case ID_LED_DEF1_OFF2:
2464 case ID_LED_ON1_OFF2:
2465 case ID_LED_OFF1_OFF2:
2466 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2467 mac->ledctl_mode2 |= (ledctl_off << shift);
2468 break;
2469 default:
2470 /* Do nothing */
2471 break;
2472 }
2473 }
2474
2475 out:
2476 return ret_val;
2477 }
2478
2479 /**
2480 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2481 * @hw: pointer to the HW structure
2482 *
2483 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2484 * register, so the the bus width is hard coded.
2485 **/
2486 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2487 {
2488 struct e1000_bus_info *bus = &hw->bus;
2489 s32 ret_val;
2490
2491 ret_val = e1000e_get_bus_info_pcie(hw);
2492
2493 /*
2494 * ICH devices are "PCI Express"-ish. They have
2495 * a configuration space, but do not contain
2496 * PCI Express Capability registers, so bus width
2497 * must be hardcoded.
2498 */
2499 if (bus->width == e1000_bus_width_unknown)
2500 bus->width = e1000_bus_width_pcie_x1;
2501
2502 return ret_val;
2503 }
2504
2505 /**
2506 * e1000_reset_hw_ich8lan - Reset the hardware
2507 * @hw: pointer to the HW structure
2508 *
2509 * Does a full reset of the hardware which includes a reset of the PHY and
2510 * MAC.
2511 **/
2512 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2513 {
2514 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2515 u16 reg;
2516 u32 ctrl, icr, kab;
2517 s32 ret_val;
2518
2519 /*
2520 * Prevent the PCI-E bus from sticking if there is no TLP connection
2521 * on the last TLP read/write transaction when MAC is reset.
2522 */
2523 ret_val = e1000e_disable_pcie_master(hw);
2524 if (ret_val)
2525 e_dbg("PCI-E Master disable polling has failed.\n");
2526
2527 e_dbg("Masking off all interrupts\n");
2528 ew32(IMC, 0xffffffff);
2529
2530 /*
2531 * Disable the Transmit and Receive units. Then delay to allow
2532 * any pending transactions to complete before we hit the MAC
2533 * with the global reset.
2534 */
2535 ew32(RCTL, 0);
2536 ew32(TCTL, E1000_TCTL_PSP);
2537 e1e_flush();
2538
2539 msleep(10);
2540
2541 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2542 if (hw->mac.type == e1000_ich8lan) {
2543 /* Set Tx and Rx buffer allocation to 8k apiece. */
2544 ew32(PBA, E1000_PBA_8K);
2545 /* Set Packet Buffer Size to 16k. */
2546 ew32(PBS, E1000_PBS_16K);
2547 }
2548
2549 if (hw->mac.type == e1000_pchlan) {
2550 /* Save the NVM K1 bit setting*/
2551 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2552 if (ret_val)
2553 return ret_val;
2554
2555 if (reg & E1000_NVM_K1_ENABLE)
2556 dev_spec->nvm_k1_enabled = true;
2557 else
2558 dev_spec->nvm_k1_enabled = false;
2559 }
2560
2561 ctrl = er32(CTRL);
2562
2563 if (!e1000_check_reset_block(hw)) {
2564 /*
2565 * Full-chip reset requires MAC and PHY reset at the same
2566 * time to make sure the interface between MAC and the
2567 * external PHY is reset.
2568 */
2569 ctrl |= E1000_CTRL_PHY_RST;
2570 }
2571 ret_val = e1000_acquire_swflag_ich8lan(hw);
2572 e_dbg("Issuing a global reset to ich8lan\n");
2573 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2574 msleep(20);
2575
2576 if (!ret_val)
2577 e1000_release_swflag_ich8lan(hw);
2578
2579 if (ctrl & E1000_CTRL_PHY_RST) {
2580 ret_val = hw->phy.ops.get_cfg_done(hw);
2581 if (ret_val)
2582 goto out;
2583
2584 ret_val = e1000_post_phy_reset_ich8lan(hw);
2585 if (ret_val)
2586 goto out;
2587 }
2588
2589 /*
2590 * For PCH, this write will make sure that any noise
2591 * will be detected as a CRC error and be dropped rather than show up
2592 * as a bad packet to the DMA engine.
2593 */
2594 if (hw->mac.type == e1000_pchlan)
2595 ew32(CRC_OFFSET, 0x65656565);
2596
2597 ew32(IMC, 0xffffffff);
2598 icr = er32(ICR);
2599
2600 kab = er32(KABGTXD);
2601 kab |= E1000_KABGTXD_BGSQLBIAS;
2602 ew32(KABGTXD, kab);
2603
2604 out:
2605 return ret_val;
2606 }
2607
2608 /**
2609 * e1000_init_hw_ich8lan - Initialize the hardware
2610 * @hw: pointer to the HW structure
2611 *
2612 * Prepares the hardware for transmit and receive by doing the following:
2613 * - initialize hardware bits
2614 * - initialize LED identification
2615 * - setup receive address registers
2616 * - setup flow control
2617 * - setup transmit descriptors
2618 * - clear statistics
2619 **/
2620 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2621 {
2622 struct e1000_mac_info *mac = &hw->mac;
2623 u32 ctrl_ext, txdctl, snoop;
2624 s32 ret_val;
2625 u16 i;
2626
2627 e1000_initialize_hw_bits_ich8lan(hw);
2628
2629 /* Initialize identification LED */
2630 ret_val = mac->ops.id_led_init(hw);
2631 if (ret_val)
2632 e_dbg("Error initializing identification LED\n");
2633 /* This is not fatal and we should not stop init due to this */
2634
2635 /* Setup the receive address. */
2636 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2637
2638 /* Zero out the Multicast HASH table */
2639 e_dbg("Zeroing the MTA\n");
2640 for (i = 0; i < mac->mta_reg_count; i++)
2641 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2642
2643 /*
2644 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2645 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2646 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2647 */
2648 if (hw->phy.type == e1000_phy_82578) {
2649 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2650 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2651 if (ret_val)
2652 return ret_val;
2653 }
2654
2655 /* Setup link and flow control */
2656 ret_val = e1000_setup_link_ich8lan(hw);
2657
2658 /* Set the transmit descriptor write-back policy for both queues */
2659 txdctl = er32(TXDCTL(0));
2660 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2661 E1000_TXDCTL_FULL_TX_DESC_WB;
2662 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2663 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2664 ew32(TXDCTL(0), txdctl);
2665 txdctl = er32(TXDCTL(1));
2666 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2667 E1000_TXDCTL_FULL_TX_DESC_WB;
2668 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2669 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2670 ew32(TXDCTL(1), txdctl);
2671
2672 /*
2673 * ICH8 has opposite polarity of no_snoop bits.
2674 * By default, we should use snoop behavior.
2675 */
2676 if (mac->type == e1000_ich8lan)
2677 snoop = PCIE_ICH8_SNOOP_ALL;
2678 else
2679 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2680 e1000e_set_pcie_no_snoop(hw, snoop);
2681
2682 ctrl_ext = er32(CTRL_EXT);
2683 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2684 ew32(CTRL_EXT, ctrl_ext);
2685
2686 /*
2687 * Clear all of the statistics registers (clear on read). It is
2688 * important that we do this after we have tried to establish link
2689 * because the symbol error count will increment wildly if there
2690 * is no link.
2691 */
2692 e1000_clear_hw_cntrs_ich8lan(hw);
2693
2694 return 0;
2695 }
2696 /**
2697 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2698 * @hw: pointer to the HW structure
2699 *
2700 * Sets/Clears required hardware bits necessary for correctly setting up the
2701 * hardware for transmit and receive.
2702 **/
2703 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2704 {
2705 u32 reg;
2706
2707 /* Extended Device Control */
2708 reg = er32(CTRL_EXT);
2709 reg |= (1 << 22);
2710 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2711 if (hw->mac.type >= e1000_pchlan)
2712 reg |= E1000_CTRL_EXT_PHYPDEN;
2713 ew32(CTRL_EXT, reg);
2714
2715 /* Transmit Descriptor Control 0 */
2716 reg = er32(TXDCTL(0));
2717 reg |= (1 << 22);
2718 ew32(TXDCTL(0), reg);
2719
2720 /* Transmit Descriptor Control 1 */
2721 reg = er32(TXDCTL(1));
2722 reg |= (1 << 22);
2723 ew32(TXDCTL(1), reg);
2724
2725 /* Transmit Arbitration Control 0 */
2726 reg = er32(TARC(0));
2727 if (hw->mac.type == e1000_ich8lan)
2728 reg |= (1 << 28) | (1 << 29);
2729 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2730 ew32(TARC(0), reg);
2731
2732 /* Transmit Arbitration Control 1 */
2733 reg = er32(TARC(1));
2734 if (er32(TCTL) & E1000_TCTL_MULR)
2735 reg &= ~(1 << 28);
2736 else
2737 reg |= (1 << 28);
2738 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2739 ew32(TARC(1), reg);
2740
2741 /* Device Status */
2742 if (hw->mac.type == e1000_ich8lan) {
2743 reg = er32(STATUS);
2744 reg &= ~(1 << 31);
2745 ew32(STATUS, reg);
2746 }
2747
2748 /*
2749 * work-around descriptor data corruption issue during nfs v2 udp
2750 * traffic, just disable the nfs filtering capability
2751 */
2752 reg = er32(RFCTL);
2753 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
2754 ew32(RFCTL, reg);
2755 }
2756
2757 /**
2758 * e1000_setup_link_ich8lan - Setup flow control and link settings
2759 * @hw: pointer to the HW structure
2760 *
2761 * Determines which flow control settings to use, then configures flow
2762 * control. Calls the appropriate media-specific link configuration
2763 * function. Assuming the adapter has a valid link partner, a valid link
2764 * should be established. Assumes the hardware has previously been reset
2765 * and the transmitter and receiver are not enabled.
2766 **/
2767 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2768 {
2769 s32 ret_val;
2770
2771 if (e1000_check_reset_block(hw))
2772 return 0;
2773
2774 /*
2775 * ICH parts do not have a word in the NVM to determine
2776 * the default flow control setting, so we explicitly
2777 * set it to full.
2778 */
2779 if (hw->fc.requested_mode == e1000_fc_default) {
2780 /* Workaround h/w hang when Tx flow control enabled */
2781 if (hw->mac.type == e1000_pchlan)
2782 hw->fc.requested_mode = e1000_fc_rx_pause;
2783 else
2784 hw->fc.requested_mode = e1000_fc_full;
2785 }
2786
2787 /*
2788 * Save off the requested flow control mode for use later. Depending
2789 * on the link partner's capabilities, we may or may not use this mode.
2790 */
2791 hw->fc.current_mode = hw->fc.requested_mode;
2792
2793 e_dbg("After fix-ups FlowControl is now = %x\n",
2794 hw->fc.current_mode);
2795
2796 /* Continue to configure the copper link. */
2797 ret_val = e1000_setup_copper_link_ich8lan(hw);
2798 if (ret_val)
2799 return ret_val;
2800
2801 ew32(FCTTV, hw->fc.pause_time);
2802 if ((hw->phy.type == e1000_phy_82578) ||
2803 (hw->phy.type == e1000_phy_82577)) {
2804 ew32(FCRTV_PCH, hw->fc.refresh_time);
2805
2806 ret_val = hw->phy.ops.write_reg(hw,
2807 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2808 hw->fc.pause_time);
2809 if (ret_val)
2810 return ret_val;
2811 }
2812
2813 return e1000e_set_fc_watermarks(hw);
2814 }
2815
2816 /**
2817 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2818 * @hw: pointer to the HW structure
2819 *
2820 * Configures the kumeran interface to the PHY to wait the appropriate time
2821 * when polling the PHY, then call the generic setup_copper_link to finish
2822 * configuring the copper link.
2823 **/
2824 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2825 {
2826 u32 ctrl;
2827 s32 ret_val;
2828 u16 reg_data;
2829
2830 ctrl = er32(CTRL);
2831 ctrl |= E1000_CTRL_SLU;
2832 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2833 ew32(CTRL, ctrl);
2834
2835 /*
2836 * Set the mac to wait the maximum time between each iteration
2837 * and increase the max iterations when polling the phy;
2838 * this fixes erroneous timeouts at 10Mbps.
2839 */
2840 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
2841 if (ret_val)
2842 return ret_val;
2843 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2844 &reg_data);
2845 if (ret_val)
2846 return ret_val;
2847 reg_data |= 0x3F;
2848 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2849 reg_data);
2850 if (ret_val)
2851 return ret_val;
2852
2853 switch (hw->phy.type) {
2854 case e1000_phy_igp_3:
2855 ret_val = e1000e_copper_link_setup_igp(hw);
2856 if (ret_val)
2857 return ret_val;
2858 break;
2859 case e1000_phy_bm:
2860 case e1000_phy_82578:
2861 ret_val = e1000e_copper_link_setup_m88(hw);
2862 if (ret_val)
2863 return ret_val;
2864 break;
2865 case e1000_phy_82577:
2866 ret_val = e1000_copper_link_setup_82577(hw);
2867 if (ret_val)
2868 return ret_val;
2869 break;
2870 case e1000_phy_ife:
2871 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2872 &reg_data);
2873 if (ret_val)
2874 return ret_val;
2875
2876 reg_data &= ~IFE_PMC_AUTO_MDIX;
2877
2878 switch (hw->phy.mdix) {
2879 case 1:
2880 reg_data &= ~IFE_PMC_FORCE_MDIX;
2881 break;
2882 case 2:
2883 reg_data |= IFE_PMC_FORCE_MDIX;
2884 break;
2885 case 0:
2886 default:
2887 reg_data |= IFE_PMC_AUTO_MDIX;
2888 break;
2889 }
2890 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2891 reg_data);
2892 if (ret_val)
2893 return ret_val;
2894 break;
2895 default:
2896 break;
2897 }
2898 return e1000e_setup_copper_link(hw);
2899 }
2900
2901 /**
2902 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2903 * @hw: pointer to the HW structure
2904 * @speed: pointer to store current link speed
2905 * @duplex: pointer to store the current link duplex
2906 *
2907 * Calls the generic get_speed_and_duplex to retrieve the current link
2908 * information and then calls the Kumeran lock loss workaround for links at
2909 * gigabit speeds.
2910 **/
2911 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2912 u16 *duplex)
2913 {
2914 s32 ret_val;
2915
2916 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2917 if (ret_val)
2918 return ret_val;
2919
2920 if ((hw->mac.type == e1000_ich8lan) &&
2921 (hw->phy.type == e1000_phy_igp_3) &&
2922 (*speed == SPEED_1000)) {
2923 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2924 }
2925
2926 return ret_val;
2927 }
2928
2929 /**
2930 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2931 * @hw: pointer to the HW structure
2932 *
2933 * Work-around for 82566 Kumeran PCS lock loss:
2934 * On link status change (i.e. PCI reset, speed change) and link is up and
2935 * speed is gigabit-
2936 * 0) if workaround is optionally disabled do nothing
2937 * 1) wait 1ms for Kumeran link to come up
2938 * 2) check Kumeran Diagnostic register PCS lock loss bit
2939 * 3) if not set the link is locked (all is good), otherwise...
2940 * 4) reset the PHY
2941 * 5) repeat up to 10 times
2942 * Note: this is only called for IGP3 copper when speed is 1gb.
2943 **/
2944 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2945 {
2946 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2947 u32 phy_ctrl;
2948 s32 ret_val;
2949 u16 i, data;
2950 bool link;
2951
2952 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2953 return 0;
2954
2955 /*
2956 * Make sure link is up before proceeding. If not just return.
2957 * Attempting this while link is negotiating fouled up link
2958 * stability
2959 */
2960 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2961 if (!link)
2962 return 0;
2963
2964 for (i = 0; i < 10; i++) {
2965 /* read once to clear */
2966 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2967 if (ret_val)
2968 return ret_val;
2969 /* and again to get new status */
2970 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2971 if (ret_val)
2972 return ret_val;
2973
2974 /* check for PCS lock */
2975 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2976 return 0;
2977
2978 /* Issue PHY reset */
2979 e1000_phy_hw_reset(hw);
2980 mdelay(5);
2981 }
2982 /* Disable GigE link negotiation */
2983 phy_ctrl = er32(PHY_CTRL);
2984 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2985 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2986 ew32(PHY_CTRL, phy_ctrl);
2987
2988 /*
2989 * Call gig speed drop workaround on Gig disable before accessing
2990 * any PHY registers
2991 */
2992 e1000e_gig_downshift_workaround_ich8lan(hw);
2993
2994 /* unable to acquire PCS lock */
2995 return -E1000_ERR_PHY;
2996 }
2997
2998 /**
2999 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3000 * @hw: pointer to the HW structure
3001 * @state: boolean value used to set the current Kumeran workaround state
3002 *
3003 * If ICH8, set the current Kumeran workaround state (enabled - true
3004 * /disabled - false).
3005 **/
3006 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3007 bool state)
3008 {
3009 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3010
3011 if (hw->mac.type != e1000_ich8lan) {
3012 e_dbg("Workaround applies to ICH8 only.\n");
3013 return;
3014 }
3015
3016 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3017 }
3018
3019 /**
3020 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3021 * @hw: pointer to the HW structure
3022 *
3023 * Workaround for 82566 power-down on D3 entry:
3024 * 1) disable gigabit link
3025 * 2) write VR power-down enable
3026 * 3) read it back
3027 * Continue if successful, else issue LCD reset and repeat
3028 **/
3029 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3030 {
3031 u32 reg;
3032 u16 data;
3033 u8 retry = 0;
3034
3035 if (hw->phy.type != e1000_phy_igp_3)
3036 return;
3037
3038 /* Try the workaround twice (if needed) */
3039 do {
3040 /* Disable link */
3041 reg = er32(PHY_CTRL);
3042 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3043 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3044 ew32(PHY_CTRL, reg);
3045
3046 /*
3047 * Call gig speed drop workaround on Gig disable before
3048 * accessing any PHY registers
3049 */
3050 if (hw->mac.type == e1000_ich8lan)
3051 e1000e_gig_downshift_workaround_ich8lan(hw);
3052
3053 /* Write VR power-down enable */
3054 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3055 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3056 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3057
3058 /* Read it back and test */
3059 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3060 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3061 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3062 break;
3063
3064 /* Issue PHY reset and repeat at most one more time */
3065 reg = er32(CTRL);
3066 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3067 retry++;
3068 } while (retry);
3069 }
3070
3071 /**
3072 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3073 * @hw: pointer to the HW structure
3074 *
3075 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3076 * LPLU, Gig disable, MDIC PHY reset):
3077 * 1) Set Kumeran Near-end loopback
3078 * 2) Clear Kumeran Near-end loopback
3079 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3080 **/
3081 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3082 {
3083 s32 ret_val;
3084 u16 reg_data;
3085
3086 if ((hw->mac.type != e1000_ich8lan) ||
3087 (hw->phy.type != e1000_phy_igp_3))
3088 return;
3089
3090 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3091 &reg_data);
3092 if (ret_val)
3093 return;
3094 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3095 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3096 reg_data);
3097 if (ret_val)
3098 return;
3099 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3100 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3101 reg_data);
3102 }
3103
3104 /**
3105 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3106 * @hw: pointer to the HW structure
3107 *
3108 * During S0 to Sx transition, it is possible the link remains at gig
3109 * instead of negotiating to a lower speed. Before going to Sx, set
3110 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3111 * to a lower speed.
3112 *
3113 * Should only be called for applicable parts.
3114 **/
3115 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3116 {
3117 u32 phy_ctrl;
3118
3119 switch (hw->mac.type) {
3120 case e1000_ich8lan:
3121 case e1000_ich9lan:
3122 case e1000_ich10lan:
3123 case e1000_pchlan:
3124 phy_ctrl = er32(PHY_CTRL);
3125 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3126 E1000_PHY_CTRL_GBE_DISABLE;
3127 ew32(PHY_CTRL, phy_ctrl);
3128
3129 if (hw->mac.type == e1000_pchlan)
3130 e1000_phy_hw_reset_ich8lan(hw);
3131 default:
3132 break;
3133 }
3134 }
3135
3136 /**
3137 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3138 * @hw: pointer to the HW structure
3139 *
3140 * Return the LED back to the default configuration.
3141 **/
3142 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3143 {
3144 if (hw->phy.type == e1000_phy_ife)
3145 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3146
3147 ew32(LEDCTL, hw->mac.ledctl_default);
3148 return 0;
3149 }
3150
3151 /**
3152 * e1000_led_on_ich8lan - Turn LEDs on
3153 * @hw: pointer to the HW structure
3154 *
3155 * Turn on the LEDs.
3156 **/
3157 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3158 {
3159 if (hw->phy.type == e1000_phy_ife)
3160 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3161 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3162
3163 ew32(LEDCTL, hw->mac.ledctl_mode2);
3164 return 0;
3165 }
3166
3167 /**
3168 * e1000_led_off_ich8lan - Turn LEDs off
3169 * @hw: pointer to the HW structure
3170 *
3171 * Turn off the LEDs.
3172 **/
3173 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3174 {
3175 if (hw->phy.type == e1000_phy_ife)
3176 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3177 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3178
3179 ew32(LEDCTL, hw->mac.ledctl_mode1);
3180 return 0;
3181 }
3182
3183 /**
3184 * e1000_setup_led_pchlan - Configures SW controllable LED
3185 * @hw: pointer to the HW structure
3186 *
3187 * This prepares the SW controllable LED for use.
3188 **/
3189 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3190 {
3191 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3192 (u16)hw->mac.ledctl_mode1);
3193 }
3194
3195 /**
3196 * e1000_cleanup_led_pchlan - Restore the default LED operation
3197 * @hw: pointer to the HW structure
3198 *
3199 * Return the LED back to the default configuration.
3200 **/
3201 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3202 {
3203 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3204 (u16)hw->mac.ledctl_default);
3205 }
3206
3207 /**
3208 * e1000_led_on_pchlan - Turn LEDs on
3209 * @hw: pointer to the HW structure
3210 *
3211 * Turn on the LEDs.
3212 **/
3213 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3214 {
3215 u16 data = (u16)hw->mac.ledctl_mode2;
3216 u32 i, led;
3217
3218 /*
3219 * If no link, then turn LED on by setting the invert bit
3220 * for each LED that's mode is "link_up" in ledctl_mode2.
3221 */
3222 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3223 for (i = 0; i < 3; i++) {
3224 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3225 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3226 E1000_LEDCTL_MODE_LINK_UP)
3227 continue;
3228 if (led & E1000_PHY_LED0_IVRT)
3229 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3230 else
3231 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3232 }
3233 }
3234
3235 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3236 }
3237
3238 /**
3239 * e1000_led_off_pchlan - Turn LEDs off
3240 * @hw: pointer to the HW structure
3241 *
3242 * Turn off the LEDs.
3243 **/
3244 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3245 {
3246 u16 data = (u16)hw->mac.ledctl_mode1;
3247 u32 i, led;
3248
3249 /*
3250 * If no link, then turn LED off by clearing the invert bit
3251 * for each LED that's mode is "link_up" in ledctl_mode1.
3252 */
3253 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3254 for (i = 0; i < 3; i++) {
3255 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3256 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3257 E1000_LEDCTL_MODE_LINK_UP)
3258 continue;
3259 if (led & E1000_PHY_LED0_IVRT)
3260 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3261 else
3262 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3263 }
3264 }
3265
3266 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3267 }
3268
3269 /**
3270 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3271 * @hw: pointer to the HW structure
3272 *
3273 * Read appropriate register for the config done bit for completion status
3274 * and configure the PHY through s/w for EEPROM-less parts.
3275 *
3276 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3277 * config done bit, so only an error is logged and continues. If we were
3278 * to return with error, EEPROM-less silicon would not be able to be reset
3279 * or change link.
3280 **/
3281 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3282 {
3283 s32 ret_val = 0;
3284 u32 bank = 0;
3285 u32 status;
3286
3287 e1000e_get_cfg_done(hw);
3288
3289 /* Wait for indication from h/w that it has completed basic config */
3290 if (hw->mac.type >= e1000_ich10lan) {
3291 e1000_lan_init_done_ich8lan(hw);
3292 } else {
3293 ret_val = e1000e_get_auto_rd_done(hw);
3294 if (ret_val) {
3295 /*
3296 * When auto config read does not complete, do not
3297 * return with an error. This can happen in situations
3298 * where there is no eeprom and prevents getting link.
3299 */
3300 e_dbg("Auto Read Done did not complete\n");
3301 ret_val = 0;
3302 }
3303 }
3304
3305 /* Clear PHY Reset Asserted bit */
3306 status = er32(STATUS);
3307 if (status & E1000_STATUS_PHYRA)
3308 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3309 else
3310 e_dbg("PHY Reset Asserted not set - needs delay\n");
3311
3312 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3313 if (hw->mac.type <= e1000_ich9lan) {
3314 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3315 (hw->phy.type == e1000_phy_igp_3)) {
3316 e1000e_phy_init_script_igp3(hw);
3317 }
3318 } else {
3319 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3320 /* Maybe we should do a basic PHY config */
3321 e_dbg("EEPROM not present\n");
3322 ret_val = -E1000_ERR_CONFIG;
3323 }
3324 }
3325
3326 return ret_val;
3327 }
3328
3329 /**
3330 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3331 * @hw: pointer to the HW structure
3332 *
3333 * In the case of a PHY power down to save power, or to turn off link during a
3334 * driver unload, or wake on lan is not enabled, remove the link.
3335 **/
3336 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3337 {
3338 /* If the management interface is not enabled, then power down */
3339 if (!(hw->mac.ops.check_mng_mode(hw) ||
3340 hw->phy.ops.check_reset_block(hw)))
3341 e1000_power_down_phy_copper(hw);
3342 }
3343
3344 /**
3345 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3346 * @hw: pointer to the HW structure
3347 *
3348 * Clears hardware counters specific to the silicon family and calls
3349 * clear_hw_cntrs_generic to clear all general purpose counters.
3350 **/
3351 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3352 {
3353 u16 phy_data;
3354
3355 e1000e_clear_hw_cntrs_base(hw);
3356
3357 er32(ALGNERRC);
3358 er32(RXERRC);
3359 er32(TNCRS);
3360 er32(CEXTERR);
3361 er32(TSCTC);
3362 er32(TSCTFC);
3363
3364 er32(MGTPRC);
3365 er32(MGTPDC);
3366 er32(MGTPTC);
3367
3368 er32(IAC);
3369 er32(ICRXOC);
3370
3371 /* Clear PHY statistics registers */
3372 if ((hw->phy.type == e1000_phy_82578) ||
3373 (hw->phy.type == e1000_phy_82577)) {
3374 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3375 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3376 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3377 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3378 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3379 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3380 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3381 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3382 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3383 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3384 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3385 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3386 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3387 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3388 }
3389 }
3390
3391 static struct e1000_mac_operations ich8_mac_ops = {
3392 .id_led_init = e1000e_id_led_init,
3393 .check_mng_mode = e1000_check_mng_mode_ich8lan,
3394 .check_for_link = e1000_check_for_copper_link_ich8lan,
3395 /* cleanup_led dependent on mac type */
3396 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3397 .get_bus_info = e1000_get_bus_info_ich8lan,
3398 .set_lan_id = e1000_set_lan_id_single_port,
3399 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3400 /* led_on dependent on mac type */
3401 /* led_off dependent on mac type */
3402 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3403 .reset_hw = e1000_reset_hw_ich8lan,
3404 .init_hw = e1000_init_hw_ich8lan,
3405 .setup_link = e1000_setup_link_ich8lan,
3406 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3407 /* id_led_init dependent on mac type */
3408 };
3409
3410 static struct e1000_phy_operations ich8_phy_ops = {
3411 .acquire = e1000_acquire_swflag_ich8lan,
3412 .check_reset_block = e1000_check_reset_block_ich8lan,
3413 .commit = NULL,
3414 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3415 .get_cable_length = e1000e_get_cable_length_igp_2,
3416 .read_reg = e1000e_read_phy_reg_igp,
3417 .release = e1000_release_swflag_ich8lan,
3418 .reset = e1000_phy_hw_reset_ich8lan,
3419 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3420 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
3421 .write_reg = e1000e_write_phy_reg_igp,
3422 };
3423
3424 static struct e1000_nvm_operations ich8_nvm_ops = {
3425 .acquire = e1000_acquire_nvm_ich8lan,
3426 .read = e1000_read_nvm_ich8lan,
3427 .release = e1000_release_nvm_ich8lan,
3428 .update = e1000_update_nvm_checksum_ich8lan,
3429 .valid_led_default = e1000_valid_led_default_ich8lan,
3430 .validate = e1000_validate_nvm_checksum_ich8lan,
3431 .write = e1000_write_nvm_ich8lan,
3432 };
3433
3434 struct e1000_info e1000_ich8_info = {
3435 .mac = e1000_ich8lan,
3436 .flags = FLAG_HAS_WOL
3437 | FLAG_IS_ICH
3438 | FLAG_RX_CSUM_ENABLED
3439 | FLAG_HAS_CTRLEXT_ON_LOAD
3440 | FLAG_HAS_AMT
3441 | FLAG_HAS_FLASH
3442 | FLAG_APME_IN_WUC,
3443 .pba = 8,
3444 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
3445 .get_variants = e1000_get_variants_ich8lan,
3446 .mac_ops = &ich8_mac_ops,
3447 .phy_ops = &ich8_phy_ops,
3448 .nvm_ops = &ich8_nvm_ops,
3449 };
3450
3451 struct e1000_info e1000_ich9_info = {
3452 .mac = e1000_ich9lan,
3453 .flags = FLAG_HAS_JUMBO_FRAMES
3454 | FLAG_IS_ICH
3455 | FLAG_HAS_WOL
3456 | FLAG_RX_CSUM_ENABLED
3457 | FLAG_HAS_CTRLEXT_ON_LOAD
3458 | FLAG_HAS_AMT
3459 | FLAG_HAS_ERT
3460 | FLAG_HAS_FLASH
3461 | FLAG_APME_IN_WUC,
3462 .pba = 10,
3463 .max_hw_frame_size = DEFAULT_JUMBO,
3464 .get_variants = e1000_get_variants_ich8lan,
3465 .mac_ops = &ich8_mac_ops,
3466 .phy_ops = &ich8_phy_ops,
3467 .nvm_ops = &ich8_nvm_ops,
3468 };
3469
3470 struct e1000_info e1000_ich10_info = {
3471 .mac = e1000_ich10lan,
3472 .flags = FLAG_HAS_JUMBO_FRAMES
3473 | FLAG_IS_ICH
3474 | FLAG_HAS_WOL
3475 | FLAG_RX_CSUM_ENABLED
3476 | FLAG_HAS_CTRLEXT_ON_LOAD
3477 | FLAG_HAS_AMT
3478 | FLAG_HAS_ERT
3479 | FLAG_HAS_FLASH
3480 | FLAG_APME_IN_WUC,
3481 .pba = 10,
3482 .max_hw_frame_size = DEFAULT_JUMBO,
3483 .get_variants = e1000_get_variants_ich8lan,
3484 .mac_ops = &ich8_mac_ops,
3485 .phy_ops = &ich8_phy_ops,
3486 .nvm_ops = &ich8_nvm_ops,
3487 };
3488
3489 struct e1000_info e1000_pch_info = {
3490 .mac = e1000_pchlan,
3491 .flags = FLAG_IS_ICH
3492 | FLAG_HAS_WOL
3493 | FLAG_RX_CSUM_ENABLED
3494 | FLAG_HAS_CTRLEXT_ON_LOAD
3495 | FLAG_HAS_AMT
3496 | FLAG_HAS_FLASH
3497 | FLAG_HAS_JUMBO_FRAMES
3498 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3499 | FLAG_APME_IN_WUC,
3500 .pba = 26,
3501 .max_hw_frame_size = 4096,
3502 .get_variants = e1000_get_variants_ich8lan,
3503 .mac_ops = &ich8_mac_ops,
3504 .phy_ops = &ich8_phy_ops,
3505 .nvm_ops = &ich8_nvm_ops,
3506 };
kernel source for telekom puls (alcatel/mediatek)