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[PATCH] irq-flags: drivers/net: Use the new IRQF_ constants
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / e100.c
1 /*******************************************************************************
2
3
4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Recieve
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * Under typical operation, the receive unit (RU) is start once,
110 * and the controller happily fills RFDs as frames arrive. If
111 * replacement RFDs cannot be allocated, or the RU goes non-active,
112 * the RU must be restarted. Frame arrival generates an interrupt,
113 * and Rx indication and re-allocation happen in the same context,
114 * therefore no locking is required. A software-generated interrupt
115 * is generated from the watchdog to recover from a failed allocation
116 * senario where all Rx resources have been indicated and none re-
117 * placed.
118 *
119 * V. Miscellaneous
120 *
121 * VLAN offloading of tagging, stripping and filtering is not
122 * supported, but driver will accommodate the extra 4-byte VLAN tag
123 * for processing by upper layers. Tx/Rx Checksum offloading is not
124 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
125 * not supported (hardware limitation).
126 *
127 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
128 *
129 * Thanks to JC (jchapman@katalix.com) for helping with
130 * testing/troubleshooting the development driver.
131 *
132 * TODO:
133 * o several entry points race with dev->close
134 * o check for tx-no-resources/stop Q races with tx clean/wake Q
135 *
136 * FIXES:
137 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
138 * - Stratus87247: protect MDI control register manipulations
139 */
140
141 #include <linux/module.h>
142 #include <linux/moduleparam.h>
143 #include <linux/kernel.h>
144 #include <linux/types.h>
145 #include <linux/slab.h>
146 #include <linux/delay.h>
147 #include <linux/init.h>
148 #include <linux/pci.h>
149 #include <linux/dma-mapping.h>
150 #include <linux/netdevice.h>
151 #include <linux/etherdevice.h>
152 #include <linux/mii.h>
153 #include <linux/if_vlan.h>
154 #include <linux/skbuff.h>
155 #include <linux/ethtool.h>
156 #include <linux/string.h>
157 #include <asm/unaligned.h>
158
159
160 #define DRV_NAME "e100"
161 #define DRV_EXT "-NAPI"
162 #define DRV_VERSION "3.5.10-k2"DRV_EXT
163 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
164 #define DRV_COPYRIGHT "Copyright(c) 1999-2005 Intel Corporation"
165 #define PFX DRV_NAME ": "
166
167 #define E100_WATCHDOG_PERIOD (2 * HZ)
168 #define E100_NAPI_WEIGHT 16
169
170 MODULE_DESCRIPTION(DRV_DESCRIPTION);
171 MODULE_AUTHOR(DRV_COPYRIGHT);
172 MODULE_LICENSE("GPL");
173 MODULE_VERSION(DRV_VERSION);
174
175 static int debug = 3;
176 module_param(debug, int, 0);
177 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
178 #define DPRINTK(nlevel, klevel, fmt, args...) \
179 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
180 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
181 __FUNCTION__ , ## args))
182
183 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
184 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
185 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
186 static struct pci_device_id e100_id_table[] = {
187 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
188 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
189 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
190 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
191 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
192 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
193 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
194 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
196 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
197 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
198 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
199 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
200 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
204 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
205 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
206 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
207 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
208 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
209 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
213 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
214 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
215 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
216 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
217 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
218 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
219 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
220 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
221 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
222 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
223 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
224 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
225 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
226 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
227 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
228 { 0, }
229 };
230 MODULE_DEVICE_TABLE(pci, e100_id_table);
231
232 enum mac {
233 mac_82557_D100_A = 0,
234 mac_82557_D100_B = 1,
235 mac_82557_D100_C = 2,
236 mac_82558_D101_A4 = 4,
237 mac_82558_D101_B0 = 5,
238 mac_82559_D101M = 8,
239 mac_82559_D101S = 9,
240 mac_82550_D102 = 12,
241 mac_82550_D102_C = 13,
242 mac_82551_E = 14,
243 mac_82551_F = 15,
244 mac_82551_10 = 16,
245 mac_unknown = 0xFF,
246 };
247
248 enum phy {
249 phy_100a = 0x000003E0,
250 phy_100c = 0x035002A8,
251 phy_82555_tx = 0x015002A8,
252 phy_nsc_tx = 0x5C002000,
253 phy_82562_et = 0x033002A8,
254 phy_82562_em = 0x032002A8,
255 phy_82562_ek = 0x031002A8,
256 phy_82562_eh = 0x017002A8,
257 phy_unknown = 0xFFFFFFFF,
258 };
259
260 /* CSR (Control/Status Registers) */
261 struct csr {
262 struct {
263 u8 status;
264 u8 stat_ack;
265 u8 cmd_lo;
266 u8 cmd_hi;
267 u32 gen_ptr;
268 } scb;
269 u32 port;
270 u16 flash_ctrl;
271 u8 eeprom_ctrl_lo;
272 u8 eeprom_ctrl_hi;
273 u32 mdi_ctrl;
274 u32 rx_dma_count;
275 };
276
277 enum scb_status {
278 rus_ready = 0x10,
279 rus_mask = 0x3C,
280 };
281
282 enum ru_state {
283 RU_SUSPENDED = 0,
284 RU_RUNNING = 1,
285 RU_UNINITIALIZED = -1,
286 };
287
288 enum scb_stat_ack {
289 stat_ack_not_ours = 0x00,
290 stat_ack_sw_gen = 0x04,
291 stat_ack_rnr = 0x10,
292 stat_ack_cu_idle = 0x20,
293 stat_ack_frame_rx = 0x40,
294 stat_ack_cu_cmd_done = 0x80,
295 stat_ack_not_present = 0xFF,
296 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
297 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
298 };
299
300 enum scb_cmd_hi {
301 irq_mask_none = 0x00,
302 irq_mask_all = 0x01,
303 irq_sw_gen = 0x02,
304 };
305
306 enum scb_cmd_lo {
307 cuc_nop = 0x00,
308 ruc_start = 0x01,
309 ruc_load_base = 0x06,
310 cuc_start = 0x10,
311 cuc_resume = 0x20,
312 cuc_dump_addr = 0x40,
313 cuc_dump_stats = 0x50,
314 cuc_load_base = 0x60,
315 cuc_dump_reset = 0x70,
316 };
317
318 enum cuc_dump {
319 cuc_dump_complete = 0x0000A005,
320 cuc_dump_reset_complete = 0x0000A007,
321 };
322
323 enum port {
324 software_reset = 0x0000,
325 selftest = 0x0001,
326 selective_reset = 0x0002,
327 };
328
329 enum eeprom_ctrl_lo {
330 eesk = 0x01,
331 eecs = 0x02,
332 eedi = 0x04,
333 eedo = 0x08,
334 };
335
336 enum mdi_ctrl {
337 mdi_write = 0x04000000,
338 mdi_read = 0x08000000,
339 mdi_ready = 0x10000000,
340 };
341
342 enum eeprom_op {
343 op_write = 0x05,
344 op_read = 0x06,
345 op_ewds = 0x10,
346 op_ewen = 0x13,
347 };
348
349 enum eeprom_offsets {
350 eeprom_cnfg_mdix = 0x03,
351 eeprom_id = 0x0A,
352 eeprom_config_asf = 0x0D,
353 eeprom_smbus_addr = 0x90,
354 };
355
356 enum eeprom_cnfg_mdix {
357 eeprom_mdix_enabled = 0x0080,
358 };
359
360 enum eeprom_id {
361 eeprom_id_wol = 0x0020,
362 };
363
364 enum eeprom_config_asf {
365 eeprom_asf = 0x8000,
366 eeprom_gcl = 0x4000,
367 };
368
369 enum cb_status {
370 cb_complete = 0x8000,
371 cb_ok = 0x2000,
372 };
373
374 enum cb_command {
375 cb_nop = 0x0000,
376 cb_iaaddr = 0x0001,
377 cb_config = 0x0002,
378 cb_multi = 0x0003,
379 cb_tx = 0x0004,
380 cb_ucode = 0x0005,
381 cb_dump = 0x0006,
382 cb_tx_sf = 0x0008,
383 cb_cid = 0x1f00,
384 cb_i = 0x2000,
385 cb_s = 0x4000,
386 cb_el = 0x8000,
387 };
388
389 struct rfd {
390 u16 status;
391 u16 command;
392 u32 link;
393 u32 rbd;
394 u16 actual_size;
395 u16 size;
396 };
397
398 struct rx {
399 struct rx *next, *prev;
400 struct sk_buff *skb;
401 dma_addr_t dma_addr;
402 };
403
404 #if defined(__BIG_ENDIAN_BITFIELD)
405 #define X(a,b) b,a
406 #else
407 #define X(a,b) a,b
408 #endif
409 struct config {
410 /*0*/ u8 X(byte_count:6, pad0:2);
411 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
412 /*2*/ u8 adaptive_ifs;
413 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
414 term_write_cache_line:1), pad3:4);
415 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
416 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
417 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
418 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
419 rx_discard_overruns:1), rx_save_bad_frames:1);
420 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
421 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
422 tx_dynamic_tbd:1);
423 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
424 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
425 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
426 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
427 loopback:2);
428 /*11*/ u8 X(linear_priority:3, pad11:5);
429 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
430 /*13*/ u8 ip_addr_lo;
431 /*14*/ u8 ip_addr_hi;
432 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
433 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
434 pad15_2:1), crs_or_cdt:1);
435 /*16*/ u8 fc_delay_lo;
436 /*17*/ u8 fc_delay_hi;
437 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
438 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
439 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
440 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
441 full_duplex_force:1), full_duplex_pin:1);
442 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
443 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
444 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
445 u8 pad_d102[9];
446 };
447
448 #define E100_MAX_MULTICAST_ADDRS 64
449 struct multi {
450 u16 count;
451 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
452 };
453
454 /* Important: keep total struct u32-aligned */
455 #define UCODE_SIZE 134
456 struct cb {
457 u16 status;
458 u16 command;
459 u32 link;
460 union {
461 u8 iaaddr[ETH_ALEN];
462 u32 ucode[UCODE_SIZE];
463 struct config config;
464 struct multi multi;
465 struct {
466 u32 tbd_array;
467 u16 tcb_byte_count;
468 u8 threshold;
469 u8 tbd_count;
470 struct {
471 u32 buf_addr;
472 u16 size;
473 u16 eol;
474 } tbd;
475 } tcb;
476 u32 dump_buffer_addr;
477 } u;
478 struct cb *next, *prev;
479 dma_addr_t dma_addr;
480 struct sk_buff *skb;
481 };
482
483 enum loopback {
484 lb_none = 0, lb_mac = 1, lb_phy = 3,
485 };
486
487 struct stats {
488 u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
489 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
490 tx_multiple_collisions, tx_total_collisions;
491 u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
492 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
493 rx_short_frame_errors;
494 u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
495 u16 xmt_tco_frames, rcv_tco_frames;
496 u32 complete;
497 };
498
499 struct mem {
500 struct {
501 u32 signature;
502 u32 result;
503 } selftest;
504 struct stats stats;
505 u8 dump_buf[596];
506 };
507
508 struct param_range {
509 u32 min;
510 u32 max;
511 u32 count;
512 };
513
514 struct params {
515 struct param_range rfds;
516 struct param_range cbs;
517 };
518
519 struct nic {
520 /* Begin: frequently used values: keep adjacent for cache effect */
521 u32 msg_enable ____cacheline_aligned;
522 struct net_device *netdev;
523 struct pci_dev *pdev;
524
525 struct rx *rxs ____cacheline_aligned;
526 struct rx *rx_to_use;
527 struct rx *rx_to_clean;
528 struct rfd blank_rfd;
529 enum ru_state ru_running;
530
531 spinlock_t cb_lock ____cacheline_aligned;
532 spinlock_t cmd_lock;
533 struct csr __iomem *csr;
534 enum scb_cmd_lo cuc_cmd;
535 unsigned int cbs_avail;
536 struct cb *cbs;
537 struct cb *cb_to_use;
538 struct cb *cb_to_send;
539 struct cb *cb_to_clean;
540 u16 tx_command;
541 /* End: frequently used values: keep adjacent for cache effect */
542
543 enum {
544 ich = (1 << 0),
545 promiscuous = (1 << 1),
546 multicast_all = (1 << 2),
547 wol_magic = (1 << 3),
548 ich_10h_workaround = (1 << 4),
549 } flags ____cacheline_aligned;
550
551 enum mac mac;
552 enum phy phy;
553 struct params params;
554 struct net_device_stats net_stats;
555 struct timer_list watchdog;
556 struct timer_list blink_timer;
557 struct mii_if_info mii;
558 struct work_struct tx_timeout_task;
559 enum loopback loopback;
560
561 struct mem *mem;
562 dma_addr_t dma_addr;
563
564 dma_addr_t cbs_dma_addr;
565 u8 adaptive_ifs;
566 u8 tx_threshold;
567 u32 tx_frames;
568 u32 tx_collisions;
569 u32 tx_deferred;
570 u32 tx_single_collisions;
571 u32 tx_multiple_collisions;
572 u32 tx_fc_pause;
573 u32 tx_tco_frames;
574
575 u32 rx_fc_pause;
576 u32 rx_fc_unsupported;
577 u32 rx_tco_frames;
578 u32 rx_over_length_errors;
579
580 u8 rev_id;
581 u16 leds;
582 u16 eeprom_wc;
583 u16 eeprom[256];
584 spinlock_t mdio_lock;
585 };
586
587 static inline void e100_write_flush(struct nic *nic)
588 {
589 /* Flush previous PCI writes through intermediate bridges
590 * by doing a benign read */
591 (void)readb(&nic->csr->scb.status);
592 }
593
594 static void e100_enable_irq(struct nic *nic)
595 {
596 unsigned long flags;
597
598 spin_lock_irqsave(&nic->cmd_lock, flags);
599 writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
600 e100_write_flush(nic);
601 spin_unlock_irqrestore(&nic->cmd_lock, flags);
602 }
603
604 static void e100_disable_irq(struct nic *nic)
605 {
606 unsigned long flags;
607
608 spin_lock_irqsave(&nic->cmd_lock, flags);
609 writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
610 e100_write_flush(nic);
611 spin_unlock_irqrestore(&nic->cmd_lock, flags);
612 }
613
614 static void e100_hw_reset(struct nic *nic)
615 {
616 /* Put CU and RU into idle with a selective reset to get
617 * device off of PCI bus */
618 writel(selective_reset, &nic->csr->port);
619 e100_write_flush(nic); udelay(20);
620
621 /* Now fully reset device */
622 writel(software_reset, &nic->csr->port);
623 e100_write_flush(nic); udelay(20);
624
625 /* Mask off our interrupt line - it's unmasked after reset */
626 e100_disable_irq(nic);
627 }
628
629 static int e100_self_test(struct nic *nic)
630 {
631 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
632
633 /* Passing the self-test is a pretty good indication
634 * that the device can DMA to/from host memory */
635
636 nic->mem->selftest.signature = 0;
637 nic->mem->selftest.result = 0xFFFFFFFF;
638
639 writel(selftest | dma_addr, &nic->csr->port);
640 e100_write_flush(nic);
641 /* Wait 10 msec for self-test to complete */
642 msleep(10);
643
644 /* Interrupts are enabled after self-test */
645 e100_disable_irq(nic);
646
647 /* Check results of self-test */
648 if(nic->mem->selftest.result != 0) {
649 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
650 nic->mem->selftest.result);
651 return -ETIMEDOUT;
652 }
653 if(nic->mem->selftest.signature == 0) {
654 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
655 return -ETIMEDOUT;
656 }
657
658 return 0;
659 }
660
661 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
662 {
663 u32 cmd_addr_data[3];
664 u8 ctrl;
665 int i, j;
666
667 /* Three cmds: write/erase enable, write data, write/erase disable */
668 cmd_addr_data[0] = op_ewen << (addr_len - 2);
669 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
670 cpu_to_le16(data);
671 cmd_addr_data[2] = op_ewds << (addr_len - 2);
672
673 /* Bit-bang cmds to write word to eeprom */
674 for(j = 0; j < 3; j++) {
675
676 /* Chip select */
677 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
678 e100_write_flush(nic); udelay(4);
679
680 for(i = 31; i >= 0; i--) {
681 ctrl = (cmd_addr_data[j] & (1 << i)) ?
682 eecs | eedi : eecs;
683 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
684 e100_write_flush(nic); udelay(4);
685
686 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
687 e100_write_flush(nic); udelay(4);
688 }
689 /* Wait 10 msec for cmd to complete */
690 msleep(10);
691
692 /* Chip deselect */
693 writeb(0, &nic->csr->eeprom_ctrl_lo);
694 e100_write_flush(nic); udelay(4);
695 }
696 };
697
698 /* General technique stolen from the eepro100 driver - very clever */
699 static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
700 {
701 u32 cmd_addr_data;
702 u16 data = 0;
703 u8 ctrl;
704 int i;
705
706 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
707
708 /* Chip select */
709 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
710 e100_write_flush(nic); udelay(4);
711
712 /* Bit-bang to read word from eeprom */
713 for(i = 31; i >= 0; i--) {
714 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
715 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
716 e100_write_flush(nic); udelay(4);
717
718 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
719 e100_write_flush(nic); udelay(4);
720
721 /* Eeprom drives a dummy zero to EEDO after receiving
722 * complete address. Use this to adjust addr_len. */
723 ctrl = readb(&nic->csr->eeprom_ctrl_lo);
724 if(!(ctrl & eedo) && i > 16) {
725 *addr_len -= (i - 16);
726 i = 17;
727 }
728
729 data = (data << 1) | (ctrl & eedo ? 1 : 0);
730 }
731
732 /* Chip deselect */
733 writeb(0, &nic->csr->eeprom_ctrl_lo);
734 e100_write_flush(nic); udelay(4);
735
736 return le16_to_cpu(data);
737 };
738
739 /* Load entire EEPROM image into driver cache and validate checksum */
740 static int e100_eeprom_load(struct nic *nic)
741 {
742 u16 addr, addr_len = 8, checksum = 0;
743
744 /* Try reading with an 8-bit addr len to discover actual addr len */
745 e100_eeprom_read(nic, &addr_len, 0);
746 nic->eeprom_wc = 1 << addr_len;
747
748 for(addr = 0; addr < nic->eeprom_wc; addr++) {
749 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
750 if(addr < nic->eeprom_wc - 1)
751 checksum += cpu_to_le16(nic->eeprom[addr]);
752 }
753
754 /* The checksum, stored in the last word, is calculated such that
755 * the sum of words should be 0xBABA */
756 checksum = le16_to_cpu(0xBABA - checksum);
757 if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
758 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
759 return -EAGAIN;
760 }
761
762 return 0;
763 }
764
765 /* Save (portion of) driver EEPROM cache to device and update checksum */
766 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
767 {
768 u16 addr, addr_len = 8, checksum = 0;
769
770 /* Try reading with an 8-bit addr len to discover actual addr len */
771 e100_eeprom_read(nic, &addr_len, 0);
772 nic->eeprom_wc = 1 << addr_len;
773
774 if(start + count >= nic->eeprom_wc)
775 return -EINVAL;
776
777 for(addr = start; addr < start + count; addr++)
778 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
779
780 /* The checksum, stored in the last word, is calculated such that
781 * the sum of words should be 0xBABA */
782 for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
783 checksum += cpu_to_le16(nic->eeprom[addr]);
784 nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);
785 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
786 nic->eeprom[nic->eeprom_wc - 1]);
787
788 return 0;
789 }
790
791 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
792 #define E100_WAIT_SCB_FAST 20 /* delay like the old code */
793 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
794 {
795 unsigned long flags;
796 unsigned int i;
797 int err = 0;
798
799 spin_lock_irqsave(&nic->cmd_lock, flags);
800
801 /* Previous command is accepted when SCB clears */
802 for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
803 if(likely(!readb(&nic->csr->scb.cmd_lo)))
804 break;
805 cpu_relax();
806 if(unlikely(i > E100_WAIT_SCB_FAST))
807 udelay(5);
808 }
809 if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
810 err = -EAGAIN;
811 goto err_unlock;
812 }
813
814 if(unlikely(cmd != cuc_resume))
815 writel(dma_addr, &nic->csr->scb.gen_ptr);
816 writeb(cmd, &nic->csr->scb.cmd_lo);
817
818 err_unlock:
819 spin_unlock_irqrestore(&nic->cmd_lock, flags);
820
821 return err;
822 }
823
824 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
825 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
826 {
827 struct cb *cb;
828 unsigned long flags;
829 int err = 0;
830
831 spin_lock_irqsave(&nic->cb_lock, flags);
832
833 if(unlikely(!nic->cbs_avail)) {
834 err = -ENOMEM;
835 goto err_unlock;
836 }
837
838 cb = nic->cb_to_use;
839 nic->cb_to_use = cb->next;
840 nic->cbs_avail--;
841 cb->skb = skb;
842
843 if(unlikely(!nic->cbs_avail))
844 err = -ENOSPC;
845
846 cb_prepare(nic, cb, skb);
847
848 /* Order is important otherwise we'll be in a race with h/w:
849 * set S-bit in current first, then clear S-bit in previous. */
850 cb->command |= cpu_to_le16(cb_s);
851 wmb();
852 cb->prev->command &= cpu_to_le16(~cb_s);
853
854 while(nic->cb_to_send != nic->cb_to_use) {
855 if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
856 nic->cb_to_send->dma_addr))) {
857 /* Ok, here's where things get sticky. It's
858 * possible that we can't schedule the command
859 * because the controller is too busy, so
860 * let's just queue the command and try again
861 * when another command is scheduled. */
862 if(err == -ENOSPC) {
863 //request a reset
864 schedule_work(&nic->tx_timeout_task);
865 }
866 break;
867 } else {
868 nic->cuc_cmd = cuc_resume;
869 nic->cb_to_send = nic->cb_to_send->next;
870 }
871 }
872
873 err_unlock:
874 spin_unlock_irqrestore(&nic->cb_lock, flags);
875
876 return err;
877 }
878
879 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
880 {
881 u32 data_out = 0;
882 unsigned int i;
883 unsigned long flags;
884
885
886 /*
887 * Stratus87247: we shouldn't be writing the MDI control
888 * register until the Ready bit shows True. Also, since
889 * manipulation of the MDI control registers is a multi-step
890 * procedure it should be done under lock.
891 */
892 spin_lock_irqsave(&nic->mdio_lock, flags);
893 for (i = 100; i; --i) {
894 if (readl(&nic->csr->mdi_ctrl) & mdi_ready)
895 break;
896 udelay(20);
897 }
898 if (unlikely(!i)) {
899 printk("e100.mdio_ctrl(%s) won't go Ready\n",
900 nic->netdev->name );
901 spin_unlock_irqrestore(&nic->mdio_lock, flags);
902 return 0; /* No way to indicate timeout error */
903 }
904 writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
905
906 for (i = 0; i < 100; i++) {
907 udelay(20);
908 if ((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)
909 break;
910 }
911 spin_unlock_irqrestore(&nic->mdio_lock, flags);
912 DPRINTK(HW, DEBUG,
913 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
914 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
915 return (u16)data_out;
916 }
917
918 static int mdio_read(struct net_device *netdev, int addr, int reg)
919 {
920 return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);
921 }
922
923 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
924 {
925 mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);
926 }
927
928 static void e100_get_defaults(struct nic *nic)
929 {
930 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
931 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
932
933 pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
934 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
935 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
936 if(nic->mac == mac_unknown)
937 nic->mac = mac_82557_D100_A;
938
939 nic->params.rfds = rfds;
940 nic->params.cbs = cbs;
941
942 /* Quadwords to DMA into FIFO before starting frame transmit */
943 nic->tx_threshold = 0xE0;
944
945 /* no interrupt for every tx completion, delay = 256us if not 557*/
946 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
947 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
948
949 /* Template for a freshly allocated RFD */
950 nic->blank_rfd.command = cpu_to_le16(cb_el);
951 nic->blank_rfd.rbd = 0xFFFFFFFF;
952 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
953
954 /* MII setup */
955 nic->mii.phy_id_mask = 0x1F;
956 nic->mii.reg_num_mask = 0x1F;
957 nic->mii.dev = nic->netdev;
958 nic->mii.mdio_read = mdio_read;
959 nic->mii.mdio_write = mdio_write;
960 }
961
962 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
963 {
964 struct config *config = &cb->u.config;
965 u8 *c = (u8 *)config;
966
967 cb->command = cpu_to_le16(cb_config);
968
969 memset(config, 0, sizeof(struct config));
970
971 config->byte_count = 0x16; /* bytes in this struct */
972 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
973 config->direct_rx_dma = 0x1; /* reserved */
974 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
975 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
976 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
977 config->tx_underrun_retry = 0x3; /* # of underrun retries */
978 config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
979 config->pad10 = 0x6;
980 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
981 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
982 config->ifs = 0x6; /* x16 = inter frame spacing */
983 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
984 config->pad15_1 = 0x1;
985 config->pad15_2 = 0x1;
986 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
987 config->fc_delay_hi = 0x40; /* time delay for fc frame */
988 config->tx_padding = 0x1; /* 1=pad short frames */
989 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
990 config->pad18 = 0x1;
991 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
992 config->pad20_1 = 0x1F;
993 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
994 config->pad21_1 = 0x5;
995
996 config->adaptive_ifs = nic->adaptive_ifs;
997 config->loopback = nic->loopback;
998
999 if(nic->mii.force_media && nic->mii.full_duplex)
1000 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1001
1002 if(nic->flags & promiscuous || nic->loopback) {
1003 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1004 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1005 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1006 }
1007
1008 if(nic->flags & multicast_all)
1009 config->multicast_all = 0x1; /* 1=accept, 0=no */
1010
1011 /* disable WoL when up */
1012 if(netif_running(nic->netdev) || !(nic->flags & wol_magic))
1013 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1014
1015 if(nic->mac >= mac_82558_D101_A4) {
1016 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1017 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1018 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1019 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1020 if(nic->mac >= mac_82559_D101M)
1021 config->tno_intr = 0x1; /* TCO stats enable */
1022 else
1023 config->standard_stat_counter = 0x0;
1024 }
1025
1026 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1027 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1028 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1029 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1030 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1031 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1032 }
1033
1034 /********************************************************/
1035 /* Micro code for 8086:1229 Rev 8 */
1036 /********************************************************/
1037
1038 /* Parameter values for the D101M B-step */
1039 #define D101M_CPUSAVER_TIMER_DWORD 78
1040 #define D101M_CPUSAVER_BUNDLE_DWORD 65
1041 #define D101M_CPUSAVER_MIN_SIZE_DWORD 126
1042
1043 #define D101M_B_RCVBUNDLE_UCODE \
1044 {\
1045 0x00550215, 0xFFFF0437, 0xFFFFFFFF, 0x06A70789, 0xFFFFFFFF, 0x0558FFFF, \
1046 0x000C0001, 0x00101312, 0x000C0008, 0x00380216, \
1047 0x0010009C, 0x00204056, 0x002380CC, 0x00380056, \
1048 0x0010009C, 0x00244C0B, 0x00000800, 0x00124818, \
1049 0x00380438, 0x00000000, 0x00140000, 0x00380555, \
1050 0x00308000, 0x00100662, 0x00100561, 0x000E0408, \
1051 0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
1052 0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
1053 0x000C007E, 0x00222C21, 0x000C0002, 0x00103093, \
1054 0x00380C7A, 0x00080000, 0x00103090, 0x00380C7A, \
1055 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1056 0x0010009C, 0x00244C2D, 0x00010004, 0x00041000, \
1057 0x003A0437, 0x00044010, 0x0038078A, 0x00000000, \
1058 0x00100099, 0x00206C7A, 0x0010009C, 0x00244C48, \
1059 0x00130824, 0x000C0001, 0x00101213, 0x00260C75, \
1060 0x00041000, 0x00010004, 0x00130826, 0x000C0006, \
1061 0x002206A8, 0x0013C926, 0x00101313, 0x003806A8, \
1062 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1063 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1064 0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
1065 0x00101210, 0x00380C34, 0x00000000, 0x00000000, \
1066 0x0021155B, 0x00100099, 0x00206559, 0x0010009C, \
1067 0x00244559, 0x00130836, 0x000C0000, 0x00220C62, \
1068 0x000C0001, 0x00101B13, 0x00229C0E, 0x00210C0E, \
1069 0x00226C0E, 0x00216C0E, 0x0022FC0E, 0x00215C0E, \
1070 0x00214C0E, 0x00380555, 0x00010004, 0x00041000, \
1071 0x00278C67, 0x00040800, 0x00018100, 0x003A0437, \
1072 0x00130826, 0x000C0001, 0x00220559, 0x00101313, \
1073 0x00380559, 0x00000000, 0x00000000, 0x00000000, \
1074 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1075 0x00000000, 0x00130831, 0x0010090B, 0x00124813, \
1076 0x000CFF80, 0x002606AB, 0x00041000, 0x00010004, \
1077 0x003806A8, 0x00000000, 0x00000000, 0x00000000, \
1078 }
1079
1080 /********************************************************/
1081 /* Micro code for 8086:1229 Rev 9 */
1082 /********************************************************/
1083
1084 /* Parameter values for the D101S */
1085 #define D101S_CPUSAVER_TIMER_DWORD 78
1086 #define D101S_CPUSAVER_BUNDLE_DWORD 67
1087 #define D101S_CPUSAVER_MIN_SIZE_DWORD 128
1088
1089 #define D101S_RCVBUNDLE_UCODE \
1090 {\
1091 0x00550242, 0xFFFF047E, 0xFFFFFFFF, 0x06FF0818, 0xFFFFFFFF, 0x05A6FFFF, \
1092 0x000C0001, 0x00101312, 0x000C0008, 0x00380243, \
1093 0x0010009C, 0x00204056, 0x002380D0, 0x00380056, \
1094 0x0010009C, 0x00244F8B, 0x00000800, 0x00124818, \
1095 0x0038047F, 0x00000000, 0x00140000, 0x003805A3, \
1096 0x00308000, 0x00100610, 0x00100561, 0x000E0408, \
1097 0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
1098 0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
1099 0x000C007E, 0x00222FA1, 0x000C0002, 0x00103093, \
1100 0x00380F90, 0x00080000, 0x00103090, 0x00380F90, \
1101 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1102 0x0010009C, 0x00244FAD, 0x00010004, 0x00041000, \
1103 0x003A047E, 0x00044010, 0x00380819, 0x00000000, \
1104 0x00100099, 0x00206FFD, 0x0010009A, 0x0020AFFD, \
1105 0x0010009C, 0x00244FC8, 0x00130824, 0x000C0001, \
1106 0x00101213, 0x00260FF7, 0x00041000, 0x00010004, \
1107 0x00130826, 0x000C0006, 0x00220700, 0x0013C926, \
1108 0x00101313, 0x00380700, 0x00000000, 0x00000000, \
1109 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1110 0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
1111 0x00101210, 0x00380FB6, 0x00000000, 0x00000000, \
1112 0x002115A9, 0x00100099, 0x002065A7, 0x0010009A, \
1113 0x0020A5A7, 0x0010009C, 0x002445A7, 0x00130836, \
1114 0x000C0000, 0x00220FE4, 0x000C0001, 0x00101B13, \
1115 0x00229F8E, 0x00210F8E, 0x00226F8E, 0x00216F8E, \
1116 0x0022FF8E, 0x00215F8E, 0x00214F8E, 0x003805A3, \
1117 0x00010004, 0x00041000, 0x00278FE9, 0x00040800, \
1118 0x00018100, 0x003A047E, 0x00130826, 0x000C0001, \
1119 0x002205A7, 0x00101313, 0x003805A7, 0x00000000, \
1120 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1121 0x00000000, 0x00000000, 0x00000000, 0x00130831, \
1122 0x0010090B, 0x00124813, 0x000CFF80, 0x00260703, \
1123 0x00041000, 0x00010004, 0x00380700 \
1124 }
1125
1126 /********************************************************/
1127 /* Micro code for the 8086:1229 Rev F/10 */
1128 /********************************************************/
1129
1130 /* Parameter values for the D102 E-step */
1131 #define D102_E_CPUSAVER_TIMER_DWORD 42
1132 #define D102_E_CPUSAVER_BUNDLE_DWORD 54
1133 #define D102_E_CPUSAVER_MIN_SIZE_DWORD 46
1134
1135 #define D102_E_RCVBUNDLE_UCODE \
1136 {\
1137 0x007D028F, 0x0E4204F9, 0x14ED0C85, 0x14FA14E9, 0x0EF70E36, 0x1FFF1FFF, \
1138 0x00E014B9, 0x00000000, 0x00000000, 0x00000000, \
1139 0x00E014BD, 0x00000000, 0x00000000, 0x00000000, \
1140 0x00E014D5, 0x00000000, 0x00000000, 0x00000000, \
1141 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1142 0x00E014C1, 0x00000000, 0x00000000, 0x00000000, \
1143 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1144 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1145 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1146 0x00E014C8, 0x00000000, 0x00000000, 0x00000000, \
1147 0x00200600, 0x00E014EE, 0x00000000, 0x00000000, \
1148 0x0030FF80, 0x00940E46, 0x00038200, 0x00102000, \
1149 0x00E00E43, 0x00000000, 0x00000000, 0x00000000, \
1150 0x00300006, 0x00E014FB, 0x00000000, 0x00000000, \
1151 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1152 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1153 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1154 0x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000, \
1155 0x00906EFD, 0x00900EFD, 0x00E00EF8, 0x00000000, \
1156 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1157 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1158 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1159 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1160 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1161 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1162 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1163 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1164 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1165 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1166 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1167 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1168 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1169 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1170 }
1171
1172 static void e100_setup_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1173 {
1174 /* *INDENT-OFF* */
1175 static struct {
1176 u32 ucode[UCODE_SIZE + 1];
1177 u8 mac;
1178 u8 timer_dword;
1179 u8 bundle_dword;
1180 u8 min_size_dword;
1181 } ucode_opts[] = {
1182 { D101M_B_RCVBUNDLE_UCODE,
1183 mac_82559_D101M,
1184 D101M_CPUSAVER_TIMER_DWORD,
1185 D101M_CPUSAVER_BUNDLE_DWORD,
1186 D101M_CPUSAVER_MIN_SIZE_DWORD },
1187 { D101S_RCVBUNDLE_UCODE,
1188 mac_82559_D101S,
1189 D101S_CPUSAVER_TIMER_DWORD,
1190 D101S_CPUSAVER_BUNDLE_DWORD,
1191 D101S_CPUSAVER_MIN_SIZE_DWORD },
1192 { D102_E_RCVBUNDLE_UCODE,
1193 mac_82551_F,
1194 D102_E_CPUSAVER_TIMER_DWORD,
1195 D102_E_CPUSAVER_BUNDLE_DWORD,
1196 D102_E_CPUSAVER_MIN_SIZE_DWORD },
1197 { D102_E_RCVBUNDLE_UCODE,
1198 mac_82551_10,
1199 D102_E_CPUSAVER_TIMER_DWORD,
1200 D102_E_CPUSAVER_BUNDLE_DWORD,
1201 D102_E_CPUSAVER_MIN_SIZE_DWORD },
1202 { {0}, 0, 0, 0, 0}
1203 }, *opts;
1204 /* *INDENT-ON* */
1205
1206 /*************************************************************************
1207 * CPUSaver parameters
1208 *
1209 * All CPUSaver parameters are 16-bit literals that are part of a
1210 * "move immediate value" instruction. By changing the value of
1211 * the literal in the instruction before the code is loaded, the
1212 * driver can change the algorithm.
1213 *
1214 * INTDELAY - This loads the dead-man timer with its inital value.
1215 * When this timer expires the interrupt is asserted, and the
1216 * timer is reset each time a new packet is received. (see
1217 * BUNDLEMAX below to set the limit on number of chained packets)
1218 * The current default is 0x600 or 1536. Experiments show that
1219 * the value should probably stay within the 0x200 - 0x1000.
1220 *
1221 * BUNDLEMAX -
1222 * This sets the maximum number of frames that will be bundled. In
1223 * some situations, such as the TCP windowing algorithm, it may be
1224 * better to limit the growth of the bundle size than let it go as
1225 * high as it can, because that could cause too much added latency.
1226 * The default is six, because this is the number of packets in the
1227 * default TCP window size. A value of 1 would make CPUSaver indicate
1228 * an interrupt for every frame received. If you do not want to put
1229 * a limit on the bundle size, set this value to xFFFF.
1230 *
1231 * BUNDLESMALL -
1232 * This contains a bit-mask describing the minimum size frame that
1233 * will be bundled. The default masks the lower 7 bits, which means
1234 * that any frame less than 128 bytes in length will not be bundled,
1235 * but will instead immediately generate an interrupt. This does
1236 * not affect the current bundle in any way. Any frame that is 128
1237 * bytes or large will be bundled normally. This feature is meant
1238 * to provide immediate indication of ACK frames in a TCP environment.
1239 * Customers were seeing poor performance when a machine with CPUSaver
1240 * enabled was sending but not receiving. The delay introduced when
1241 * the ACKs were received was enough to reduce total throughput, because
1242 * the sender would sit idle until the ACK was finally seen.
1243 *
1244 * The current default is 0xFF80, which masks out the lower 7 bits.
1245 * This means that any frame which is x7F (127) bytes or smaller
1246 * will cause an immediate interrupt. Because this value must be a
1247 * bit mask, there are only a few valid values that can be used. To
1248 * turn this feature off, the driver can write the value xFFFF to the
1249 * lower word of this instruction (in the same way that the other
1250 * parameters are used). Likewise, a value of 0xF800 (2047) would
1251 * cause an interrupt to be generated for every frame, because all
1252 * standard Ethernet frames are <= 2047 bytes in length.
1253 *************************************************************************/
1254
1255 /* if you wish to disable the ucode functionality, while maintaining the
1256 * workarounds it provides, set the following defines to:
1257 * BUNDLESMALL 0
1258 * BUNDLEMAX 1
1259 * INTDELAY 1
1260 */
1261 #define BUNDLESMALL 1
1262 #define BUNDLEMAX (u16)6
1263 #define INTDELAY (u16)1536 /* 0x600 */
1264
1265 /* do not load u-code for ICH devices */
1266 if (nic->flags & ich)
1267 goto noloaducode;
1268
1269 /* Search for ucode match against h/w rev_id */
1270 for (opts = ucode_opts; opts->mac; opts++) {
1271 int i;
1272 u32 *ucode = opts->ucode;
1273 if (nic->mac != opts->mac)
1274 continue;
1275
1276 /* Insert user-tunable settings */
1277 ucode[opts->timer_dword] &= 0xFFFF0000;
1278 ucode[opts->timer_dword] |= INTDELAY;
1279 ucode[opts->bundle_dword] &= 0xFFFF0000;
1280 ucode[opts->bundle_dword] |= BUNDLEMAX;
1281 ucode[opts->min_size_dword] &= 0xFFFF0000;
1282 ucode[opts->min_size_dword] |= (BUNDLESMALL) ? 0xFFFF : 0xFF80;
1283
1284 for (i = 0; i < UCODE_SIZE; i++)
1285 cb->u.ucode[i] = cpu_to_le32(ucode[i]);
1286 cb->command = cpu_to_le16(cb_ucode | cb_el);
1287 return;
1288 }
1289
1290 noloaducode:
1291 cb->command = cpu_to_le16(cb_nop | cb_el);
1292 }
1293
1294 static inline int e100_exec_cb_wait(struct nic *nic, struct sk_buff *skb,
1295 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
1296 {
1297 int err = 0, counter = 50;
1298 struct cb *cb = nic->cb_to_clean;
1299
1300 if ((err = e100_exec_cb(nic, NULL, e100_setup_ucode)))
1301 DPRINTK(PROBE,ERR, "ucode cmd failed with error %d\n", err);
1302
1303 /* must restart cuc */
1304 nic->cuc_cmd = cuc_start;
1305
1306 /* wait for completion */
1307 e100_write_flush(nic);
1308 udelay(10);
1309
1310 /* wait for possibly (ouch) 500ms */
1311 while (!(cb->status & cpu_to_le16(cb_complete))) {
1312 msleep(10);
1313 if (!--counter) break;
1314 }
1315
1316 /* ack any interupts, something could have been set */
1317 writeb(~0, &nic->csr->scb.stat_ack);
1318
1319 /* if the command failed, or is not OK, notify and return */
1320 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1321 DPRINTK(PROBE,ERR, "ucode load failed\n");
1322 err = -EPERM;
1323 }
1324
1325 return err;
1326 }
1327
1328 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1329 struct sk_buff *skb)
1330 {
1331 cb->command = cpu_to_le16(cb_iaaddr);
1332 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1333 }
1334
1335 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1336 {
1337 cb->command = cpu_to_le16(cb_dump);
1338 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1339 offsetof(struct mem, dump_buf));
1340 }
1341
1342 #define NCONFIG_AUTO_SWITCH 0x0080
1343 #define MII_NSC_CONG MII_RESV1
1344 #define NSC_CONG_ENABLE 0x0100
1345 #define NSC_CONG_TXREADY 0x0400
1346 #define ADVERTISE_FC_SUPPORTED 0x0400
1347 static int e100_phy_init(struct nic *nic)
1348 {
1349 struct net_device *netdev = nic->netdev;
1350 u32 addr;
1351 u16 bmcr, stat, id_lo, id_hi, cong;
1352
1353 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1354 for(addr = 0; addr < 32; addr++) {
1355 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1356 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1357 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1358 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1359 if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1360 break;
1361 }
1362 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1363 if(addr == 32)
1364 return -EAGAIN;
1365
1366 /* Selected the phy and isolate the rest */
1367 for(addr = 0; addr < 32; addr++) {
1368 if(addr != nic->mii.phy_id) {
1369 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1370 } else {
1371 bmcr = mdio_read(netdev, addr, MII_BMCR);
1372 mdio_write(netdev, addr, MII_BMCR,
1373 bmcr & ~BMCR_ISOLATE);
1374 }
1375 }
1376
1377 /* Get phy ID */
1378 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1379 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1380 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1381 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1382
1383 /* Handle National tx phys */
1384 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1385 if((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1386 /* Disable congestion control */
1387 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1388 cong |= NSC_CONG_TXREADY;
1389 cong &= ~NSC_CONG_ENABLE;
1390 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1391 }
1392
1393 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1394 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000))) {
1395 /* enable/disable MDI/MDI-X auto-switching.
1396 MDI/MDI-X auto-switching is disabled for 82551ER/QM chips */
1397 if((nic->mac == mac_82551_E) || (nic->mac == mac_82551_F) ||
1398 (nic->mac == mac_82551_10) || (nic->mii.force_media) ||
1399 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))
1400 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, 0);
1401 else
1402 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, NCONFIG_AUTO_SWITCH);
1403 }
1404
1405 return 0;
1406 }
1407
1408 static int e100_hw_init(struct nic *nic)
1409 {
1410 int err;
1411
1412 e100_hw_reset(nic);
1413
1414 DPRINTK(HW, ERR, "e100_hw_init\n");
1415 if(!in_interrupt() && (err = e100_self_test(nic)))
1416 return err;
1417
1418 if((err = e100_phy_init(nic)))
1419 return err;
1420 if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1421 return err;
1422 if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1423 return err;
1424 if ((err = e100_exec_cb_wait(nic, NULL, e100_setup_ucode)))
1425 return err;
1426 if((err = e100_exec_cb(nic, NULL, e100_configure)))
1427 return err;
1428 if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1429 return err;
1430 if((err = e100_exec_cmd(nic, cuc_dump_addr,
1431 nic->dma_addr + offsetof(struct mem, stats))))
1432 return err;
1433 if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1434 return err;
1435
1436 e100_disable_irq(nic);
1437
1438 return 0;
1439 }
1440
1441 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1442 {
1443 struct net_device *netdev = nic->netdev;
1444 struct dev_mc_list *list = netdev->mc_list;
1445 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1446
1447 cb->command = cpu_to_le16(cb_multi);
1448 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1449 for(i = 0; list && i < count; i++, list = list->next)
1450 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1451 ETH_ALEN);
1452 }
1453
1454 static void e100_set_multicast_list(struct net_device *netdev)
1455 {
1456 struct nic *nic = netdev_priv(netdev);
1457
1458 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1459 netdev->mc_count, netdev->flags);
1460
1461 if(netdev->flags & IFF_PROMISC)
1462 nic->flags |= promiscuous;
1463 else
1464 nic->flags &= ~promiscuous;
1465
1466 if(netdev->flags & IFF_ALLMULTI ||
1467 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1468 nic->flags |= multicast_all;
1469 else
1470 nic->flags &= ~multicast_all;
1471
1472 e100_exec_cb(nic, NULL, e100_configure);
1473 e100_exec_cb(nic, NULL, e100_multi);
1474 }
1475
1476 static void e100_update_stats(struct nic *nic)
1477 {
1478 struct net_device_stats *ns = &nic->net_stats;
1479 struct stats *s = &nic->mem->stats;
1480 u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1481 (nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
1482 &s->complete;
1483
1484 /* Device's stats reporting may take several microseconds to
1485 * complete, so where always waiting for results of the
1486 * previous command. */
1487
1488 if(*complete == le32_to_cpu(cuc_dump_reset_complete)) {
1489 *complete = 0;
1490 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1491 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1492 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1493 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1494 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1495 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1496 ns->collisions += nic->tx_collisions;
1497 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1498 le32_to_cpu(s->tx_lost_crs);
1499 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1500 nic->rx_over_length_errors;
1501 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1502 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1503 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1504 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1505 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1506 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1507 le32_to_cpu(s->rx_alignment_errors) +
1508 le32_to_cpu(s->rx_short_frame_errors) +
1509 le32_to_cpu(s->rx_cdt_errors);
1510 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1511 nic->tx_single_collisions +=
1512 le32_to_cpu(s->tx_single_collisions);
1513 nic->tx_multiple_collisions +=
1514 le32_to_cpu(s->tx_multiple_collisions);
1515 if(nic->mac >= mac_82558_D101_A4) {
1516 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1517 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1518 nic->rx_fc_unsupported +=
1519 le32_to_cpu(s->fc_rcv_unsupported);
1520 if(nic->mac >= mac_82559_D101M) {
1521 nic->tx_tco_frames +=
1522 le16_to_cpu(s->xmt_tco_frames);
1523 nic->rx_tco_frames +=
1524 le16_to_cpu(s->rcv_tco_frames);
1525 }
1526 }
1527 }
1528
1529
1530 if(e100_exec_cmd(nic, cuc_dump_reset, 0))
1531 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1532 }
1533
1534 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1535 {
1536 /* Adjust inter-frame-spacing (IFS) between two transmits if
1537 * we're getting collisions on a half-duplex connection. */
1538
1539 if(duplex == DUPLEX_HALF) {
1540 u32 prev = nic->adaptive_ifs;
1541 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1542
1543 if((nic->tx_frames / 32 < nic->tx_collisions) &&
1544 (nic->tx_frames > min_frames)) {
1545 if(nic->adaptive_ifs < 60)
1546 nic->adaptive_ifs += 5;
1547 } else if (nic->tx_frames < min_frames) {
1548 if(nic->adaptive_ifs >= 5)
1549 nic->adaptive_ifs -= 5;
1550 }
1551 if(nic->adaptive_ifs != prev)
1552 e100_exec_cb(nic, NULL, e100_configure);
1553 }
1554 }
1555
1556 static void e100_watchdog(unsigned long data)
1557 {
1558 struct nic *nic = (struct nic *)data;
1559 struct ethtool_cmd cmd;
1560
1561 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1562
1563 /* mii library handles link maintenance tasks */
1564
1565 mii_ethtool_gset(&nic->mii, &cmd);
1566
1567 if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1568 DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
1569 cmd.speed == SPEED_100 ? "100" : "10",
1570 cmd.duplex == DUPLEX_FULL ? "full" : "half");
1571 } else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1572 DPRINTK(LINK, INFO, "link down\n");
1573 }
1574
1575 mii_check_link(&nic->mii);
1576
1577 /* Software generated interrupt to recover from (rare) Rx
1578 * allocation failure.
1579 * Unfortunately have to use a spinlock to not re-enable interrupts
1580 * accidentally, due to hardware that shares a register between the
1581 * interrupt mask bit and the SW Interrupt generation bit */
1582 spin_lock_irq(&nic->cmd_lock);
1583 writeb(readb(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1584 e100_write_flush(nic);
1585 spin_unlock_irq(&nic->cmd_lock);
1586
1587 e100_update_stats(nic);
1588 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1589
1590 if(nic->mac <= mac_82557_D100_C)
1591 /* Issue a multicast command to workaround a 557 lock up */
1592 e100_set_multicast_list(nic->netdev);
1593
1594 if(nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1595 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1596 nic->flags |= ich_10h_workaround;
1597 else
1598 nic->flags &= ~ich_10h_workaround;
1599
1600 mod_timer(&nic->watchdog, jiffies + E100_WATCHDOG_PERIOD);
1601 }
1602
1603 static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1604 struct sk_buff *skb)
1605 {
1606 cb->command = nic->tx_command;
1607 /* interrupt every 16 packets regardless of delay */
1608 if((nic->cbs_avail & ~15) == nic->cbs_avail)
1609 cb->command |= cpu_to_le16(cb_i);
1610 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1611 cb->u.tcb.tcb_byte_count = 0;
1612 cb->u.tcb.threshold = nic->tx_threshold;
1613 cb->u.tcb.tbd_count = 1;
1614 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1615 skb->data, skb->len, PCI_DMA_TODEVICE));
1616 /* check for mapping failure? */
1617 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1618 }
1619
1620 static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1621 {
1622 struct nic *nic = netdev_priv(netdev);
1623 int err;
1624
1625 if(nic->flags & ich_10h_workaround) {
1626 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1627 Issue a NOP command followed by a 1us delay before
1628 issuing the Tx command. */
1629 if(e100_exec_cmd(nic, cuc_nop, 0))
1630 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1631 udelay(1);
1632 }
1633
1634 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1635
1636 switch(err) {
1637 case -ENOSPC:
1638 /* We queued the skb, but now we're out of space. */
1639 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1640 netif_stop_queue(netdev);
1641 break;
1642 case -ENOMEM:
1643 /* This is a hard error - log it. */
1644 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1645 netif_stop_queue(netdev);
1646 return 1;
1647 }
1648
1649 netdev->trans_start = jiffies;
1650 return 0;
1651 }
1652
1653 static int e100_tx_clean(struct nic *nic)
1654 {
1655 struct cb *cb;
1656 int tx_cleaned = 0;
1657
1658 spin_lock(&nic->cb_lock);
1659
1660 DPRINTK(TX_DONE, DEBUG, "cb->status = 0x%04X\n",
1661 nic->cb_to_clean->status);
1662
1663 /* Clean CBs marked complete */
1664 for(cb = nic->cb_to_clean;
1665 cb->status & cpu_to_le16(cb_complete);
1666 cb = nic->cb_to_clean = cb->next) {
1667 if(likely(cb->skb != NULL)) {
1668 nic->net_stats.tx_packets++;
1669 nic->net_stats.tx_bytes += cb->skb->len;
1670
1671 pci_unmap_single(nic->pdev,
1672 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1673 le16_to_cpu(cb->u.tcb.tbd.size),
1674 PCI_DMA_TODEVICE);
1675 dev_kfree_skb_any(cb->skb);
1676 cb->skb = NULL;
1677 tx_cleaned = 1;
1678 }
1679 cb->status = 0;
1680 nic->cbs_avail++;
1681 }
1682
1683 spin_unlock(&nic->cb_lock);
1684
1685 /* Recover from running out of Tx resources in xmit_frame */
1686 if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1687 netif_wake_queue(nic->netdev);
1688
1689 return tx_cleaned;
1690 }
1691
1692 static void e100_clean_cbs(struct nic *nic)
1693 {
1694 if(nic->cbs) {
1695 while(nic->cbs_avail != nic->params.cbs.count) {
1696 struct cb *cb = nic->cb_to_clean;
1697 if(cb->skb) {
1698 pci_unmap_single(nic->pdev,
1699 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1700 le16_to_cpu(cb->u.tcb.tbd.size),
1701 PCI_DMA_TODEVICE);
1702 dev_kfree_skb(cb->skb);
1703 }
1704 nic->cb_to_clean = nic->cb_to_clean->next;
1705 nic->cbs_avail++;
1706 }
1707 pci_free_consistent(nic->pdev,
1708 sizeof(struct cb) * nic->params.cbs.count,
1709 nic->cbs, nic->cbs_dma_addr);
1710 nic->cbs = NULL;
1711 nic->cbs_avail = 0;
1712 }
1713 nic->cuc_cmd = cuc_start;
1714 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1715 nic->cbs;
1716 }
1717
1718 static int e100_alloc_cbs(struct nic *nic)
1719 {
1720 struct cb *cb;
1721 unsigned int i, count = nic->params.cbs.count;
1722
1723 nic->cuc_cmd = cuc_start;
1724 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1725 nic->cbs_avail = 0;
1726
1727 nic->cbs = pci_alloc_consistent(nic->pdev,
1728 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1729 if(!nic->cbs)
1730 return -ENOMEM;
1731
1732 for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
1733 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1734 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1735
1736 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1737 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1738 ((i+1) % count) * sizeof(struct cb));
1739 cb->skb = NULL;
1740 }
1741
1742 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1743 nic->cbs_avail = count;
1744
1745 return 0;
1746 }
1747
1748 static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1749 {
1750 if(!nic->rxs) return;
1751 if(RU_SUSPENDED != nic->ru_running) return;
1752
1753 /* handle init time starts */
1754 if(!rx) rx = nic->rxs;
1755
1756 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1757 if(rx->skb) {
1758 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1759 nic->ru_running = RU_RUNNING;
1760 }
1761 }
1762
1763 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1764 static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1765 {
1766 if(!(rx->skb = dev_alloc_skb(RFD_BUF_LEN + NET_IP_ALIGN)))
1767 return -ENOMEM;
1768
1769 /* Align, init, and map the RFD. */
1770 rx->skb->dev = nic->netdev;
1771 skb_reserve(rx->skb, NET_IP_ALIGN);
1772 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd));
1773 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1774 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1775
1776 if(pci_dma_mapping_error(rx->dma_addr)) {
1777 dev_kfree_skb_any(rx->skb);
1778 rx->skb = NULL;
1779 rx->dma_addr = 0;
1780 return -ENOMEM;
1781 }
1782
1783 /* Link the RFD to end of RFA by linking previous RFD to
1784 * this one, and clearing EL bit of previous. */
1785 if(rx->prev->skb) {
1786 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1787 put_unaligned(cpu_to_le32(rx->dma_addr),
1788 (u32 *)&prev_rfd->link);
1789 wmb();
1790 prev_rfd->command &= ~cpu_to_le16(cb_el);
1791 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1792 sizeof(struct rfd), PCI_DMA_TODEVICE);
1793 }
1794
1795 return 0;
1796 }
1797
1798 static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1799 unsigned int *work_done, unsigned int work_to_do)
1800 {
1801 struct sk_buff *skb = rx->skb;
1802 struct rfd *rfd = (struct rfd *)skb->data;
1803 u16 rfd_status, actual_size;
1804
1805 if(unlikely(work_done && *work_done >= work_to_do))
1806 return -EAGAIN;
1807
1808 /* Need to sync before taking a peek at cb_complete bit */
1809 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1810 sizeof(struct rfd), PCI_DMA_FROMDEVICE);
1811 rfd_status = le16_to_cpu(rfd->status);
1812
1813 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1814
1815 /* If data isn't ready, nothing to indicate */
1816 if(unlikely(!(rfd_status & cb_complete)))
1817 return -ENODATA;
1818
1819 /* Get actual data size */
1820 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1821 if(unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1822 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1823
1824 /* Get data */
1825 pci_unmap_single(nic->pdev, rx->dma_addr,
1826 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1827
1828 /* this allows for a fast restart without re-enabling interrupts */
1829 if(le16_to_cpu(rfd->command) & cb_el)
1830 nic->ru_running = RU_SUSPENDED;
1831
1832 /* Pull off the RFD and put the actual data (minus eth hdr) */
1833 skb_reserve(skb, sizeof(struct rfd));
1834 skb_put(skb, actual_size);
1835 skb->protocol = eth_type_trans(skb, nic->netdev);
1836
1837 if(unlikely(!(rfd_status & cb_ok))) {
1838 /* Don't indicate if hardware indicates errors */
1839 dev_kfree_skb_any(skb);
1840 } else if(actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1841 /* Don't indicate oversized frames */
1842 nic->rx_over_length_errors++;
1843 dev_kfree_skb_any(skb);
1844 } else {
1845 nic->net_stats.rx_packets++;
1846 nic->net_stats.rx_bytes += actual_size;
1847 nic->netdev->last_rx = jiffies;
1848 netif_receive_skb(skb);
1849 if(work_done)
1850 (*work_done)++;
1851 }
1852
1853 rx->skb = NULL;
1854
1855 return 0;
1856 }
1857
1858 static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1859 unsigned int work_to_do)
1860 {
1861 struct rx *rx;
1862 int restart_required = 0;
1863 struct rx *rx_to_start = NULL;
1864
1865 /* are we already rnr? then pay attention!!! this ensures that
1866 * the state machine progression never allows a start with a
1867 * partially cleaned list, avoiding a race between hardware
1868 * and rx_to_clean when in NAPI mode */
1869 if(RU_SUSPENDED == nic->ru_running)
1870 restart_required = 1;
1871
1872 /* Indicate newly arrived packets */
1873 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1874 int err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1875 if(-EAGAIN == err) {
1876 /* hit quota so have more work to do, restart once
1877 * cleanup is complete */
1878 restart_required = 0;
1879 break;
1880 } else if(-ENODATA == err)
1881 break; /* No more to clean */
1882 }
1883
1884 /* save our starting point as the place we'll restart the receiver */
1885 if(restart_required)
1886 rx_to_start = nic->rx_to_clean;
1887
1888 /* Alloc new skbs to refill list */
1889 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1890 if(unlikely(e100_rx_alloc_skb(nic, rx)))
1891 break; /* Better luck next time (see watchdog) */
1892 }
1893
1894 if(restart_required) {
1895 // ack the rnr?
1896 writeb(stat_ack_rnr, &nic->csr->scb.stat_ack);
1897 e100_start_receiver(nic, rx_to_start);
1898 if(work_done)
1899 (*work_done)++;
1900 }
1901 }
1902
1903 static void e100_rx_clean_list(struct nic *nic)
1904 {
1905 struct rx *rx;
1906 unsigned int i, count = nic->params.rfds.count;
1907
1908 nic->ru_running = RU_UNINITIALIZED;
1909
1910 if(nic->rxs) {
1911 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1912 if(rx->skb) {
1913 pci_unmap_single(nic->pdev, rx->dma_addr,
1914 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1915 dev_kfree_skb(rx->skb);
1916 }
1917 }
1918 kfree(nic->rxs);
1919 nic->rxs = NULL;
1920 }
1921
1922 nic->rx_to_use = nic->rx_to_clean = NULL;
1923 }
1924
1925 static int e100_rx_alloc_list(struct nic *nic)
1926 {
1927 struct rx *rx;
1928 unsigned int i, count = nic->params.rfds.count;
1929
1930 nic->rx_to_use = nic->rx_to_clean = NULL;
1931 nic->ru_running = RU_UNINITIALIZED;
1932
1933 if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC)))
1934 return -ENOMEM;
1935 memset(nic->rxs, 0, sizeof(struct rx) * count);
1936
1937 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1938 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
1939 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
1940 if(e100_rx_alloc_skb(nic, rx)) {
1941 e100_rx_clean_list(nic);
1942 return -ENOMEM;
1943 }
1944 }
1945
1946 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
1947 nic->ru_running = RU_SUSPENDED;
1948
1949 return 0;
1950 }
1951
1952 static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
1953 {
1954 struct net_device *netdev = dev_id;
1955 struct nic *nic = netdev_priv(netdev);
1956 u8 stat_ack = readb(&nic->csr->scb.stat_ack);
1957
1958 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
1959
1960 if(stat_ack == stat_ack_not_ours || /* Not our interrupt */
1961 stat_ack == stat_ack_not_present) /* Hardware is ejected */
1962 return IRQ_NONE;
1963
1964 /* Ack interrupt(s) */
1965 writeb(stat_ack, &nic->csr->scb.stat_ack);
1966
1967 /* We hit Receive No Resource (RNR); restart RU after cleaning */
1968 if(stat_ack & stat_ack_rnr)
1969 nic->ru_running = RU_SUSPENDED;
1970
1971 if(likely(netif_rx_schedule_prep(netdev))) {
1972 e100_disable_irq(nic);
1973 __netif_rx_schedule(netdev);
1974 }
1975
1976 return IRQ_HANDLED;
1977 }
1978
1979 static int e100_poll(struct net_device *netdev, int *budget)
1980 {
1981 struct nic *nic = netdev_priv(netdev);
1982 unsigned int work_to_do = min(netdev->quota, *budget);
1983 unsigned int work_done = 0;
1984 int tx_cleaned;
1985
1986 e100_rx_clean(nic, &work_done, work_to_do);
1987 tx_cleaned = e100_tx_clean(nic);
1988
1989 /* If no Rx and Tx cleanup work was done, exit polling mode. */
1990 if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
1991 netif_rx_complete(netdev);
1992 e100_enable_irq(nic);
1993 return 0;
1994 }
1995
1996 *budget -= work_done;
1997 netdev->quota -= work_done;
1998
1999 return 1;
2000 }
2001
2002 #ifdef CONFIG_NET_POLL_CONTROLLER
2003 static void e100_netpoll(struct net_device *netdev)
2004 {
2005 struct nic *nic = netdev_priv(netdev);
2006
2007 e100_disable_irq(nic);
2008 e100_intr(nic->pdev->irq, netdev, NULL);
2009 e100_tx_clean(nic);
2010 e100_enable_irq(nic);
2011 }
2012 #endif
2013
2014 static struct net_device_stats *e100_get_stats(struct net_device *netdev)
2015 {
2016 struct nic *nic = netdev_priv(netdev);
2017 return &nic->net_stats;
2018 }
2019
2020 static int e100_set_mac_address(struct net_device *netdev, void *p)
2021 {
2022 struct nic *nic = netdev_priv(netdev);
2023 struct sockaddr *addr = p;
2024
2025 if (!is_valid_ether_addr(addr->sa_data))
2026 return -EADDRNOTAVAIL;
2027
2028 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2029 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2030
2031 return 0;
2032 }
2033
2034 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2035 {
2036 if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
2037 return -EINVAL;
2038 netdev->mtu = new_mtu;
2039 return 0;
2040 }
2041
2042 #ifdef CONFIG_PM
2043 static int e100_asf(struct nic *nic)
2044 {
2045 /* ASF can be enabled from eeprom */
2046 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2047 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2048 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2049 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
2050 }
2051 #endif
2052
2053 static int e100_up(struct nic *nic)
2054 {
2055 int err;
2056
2057 if((err = e100_rx_alloc_list(nic)))
2058 return err;
2059 if((err = e100_alloc_cbs(nic)))
2060 goto err_rx_clean_list;
2061 if((err = e100_hw_init(nic)))
2062 goto err_clean_cbs;
2063 e100_set_multicast_list(nic->netdev);
2064 e100_start_receiver(nic, NULL);
2065 mod_timer(&nic->watchdog, jiffies);
2066 if((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2067 nic->netdev->name, nic->netdev)))
2068 goto err_no_irq;
2069 netif_wake_queue(nic->netdev);
2070 netif_poll_enable(nic->netdev);
2071 /* enable ints _after_ enabling poll, preventing a race between
2072 * disable ints+schedule */
2073 e100_enable_irq(nic);
2074 return 0;
2075
2076 err_no_irq:
2077 del_timer_sync(&nic->watchdog);
2078 err_clean_cbs:
2079 e100_clean_cbs(nic);
2080 err_rx_clean_list:
2081 e100_rx_clean_list(nic);
2082 return err;
2083 }
2084
2085 static void e100_down(struct nic *nic)
2086 {
2087 /* wait here for poll to complete */
2088 netif_poll_disable(nic->netdev);
2089 netif_stop_queue(nic->netdev);
2090 e100_hw_reset(nic);
2091 free_irq(nic->pdev->irq, nic->netdev);
2092 del_timer_sync(&nic->watchdog);
2093 netif_carrier_off(nic->netdev);
2094 e100_clean_cbs(nic);
2095 e100_rx_clean_list(nic);
2096 }
2097
2098 static void e100_tx_timeout(struct net_device *netdev)
2099 {
2100 struct nic *nic = netdev_priv(netdev);
2101
2102 /* Reset outside of interrupt context, to avoid request_irq
2103 * in interrupt context */
2104 schedule_work(&nic->tx_timeout_task);
2105 }
2106
2107 static void e100_tx_timeout_task(struct net_device *netdev)
2108 {
2109 struct nic *nic = netdev_priv(netdev);
2110
2111 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
2112 readb(&nic->csr->scb.status));
2113 e100_down(netdev_priv(netdev));
2114 e100_up(netdev_priv(netdev));
2115 }
2116
2117 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2118 {
2119 int err;
2120 struct sk_buff *skb;
2121
2122 /* Use driver resources to perform internal MAC or PHY
2123 * loopback test. A single packet is prepared and transmitted
2124 * in loopback mode, and the test passes if the received
2125 * packet compares byte-for-byte to the transmitted packet. */
2126
2127 if((err = e100_rx_alloc_list(nic)))
2128 return err;
2129 if((err = e100_alloc_cbs(nic)))
2130 goto err_clean_rx;
2131
2132 /* ICH PHY loopback is broken so do MAC loopback instead */
2133 if(nic->flags & ich && loopback_mode == lb_phy)
2134 loopback_mode = lb_mac;
2135
2136 nic->loopback = loopback_mode;
2137 if((err = e100_hw_init(nic)))
2138 goto err_loopback_none;
2139
2140 if(loopback_mode == lb_phy)
2141 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2142 BMCR_LOOPBACK);
2143
2144 e100_start_receiver(nic, NULL);
2145
2146 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
2147 err = -ENOMEM;
2148 goto err_loopback_none;
2149 }
2150 skb_put(skb, ETH_DATA_LEN);
2151 memset(skb->data, 0xFF, ETH_DATA_LEN);
2152 e100_xmit_frame(skb, nic->netdev);
2153
2154 msleep(10);
2155
2156 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2157 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
2158
2159 if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2160 skb->data, ETH_DATA_LEN))
2161 err = -EAGAIN;
2162
2163 err_loopback_none:
2164 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2165 nic->loopback = lb_none;
2166 e100_clean_cbs(nic);
2167 e100_hw_reset(nic);
2168 err_clean_rx:
2169 e100_rx_clean_list(nic);
2170 return err;
2171 }
2172
2173 #define MII_LED_CONTROL 0x1B
2174 static void e100_blink_led(unsigned long data)
2175 {
2176 struct nic *nic = (struct nic *)data;
2177 enum led_state {
2178 led_on = 0x01,
2179 led_off = 0x04,
2180 led_on_559 = 0x05,
2181 led_on_557 = 0x07,
2182 };
2183
2184 nic->leds = (nic->leds & led_on) ? led_off :
2185 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
2186 mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
2187 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2188 }
2189
2190 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2191 {
2192 struct nic *nic = netdev_priv(netdev);
2193 return mii_ethtool_gset(&nic->mii, cmd);
2194 }
2195
2196 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2197 {
2198 struct nic *nic = netdev_priv(netdev);
2199 int err;
2200
2201 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2202 err = mii_ethtool_sset(&nic->mii, cmd);
2203 e100_exec_cb(nic, NULL, e100_configure);
2204
2205 return err;
2206 }
2207
2208 static void e100_get_drvinfo(struct net_device *netdev,
2209 struct ethtool_drvinfo *info)
2210 {
2211 struct nic *nic = netdev_priv(netdev);
2212 strcpy(info->driver, DRV_NAME);
2213 strcpy(info->version, DRV_VERSION);
2214 strcpy(info->fw_version, "N/A");
2215 strcpy(info->bus_info, pci_name(nic->pdev));
2216 }
2217
2218 static int e100_get_regs_len(struct net_device *netdev)
2219 {
2220 struct nic *nic = netdev_priv(netdev);
2221 #define E100_PHY_REGS 0x1C
2222 #define E100_REGS_LEN 1 + E100_PHY_REGS + \
2223 sizeof(nic->mem->dump_buf) / sizeof(u32)
2224 return E100_REGS_LEN * sizeof(u32);
2225 }
2226
2227 static void e100_get_regs(struct net_device *netdev,
2228 struct ethtool_regs *regs, void *p)
2229 {
2230 struct nic *nic = netdev_priv(netdev);
2231 u32 *buff = p;
2232 int i;
2233
2234 regs->version = (1 << 24) | nic->rev_id;
2235 buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 |
2236 readb(&nic->csr->scb.cmd_lo) << 16 |
2237 readw(&nic->csr->scb.status);
2238 for(i = E100_PHY_REGS; i >= 0; i--)
2239 buff[1 + E100_PHY_REGS - i] =
2240 mdio_read(netdev, nic->mii.phy_id, i);
2241 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2242 e100_exec_cb(nic, NULL, e100_dump);
2243 msleep(10);
2244 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2245 sizeof(nic->mem->dump_buf));
2246 }
2247
2248 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2249 {
2250 struct nic *nic = netdev_priv(netdev);
2251 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2252 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2253 }
2254
2255 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2256 {
2257 struct nic *nic = netdev_priv(netdev);
2258
2259 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2260 return -EOPNOTSUPP;
2261
2262 if(wol->wolopts)
2263 nic->flags |= wol_magic;
2264 else
2265 nic->flags &= ~wol_magic;
2266
2267 e100_exec_cb(nic, NULL, e100_configure);
2268
2269 return 0;
2270 }
2271
2272 static u32 e100_get_msglevel(struct net_device *netdev)
2273 {
2274 struct nic *nic = netdev_priv(netdev);
2275 return nic->msg_enable;
2276 }
2277
2278 static void e100_set_msglevel(struct net_device *netdev, u32 value)
2279 {
2280 struct nic *nic = netdev_priv(netdev);
2281 nic->msg_enable = value;
2282 }
2283
2284 static int e100_nway_reset(struct net_device *netdev)
2285 {
2286 struct nic *nic = netdev_priv(netdev);
2287 return mii_nway_restart(&nic->mii);
2288 }
2289
2290 static u32 e100_get_link(struct net_device *netdev)
2291 {
2292 struct nic *nic = netdev_priv(netdev);
2293 return mii_link_ok(&nic->mii);
2294 }
2295
2296 static int e100_get_eeprom_len(struct net_device *netdev)
2297 {
2298 struct nic *nic = netdev_priv(netdev);
2299 return nic->eeprom_wc << 1;
2300 }
2301
2302 #define E100_EEPROM_MAGIC 0x1234
2303 static int e100_get_eeprom(struct net_device *netdev,
2304 struct ethtool_eeprom *eeprom, u8 *bytes)
2305 {
2306 struct nic *nic = netdev_priv(netdev);
2307
2308 eeprom->magic = E100_EEPROM_MAGIC;
2309 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2310
2311 return 0;
2312 }
2313
2314 static int e100_set_eeprom(struct net_device *netdev,
2315 struct ethtool_eeprom *eeprom, u8 *bytes)
2316 {
2317 struct nic *nic = netdev_priv(netdev);
2318
2319 if(eeprom->magic != E100_EEPROM_MAGIC)
2320 return -EINVAL;
2321
2322 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2323
2324 return e100_eeprom_save(nic, eeprom->offset >> 1,
2325 (eeprom->len >> 1) + 1);
2326 }
2327
2328 static void e100_get_ringparam(struct net_device *netdev,
2329 struct ethtool_ringparam *ring)
2330 {
2331 struct nic *nic = netdev_priv(netdev);
2332 struct param_range *rfds = &nic->params.rfds;
2333 struct param_range *cbs = &nic->params.cbs;
2334
2335 ring->rx_max_pending = rfds->max;
2336 ring->tx_max_pending = cbs->max;
2337 ring->rx_mini_max_pending = 0;
2338 ring->rx_jumbo_max_pending = 0;
2339 ring->rx_pending = rfds->count;
2340 ring->tx_pending = cbs->count;
2341 ring->rx_mini_pending = 0;
2342 ring->rx_jumbo_pending = 0;
2343 }
2344
2345 static int e100_set_ringparam(struct net_device *netdev,
2346 struct ethtool_ringparam *ring)
2347 {
2348 struct nic *nic = netdev_priv(netdev);
2349 struct param_range *rfds = &nic->params.rfds;
2350 struct param_range *cbs = &nic->params.cbs;
2351
2352 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2353 return -EINVAL;
2354
2355 if(netif_running(netdev))
2356 e100_down(nic);
2357 rfds->count = max(ring->rx_pending, rfds->min);
2358 rfds->count = min(rfds->count, rfds->max);
2359 cbs->count = max(ring->tx_pending, cbs->min);
2360 cbs->count = min(cbs->count, cbs->max);
2361 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2362 rfds->count, cbs->count);
2363 if(netif_running(netdev))
2364 e100_up(nic);
2365
2366 return 0;
2367 }
2368
2369 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2370 "Link test (on/offline)",
2371 "Eeprom test (on/offline)",
2372 "Self test (offline)",
2373 "Mac loopback (offline)",
2374 "Phy loopback (offline)",
2375 };
2376 #define E100_TEST_LEN sizeof(e100_gstrings_test) / ETH_GSTRING_LEN
2377
2378 static int e100_diag_test_count(struct net_device *netdev)
2379 {
2380 return E100_TEST_LEN;
2381 }
2382
2383 static void e100_diag_test(struct net_device *netdev,
2384 struct ethtool_test *test, u64 *data)
2385 {
2386 struct ethtool_cmd cmd;
2387 struct nic *nic = netdev_priv(netdev);
2388 int i, err;
2389
2390 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2391 data[0] = !mii_link_ok(&nic->mii);
2392 data[1] = e100_eeprom_load(nic);
2393 if(test->flags & ETH_TEST_FL_OFFLINE) {
2394
2395 /* save speed, duplex & autoneg settings */
2396 err = mii_ethtool_gset(&nic->mii, &cmd);
2397
2398 if(netif_running(netdev))
2399 e100_down(nic);
2400 data[2] = e100_self_test(nic);
2401 data[3] = e100_loopback_test(nic, lb_mac);
2402 data[4] = e100_loopback_test(nic, lb_phy);
2403
2404 /* restore speed, duplex & autoneg settings */
2405 err = mii_ethtool_sset(&nic->mii, &cmd);
2406
2407 if(netif_running(netdev))
2408 e100_up(nic);
2409 }
2410 for(i = 0; i < E100_TEST_LEN; i++)
2411 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2412
2413 msleep_interruptible(4 * 1000);
2414 }
2415
2416 static int e100_phys_id(struct net_device *netdev, u32 data)
2417 {
2418 struct nic *nic = netdev_priv(netdev);
2419
2420 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2421 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2422 mod_timer(&nic->blink_timer, jiffies);
2423 msleep_interruptible(data * 1000);
2424 del_timer_sync(&nic->blink_timer);
2425 mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);
2426
2427 return 0;
2428 }
2429
2430 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2431 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2432 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2433 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2434 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2435 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2436 "tx_heartbeat_errors", "tx_window_errors",
2437 /* device-specific stats */
2438 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2439 "tx_flow_control_pause", "rx_flow_control_pause",
2440 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2441 };
2442 #define E100_NET_STATS_LEN 21
2443 #define E100_STATS_LEN sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN
2444
2445 static int e100_get_stats_count(struct net_device *netdev)
2446 {
2447 return E100_STATS_LEN;
2448 }
2449
2450 static void e100_get_ethtool_stats(struct net_device *netdev,
2451 struct ethtool_stats *stats, u64 *data)
2452 {
2453 struct nic *nic = netdev_priv(netdev);
2454 int i;
2455
2456 for(i = 0; i < E100_NET_STATS_LEN; i++)
2457 data[i] = ((unsigned long *)&nic->net_stats)[i];
2458
2459 data[i++] = nic->tx_deferred;
2460 data[i++] = nic->tx_single_collisions;
2461 data[i++] = nic->tx_multiple_collisions;
2462 data[i++] = nic->tx_fc_pause;
2463 data[i++] = nic->rx_fc_pause;
2464 data[i++] = nic->rx_fc_unsupported;
2465 data[i++] = nic->tx_tco_frames;
2466 data[i++] = nic->rx_tco_frames;
2467 }
2468
2469 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2470 {
2471 switch(stringset) {
2472 case ETH_SS_TEST:
2473 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2474 break;
2475 case ETH_SS_STATS:
2476 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2477 break;
2478 }
2479 }
2480
2481 static struct ethtool_ops e100_ethtool_ops = {
2482 .get_settings = e100_get_settings,
2483 .set_settings = e100_set_settings,
2484 .get_drvinfo = e100_get_drvinfo,
2485 .get_regs_len = e100_get_regs_len,
2486 .get_regs = e100_get_regs,
2487 .get_wol = e100_get_wol,
2488 .set_wol = e100_set_wol,
2489 .get_msglevel = e100_get_msglevel,
2490 .set_msglevel = e100_set_msglevel,
2491 .nway_reset = e100_nway_reset,
2492 .get_link = e100_get_link,
2493 .get_eeprom_len = e100_get_eeprom_len,
2494 .get_eeprom = e100_get_eeprom,
2495 .set_eeprom = e100_set_eeprom,
2496 .get_ringparam = e100_get_ringparam,
2497 .set_ringparam = e100_set_ringparam,
2498 .self_test_count = e100_diag_test_count,
2499 .self_test = e100_diag_test,
2500 .get_strings = e100_get_strings,
2501 .phys_id = e100_phys_id,
2502 .get_stats_count = e100_get_stats_count,
2503 .get_ethtool_stats = e100_get_ethtool_stats,
2504 .get_perm_addr = ethtool_op_get_perm_addr,
2505 };
2506
2507 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2508 {
2509 struct nic *nic = netdev_priv(netdev);
2510
2511 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2512 }
2513
2514 static int e100_alloc(struct nic *nic)
2515 {
2516 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2517 &nic->dma_addr);
2518 return nic->mem ? 0 : -ENOMEM;
2519 }
2520
2521 static void e100_free(struct nic *nic)
2522 {
2523 if(nic->mem) {
2524 pci_free_consistent(nic->pdev, sizeof(struct mem),
2525 nic->mem, nic->dma_addr);
2526 nic->mem = NULL;
2527 }
2528 }
2529
2530 static int e100_open(struct net_device *netdev)
2531 {
2532 struct nic *nic = netdev_priv(netdev);
2533 int err = 0;
2534
2535 netif_carrier_off(netdev);
2536 if((err = e100_up(nic)))
2537 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2538 return err;
2539 }
2540
2541 static int e100_close(struct net_device *netdev)
2542 {
2543 e100_down(netdev_priv(netdev));
2544 return 0;
2545 }
2546
2547 static int __devinit e100_probe(struct pci_dev *pdev,
2548 const struct pci_device_id *ent)
2549 {
2550 struct net_device *netdev;
2551 struct nic *nic;
2552 int err;
2553
2554 if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2555 if(((1 << debug) - 1) & NETIF_MSG_PROBE)
2556 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2557 return -ENOMEM;
2558 }
2559
2560 netdev->open = e100_open;
2561 netdev->stop = e100_close;
2562 netdev->hard_start_xmit = e100_xmit_frame;
2563 netdev->get_stats = e100_get_stats;
2564 netdev->set_multicast_list = e100_set_multicast_list;
2565 netdev->set_mac_address = e100_set_mac_address;
2566 netdev->change_mtu = e100_change_mtu;
2567 netdev->do_ioctl = e100_do_ioctl;
2568 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2569 netdev->tx_timeout = e100_tx_timeout;
2570 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2571 netdev->poll = e100_poll;
2572 netdev->weight = E100_NAPI_WEIGHT;
2573 #ifdef CONFIG_NET_POLL_CONTROLLER
2574 netdev->poll_controller = e100_netpoll;
2575 #endif
2576 strcpy(netdev->name, pci_name(pdev));
2577
2578 nic = netdev_priv(netdev);
2579 nic->netdev = netdev;
2580 nic->pdev = pdev;
2581 nic->msg_enable = (1 << debug) - 1;
2582 pci_set_drvdata(pdev, netdev);
2583
2584 if((err = pci_enable_device(pdev))) {
2585 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2586 goto err_out_free_dev;
2587 }
2588
2589 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2590 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2591 "base address, aborting.\n");
2592 err = -ENODEV;
2593 goto err_out_disable_pdev;
2594 }
2595
2596 if((err = pci_request_regions(pdev, DRV_NAME))) {
2597 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2598 goto err_out_disable_pdev;
2599 }
2600
2601 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
2602 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2603 goto err_out_free_res;
2604 }
2605
2606 SET_MODULE_OWNER(netdev);
2607 SET_NETDEV_DEV(netdev, &pdev->dev);
2608
2609 nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr));
2610 if(!nic->csr) {
2611 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2612 err = -ENOMEM;
2613 goto err_out_free_res;
2614 }
2615
2616 if(ent->driver_data)
2617 nic->flags |= ich;
2618 else
2619 nic->flags &= ~ich;
2620
2621 e100_get_defaults(nic);
2622
2623 /* locks must be initialized before calling hw_reset */
2624 spin_lock_init(&nic->cb_lock);
2625 spin_lock_init(&nic->cmd_lock);
2626 spin_lock_init(&nic->mdio_lock);
2627
2628 /* Reset the device before pci_set_master() in case device is in some
2629 * funky state and has an interrupt pending - hint: we don't have the
2630 * interrupt handler registered yet. */
2631 e100_hw_reset(nic);
2632
2633 pci_set_master(pdev);
2634
2635 init_timer(&nic->watchdog);
2636 nic->watchdog.function = e100_watchdog;
2637 nic->watchdog.data = (unsigned long)nic;
2638 init_timer(&nic->blink_timer);
2639 nic->blink_timer.function = e100_blink_led;
2640 nic->blink_timer.data = (unsigned long)nic;
2641
2642 INIT_WORK(&nic->tx_timeout_task,
2643 (void (*)(void *))e100_tx_timeout_task, netdev);
2644
2645 if((err = e100_alloc(nic))) {
2646 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2647 goto err_out_iounmap;
2648 }
2649
2650 if((err = e100_eeprom_load(nic)))
2651 goto err_out_free;
2652
2653 e100_phy_init(nic);
2654
2655 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2656 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2657 if(!is_valid_ether_addr(netdev->perm_addr)) {
2658 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2659 "EEPROM, aborting.\n");
2660 err = -EAGAIN;
2661 goto err_out_free;
2662 }
2663
2664 /* Wol magic packet can be enabled from eeprom */
2665 if((nic->mac >= mac_82558_D101_A4) &&
2666 (nic->eeprom[eeprom_id] & eeprom_id_wol))
2667 nic->flags |= wol_magic;
2668
2669 /* ack any pending wake events, disable PME */
2670 err = pci_enable_wake(pdev, 0, 0);
2671 if (err)
2672 DPRINTK(PROBE, ERR, "Error clearing wake event\n");
2673
2674 strcpy(netdev->name, "eth%d");
2675 if((err = register_netdev(netdev))) {
2676 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2677 goto err_out_free;
2678 }
2679
2680 DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, "
2681 "MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
2682 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
2683 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
2684 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
2685
2686 return 0;
2687
2688 err_out_free:
2689 e100_free(nic);
2690 err_out_iounmap:
2691 iounmap(nic->csr);
2692 err_out_free_res:
2693 pci_release_regions(pdev);
2694 err_out_disable_pdev:
2695 pci_disable_device(pdev);
2696 err_out_free_dev:
2697 pci_set_drvdata(pdev, NULL);
2698 free_netdev(netdev);
2699 return err;
2700 }
2701
2702 static void __devexit e100_remove(struct pci_dev *pdev)
2703 {
2704 struct net_device *netdev = pci_get_drvdata(pdev);
2705
2706 if(netdev) {
2707 struct nic *nic = netdev_priv(netdev);
2708 unregister_netdev(netdev);
2709 e100_free(nic);
2710 iounmap(nic->csr);
2711 free_netdev(netdev);
2712 pci_release_regions(pdev);
2713 pci_disable_device(pdev);
2714 pci_set_drvdata(pdev, NULL);
2715 }
2716 }
2717
2718 #ifdef CONFIG_PM
2719 static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2720 {
2721 struct net_device *netdev = pci_get_drvdata(pdev);
2722 struct nic *nic = netdev_priv(netdev);
2723 int retval;
2724
2725 if(netif_running(netdev))
2726 e100_down(nic);
2727 e100_hw_reset(nic);
2728 netif_device_detach(netdev);
2729
2730 pci_save_state(pdev);
2731 retval = pci_enable_wake(pdev, pci_choose_state(pdev, state),
2732 nic->flags & (wol_magic | e100_asf(nic)));
2733 if (retval)
2734 DPRINTK(PROBE,ERR, "Error enabling wake\n");
2735 pci_disable_device(pdev);
2736 retval = pci_set_power_state(pdev, pci_choose_state(pdev, state));
2737 if (retval)
2738 DPRINTK(PROBE,ERR, "Error %d setting power state\n", retval);
2739
2740 return 0;
2741 }
2742
2743 static int e100_resume(struct pci_dev *pdev)
2744 {
2745 struct net_device *netdev = pci_get_drvdata(pdev);
2746 struct nic *nic = netdev_priv(netdev);
2747 int retval;
2748
2749 retval = pci_set_power_state(pdev, PCI_D0);
2750 if (retval)
2751 DPRINTK(PROBE,ERR, "Error waking adapter\n");
2752 pci_restore_state(pdev);
2753 /* ack any pending wake events, disable PME */
2754 retval = pci_enable_wake(pdev, 0, 0);
2755 if (retval)
2756 DPRINTK(PROBE,ERR, "Error clearing wake events\n");
2757
2758 netif_device_attach(netdev);
2759 if(netif_running(netdev))
2760 e100_up(nic);
2761
2762 return 0;
2763 }
2764 #endif
2765
2766
2767 static void e100_shutdown(struct pci_dev *pdev)
2768 {
2769 struct net_device *netdev = pci_get_drvdata(pdev);
2770 struct nic *nic = netdev_priv(netdev);
2771 int retval;
2772
2773 #ifdef CONFIG_PM
2774 retval = pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
2775 #else
2776 retval = pci_enable_wake(pdev, 0, nic->flags & (wol_magic));
2777 #endif
2778 if (retval)
2779 DPRINTK(PROBE,ERR, "Error enabling wake\n");
2780 }
2781
2782 /* ------------------ PCI Error Recovery infrastructure -------------- */
2783 /**
2784 * e100_io_error_detected - called when PCI error is detected.
2785 * @pdev: Pointer to PCI device
2786 * @state: The current pci conneection state
2787 */
2788 static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2789 {
2790 struct net_device *netdev = pci_get_drvdata(pdev);
2791
2792 /* Similar to calling e100_down(), but avoids adpater I/O. */
2793 netdev->stop(netdev);
2794
2795 /* Detach; put netif into state similar to hotplug unplug. */
2796 netif_poll_enable(netdev);
2797 netif_device_detach(netdev);
2798
2799 /* Request a slot reset. */
2800 return PCI_ERS_RESULT_NEED_RESET;
2801 }
2802
2803 /**
2804 * e100_io_slot_reset - called after the pci bus has been reset.
2805 * @pdev: Pointer to PCI device
2806 *
2807 * Restart the card from scratch.
2808 */
2809 static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
2810 {
2811 struct net_device *netdev = pci_get_drvdata(pdev);
2812 struct nic *nic = netdev_priv(netdev);
2813
2814 if (pci_enable_device(pdev)) {
2815 printk(KERN_ERR "e100: Cannot re-enable PCI device after reset.\n");
2816 return PCI_ERS_RESULT_DISCONNECT;
2817 }
2818 pci_set_master(pdev);
2819
2820 /* Only one device per card can do a reset */
2821 if (0 != PCI_FUNC(pdev->devfn))
2822 return PCI_ERS_RESULT_RECOVERED;
2823 e100_hw_reset(nic);
2824 e100_phy_init(nic);
2825
2826 return PCI_ERS_RESULT_RECOVERED;
2827 }
2828
2829 /**
2830 * e100_io_resume - resume normal operations
2831 * @pdev: Pointer to PCI device
2832 *
2833 * Resume normal operations after an error recovery
2834 * sequence has been completed.
2835 */
2836 static void e100_io_resume(struct pci_dev *pdev)
2837 {
2838 struct net_device *netdev = pci_get_drvdata(pdev);
2839 struct nic *nic = netdev_priv(netdev);
2840
2841 /* ack any pending wake events, disable PME */
2842 pci_enable_wake(pdev, 0, 0);
2843
2844 netif_device_attach(netdev);
2845 if (netif_running(netdev)) {
2846 e100_open(netdev);
2847 mod_timer(&nic->watchdog, jiffies);
2848 }
2849 }
2850
2851 static struct pci_error_handlers e100_err_handler = {
2852 .error_detected = e100_io_error_detected,
2853 .slot_reset = e100_io_slot_reset,
2854 .resume = e100_io_resume,
2855 };
2856
2857 static struct pci_driver e100_driver = {
2858 .name = DRV_NAME,
2859 .id_table = e100_id_table,
2860 .probe = e100_probe,
2861 .remove = __devexit_p(e100_remove),
2862 #ifdef CONFIG_PM
2863 .suspend = e100_suspend,
2864 .resume = e100_resume,
2865 #endif
2866 .shutdown = e100_shutdown,
2867 .err_handler = &e100_err_handler,
2868 };
2869
2870 static int __init e100_init_module(void)
2871 {
2872 if(((1 << debug) - 1) & NETIF_MSG_DRV) {
2873 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2874 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2875 }
2876 return pci_module_init(&e100_driver);
2877 }
2878
2879 static void __exit e100_cleanup_module(void)
2880 {
2881 pci_unregister_driver(&e100_driver);
2882 }
2883
2884 module_init(e100_init_module);
2885 module_exit(e100_cleanup_module);