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[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / net / e100.c
1 /*******************************************************************************
2
3 Intel PRO/100 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Recieve
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * Under typical operation, the receive unit (RU) is start once,
110 * and the controller happily fills RFDs as frames arrive. If
111 * replacement RFDs cannot be allocated, or the RU goes non-active,
112 * the RU must be restarted. Frame arrival generates an interrupt,
113 * and Rx indication and re-allocation happen in the same context,
114 * therefore no locking is required. A software-generated interrupt
115 * is generated from the watchdog to recover from a failed allocation
116 * senario where all Rx resources have been indicated and none re-
117 * placed.
118 *
119 * V. Miscellaneous
120 *
121 * VLAN offloading of tagging, stripping and filtering is not
122 * supported, but driver will accommodate the extra 4-byte VLAN tag
123 * for processing by upper layers. Tx/Rx Checksum offloading is not
124 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
125 * not supported (hardware limitation).
126 *
127 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
128 *
129 * Thanks to JC (jchapman@katalix.com) for helping with
130 * testing/troubleshooting the development driver.
131 *
132 * TODO:
133 * o several entry points race with dev->close
134 * o check for tx-no-resources/stop Q races with tx clean/wake Q
135 *
136 * FIXES:
137 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
138 * - Stratus87247: protect MDI control register manipulations
139 */
140
141 #include <linux/module.h>
142 #include <linux/moduleparam.h>
143 #include <linux/kernel.h>
144 #include <linux/types.h>
145 #include <linux/slab.h>
146 #include <linux/delay.h>
147 #include <linux/init.h>
148 #include <linux/pci.h>
149 #include <linux/dma-mapping.h>
150 #include <linux/netdevice.h>
151 #include <linux/etherdevice.h>
152 #include <linux/mii.h>
153 #include <linux/if_vlan.h>
154 #include <linux/skbuff.h>
155 #include <linux/ethtool.h>
156 #include <linux/string.h>
157 #include <asm/unaligned.h>
158
159
160 #define DRV_NAME "e100"
161 #define DRV_EXT "-NAPI"
162 #define DRV_VERSION "3.5.23-k4"DRV_EXT
163 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
164 #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
165 #define PFX DRV_NAME ": "
166
167 #define E100_WATCHDOG_PERIOD (2 * HZ)
168 #define E100_NAPI_WEIGHT 16
169
170 MODULE_DESCRIPTION(DRV_DESCRIPTION);
171 MODULE_AUTHOR(DRV_COPYRIGHT);
172 MODULE_LICENSE("GPL");
173 MODULE_VERSION(DRV_VERSION);
174
175 static int debug = 3;
176 static int eeprom_bad_csum_allow = 0;
177 static int use_io = 0;
178 module_param(debug, int, 0);
179 module_param(eeprom_bad_csum_allow, int, 0);
180 module_param(use_io, int, 0);
181 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
182 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
183 MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
184 #define DPRINTK(nlevel, klevel, fmt, args...) \
185 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
186 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
187 __FUNCTION__ , ## args))
188
189 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
190 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
191 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
192 static struct pci_device_id e100_id_table[] = {
193 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
194 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
195 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
196 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
197 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
198 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
199 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
200 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
201 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
202 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
203 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
204 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
205 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
206 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
207 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
208 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
209 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
210 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
211 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
212 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
213 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
214 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
215 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
216 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
217 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
218 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
219 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
220 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
221 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
222 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
223 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
224 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
225 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
226 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
227 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
228 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
229 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
230 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
231 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
232 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
233 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
234 { 0, }
235 };
236 MODULE_DEVICE_TABLE(pci, e100_id_table);
237
238 enum mac {
239 mac_82557_D100_A = 0,
240 mac_82557_D100_B = 1,
241 mac_82557_D100_C = 2,
242 mac_82558_D101_A4 = 4,
243 mac_82558_D101_B0 = 5,
244 mac_82559_D101M = 8,
245 mac_82559_D101S = 9,
246 mac_82550_D102 = 12,
247 mac_82550_D102_C = 13,
248 mac_82551_E = 14,
249 mac_82551_F = 15,
250 mac_82551_10 = 16,
251 mac_unknown = 0xFF,
252 };
253
254 enum phy {
255 phy_100a = 0x000003E0,
256 phy_100c = 0x035002A8,
257 phy_82555_tx = 0x015002A8,
258 phy_nsc_tx = 0x5C002000,
259 phy_82562_et = 0x033002A8,
260 phy_82562_em = 0x032002A8,
261 phy_82562_ek = 0x031002A8,
262 phy_82562_eh = 0x017002A8,
263 phy_unknown = 0xFFFFFFFF,
264 };
265
266 /* CSR (Control/Status Registers) */
267 struct csr {
268 struct {
269 u8 status;
270 u8 stat_ack;
271 u8 cmd_lo;
272 u8 cmd_hi;
273 u32 gen_ptr;
274 } scb;
275 u32 port;
276 u16 flash_ctrl;
277 u8 eeprom_ctrl_lo;
278 u8 eeprom_ctrl_hi;
279 u32 mdi_ctrl;
280 u32 rx_dma_count;
281 };
282
283 enum scb_status {
284 rus_ready = 0x10,
285 rus_mask = 0x3C,
286 };
287
288 enum ru_state {
289 RU_SUSPENDED = 0,
290 RU_RUNNING = 1,
291 RU_UNINITIALIZED = -1,
292 };
293
294 enum scb_stat_ack {
295 stat_ack_not_ours = 0x00,
296 stat_ack_sw_gen = 0x04,
297 stat_ack_rnr = 0x10,
298 stat_ack_cu_idle = 0x20,
299 stat_ack_frame_rx = 0x40,
300 stat_ack_cu_cmd_done = 0x80,
301 stat_ack_not_present = 0xFF,
302 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
303 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
304 };
305
306 enum scb_cmd_hi {
307 irq_mask_none = 0x00,
308 irq_mask_all = 0x01,
309 irq_sw_gen = 0x02,
310 };
311
312 enum scb_cmd_lo {
313 cuc_nop = 0x00,
314 ruc_start = 0x01,
315 ruc_load_base = 0x06,
316 cuc_start = 0x10,
317 cuc_resume = 0x20,
318 cuc_dump_addr = 0x40,
319 cuc_dump_stats = 0x50,
320 cuc_load_base = 0x60,
321 cuc_dump_reset = 0x70,
322 };
323
324 enum cuc_dump {
325 cuc_dump_complete = 0x0000A005,
326 cuc_dump_reset_complete = 0x0000A007,
327 };
328
329 enum port {
330 software_reset = 0x0000,
331 selftest = 0x0001,
332 selective_reset = 0x0002,
333 };
334
335 enum eeprom_ctrl_lo {
336 eesk = 0x01,
337 eecs = 0x02,
338 eedi = 0x04,
339 eedo = 0x08,
340 };
341
342 enum mdi_ctrl {
343 mdi_write = 0x04000000,
344 mdi_read = 0x08000000,
345 mdi_ready = 0x10000000,
346 };
347
348 enum eeprom_op {
349 op_write = 0x05,
350 op_read = 0x06,
351 op_ewds = 0x10,
352 op_ewen = 0x13,
353 };
354
355 enum eeprom_offsets {
356 eeprom_cnfg_mdix = 0x03,
357 eeprom_id = 0x0A,
358 eeprom_config_asf = 0x0D,
359 eeprom_smbus_addr = 0x90,
360 };
361
362 enum eeprom_cnfg_mdix {
363 eeprom_mdix_enabled = 0x0080,
364 };
365
366 enum eeprom_id {
367 eeprom_id_wol = 0x0020,
368 };
369
370 enum eeprom_config_asf {
371 eeprom_asf = 0x8000,
372 eeprom_gcl = 0x4000,
373 };
374
375 enum cb_status {
376 cb_complete = 0x8000,
377 cb_ok = 0x2000,
378 };
379
380 enum cb_command {
381 cb_nop = 0x0000,
382 cb_iaaddr = 0x0001,
383 cb_config = 0x0002,
384 cb_multi = 0x0003,
385 cb_tx = 0x0004,
386 cb_ucode = 0x0005,
387 cb_dump = 0x0006,
388 cb_tx_sf = 0x0008,
389 cb_cid = 0x1f00,
390 cb_i = 0x2000,
391 cb_s = 0x4000,
392 cb_el = 0x8000,
393 };
394
395 struct rfd {
396 u16 status;
397 u16 command;
398 u32 link;
399 u32 rbd;
400 u16 actual_size;
401 u16 size;
402 };
403
404 struct rx {
405 struct rx *next, *prev;
406 struct sk_buff *skb;
407 dma_addr_t dma_addr;
408 };
409
410 #if defined(__BIG_ENDIAN_BITFIELD)
411 #define X(a,b) b,a
412 #else
413 #define X(a,b) a,b
414 #endif
415 struct config {
416 /*0*/ u8 X(byte_count:6, pad0:2);
417 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
418 /*2*/ u8 adaptive_ifs;
419 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
420 term_write_cache_line:1), pad3:4);
421 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
422 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
423 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
424 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
425 rx_discard_overruns:1), rx_save_bad_frames:1);
426 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
427 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
428 tx_dynamic_tbd:1);
429 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
430 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
431 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
432 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
433 loopback:2);
434 /*11*/ u8 X(linear_priority:3, pad11:5);
435 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
436 /*13*/ u8 ip_addr_lo;
437 /*14*/ u8 ip_addr_hi;
438 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
439 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
440 pad15_2:1), crs_or_cdt:1);
441 /*16*/ u8 fc_delay_lo;
442 /*17*/ u8 fc_delay_hi;
443 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
444 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
445 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
446 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
447 full_duplex_force:1), full_duplex_pin:1);
448 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
449 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
450 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
451 u8 pad_d102[9];
452 };
453
454 #define E100_MAX_MULTICAST_ADDRS 64
455 struct multi {
456 u16 count;
457 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
458 };
459
460 /* Important: keep total struct u32-aligned */
461 #define UCODE_SIZE 134
462 struct cb {
463 u16 status;
464 u16 command;
465 u32 link;
466 union {
467 u8 iaaddr[ETH_ALEN];
468 u32 ucode[UCODE_SIZE];
469 struct config config;
470 struct multi multi;
471 struct {
472 u32 tbd_array;
473 u16 tcb_byte_count;
474 u8 threshold;
475 u8 tbd_count;
476 struct {
477 u32 buf_addr;
478 u16 size;
479 u16 eol;
480 } tbd;
481 } tcb;
482 u32 dump_buffer_addr;
483 } u;
484 struct cb *next, *prev;
485 dma_addr_t dma_addr;
486 struct sk_buff *skb;
487 };
488
489 enum loopback {
490 lb_none = 0, lb_mac = 1, lb_phy = 3,
491 };
492
493 struct stats {
494 u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
495 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
496 tx_multiple_collisions, tx_total_collisions;
497 u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
498 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
499 rx_short_frame_errors;
500 u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
501 u16 xmt_tco_frames, rcv_tco_frames;
502 u32 complete;
503 };
504
505 struct mem {
506 struct {
507 u32 signature;
508 u32 result;
509 } selftest;
510 struct stats stats;
511 u8 dump_buf[596];
512 };
513
514 struct param_range {
515 u32 min;
516 u32 max;
517 u32 count;
518 };
519
520 struct params {
521 struct param_range rfds;
522 struct param_range cbs;
523 };
524
525 struct nic {
526 /* Begin: frequently used values: keep adjacent for cache effect */
527 u32 msg_enable ____cacheline_aligned;
528 struct net_device *netdev;
529 struct pci_dev *pdev;
530
531 struct rx *rxs ____cacheline_aligned;
532 struct rx *rx_to_use;
533 struct rx *rx_to_clean;
534 struct rfd blank_rfd;
535 enum ru_state ru_running;
536
537 spinlock_t cb_lock ____cacheline_aligned;
538 spinlock_t cmd_lock;
539 struct csr __iomem *csr;
540 enum scb_cmd_lo cuc_cmd;
541 unsigned int cbs_avail;
542 struct cb *cbs;
543 struct cb *cb_to_use;
544 struct cb *cb_to_send;
545 struct cb *cb_to_clean;
546 u16 tx_command;
547 /* End: frequently used values: keep adjacent for cache effect */
548
549 enum {
550 ich = (1 << 0),
551 promiscuous = (1 << 1),
552 multicast_all = (1 << 2),
553 wol_magic = (1 << 3),
554 ich_10h_workaround = (1 << 4),
555 } flags ____cacheline_aligned;
556
557 enum mac mac;
558 enum phy phy;
559 struct params params;
560 struct net_device_stats net_stats;
561 struct timer_list watchdog;
562 struct timer_list blink_timer;
563 struct mii_if_info mii;
564 struct work_struct tx_timeout_task;
565 enum loopback loopback;
566
567 struct mem *mem;
568 dma_addr_t dma_addr;
569
570 dma_addr_t cbs_dma_addr;
571 u8 adaptive_ifs;
572 u8 tx_threshold;
573 u32 tx_frames;
574 u32 tx_collisions;
575 u32 tx_deferred;
576 u32 tx_single_collisions;
577 u32 tx_multiple_collisions;
578 u32 tx_fc_pause;
579 u32 tx_tco_frames;
580
581 u32 rx_fc_pause;
582 u32 rx_fc_unsupported;
583 u32 rx_tco_frames;
584 u32 rx_over_length_errors;
585
586 u8 rev_id;
587 u16 leds;
588 u16 eeprom_wc;
589 u16 eeprom[256];
590 spinlock_t mdio_lock;
591 };
592
593 static inline void e100_write_flush(struct nic *nic)
594 {
595 /* Flush previous PCI writes through intermediate bridges
596 * by doing a benign read */
597 (void)ioread8(&nic->csr->scb.status);
598 }
599
600 static void e100_enable_irq(struct nic *nic)
601 {
602 unsigned long flags;
603
604 spin_lock_irqsave(&nic->cmd_lock, flags);
605 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
606 e100_write_flush(nic);
607 spin_unlock_irqrestore(&nic->cmd_lock, flags);
608 }
609
610 static void e100_disable_irq(struct nic *nic)
611 {
612 unsigned long flags;
613
614 spin_lock_irqsave(&nic->cmd_lock, flags);
615 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
616 e100_write_flush(nic);
617 spin_unlock_irqrestore(&nic->cmd_lock, flags);
618 }
619
620 static void e100_hw_reset(struct nic *nic)
621 {
622 /* Put CU and RU into idle with a selective reset to get
623 * device off of PCI bus */
624 iowrite32(selective_reset, &nic->csr->port);
625 e100_write_flush(nic); udelay(20);
626
627 /* Now fully reset device */
628 iowrite32(software_reset, &nic->csr->port);
629 e100_write_flush(nic); udelay(20);
630
631 /* Mask off our interrupt line - it's unmasked after reset */
632 e100_disable_irq(nic);
633 }
634
635 static int e100_self_test(struct nic *nic)
636 {
637 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
638
639 /* Passing the self-test is a pretty good indication
640 * that the device can DMA to/from host memory */
641
642 nic->mem->selftest.signature = 0;
643 nic->mem->selftest.result = 0xFFFFFFFF;
644
645 iowrite32(selftest | dma_addr, &nic->csr->port);
646 e100_write_flush(nic);
647 /* Wait 10 msec for self-test to complete */
648 msleep(10);
649
650 /* Interrupts are enabled after self-test */
651 e100_disable_irq(nic);
652
653 /* Check results of self-test */
654 if(nic->mem->selftest.result != 0) {
655 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
656 nic->mem->selftest.result);
657 return -ETIMEDOUT;
658 }
659 if(nic->mem->selftest.signature == 0) {
660 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
661 return -ETIMEDOUT;
662 }
663
664 return 0;
665 }
666
667 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
668 {
669 u32 cmd_addr_data[3];
670 u8 ctrl;
671 int i, j;
672
673 /* Three cmds: write/erase enable, write data, write/erase disable */
674 cmd_addr_data[0] = op_ewen << (addr_len - 2);
675 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
676 cpu_to_le16(data);
677 cmd_addr_data[2] = op_ewds << (addr_len - 2);
678
679 /* Bit-bang cmds to write word to eeprom */
680 for(j = 0; j < 3; j++) {
681
682 /* Chip select */
683 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
684 e100_write_flush(nic); udelay(4);
685
686 for(i = 31; i >= 0; i--) {
687 ctrl = (cmd_addr_data[j] & (1 << i)) ?
688 eecs | eedi : eecs;
689 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
690 e100_write_flush(nic); udelay(4);
691
692 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
693 e100_write_flush(nic); udelay(4);
694 }
695 /* Wait 10 msec for cmd to complete */
696 msleep(10);
697
698 /* Chip deselect */
699 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
700 e100_write_flush(nic); udelay(4);
701 }
702 };
703
704 /* General technique stolen from the eepro100 driver - very clever */
705 static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
706 {
707 u32 cmd_addr_data;
708 u16 data = 0;
709 u8 ctrl;
710 int i;
711
712 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
713
714 /* Chip select */
715 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
716 e100_write_flush(nic); udelay(4);
717
718 /* Bit-bang to read word from eeprom */
719 for(i = 31; i >= 0; i--) {
720 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
721 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
722 e100_write_flush(nic); udelay(4);
723
724 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
725 e100_write_flush(nic); udelay(4);
726
727 /* Eeprom drives a dummy zero to EEDO after receiving
728 * complete address. Use this to adjust addr_len. */
729 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
730 if(!(ctrl & eedo) && i > 16) {
731 *addr_len -= (i - 16);
732 i = 17;
733 }
734
735 data = (data << 1) | (ctrl & eedo ? 1 : 0);
736 }
737
738 /* Chip deselect */
739 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
740 e100_write_flush(nic); udelay(4);
741
742 return le16_to_cpu(data);
743 };
744
745 /* Load entire EEPROM image into driver cache and validate checksum */
746 static int e100_eeprom_load(struct nic *nic)
747 {
748 u16 addr, addr_len = 8, checksum = 0;
749
750 /* Try reading with an 8-bit addr len to discover actual addr len */
751 e100_eeprom_read(nic, &addr_len, 0);
752 nic->eeprom_wc = 1 << addr_len;
753
754 for(addr = 0; addr < nic->eeprom_wc; addr++) {
755 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
756 if(addr < nic->eeprom_wc - 1)
757 checksum += cpu_to_le16(nic->eeprom[addr]);
758 }
759
760 /* The checksum, stored in the last word, is calculated such that
761 * the sum of words should be 0xBABA */
762 checksum = le16_to_cpu(0xBABA - checksum);
763 if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
764 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
765 if (!eeprom_bad_csum_allow)
766 return -EAGAIN;
767 }
768
769 return 0;
770 }
771
772 /* Save (portion of) driver EEPROM cache to device and update checksum */
773 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
774 {
775 u16 addr, addr_len = 8, checksum = 0;
776
777 /* Try reading with an 8-bit addr len to discover actual addr len */
778 e100_eeprom_read(nic, &addr_len, 0);
779 nic->eeprom_wc = 1 << addr_len;
780
781 if(start + count >= nic->eeprom_wc)
782 return -EINVAL;
783
784 for(addr = start; addr < start + count; addr++)
785 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
786
787 /* The checksum, stored in the last word, is calculated such that
788 * the sum of words should be 0xBABA */
789 for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
790 checksum += cpu_to_le16(nic->eeprom[addr]);
791 nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);
792 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
793 nic->eeprom[nic->eeprom_wc - 1]);
794
795 return 0;
796 }
797
798 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
799 #define E100_WAIT_SCB_FAST 20 /* delay like the old code */
800 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
801 {
802 unsigned long flags;
803 unsigned int i;
804 int err = 0;
805
806 spin_lock_irqsave(&nic->cmd_lock, flags);
807
808 /* Previous command is accepted when SCB clears */
809 for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
810 if(likely(!ioread8(&nic->csr->scb.cmd_lo)))
811 break;
812 cpu_relax();
813 if(unlikely(i > E100_WAIT_SCB_FAST))
814 udelay(5);
815 }
816 if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
817 err = -EAGAIN;
818 goto err_unlock;
819 }
820
821 if(unlikely(cmd != cuc_resume))
822 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
823 iowrite8(cmd, &nic->csr->scb.cmd_lo);
824
825 err_unlock:
826 spin_unlock_irqrestore(&nic->cmd_lock, flags);
827
828 return err;
829 }
830
831 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
832 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
833 {
834 struct cb *cb;
835 unsigned long flags;
836 int err = 0;
837
838 spin_lock_irqsave(&nic->cb_lock, flags);
839
840 if(unlikely(!nic->cbs_avail)) {
841 err = -ENOMEM;
842 goto err_unlock;
843 }
844
845 cb = nic->cb_to_use;
846 nic->cb_to_use = cb->next;
847 nic->cbs_avail--;
848 cb->skb = skb;
849
850 if(unlikely(!nic->cbs_avail))
851 err = -ENOSPC;
852
853 cb_prepare(nic, cb, skb);
854
855 /* Order is important otherwise we'll be in a race with h/w:
856 * set S-bit in current first, then clear S-bit in previous. */
857 cb->command |= cpu_to_le16(cb_s);
858 wmb();
859 cb->prev->command &= cpu_to_le16(~cb_s);
860
861 while(nic->cb_to_send != nic->cb_to_use) {
862 if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
863 nic->cb_to_send->dma_addr))) {
864 /* Ok, here's where things get sticky. It's
865 * possible that we can't schedule the command
866 * because the controller is too busy, so
867 * let's just queue the command and try again
868 * when another command is scheduled. */
869 if(err == -ENOSPC) {
870 //request a reset
871 schedule_work(&nic->tx_timeout_task);
872 }
873 break;
874 } else {
875 nic->cuc_cmd = cuc_resume;
876 nic->cb_to_send = nic->cb_to_send->next;
877 }
878 }
879
880 err_unlock:
881 spin_unlock_irqrestore(&nic->cb_lock, flags);
882
883 return err;
884 }
885
886 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
887 {
888 u32 data_out = 0;
889 unsigned int i;
890 unsigned long flags;
891
892
893 /*
894 * Stratus87247: we shouldn't be writing the MDI control
895 * register until the Ready bit shows True. Also, since
896 * manipulation of the MDI control registers is a multi-step
897 * procedure it should be done under lock.
898 */
899 spin_lock_irqsave(&nic->mdio_lock, flags);
900 for (i = 100; i; --i) {
901 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
902 break;
903 udelay(20);
904 }
905 if (unlikely(!i)) {
906 printk("e100.mdio_ctrl(%s) won't go Ready\n",
907 nic->netdev->name );
908 spin_unlock_irqrestore(&nic->mdio_lock, flags);
909 return 0; /* No way to indicate timeout error */
910 }
911 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
912
913 for (i = 0; i < 100; i++) {
914 udelay(20);
915 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
916 break;
917 }
918 spin_unlock_irqrestore(&nic->mdio_lock, flags);
919 DPRINTK(HW, DEBUG,
920 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
921 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
922 return (u16)data_out;
923 }
924
925 static int mdio_read(struct net_device *netdev, int addr, int reg)
926 {
927 return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);
928 }
929
930 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
931 {
932 mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);
933 }
934
935 static void e100_get_defaults(struct nic *nic)
936 {
937 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
938 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
939
940 pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
941 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
942 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
943 if(nic->mac == mac_unknown)
944 nic->mac = mac_82557_D100_A;
945
946 nic->params.rfds = rfds;
947 nic->params.cbs = cbs;
948
949 /* Quadwords to DMA into FIFO before starting frame transmit */
950 nic->tx_threshold = 0xE0;
951
952 /* no interrupt for every tx completion, delay = 256us if not 557*/
953 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
954 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
955
956 /* Template for a freshly allocated RFD */
957 nic->blank_rfd.command = cpu_to_le16(cb_el);
958 nic->blank_rfd.rbd = 0xFFFFFFFF;
959 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
960
961 /* MII setup */
962 nic->mii.phy_id_mask = 0x1F;
963 nic->mii.reg_num_mask = 0x1F;
964 nic->mii.dev = nic->netdev;
965 nic->mii.mdio_read = mdio_read;
966 nic->mii.mdio_write = mdio_write;
967 }
968
969 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
970 {
971 struct config *config = &cb->u.config;
972 u8 *c = (u8 *)config;
973
974 cb->command = cpu_to_le16(cb_config);
975
976 memset(config, 0, sizeof(struct config));
977
978 config->byte_count = 0x16; /* bytes in this struct */
979 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
980 config->direct_rx_dma = 0x1; /* reserved */
981 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
982 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
983 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
984 config->tx_underrun_retry = 0x3; /* # of underrun retries */
985 config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
986 config->pad10 = 0x6;
987 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
988 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
989 config->ifs = 0x6; /* x16 = inter frame spacing */
990 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
991 config->pad15_1 = 0x1;
992 config->pad15_2 = 0x1;
993 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
994 config->fc_delay_hi = 0x40; /* time delay for fc frame */
995 config->tx_padding = 0x1; /* 1=pad short frames */
996 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
997 config->pad18 = 0x1;
998 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
999 config->pad20_1 = 0x1F;
1000 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1001 config->pad21_1 = 0x5;
1002
1003 config->adaptive_ifs = nic->adaptive_ifs;
1004 config->loopback = nic->loopback;
1005
1006 if(nic->mii.force_media && nic->mii.full_duplex)
1007 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1008
1009 if(nic->flags & promiscuous || nic->loopback) {
1010 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1011 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1012 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1013 }
1014
1015 if(nic->flags & multicast_all)
1016 config->multicast_all = 0x1; /* 1=accept, 0=no */
1017
1018 /* disable WoL when up */
1019 if(netif_running(nic->netdev) || !(nic->flags & wol_magic))
1020 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1021
1022 if(nic->mac >= mac_82558_D101_A4) {
1023 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1024 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1025 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1026 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1027 if (nic->mac >= mac_82559_D101M) {
1028 config->tno_intr = 0x1; /* TCO stats enable */
1029 /* Enable TCO in extended config */
1030 if (nic->mac >= mac_82551_10) {
1031 config->byte_count = 0x20; /* extended bytes */
1032 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1033 }
1034 } else {
1035 config->standard_stat_counter = 0x0;
1036 }
1037 }
1038
1039 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1040 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1041 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1042 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1043 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1044 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1045 }
1046
1047 /********************************************************/
1048 /* Micro code for 8086:1229 Rev 8 */
1049 /********************************************************/
1050
1051 /* Parameter values for the D101M B-step */
1052 #define D101M_CPUSAVER_TIMER_DWORD 78
1053 #define D101M_CPUSAVER_BUNDLE_DWORD 65
1054 #define D101M_CPUSAVER_MIN_SIZE_DWORD 126
1055
1056 #define D101M_B_RCVBUNDLE_UCODE \
1057 {\
1058 0x00550215, 0xFFFF0437, 0xFFFFFFFF, 0x06A70789, 0xFFFFFFFF, 0x0558FFFF, \
1059 0x000C0001, 0x00101312, 0x000C0008, 0x00380216, \
1060 0x0010009C, 0x00204056, 0x002380CC, 0x00380056, \
1061 0x0010009C, 0x00244C0B, 0x00000800, 0x00124818, \
1062 0x00380438, 0x00000000, 0x00140000, 0x00380555, \
1063 0x00308000, 0x00100662, 0x00100561, 0x000E0408, \
1064 0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
1065 0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
1066 0x000C007E, 0x00222C21, 0x000C0002, 0x00103093, \
1067 0x00380C7A, 0x00080000, 0x00103090, 0x00380C7A, \
1068 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1069 0x0010009C, 0x00244C2D, 0x00010004, 0x00041000, \
1070 0x003A0437, 0x00044010, 0x0038078A, 0x00000000, \
1071 0x00100099, 0x00206C7A, 0x0010009C, 0x00244C48, \
1072 0x00130824, 0x000C0001, 0x00101213, 0x00260C75, \
1073 0x00041000, 0x00010004, 0x00130826, 0x000C0006, \
1074 0x002206A8, 0x0013C926, 0x00101313, 0x003806A8, \
1075 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1076 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1077 0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
1078 0x00101210, 0x00380C34, 0x00000000, 0x00000000, \
1079 0x0021155B, 0x00100099, 0x00206559, 0x0010009C, \
1080 0x00244559, 0x00130836, 0x000C0000, 0x00220C62, \
1081 0x000C0001, 0x00101B13, 0x00229C0E, 0x00210C0E, \
1082 0x00226C0E, 0x00216C0E, 0x0022FC0E, 0x00215C0E, \
1083 0x00214C0E, 0x00380555, 0x00010004, 0x00041000, \
1084 0x00278C67, 0x00040800, 0x00018100, 0x003A0437, \
1085 0x00130826, 0x000C0001, 0x00220559, 0x00101313, \
1086 0x00380559, 0x00000000, 0x00000000, 0x00000000, \
1087 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1088 0x00000000, 0x00130831, 0x0010090B, 0x00124813, \
1089 0x000CFF80, 0x002606AB, 0x00041000, 0x00010004, \
1090 0x003806A8, 0x00000000, 0x00000000, 0x00000000, \
1091 }
1092
1093 /********************************************************/
1094 /* Micro code for 8086:1229 Rev 9 */
1095 /********************************************************/
1096
1097 /* Parameter values for the D101S */
1098 #define D101S_CPUSAVER_TIMER_DWORD 78
1099 #define D101S_CPUSAVER_BUNDLE_DWORD 67
1100 #define D101S_CPUSAVER_MIN_SIZE_DWORD 128
1101
1102 #define D101S_RCVBUNDLE_UCODE \
1103 {\
1104 0x00550242, 0xFFFF047E, 0xFFFFFFFF, 0x06FF0818, 0xFFFFFFFF, 0x05A6FFFF, \
1105 0x000C0001, 0x00101312, 0x000C0008, 0x00380243, \
1106 0x0010009C, 0x00204056, 0x002380D0, 0x00380056, \
1107 0x0010009C, 0x00244F8B, 0x00000800, 0x00124818, \
1108 0x0038047F, 0x00000000, 0x00140000, 0x003805A3, \
1109 0x00308000, 0x00100610, 0x00100561, 0x000E0408, \
1110 0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
1111 0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
1112 0x000C007E, 0x00222FA1, 0x000C0002, 0x00103093, \
1113 0x00380F90, 0x00080000, 0x00103090, 0x00380F90, \
1114 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1115 0x0010009C, 0x00244FAD, 0x00010004, 0x00041000, \
1116 0x003A047E, 0x00044010, 0x00380819, 0x00000000, \
1117 0x00100099, 0x00206FFD, 0x0010009A, 0x0020AFFD, \
1118 0x0010009C, 0x00244FC8, 0x00130824, 0x000C0001, \
1119 0x00101213, 0x00260FF7, 0x00041000, 0x00010004, \
1120 0x00130826, 0x000C0006, 0x00220700, 0x0013C926, \
1121 0x00101313, 0x00380700, 0x00000000, 0x00000000, \
1122 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1123 0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
1124 0x00101210, 0x00380FB6, 0x00000000, 0x00000000, \
1125 0x002115A9, 0x00100099, 0x002065A7, 0x0010009A, \
1126 0x0020A5A7, 0x0010009C, 0x002445A7, 0x00130836, \
1127 0x000C0000, 0x00220FE4, 0x000C0001, 0x00101B13, \
1128 0x00229F8E, 0x00210F8E, 0x00226F8E, 0x00216F8E, \
1129 0x0022FF8E, 0x00215F8E, 0x00214F8E, 0x003805A3, \
1130 0x00010004, 0x00041000, 0x00278FE9, 0x00040800, \
1131 0x00018100, 0x003A047E, 0x00130826, 0x000C0001, \
1132 0x002205A7, 0x00101313, 0x003805A7, 0x00000000, \
1133 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1134 0x00000000, 0x00000000, 0x00000000, 0x00130831, \
1135 0x0010090B, 0x00124813, 0x000CFF80, 0x00260703, \
1136 0x00041000, 0x00010004, 0x00380700 \
1137 }
1138
1139 /********************************************************/
1140 /* Micro code for the 8086:1229 Rev F/10 */
1141 /********************************************************/
1142
1143 /* Parameter values for the D102 E-step */
1144 #define D102_E_CPUSAVER_TIMER_DWORD 42
1145 #define D102_E_CPUSAVER_BUNDLE_DWORD 54
1146 #define D102_E_CPUSAVER_MIN_SIZE_DWORD 46
1147
1148 #define D102_E_RCVBUNDLE_UCODE \
1149 {\
1150 0x007D028F, 0x0E4204F9, 0x14ED0C85, 0x14FA14E9, 0x0EF70E36, 0x1FFF1FFF, \
1151 0x00E014B9, 0x00000000, 0x00000000, 0x00000000, \
1152 0x00E014BD, 0x00000000, 0x00000000, 0x00000000, \
1153 0x00E014D5, 0x00000000, 0x00000000, 0x00000000, \
1154 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1155 0x00E014C1, 0x00000000, 0x00000000, 0x00000000, \
1156 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1157 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1158 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1159 0x00E014C8, 0x00000000, 0x00000000, 0x00000000, \
1160 0x00200600, 0x00E014EE, 0x00000000, 0x00000000, \
1161 0x0030FF80, 0x00940E46, 0x00038200, 0x00102000, \
1162 0x00E00E43, 0x00000000, 0x00000000, 0x00000000, \
1163 0x00300006, 0x00E014FB, 0x00000000, 0x00000000, \
1164 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1165 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1166 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1167 0x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000, \
1168 0x00906EFD, 0x00900EFD, 0x00E00EF8, 0x00000000, \
1169 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1170 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1171 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1172 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1173 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1174 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1175 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1176 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1177 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1178 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1179 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1180 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1181 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1182 0x00000000, 0x00000000, 0x00000000, 0x00000000, \
1183 }
1184
1185 static void e100_setup_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1186 {
1187 /* *INDENT-OFF* */
1188 static struct {
1189 u32 ucode[UCODE_SIZE + 1];
1190 u8 mac;
1191 u8 timer_dword;
1192 u8 bundle_dword;
1193 u8 min_size_dword;
1194 } ucode_opts[] = {
1195 { D101M_B_RCVBUNDLE_UCODE,
1196 mac_82559_D101M,
1197 D101M_CPUSAVER_TIMER_DWORD,
1198 D101M_CPUSAVER_BUNDLE_DWORD,
1199 D101M_CPUSAVER_MIN_SIZE_DWORD },
1200 { D101S_RCVBUNDLE_UCODE,
1201 mac_82559_D101S,
1202 D101S_CPUSAVER_TIMER_DWORD,
1203 D101S_CPUSAVER_BUNDLE_DWORD,
1204 D101S_CPUSAVER_MIN_SIZE_DWORD },
1205 { D102_E_RCVBUNDLE_UCODE,
1206 mac_82551_F,
1207 D102_E_CPUSAVER_TIMER_DWORD,
1208 D102_E_CPUSAVER_BUNDLE_DWORD,
1209 D102_E_CPUSAVER_MIN_SIZE_DWORD },
1210 { D102_E_RCVBUNDLE_UCODE,
1211 mac_82551_10,
1212 D102_E_CPUSAVER_TIMER_DWORD,
1213 D102_E_CPUSAVER_BUNDLE_DWORD,
1214 D102_E_CPUSAVER_MIN_SIZE_DWORD },
1215 { {0}, 0, 0, 0, 0}
1216 }, *opts;
1217 /* *INDENT-ON* */
1218
1219 /*************************************************************************
1220 * CPUSaver parameters
1221 *
1222 * All CPUSaver parameters are 16-bit literals that are part of a
1223 * "move immediate value" instruction. By changing the value of
1224 * the literal in the instruction before the code is loaded, the
1225 * driver can change the algorithm.
1226 *
1227 * INTDELAY - This loads the dead-man timer with its initial value.
1228 * When this timer expires the interrupt is asserted, and the
1229 * timer is reset each time a new packet is received. (see
1230 * BUNDLEMAX below to set the limit on number of chained packets)
1231 * The current default is 0x600 or 1536. Experiments show that
1232 * the value should probably stay within the 0x200 - 0x1000.
1233 *
1234 * BUNDLEMAX -
1235 * This sets the maximum number of frames that will be bundled. In
1236 * some situations, such as the TCP windowing algorithm, it may be
1237 * better to limit the growth of the bundle size than let it go as
1238 * high as it can, because that could cause too much added latency.
1239 * The default is six, because this is the number of packets in the
1240 * default TCP window size. A value of 1 would make CPUSaver indicate
1241 * an interrupt for every frame received. If you do not want to put
1242 * a limit on the bundle size, set this value to xFFFF.
1243 *
1244 * BUNDLESMALL -
1245 * This contains a bit-mask describing the minimum size frame that
1246 * will be bundled. The default masks the lower 7 bits, which means
1247 * that any frame less than 128 bytes in length will not be bundled,
1248 * but will instead immediately generate an interrupt. This does
1249 * not affect the current bundle in any way. Any frame that is 128
1250 * bytes or large will be bundled normally. This feature is meant
1251 * to provide immediate indication of ACK frames in a TCP environment.
1252 * Customers were seeing poor performance when a machine with CPUSaver
1253 * enabled was sending but not receiving. The delay introduced when
1254 * the ACKs were received was enough to reduce total throughput, because
1255 * the sender would sit idle until the ACK was finally seen.
1256 *
1257 * The current default is 0xFF80, which masks out the lower 7 bits.
1258 * This means that any frame which is x7F (127) bytes or smaller
1259 * will cause an immediate interrupt. Because this value must be a
1260 * bit mask, there are only a few valid values that can be used. To
1261 * turn this feature off, the driver can write the value xFFFF to the
1262 * lower word of this instruction (in the same way that the other
1263 * parameters are used). Likewise, a value of 0xF800 (2047) would
1264 * cause an interrupt to be generated for every frame, because all
1265 * standard Ethernet frames are <= 2047 bytes in length.
1266 *************************************************************************/
1267
1268 /* if you wish to disable the ucode functionality, while maintaining the
1269 * workarounds it provides, set the following defines to:
1270 * BUNDLESMALL 0
1271 * BUNDLEMAX 1
1272 * INTDELAY 1
1273 */
1274 #define BUNDLESMALL 1
1275 #define BUNDLEMAX (u16)6
1276 #define INTDELAY (u16)1536 /* 0x600 */
1277
1278 /* do not load u-code for ICH devices */
1279 if (nic->flags & ich)
1280 goto noloaducode;
1281
1282 /* Search for ucode match against h/w rev_id */
1283 for (opts = ucode_opts; opts->mac; opts++) {
1284 int i;
1285 u32 *ucode = opts->ucode;
1286 if (nic->mac != opts->mac)
1287 continue;
1288
1289 /* Insert user-tunable settings */
1290 ucode[opts->timer_dword] &= 0xFFFF0000;
1291 ucode[opts->timer_dword] |= INTDELAY;
1292 ucode[opts->bundle_dword] &= 0xFFFF0000;
1293 ucode[opts->bundle_dword] |= BUNDLEMAX;
1294 ucode[opts->min_size_dword] &= 0xFFFF0000;
1295 ucode[opts->min_size_dword] |= (BUNDLESMALL) ? 0xFFFF : 0xFF80;
1296
1297 for (i = 0; i < UCODE_SIZE; i++)
1298 cb->u.ucode[i] = cpu_to_le32(ucode[i]);
1299 cb->command = cpu_to_le16(cb_ucode | cb_el);
1300 return;
1301 }
1302
1303 noloaducode:
1304 cb->command = cpu_to_le16(cb_nop | cb_el);
1305 }
1306
1307 static inline int e100_exec_cb_wait(struct nic *nic, struct sk_buff *skb,
1308 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
1309 {
1310 int err = 0, counter = 50;
1311 struct cb *cb = nic->cb_to_clean;
1312
1313 if ((err = e100_exec_cb(nic, NULL, e100_setup_ucode)))
1314 DPRINTK(PROBE,ERR, "ucode cmd failed with error %d\n", err);
1315
1316 /* must restart cuc */
1317 nic->cuc_cmd = cuc_start;
1318
1319 /* wait for completion */
1320 e100_write_flush(nic);
1321 udelay(10);
1322
1323 /* wait for possibly (ouch) 500ms */
1324 while (!(cb->status & cpu_to_le16(cb_complete))) {
1325 msleep(10);
1326 if (!--counter) break;
1327 }
1328
1329 /* ack any interupts, something could have been set */
1330 iowrite8(~0, &nic->csr->scb.stat_ack);
1331
1332 /* if the command failed, or is not OK, notify and return */
1333 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1334 DPRINTK(PROBE,ERR, "ucode load failed\n");
1335 err = -EPERM;
1336 }
1337
1338 return err;
1339 }
1340
1341 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1342 struct sk_buff *skb)
1343 {
1344 cb->command = cpu_to_le16(cb_iaaddr);
1345 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1346 }
1347
1348 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1349 {
1350 cb->command = cpu_to_le16(cb_dump);
1351 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1352 offsetof(struct mem, dump_buf));
1353 }
1354
1355 #define NCONFIG_AUTO_SWITCH 0x0080
1356 #define MII_NSC_CONG MII_RESV1
1357 #define NSC_CONG_ENABLE 0x0100
1358 #define NSC_CONG_TXREADY 0x0400
1359 #define ADVERTISE_FC_SUPPORTED 0x0400
1360 static int e100_phy_init(struct nic *nic)
1361 {
1362 struct net_device *netdev = nic->netdev;
1363 u32 addr;
1364 u16 bmcr, stat, id_lo, id_hi, cong;
1365
1366 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1367 for(addr = 0; addr < 32; addr++) {
1368 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1369 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1370 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1371 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1372 if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1373 break;
1374 }
1375 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1376 if(addr == 32)
1377 return -EAGAIN;
1378
1379 /* Selected the phy and isolate the rest */
1380 for(addr = 0; addr < 32; addr++) {
1381 if(addr != nic->mii.phy_id) {
1382 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1383 } else {
1384 bmcr = mdio_read(netdev, addr, MII_BMCR);
1385 mdio_write(netdev, addr, MII_BMCR,
1386 bmcr & ~BMCR_ISOLATE);
1387 }
1388 }
1389
1390 /* Get phy ID */
1391 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1392 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1393 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1394 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1395
1396 /* Handle National tx phys */
1397 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1398 if((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1399 /* Disable congestion control */
1400 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1401 cong |= NSC_CONG_TXREADY;
1402 cong &= ~NSC_CONG_ENABLE;
1403 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1404 }
1405
1406 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1407 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1408 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1409 /* enable/disable MDI/MDI-X auto-switching. */
1410 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1411 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1412 }
1413
1414 return 0;
1415 }
1416
1417 static int e100_hw_init(struct nic *nic)
1418 {
1419 int err;
1420
1421 e100_hw_reset(nic);
1422
1423 DPRINTK(HW, ERR, "e100_hw_init\n");
1424 if(!in_interrupt() && (err = e100_self_test(nic)))
1425 return err;
1426
1427 if((err = e100_phy_init(nic)))
1428 return err;
1429 if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1430 return err;
1431 if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1432 return err;
1433 if ((err = e100_exec_cb_wait(nic, NULL, e100_setup_ucode)))
1434 return err;
1435 if((err = e100_exec_cb(nic, NULL, e100_configure)))
1436 return err;
1437 if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1438 return err;
1439 if((err = e100_exec_cmd(nic, cuc_dump_addr,
1440 nic->dma_addr + offsetof(struct mem, stats))))
1441 return err;
1442 if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1443 return err;
1444
1445 e100_disable_irq(nic);
1446
1447 return 0;
1448 }
1449
1450 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1451 {
1452 struct net_device *netdev = nic->netdev;
1453 struct dev_mc_list *list = netdev->mc_list;
1454 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1455
1456 cb->command = cpu_to_le16(cb_multi);
1457 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1458 for(i = 0; list && i < count; i++, list = list->next)
1459 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1460 ETH_ALEN);
1461 }
1462
1463 static void e100_set_multicast_list(struct net_device *netdev)
1464 {
1465 struct nic *nic = netdev_priv(netdev);
1466
1467 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1468 netdev->mc_count, netdev->flags);
1469
1470 if(netdev->flags & IFF_PROMISC)
1471 nic->flags |= promiscuous;
1472 else
1473 nic->flags &= ~promiscuous;
1474
1475 if(netdev->flags & IFF_ALLMULTI ||
1476 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1477 nic->flags |= multicast_all;
1478 else
1479 nic->flags &= ~multicast_all;
1480
1481 e100_exec_cb(nic, NULL, e100_configure);
1482 e100_exec_cb(nic, NULL, e100_multi);
1483 }
1484
1485 static void e100_update_stats(struct nic *nic)
1486 {
1487 struct net_device_stats *ns = &nic->net_stats;
1488 struct stats *s = &nic->mem->stats;
1489 u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1490 (nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
1491 &s->complete;
1492
1493 /* Device's stats reporting may take several microseconds to
1494 * complete, so where always waiting for results of the
1495 * previous command. */
1496
1497 if(*complete == le32_to_cpu(cuc_dump_reset_complete)) {
1498 *complete = 0;
1499 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1500 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1501 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1502 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1503 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1504 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1505 ns->collisions += nic->tx_collisions;
1506 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1507 le32_to_cpu(s->tx_lost_crs);
1508 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1509 nic->rx_over_length_errors;
1510 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1511 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1512 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1513 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1514 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1515 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1516 le32_to_cpu(s->rx_alignment_errors) +
1517 le32_to_cpu(s->rx_short_frame_errors) +
1518 le32_to_cpu(s->rx_cdt_errors);
1519 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1520 nic->tx_single_collisions +=
1521 le32_to_cpu(s->tx_single_collisions);
1522 nic->tx_multiple_collisions +=
1523 le32_to_cpu(s->tx_multiple_collisions);
1524 if(nic->mac >= mac_82558_D101_A4) {
1525 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1526 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1527 nic->rx_fc_unsupported +=
1528 le32_to_cpu(s->fc_rcv_unsupported);
1529 if(nic->mac >= mac_82559_D101M) {
1530 nic->tx_tco_frames +=
1531 le16_to_cpu(s->xmt_tco_frames);
1532 nic->rx_tco_frames +=
1533 le16_to_cpu(s->rcv_tco_frames);
1534 }
1535 }
1536 }
1537
1538
1539 if(e100_exec_cmd(nic, cuc_dump_reset, 0))
1540 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1541 }
1542
1543 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1544 {
1545 /* Adjust inter-frame-spacing (IFS) between two transmits if
1546 * we're getting collisions on a half-duplex connection. */
1547
1548 if(duplex == DUPLEX_HALF) {
1549 u32 prev = nic->adaptive_ifs;
1550 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1551
1552 if((nic->tx_frames / 32 < nic->tx_collisions) &&
1553 (nic->tx_frames > min_frames)) {
1554 if(nic->adaptive_ifs < 60)
1555 nic->adaptive_ifs += 5;
1556 } else if (nic->tx_frames < min_frames) {
1557 if(nic->adaptive_ifs >= 5)
1558 nic->adaptive_ifs -= 5;
1559 }
1560 if(nic->adaptive_ifs != prev)
1561 e100_exec_cb(nic, NULL, e100_configure);
1562 }
1563 }
1564
1565 static void e100_watchdog(unsigned long data)
1566 {
1567 struct nic *nic = (struct nic *)data;
1568 struct ethtool_cmd cmd;
1569
1570 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1571
1572 /* mii library handles link maintenance tasks */
1573
1574 mii_ethtool_gset(&nic->mii, &cmd);
1575
1576 if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1577 DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
1578 cmd.speed == SPEED_100 ? "100" : "10",
1579 cmd.duplex == DUPLEX_FULL ? "full" : "half");
1580 } else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1581 DPRINTK(LINK, INFO, "link down\n");
1582 }
1583
1584 mii_check_link(&nic->mii);
1585
1586 /* Software generated interrupt to recover from (rare) Rx
1587 * allocation failure.
1588 * Unfortunately have to use a spinlock to not re-enable interrupts
1589 * accidentally, due to hardware that shares a register between the
1590 * interrupt mask bit and the SW Interrupt generation bit */
1591 spin_lock_irq(&nic->cmd_lock);
1592 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1593 e100_write_flush(nic);
1594 spin_unlock_irq(&nic->cmd_lock);
1595
1596 e100_update_stats(nic);
1597 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1598
1599 if(nic->mac <= mac_82557_D100_C)
1600 /* Issue a multicast command to workaround a 557 lock up */
1601 e100_set_multicast_list(nic->netdev);
1602
1603 if(nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1604 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1605 nic->flags |= ich_10h_workaround;
1606 else
1607 nic->flags &= ~ich_10h_workaround;
1608
1609 mod_timer(&nic->watchdog, jiffies + E100_WATCHDOG_PERIOD);
1610 }
1611
1612 static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1613 struct sk_buff *skb)
1614 {
1615 cb->command = nic->tx_command;
1616 /* interrupt every 16 packets regardless of delay */
1617 if((nic->cbs_avail & ~15) == nic->cbs_avail)
1618 cb->command |= cpu_to_le16(cb_i);
1619 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1620 cb->u.tcb.tcb_byte_count = 0;
1621 cb->u.tcb.threshold = nic->tx_threshold;
1622 cb->u.tcb.tbd_count = 1;
1623 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1624 skb->data, skb->len, PCI_DMA_TODEVICE));
1625 /* check for mapping failure? */
1626 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1627 }
1628
1629 static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1630 {
1631 struct nic *nic = netdev_priv(netdev);
1632 int err;
1633
1634 if(nic->flags & ich_10h_workaround) {
1635 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1636 Issue a NOP command followed by a 1us delay before
1637 issuing the Tx command. */
1638 if(e100_exec_cmd(nic, cuc_nop, 0))
1639 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1640 udelay(1);
1641 }
1642
1643 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1644
1645 switch(err) {
1646 case -ENOSPC:
1647 /* We queued the skb, but now we're out of space. */
1648 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1649 netif_stop_queue(netdev);
1650 break;
1651 case -ENOMEM:
1652 /* This is a hard error - log it. */
1653 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1654 netif_stop_queue(netdev);
1655 return 1;
1656 }
1657
1658 netdev->trans_start = jiffies;
1659 return 0;
1660 }
1661
1662 static int e100_tx_clean(struct nic *nic)
1663 {
1664 struct cb *cb;
1665 int tx_cleaned = 0;
1666
1667 spin_lock(&nic->cb_lock);
1668
1669 /* Clean CBs marked complete */
1670 for(cb = nic->cb_to_clean;
1671 cb->status & cpu_to_le16(cb_complete);
1672 cb = nic->cb_to_clean = cb->next) {
1673 DPRINTK(TX_DONE, DEBUG, "cb[%d]->status = 0x%04X\n",
1674 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1675 cb->status);
1676
1677 if(likely(cb->skb != NULL)) {
1678 nic->net_stats.tx_packets++;
1679 nic->net_stats.tx_bytes += cb->skb->len;
1680
1681 pci_unmap_single(nic->pdev,
1682 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1683 le16_to_cpu(cb->u.tcb.tbd.size),
1684 PCI_DMA_TODEVICE);
1685 dev_kfree_skb_any(cb->skb);
1686 cb->skb = NULL;
1687 tx_cleaned = 1;
1688 }
1689 cb->status = 0;
1690 nic->cbs_avail++;
1691 }
1692
1693 spin_unlock(&nic->cb_lock);
1694
1695 /* Recover from running out of Tx resources in xmit_frame */
1696 if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1697 netif_wake_queue(nic->netdev);
1698
1699 return tx_cleaned;
1700 }
1701
1702 static void e100_clean_cbs(struct nic *nic)
1703 {
1704 if(nic->cbs) {
1705 while(nic->cbs_avail != nic->params.cbs.count) {
1706 struct cb *cb = nic->cb_to_clean;
1707 if(cb->skb) {
1708 pci_unmap_single(nic->pdev,
1709 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1710 le16_to_cpu(cb->u.tcb.tbd.size),
1711 PCI_DMA_TODEVICE);
1712 dev_kfree_skb(cb->skb);
1713 }
1714 nic->cb_to_clean = nic->cb_to_clean->next;
1715 nic->cbs_avail++;
1716 }
1717 pci_free_consistent(nic->pdev,
1718 sizeof(struct cb) * nic->params.cbs.count,
1719 nic->cbs, nic->cbs_dma_addr);
1720 nic->cbs = NULL;
1721 nic->cbs_avail = 0;
1722 }
1723 nic->cuc_cmd = cuc_start;
1724 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1725 nic->cbs;
1726 }
1727
1728 static int e100_alloc_cbs(struct nic *nic)
1729 {
1730 struct cb *cb;
1731 unsigned int i, count = nic->params.cbs.count;
1732
1733 nic->cuc_cmd = cuc_start;
1734 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1735 nic->cbs_avail = 0;
1736
1737 nic->cbs = pci_alloc_consistent(nic->pdev,
1738 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1739 if(!nic->cbs)
1740 return -ENOMEM;
1741
1742 for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
1743 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1744 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1745
1746 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1747 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1748 ((i+1) % count) * sizeof(struct cb));
1749 cb->skb = NULL;
1750 }
1751
1752 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1753 nic->cbs_avail = count;
1754
1755 return 0;
1756 }
1757
1758 static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1759 {
1760 if(!nic->rxs) return;
1761 if(RU_SUSPENDED != nic->ru_running) return;
1762
1763 /* handle init time starts */
1764 if(!rx) rx = nic->rxs;
1765
1766 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1767 if(rx->skb) {
1768 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1769 nic->ru_running = RU_RUNNING;
1770 }
1771 }
1772
1773 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1774 static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1775 {
1776 if(!(rx->skb = netdev_alloc_skb(nic->netdev, RFD_BUF_LEN + NET_IP_ALIGN)))
1777 return -ENOMEM;
1778
1779 /* Align, init, and map the RFD. */
1780 skb_reserve(rx->skb, NET_IP_ALIGN);
1781 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1782 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1783 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1784
1785 if(pci_dma_mapping_error(rx->dma_addr)) {
1786 dev_kfree_skb_any(rx->skb);
1787 rx->skb = NULL;
1788 rx->dma_addr = 0;
1789 return -ENOMEM;
1790 }
1791
1792 /* Link the RFD to end of RFA by linking previous RFD to
1793 * this one, and clearing EL bit of previous. */
1794 if(rx->prev->skb) {
1795 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1796 put_unaligned(cpu_to_le32(rx->dma_addr),
1797 (u32 *)&prev_rfd->link);
1798 wmb();
1799 prev_rfd->command &= ~cpu_to_le16(cb_el);
1800 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1801 sizeof(struct rfd), PCI_DMA_TODEVICE);
1802 }
1803
1804 return 0;
1805 }
1806
1807 static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1808 unsigned int *work_done, unsigned int work_to_do)
1809 {
1810 struct sk_buff *skb = rx->skb;
1811 struct rfd *rfd = (struct rfd *)skb->data;
1812 u16 rfd_status, actual_size;
1813
1814 if(unlikely(work_done && *work_done >= work_to_do))
1815 return -EAGAIN;
1816
1817 /* Need to sync before taking a peek at cb_complete bit */
1818 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1819 sizeof(struct rfd), PCI_DMA_FROMDEVICE);
1820 rfd_status = le16_to_cpu(rfd->status);
1821
1822 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1823
1824 /* If data isn't ready, nothing to indicate */
1825 if(unlikely(!(rfd_status & cb_complete)))
1826 return -ENODATA;
1827
1828 /* Get actual data size */
1829 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1830 if(unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1831 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1832
1833 /* Get data */
1834 pci_unmap_single(nic->pdev, rx->dma_addr,
1835 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1836
1837 /* this allows for a fast restart without re-enabling interrupts */
1838 if(le16_to_cpu(rfd->command) & cb_el)
1839 nic->ru_running = RU_SUSPENDED;
1840
1841 /* Pull off the RFD and put the actual data (minus eth hdr) */
1842 skb_reserve(skb, sizeof(struct rfd));
1843 skb_put(skb, actual_size);
1844 skb->protocol = eth_type_trans(skb, nic->netdev);
1845
1846 if(unlikely(!(rfd_status & cb_ok))) {
1847 /* Don't indicate if hardware indicates errors */
1848 dev_kfree_skb_any(skb);
1849 } else if(actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1850 /* Don't indicate oversized frames */
1851 nic->rx_over_length_errors++;
1852 dev_kfree_skb_any(skb);
1853 } else {
1854 nic->net_stats.rx_packets++;
1855 nic->net_stats.rx_bytes += actual_size;
1856 nic->netdev->last_rx = jiffies;
1857 netif_receive_skb(skb);
1858 if(work_done)
1859 (*work_done)++;
1860 }
1861
1862 rx->skb = NULL;
1863
1864 return 0;
1865 }
1866
1867 static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1868 unsigned int work_to_do)
1869 {
1870 struct rx *rx;
1871 int restart_required = 0;
1872 struct rx *rx_to_start = NULL;
1873
1874 /* are we already rnr? then pay attention!!! this ensures that
1875 * the state machine progression never allows a start with a
1876 * partially cleaned list, avoiding a race between hardware
1877 * and rx_to_clean when in NAPI mode */
1878 if(RU_SUSPENDED == nic->ru_running)
1879 restart_required = 1;
1880
1881 /* Indicate newly arrived packets */
1882 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1883 int err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1884 if(-EAGAIN == err) {
1885 /* hit quota so have more work to do, restart once
1886 * cleanup is complete */
1887 restart_required = 0;
1888 break;
1889 } else if(-ENODATA == err)
1890 break; /* No more to clean */
1891 }
1892
1893 /* save our starting point as the place we'll restart the receiver */
1894 if(restart_required)
1895 rx_to_start = nic->rx_to_clean;
1896
1897 /* Alloc new skbs to refill list */
1898 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1899 if(unlikely(e100_rx_alloc_skb(nic, rx)))
1900 break; /* Better luck next time (see watchdog) */
1901 }
1902
1903 if(restart_required) {
1904 // ack the rnr?
1905 writeb(stat_ack_rnr, &nic->csr->scb.stat_ack);
1906 e100_start_receiver(nic, rx_to_start);
1907 if(work_done)
1908 (*work_done)++;
1909 }
1910 }
1911
1912 static void e100_rx_clean_list(struct nic *nic)
1913 {
1914 struct rx *rx;
1915 unsigned int i, count = nic->params.rfds.count;
1916
1917 nic->ru_running = RU_UNINITIALIZED;
1918
1919 if(nic->rxs) {
1920 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1921 if(rx->skb) {
1922 pci_unmap_single(nic->pdev, rx->dma_addr,
1923 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1924 dev_kfree_skb(rx->skb);
1925 }
1926 }
1927 kfree(nic->rxs);
1928 nic->rxs = NULL;
1929 }
1930
1931 nic->rx_to_use = nic->rx_to_clean = NULL;
1932 }
1933
1934 static int e100_rx_alloc_list(struct nic *nic)
1935 {
1936 struct rx *rx;
1937 unsigned int i, count = nic->params.rfds.count;
1938
1939 nic->rx_to_use = nic->rx_to_clean = NULL;
1940 nic->ru_running = RU_UNINITIALIZED;
1941
1942 if(!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
1943 return -ENOMEM;
1944
1945 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1946 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
1947 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
1948 if(e100_rx_alloc_skb(nic, rx)) {
1949 e100_rx_clean_list(nic);
1950 return -ENOMEM;
1951 }
1952 }
1953
1954 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
1955 nic->ru_running = RU_SUSPENDED;
1956
1957 return 0;
1958 }
1959
1960 static irqreturn_t e100_intr(int irq, void *dev_id)
1961 {
1962 struct net_device *netdev = dev_id;
1963 struct nic *nic = netdev_priv(netdev);
1964 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
1965
1966 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
1967
1968 if(stat_ack == stat_ack_not_ours || /* Not our interrupt */
1969 stat_ack == stat_ack_not_present) /* Hardware is ejected */
1970 return IRQ_NONE;
1971
1972 /* Ack interrupt(s) */
1973 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
1974
1975 /* We hit Receive No Resource (RNR); restart RU after cleaning */
1976 if(stat_ack & stat_ack_rnr)
1977 nic->ru_running = RU_SUSPENDED;
1978
1979 if(likely(netif_rx_schedule_prep(netdev))) {
1980 e100_disable_irq(nic);
1981 __netif_rx_schedule(netdev);
1982 }
1983
1984 return IRQ_HANDLED;
1985 }
1986
1987 static int e100_poll(struct net_device *netdev, int *budget)
1988 {
1989 struct nic *nic = netdev_priv(netdev);
1990 unsigned int work_to_do = min(netdev->quota, *budget);
1991 unsigned int work_done = 0;
1992 int tx_cleaned;
1993
1994 e100_rx_clean(nic, &work_done, work_to_do);
1995 tx_cleaned = e100_tx_clean(nic);
1996
1997 /* If no Rx and Tx cleanup work was done, exit polling mode. */
1998 if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
1999 netif_rx_complete(netdev);
2000 e100_enable_irq(nic);
2001 return 0;
2002 }
2003
2004 *budget -= work_done;
2005 netdev->quota -= work_done;
2006
2007 return 1;
2008 }
2009
2010 #ifdef CONFIG_NET_POLL_CONTROLLER
2011 static void e100_netpoll(struct net_device *netdev)
2012 {
2013 struct nic *nic = netdev_priv(netdev);
2014
2015 e100_disable_irq(nic);
2016 e100_intr(nic->pdev->irq, netdev);
2017 e100_tx_clean(nic);
2018 e100_enable_irq(nic);
2019 }
2020 #endif
2021
2022 static struct net_device_stats *e100_get_stats(struct net_device *netdev)
2023 {
2024 struct nic *nic = netdev_priv(netdev);
2025 return &nic->net_stats;
2026 }
2027
2028 static int e100_set_mac_address(struct net_device *netdev, void *p)
2029 {
2030 struct nic *nic = netdev_priv(netdev);
2031 struct sockaddr *addr = p;
2032
2033 if (!is_valid_ether_addr(addr->sa_data))
2034 return -EADDRNOTAVAIL;
2035
2036 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2037 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2038
2039 return 0;
2040 }
2041
2042 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2043 {
2044 if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
2045 return -EINVAL;
2046 netdev->mtu = new_mtu;
2047 return 0;
2048 }
2049
2050 static int e100_asf(struct nic *nic)
2051 {
2052 /* ASF can be enabled from eeprom */
2053 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2054 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2055 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2056 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
2057 }
2058
2059 static int e100_up(struct nic *nic)
2060 {
2061 int err;
2062
2063 if((err = e100_rx_alloc_list(nic)))
2064 return err;
2065 if((err = e100_alloc_cbs(nic)))
2066 goto err_rx_clean_list;
2067 if((err = e100_hw_init(nic)))
2068 goto err_clean_cbs;
2069 e100_set_multicast_list(nic->netdev);
2070 e100_start_receiver(nic, NULL);
2071 mod_timer(&nic->watchdog, jiffies);
2072 if((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2073 nic->netdev->name, nic->netdev)))
2074 goto err_no_irq;
2075 netif_wake_queue(nic->netdev);
2076 netif_poll_enable(nic->netdev);
2077 /* enable ints _after_ enabling poll, preventing a race between
2078 * disable ints+schedule */
2079 e100_enable_irq(nic);
2080 return 0;
2081
2082 err_no_irq:
2083 del_timer_sync(&nic->watchdog);
2084 err_clean_cbs:
2085 e100_clean_cbs(nic);
2086 err_rx_clean_list:
2087 e100_rx_clean_list(nic);
2088 return err;
2089 }
2090
2091 static void e100_down(struct nic *nic)
2092 {
2093 /* wait here for poll to complete */
2094 netif_poll_disable(nic->netdev);
2095 netif_stop_queue(nic->netdev);
2096 e100_hw_reset(nic);
2097 free_irq(nic->pdev->irq, nic->netdev);
2098 del_timer_sync(&nic->watchdog);
2099 netif_carrier_off(nic->netdev);
2100 e100_clean_cbs(nic);
2101 e100_rx_clean_list(nic);
2102 }
2103
2104 static void e100_tx_timeout(struct net_device *netdev)
2105 {
2106 struct nic *nic = netdev_priv(netdev);
2107
2108 /* Reset outside of interrupt context, to avoid request_irq
2109 * in interrupt context */
2110 schedule_work(&nic->tx_timeout_task);
2111 }
2112
2113 static void e100_tx_timeout_task(struct work_struct *work)
2114 {
2115 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2116 struct net_device *netdev = nic->netdev;
2117
2118 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
2119 ioread8(&nic->csr->scb.status));
2120 e100_down(netdev_priv(netdev));
2121 e100_up(netdev_priv(netdev));
2122 }
2123
2124 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2125 {
2126 int err;
2127 struct sk_buff *skb;
2128
2129 /* Use driver resources to perform internal MAC or PHY
2130 * loopback test. A single packet is prepared and transmitted
2131 * in loopback mode, and the test passes if the received
2132 * packet compares byte-for-byte to the transmitted packet. */
2133
2134 if((err = e100_rx_alloc_list(nic)))
2135 return err;
2136 if((err = e100_alloc_cbs(nic)))
2137 goto err_clean_rx;
2138
2139 /* ICH PHY loopback is broken so do MAC loopback instead */
2140 if(nic->flags & ich && loopback_mode == lb_phy)
2141 loopback_mode = lb_mac;
2142
2143 nic->loopback = loopback_mode;
2144 if((err = e100_hw_init(nic)))
2145 goto err_loopback_none;
2146
2147 if(loopback_mode == lb_phy)
2148 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2149 BMCR_LOOPBACK);
2150
2151 e100_start_receiver(nic, NULL);
2152
2153 if(!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2154 err = -ENOMEM;
2155 goto err_loopback_none;
2156 }
2157 skb_put(skb, ETH_DATA_LEN);
2158 memset(skb->data, 0xFF, ETH_DATA_LEN);
2159 e100_xmit_frame(skb, nic->netdev);
2160
2161 msleep(10);
2162
2163 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2164 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
2165
2166 if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2167 skb->data, ETH_DATA_LEN))
2168 err = -EAGAIN;
2169
2170 err_loopback_none:
2171 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2172 nic->loopback = lb_none;
2173 e100_clean_cbs(nic);
2174 e100_hw_reset(nic);
2175 err_clean_rx:
2176 e100_rx_clean_list(nic);
2177 return err;
2178 }
2179
2180 #define MII_LED_CONTROL 0x1B
2181 static void e100_blink_led(unsigned long data)
2182 {
2183 struct nic *nic = (struct nic *)data;
2184 enum led_state {
2185 led_on = 0x01,
2186 led_off = 0x04,
2187 led_on_559 = 0x05,
2188 led_on_557 = 0x07,
2189 };
2190
2191 nic->leds = (nic->leds & led_on) ? led_off :
2192 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
2193 mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
2194 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2195 }
2196
2197 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2198 {
2199 struct nic *nic = netdev_priv(netdev);
2200 return mii_ethtool_gset(&nic->mii, cmd);
2201 }
2202
2203 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2204 {
2205 struct nic *nic = netdev_priv(netdev);
2206 int err;
2207
2208 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2209 err = mii_ethtool_sset(&nic->mii, cmd);
2210 e100_exec_cb(nic, NULL, e100_configure);
2211
2212 return err;
2213 }
2214
2215 static void e100_get_drvinfo(struct net_device *netdev,
2216 struct ethtool_drvinfo *info)
2217 {
2218 struct nic *nic = netdev_priv(netdev);
2219 strcpy(info->driver, DRV_NAME);
2220 strcpy(info->version, DRV_VERSION);
2221 strcpy(info->fw_version, "N/A");
2222 strcpy(info->bus_info, pci_name(nic->pdev));
2223 }
2224
2225 static int e100_get_regs_len(struct net_device *netdev)
2226 {
2227 struct nic *nic = netdev_priv(netdev);
2228 #define E100_PHY_REGS 0x1C
2229 #define E100_REGS_LEN 1 + E100_PHY_REGS + \
2230 sizeof(nic->mem->dump_buf) / sizeof(u32)
2231 return E100_REGS_LEN * sizeof(u32);
2232 }
2233
2234 static void e100_get_regs(struct net_device *netdev,
2235 struct ethtool_regs *regs, void *p)
2236 {
2237 struct nic *nic = netdev_priv(netdev);
2238 u32 *buff = p;
2239 int i;
2240
2241 regs->version = (1 << 24) | nic->rev_id;
2242 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2243 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2244 ioread16(&nic->csr->scb.status);
2245 for(i = E100_PHY_REGS; i >= 0; i--)
2246 buff[1 + E100_PHY_REGS - i] =
2247 mdio_read(netdev, nic->mii.phy_id, i);
2248 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2249 e100_exec_cb(nic, NULL, e100_dump);
2250 msleep(10);
2251 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2252 sizeof(nic->mem->dump_buf));
2253 }
2254
2255 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2256 {
2257 struct nic *nic = netdev_priv(netdev);
2258 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2259 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2260 }
2261
2262 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2263 {
2264 struct nic *nic = netdev_priv(netdev);
2265
2266 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2267 return -EOPNOTSUPP;
2268
2269 if(wol->wolopts)
2270 nic->flags |= wol_magic;
2271 else
2272 nic->flags &= ~wol_magic;
2273
2274 e100_exec_cb(nic, NULL, e100_configure);
2275
2276 return 0;
2277 }
2278
2279 static u32 e100_get_msglevel(struct net_device *netdev)
2280 {
2281 struct nic *nic = netdev_priv(netdev);
2282 return nic->msg_enable;
2283 }
2284
2285 static void e100_set_msglevel(struct net_device *netdev, u32 value)
2286 {
2287 struct nic *nic = netdev_priv(netdev);
2288 nic->msg_enable = value;
2289 }
2290
2291 static int e100_nway_reset(struct net_device *netdev)
2292 {
2293 struct nic *nic = netdev_priv(netdev);
2294 return mii_nway_restart(&nic->mii);
2295 }
2296
2297 static u32 e100_get_link(struct net_device *netdev)
2298 {
2299 struct nic *nic = netdev_priv(netdev);
2300 return mii_link_ok(&nic->mii);
2301 }
2302
2303 static int e100_get_eeprom_len(struct net_device *netdev)
2304 {
2305 struct nic *nic = netdev_priv(netdev);
2306 return nic->eeprom_wc << 1;
2307 }
2308
2309 #define E100_EEPROM_MAGIC 0x1234
2310 static int e100_get_eeprom(struct net_device *netdev,
2311 struct ethtool_eeprom *eeprom, u8 *bytes)
2312 {
2313 struct nic *nic = netdev_priv(netdev);
2314
2315 eeprom->magic = E100_EEPROM_MAGIC;
2316 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2317
2318 return 0;
2319 }
2320
2321 static int e100_set_eeprom(struct net_device *netdev,
2322 struct ethtool_eeprom *eeprom, u8 *bytes)
2323 {
2324 struct nic *nic = netdev_priv(netdev);
2325
2326 if(eeprom->magic != E100_EEPROM_MAGIC)
2327 return -EINVAL;
2328
2329 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2330
2331 return e100_eeprom_save(nic, eeprom->offset >> 1,
2332 (eeprom->len >> 1) + 1);
2333 }
2334
2335 static void e100_get_ringparam(struct net_device *netdev,
2336 struct ethtool_ringparam *ring)
2337 {
2338 struct nic *nic = netdev_priv(netdev);
2339 struct param_range *rfds = &nic->params.rfds;
2340 struct param_range *cbs = &nic->params.cbs;
2341
2342 ring->rx_max_pending = rfds->max;
2343 ring->tx_max_pending = cbs->max;
2344 ring->rx_mini_max_pending = 0;
2345 ring->rx_jumbo_max_pending = 0;
2346 ring->rx_pending = rfds->count;
2347 ring->tx_pending = cbs->count;
2348 ring->rx_mini_pending = 0;
2349 ring->rx_jumbo_pending = 0;
2350 }
2351
2352 static int e100_set_ringparam(struct net_device *netdev,
2353 struct ethtool_ringparam *ring)
2354 {
2355 struct nic *nic = netdev_priv(netdev);
2356 struct param_range *rfds = &nic->params.rfds;
2357 struct param_range *cbs = &nic->params.cbs;
2358
2359 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2360 return -EINVAL;
2361
2362 if(netif_running(netdev))
2363 e100_down(nic);
2364 rfds->count = max(ring->rx_pending, rfds->min);
2365 rfds->count = min(rfds->count, rfds->max);
2366 cbs->count = max(ring->tx_pending, cbs->min);
2367 cbs->count = min(cbs->count, cbs->max);
2368 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2369 rfds->count, cbs->count);
2370 if(netif_running(netdev))
2371 e100_up(nic);
2372
2373 return 0;
2374 }
2375
2376 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2377 "Link test (on/offline)",
2378 "Eeprom test (on/offline)",
2379 "Self test (offline)",
2380 "Mac loopback (offline)",
2381 "Phy loopback (offline)",
2382 };
2383 #define E100_TEST_LEN sizeof(e100_gstrings_test) / ETH_GSTRING_LEN
2384
2385 static int e100_diag_test_count(struct net_device *netdev)
2386 {
2387 return E100_TEST_LEN;
2388 }
2389
2390 static void e100_diag_test(struct net_device *netdev,
2391 struct ethtool_test *test, u64 *data)
2392 {
2393 struct ethtool_cmd cmd;
2394 struct nic *nic = netdev_priv(netdev);
2395 int i, err;
2396
2397 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2398 data[0] = !mii_link_ok(&nic->mii);
2399 data[1] = e100_eeprom_load(nic);
2400 if(test->flags & ETH_TEST_FL_OFFLINE) {
2401
2402 /* save speed, duplex & autoneg settings */
2403 err = mii_ethtool_gset(&nic->mii, &cmd);
2404
2405 if(netif_running(netdev))
2406 e100_down(nic);
2407 data[2] = e100_self_test(nic);
2408 data[3] = e100_loopback_test(nic, lb_mac);
2409 data[4] = e100_loopback_test(nic, lb_phy);
2410
2411 /* restore speed, duplex & autoneg settings */
2412 err = mii_ethtool_sset(&nic->mii, &cmd);
2413
2414 if(netif_running(netdev))
2415 e100_up(nic);
2416 }
2417 for(i = 0; i < E100_TEST_LEN; i++)
2418 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2419
2420 msleep_interruptible(4 * 1000);
2421 }
2422
2423 static int e100_phys_id(struct net_device *netdev, u32 data)
2424 {
2425 struct nic *nic = netdev_priv(netdev);
2426
2427 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2428 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2429 mod_timer(&nic->blink_timer, jiffies);
2430 msleep_interruptible(data * 1000);
2431 del_timer_sync(&nic->blink_timer);
2432 mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);
2433
2434 return 0;
2435 }
2436
2437 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2438 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2439 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2440 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2441 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2442 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2443 "tx_heartbeat_errors", "tx_window_errors",
2444 /* device-specific stats */
2445 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2446 "tx_flow_control_pause", "rx_flow_control_pause",
2447 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2448 };
2449 #define E100_NET_STATS_LEN 21
2450 #define E100_STATS_LEN sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN
2451
2452 static int e100_get_stats_count(struct net_device *netdev)
2453 {
2454 return E100_STATS_LEN;
2455 }
2456
2457 static void e100_get_ethtool_stats(struct net_device *netdev,
2458 struct ethtool_stats *stats, u64 *data)
2459 {
2460 struct nic *nic = netdev_priv(netdev);
2461 int i;
2462
2463 for(i = 0; i < E100_NET_STATS_LEN; i++)
2464 data[i] = ((unsigned long *)&nic->net_stats)[i];
2465
2466 data[i++] = nic->tx_deferred;
2467 data[i++] = nic->tx_single_collisions;
2468 data[i++] = nic->tx_multiple_collisions;
2469 data[i++] = nic->tx_fc_pause;
2470 data[i++] = nic->rx_fc_pause;
2471 data[i++] = nic->rx_fc_unsupported;
2472 data[i++] = nic->tx_tco_frames;
2473 data[i++] = nic->rx_tco_frames;
2474 }
2475
2476 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2477 {
2478 switch(stringset) {
2479 case ETH_SS_TEST:
2480 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2481 break;
2482 case ETH_SS_STATS:
2483 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2484 break;
2485 }
2486 }
2487
2488 static const struct ethtool_ops e100_ethtool_ops = {
2489 .get_settings = e100_get_settings,
2490 .set_settings = e100_set_settings,
2491 .get_drvinfo = e100_get_drvinfo,
2492 .get_regs_len = e100_get_regs_len,
2493 .get_regs = e100_get_regs,
2494 .get_wol = e100_get_wol,
2495 .set_wol = e100_set_wol,
2496 .get_msglevel = e100_get_msglevel,
2497 .set_msglevel = e100_set_msglevel,
2498 .nway_reset = e100_nway_reset,
2499 .get_link = e100_get_link,
2500 .get_eeprom_len = e100_get_eeprom_len,
2501 .get_eeprom = e100_get_eeprom,
2502 .set_eeprom = e100_set_eeprom,
2503 .get_ringparam = e100_get_ringparam,
2504 .set_ringparam = e100_set_ringparam,
2505 .self_test_count = e100_diag_test_count,
2506 .self_test = e100_diag_test,
2507 .get_strings = e100_get_strings,
2508 .phys_id = e100_phys_id,
2509 .get_stats_count = e100_get_stats_count,
2510 .get_ethtool_stats = e100_get_ethtool_stats,
2511 .get_perm_addr = ethtool_op_get_perm_addr,
2512 };
2513
2514 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2515 {
2516 struct nic *nic = netdev_priv(netdev);
2517
2518 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2519 }
2520
2521 static int e100_alloc(struct nic *nic)
2522 {
2523 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2524 &nic->dma_addr);
2525 return nic->mem ? 0 : -ENOMEM;
2526 }
2527
2528 static void e100_free(struct nic *nic)
2529 {
2530 if(nic->mem) {
2531 pci_free_consistent(nic->pdev, sizeof(struct mem),
2532 nic->mem, nic->dma_addr);
2533 nic->mem = NULL;
2534 }
2535 }
2536
2537 static int e100_open(struct net_device *netdev)
2538 {
2539 struct nic *nic = netdev_priv(netdev);
2540 int err = 0;
2541
2542 netif_carrier_off(netdev);
2543 if((err = e100_up(nic)))
2544 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2545 return err;
2546 }
2547
2548 static int e100_close(struct net_device *netdev)
2549 {
2550 e100_down(netdev_priv(netdev));
2551 return 0;
2552 }
2553
2554 static int __devinit e100_probe(struct pci_dev *pdev,
2555 const struct pci_device_id *ent)
2556 {
2557 struct net_device *netdev;
2558 struct nic *nic;
2559 int err;
2560
2561 if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2562 if(((1 << debug) - 1) & NETIF_MSG_PROBE)
2563 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2564 return -ENOMEM;
2565 }
2566
2567 netdev->open = e100_open;
2568 netdev->stop = e100_close;
2569 netdev->hard_start_xmit = e100_xmit_frame;
2570 netdev->get_stats = e100_get_stats;
2571 netdev->set_multicast_list = e100_set_multicast_list;
2572 netdev->set_mac_address = e100_set_mac_address;
2573 netdev->change_mtu = e100_change_mtu;
2574 netdev->do_ioctl = e100_do_ioctl;
2575 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2576 netdev->tx_timeout = e100_tx_timeout;
2577 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2578 netdev->poll = e100_poll;
2579 netdev->weight = E100_NAPI_WEIGHT;
2580 #ifdef CONFIG_NET_POLL_CONTROLLER
2581 netdev->poll_controller = e100_netpoll;
2582 #endif
2583 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2584
2585 nic = netdev_priv(netdev);
2586 nic->netdev = netdev;
2587 nic->pdev = pdev;
2588 nic->msg_enable = (1 << debug) - 1;
2589 pci_set_drvdata(pdev, netdev);
2590
2591 if((err = pci_enable_device(pdev))) {
2592 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2593 goto err_out_free_dev;
2594 }
2595
2596 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2597 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2598 "base address, aborting.\n");
2599 err = -ENODEV;
2600 goto err_out_disable_pdev;
2601 }
2602
2603 if((err = pci_request_regions(pdev, DRV_NAME))) {
2604 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2605 goto err_out_disable_pdev;
2606 }
2607
2608 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
2609 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2610 goto err_out_free_res;
2611 }
2612
2613 SET_MODULE_OWNER(netdev);
2614 SET_NETDEV_DEV(netdev, &pdev->dev);
2615
2616 if (use_io)
2617 DPRINTK(PROBE, INFO, "using i/o access mode\n");
2618
2619 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2620 if(!nic->csr) {
2621 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2622 err = -ENOMEM;
2623 goto err_out_free_res;
2624 }
2625
2626 if(ent->driver_data)
2627 nic->flags |= ich;
2628 else
2629 nic->flags &= ~ich;
2630
2631 e100_get_defaults(nic);
2632
2633 /* locks must be initialized before calling hw_reset */
2634 spin_lock_init(&nic->cb_lock);
2635 spin_lock_init(&nic->cmd_lock);
2636 spin_lock_init(&nic->mdio_lock);
2637
2638 /* Reset the device before pci_set_master() in case device is in some
2639 * funky state and has an interrupt pending - hint: we don't have the
2640 * interrupt handler registered yet. */
2641 e100_hw_reset(nic);
2642
2643 pci_set_master(pdev);
2644
2645 init_timer(&nic->watchdog);
2646 nic->watchdog.function = e100_watchdog;
2647 nic->watchdog.data = (unsigned long)nic;
2648 init_timer(&nic->blink_timer);
2649 nic->blink_timer.function = e100_blink_led;
2650 nic->blink_timer.data = (unsigned long)nic;
2651
2652 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2653
2654 if((err = e100_alloc(nic))) {
2655 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2656 goto err_out_iounmap;
2657 }
2658
2659 if((err = e100_eeprom_load(nic)))
2660 goto err_out_free;
2661
2662 e100_phy_init(nic);
2663
2664 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2665 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2666 if (!is_valid_ether_addr(netdev->perm_addr)) {
2667 if (!eeprom_bad_csum_allow) {
2668 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2669 "EEPROM, aborting.\n");
2670 err = -EAGAIN;
2671 goto err_out_free;
2672 } else {
2673 DPRINTK(PROBE, ERR, "Invalid MAC address from EEPROM, "
2674 "you MUST configure one.\n");
2675 }
2676 }
2677
2678 /* Wol magic packet can be enabled from eeprom */
2679 if((nic->mac >= mac_82558_D101_A4) &&
2680 (nic->eeprom[eeprom_id] & eeprom_id_wol))
2681 nic->flags |= wol_magic;
2682
2683 /* ack any pending wake events, disable PME */
2684 err = pci_enable_wake(pdev, 0, 0);
2685 if (err)
2686 DPRINTK(PROBE, ERR, "Error clearing wake event\n");
2687
2688 strcpy(netdev->name, "eth%d");
2689 if((err = register_netdev(netdev))) {
2690 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2691 goto err_out_free;
2692 }
2693
2694 DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, "
2695 "MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
2696 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0), pdev->irq,
2697 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
2698 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
2699
2700 return 0;
2701
2702 err_out_free:
2703 e100_free(nic);
2704 err_out_iounmap:
2705 pci_iounmap(pdev, nic->csr);
2706 err_out_free_res:
2707 pci_release_regions(pdev);
2708 err_out_disable_pdev:
2709 pci_disable_device(pdev);
2710 err_out_free_dev:
2711 pci_set_drvdata(pdev, NULL);
2712 free_netdev(netdev);
2713 return err;
2714 }
2715
2716 static void __devexit e100_remove(struct pci_dev *pdev)
2717 {
2718 struct net_device *netdev = pci_get_drvdata(pdev);
2719
2720 if(netdev) {
2721 struct nic *nic = netdev_priv(netdev);
2722 unregister_netdev(netdev);
2723 e100_free(nic);
2724 iounmap(nic->csr);
2725 free_netdev(netdev);
2726 pci_release_regions(pdev);
2727 pci_disable_device(pdev);
2728 pci_set_drvdata(pdev, NULL);
2729 }
2730 }
2731
2732 #ifdef CONFIG_PM
2733 static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2734 {
2735 struct net_device *netdev = pci_get_drvdata(pdev);
2736 struct nic *nic = netdev_priv(netdev);
2737
2738 if (netif_running(netdev))
2739 netif_poll_disable(nic->netdev);
2740 del_timer_sync(&nic->watchdog);
2741 netif_carrier_off(nic->netdev);
2742 netif_device_detach(netdev);
2743
2744 pci_save_state(pdev);
2745
2746 if ((nic->flags & wol_magic) | e100_asf(nic)) {
2747 pci_enable_wake(pdev, PCI_D3hot, 1);
2748 pci_enable_wake(pdev, PCI_D3cold, 1);
2749 } else {
2750 pci_enable_wake(pdev, PCI_D3hot, 0);
2751 pci_enable_wake(pdev, PCI_D3cold, 0);
2752 }
2753
2754 pci_disable_device(pdev);
2755 free_irq(pdev->irq, netdev);
2756 pci_set_power_state(pdev, PCI_D3hot);
2757
2758 return 0;
2759 }
2760
2761 static int e100_resume(struct pci_dev *pdev)
2762 {
2763 struct net_device *netdev = pci_get_drvdata(pdev);
2764 struct nic *nic = netdev_priv(netdev);
2765
2766 pci_set_power_state(pdev, PCI_D0);
2767 pci_restore_state(pdev);
2768 /* ack any pending wake events, disable PME */
2769 pci_enable_wake(pdev, 0, 0);
2770
2771 netif_device_attach(netdev);
2772 if (netif_running(netdev))
2773 e100_up(nic);
2774
2775 return 0;
2776 }
2777 #endif /* CONFIG_PM */
2778
2779 static void e100_shutdown(struct pci_dev *pdev)
2780 {
2781 struct net_device *netdev = pci_get_drvdata(pdev);
2782 struct nic *nic = netdev_priv(netdev);
2783
2784 if (netif_running(netdev))
2785 netif_poll_disable(nic->netdev);
2786 del_timer_sync(&nic->watchdog);
2787 netif_carrier_off(nic->netdev);
2788
2789 if ((nic->flags & wol_magic) | e100_asf(nic)) {
2790 pci_enable_wake(pdev, PCI_D3hot, 1);
2791 pci_enable_wake(pdev, PCI_D3cold, 1);
2792 } else {
2793 pci_enable_wake(pdev, PCI_D3hot, 0);
2794 pci_enable_wake(pdev, PCI_D3cold, 0);
2795 }
2796
2797 pci_disable_device(pdev);
2798 pci_set_power_state(pdev, PCI_D3hot);
2799 }
2800
2801 /* ------------------ PCI Error Recovery infrastructure -------------- */
2802 /**
2803 * e100_io_error_detected - called when PCI error is detected.
2804 * @pdev: Pointer to PCI device
2805 * @state: The current pci conneection state
2806 */
2807 static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2808 {
2809 struct net_device *netdev = pci_get_drvdata(pdev);
2810
2811 /* Similar to calling e100_down(), but avoids adpater I/O. */
2812 netdev->stop(netdev);
2813
2814 /* Detach; put netif into state similar to hotplug unplug. */
2815 netif_poll_enable(netdev);
2816 netif_device_detach(netdev);
2817 pci_disable_device(pdev);
2818
2819 /* Request a slot reset. */
2820 return PCI_ERS_RESULT_NEED_RESET;
2821 }
2822
2823 /**
2824 * e100_io_slot_reset - called after the pci bus has been reset.
2825 * @pdev: Pointer to PCI device
2826 *
2827 * Restart the card from scratch.
2828 */
2829 static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
2830 {
2831 struct net_device *netdev = pci_get_drvdata(pdev);
2832 struct nic *nic = netdev_priv(netdev);
2833
2834 if (pci_enable_device(pdev)) {
2835 printk(KERN_ERR "e100: Cannot re-enable PCI device after reset.\n");
2836 return PCI_ERS_RESULT_DISCONNECT;
2837 }
2838 pci_set_master(pdev);
2839
2840 /* Only one device per card can do a reset */
2841 if (0 != PCI_FUNC(pdev->devfn))
2842 return PCI_ERS_RESULT_RECOVERED;
2843 e100_hw_reset(nic);
2844 e100_phy_init(nic);
2845
2846 return PCI_ERS_RESULT_RECOVERED;
2847 }
2848
2849 /**
2850 * e100_io_resume - resume normal operations
2851 * @pdev: Pointer to PCI device
2852 *
2853 * Resume normal operations after an error recovery
2854 * sequence has been completed.
2855 */
2856 static void e100_io_resume(struct pci_dev *pdev)
2857 {
2858 struct net_device *netdev = pci_get_drvdata(pdev);
2859 struct nic *nic = netdev_priv(netdev);
2860
2861 /* ack any pending wake events, disable PME */
2862 pci_enable_wake(pdev, 0, 0);
2863
2864 netif_device_attach(netdev);
2865 if (netif_running(netdev)) {
2866 e100_open(netdev);
2867 mod_timer(&nic->watchdog, jiffies);
2868 }
2869 }
2870
2871 static struct pci_error_handlers e100_err_handler = {
2872 .error_detected = e100_io_error_detected,
2873 .slot_reset = e100_io_slot_reset,
2874 .resume = e100_io_resume,
2875 };
2876
2877 static struct pci_driver e100_driver = {
2878 .name = DRV_NAME,
2879 .id_table = e100_id_table,
2880 .probe = e100_probe,
2881 .remove = __devexit_p(e100_remove),
2882 #ifdef CONFIG_PM
2883 /* Power Management hooks */
2884 .suspend = e100_suspend,
2885 .resume = e100_resume,
2886 #endif
2887 .shutdown = e100_shutdown,
2888 .err_handler = &e100_err_handler,
2889 };
2890
2891 static int __init e100_init_module(void)
2892 {
2893 if(((1 << debug) - 1) & NETIF_MSG_DRV) {
2894 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2895 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2896 }
2897 return pci_register_driver(&e100_driver);
2898 }
2899
2900 static void __exit e100_cleanup_module(void)
2901 {
2902 pci_unregister_driver(&e100_driver);
2903 }
2904
2905 module_init(e100_init_module);
2906 module_exit(e100_cleanup_module);