2 * Copyright (C) 2006, 2007 Eugene Konev
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/moduleparam.h>
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/types.h>
28 #include <linux/delay.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/skbuff.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/phy_fixed.h>
37 #include <linux/platform_device.h>
38 #include <linux/dma-mapping.h>
40 #include <asm/atomic.h>
42 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
43 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
44 MODULE_LICENSE("GPL");
45 MODULE_ALIAS("platform:cpmac");
47 static int debug_level
= 8;
48 static int dumb_switch
;
50 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
51 module_param(debug_level
, int, 0444);
52 module_param(dumb_switch
, int, 0444);
54 MODULE_PARM_DESC(debug_level
, "Number of NETIF_MSG bits to enable");
55 MODULE_PARM_DESC(dumb_switch
, "Assume switch is not connected to MDIO bus");
57 #define CPMAC_VERSION "0.5.0"
58 /* frame size + 802.1q tag */
59 #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4)
60 #define CPMAC_QUEUES 8
62 /* Ethernet registers */
63 #define CPMAC_TX_CONTROL 0x0004
64 #define CPMAC_TX_TEARDOWN 0x0008
65 #define CPMAC_RX_CONTROL 0x0014
66 #define CPMAC_RX_TEARDOWN 0x0018
67 #define CPMAC_MBP 0x0100
68 # define MBP_RXPASSCRC 0x40000000
69 # define MBP_RXQOS 0x20000000
70 # define MBP_RXNOCHAIN 0x10000000
71 # define MBP_RXCMF 0x01000000
72 # define MBP_RXSHORT 0x00800000
73 # define MBP_RXCEF 0x00400000
74 # define MBP_RXPROMISC 0x00200000
75 # define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
76 # define MBP_RXBCAST 0x00002000
77 # define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
78 # define MBP_RXMCAST 0x00000020
79 # define MBP_MCASTCHAN(channel) ((channel) & 0x7)
80 #define CPMAC_UNICAST_ENABLE 0x0104
81 #define CPMAC_UNICAST_CLEAR 0x0108
82 #define CPMAC_MAX_LENGTH 0x010c
83 #define CPMAC_BUFFER_OFFSET 0x0110
84 #define CPMAC_MAC_CONTROL 0x0160
85 # define MAC_TXPTYPE 0x00000200
86 # define MAC_TXPACE 0x00000040
87 # define MAC_MII 0x00000020
88 # define MAC_TXFLOW 0x00000010
89 # define MAC_RXFLOW 0x00000008
90 # define MAC_MTEST 0x00000004
91 # define MAC_LOOPBACK 0x00000002
92 # define MAC_FDX 0x00000001
93 #define CPMAC_MAC_STATUS 0x0164
94 # define MAC_STATUS_QOS 0x00000004
95 # define MAC_STATUS_RXFLOW 0x00000002
96 # define MAC_STATUS_TXFLOW 0x00000001
97 #define CPMAC_TX_INT_ENABLE 0x0178
98 #define CPMAC_TX_INT_CLEAR 0x017c
99 #define CPMAC_MAC_INT_VECTOR 0x0180
100 # define MAC_INT_STATUS 0x00080000
101 # define MAC_INT_HOST 0x00040000
102 # define MAC_INT_RX 0x00020000
103 # define MAC_INT_TX 0x00010000
104 #define CPMAC_MAC_EOI_VECTOR 0x0184
105 #define CPMAC_RX_INT_ENABLE 0x0198
106 #define CPMAC_RX_INT_CLEAR 0x019c
107 #define CPMAC_MAC_INT_ENABLE 0x01a8
108 #define CPMAC_MAC_INT_CLEAR 0x01ac
109 #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
110 #define CPMAC_MAC_ADDR_MID 0x01d0
111 #define CPMAC_MAC_ADDR_HI 0x01d4
112 #define CPMAC_MAC_HASH_LO 0x01d8
113 #define CPMAC_MAC_HASH_HI 0x01dc
114 #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
115 #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
116 #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
117 #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
118 #define CPMAC_REG_END 0x0680
121 * TODO: use some of them to fill stats in cpmac_stats()
123 #define CPMAC_STATS_RX_GOOD 0x0200
124 #define CPMAC_STATS_RX_BCAST 0x0204
125 #define CPMAC_STATS_RX_MCAST 0x0208
126 #define CPMAC_STATS_RX_PAUSE 0x020c
127 #define CPMAC_STATS_RX_CRC 0x0210
128 #define CPMAC_STATS_RX_ALIGN 0x0214
129 #define CPMAC_STATS_RX_OVER 0x0218
130 #define CPMAC_STATS_RX_JABBER 0x021c
131 #define CPMAC_STATS_RX_UNDER 0x0220
132 #define CPMAC_STATS_RX_FRAG 0x0224
133 #define CPMAC_STATS_RX_FILTER 0x0228
134 #define CPMAC_STATS_RX_QOSFILTER 0x022c
135 #define CPMAC_STATS_RX_OCTETS 0x0230
137 #define CPMAC_STATS_TX_GOOD 0x0234
138 #define CPMAC_STATS_TX_BCAST 0x0238
139 #define CPMAC_STATS_TX_MCAST 0x023c
140 #define CPMAC_STATS_TX_PAUSE 0x0240
141 #define CPMAC_STATS_TX_DEFER 0x0244
142 #define CPMAC_STATS_TX_COLLISION 0x0248
143 #define CPMAC_STATS_TX_SINGLECOLL 0x024c
144 #define CPMAC_STATS_TX_MULTICOLL 0x0250
145 #define CPMAC_STATS_TX_EXCESSCOLL 0x0254
146 #define CPMAC_STATS_TX_LATECOLL 0x0258
147 #define CPMAC_STATS_TX_UNDERRUN 0x025c
148 #define CPMAC_STATS_TX_CARRIERSENSE 0x0260
149 #define CPMAC_STATS_TX_OCTETS 0x0264
151 #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
152 #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
156 #define CPMAC_MDIO_VERSION 0x0000
157 #define CPMAC_MDIO_CONTROL 0x0004
158 # define MDIOC_IDLE 0x80000000
159 # define MDIOC_ENABLE 0x40000000
160 # define MDIOC_PREAMBLE 0x00100000
161 # define MDIOC_FAULT 0x00080000
162 # define MDIOC_FAULTDETECT 0x00040000
163 # define MDIOC_INTTEST 0x00020000
164 # define MDIOC_CLKDIV(div) ((div) & 0xff)
165 #define CPMAC_MDIO_ALIVE 0x0008
166 #define CPMAC_MDIO_LINK 0x000c
167 #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
168 # define MDIO_BUSY 0x80000000
169 # define MDIO_WRITE 0x40000000
170 # define MDIO_REG(reg) (((reg) & 0x1f) << 21)
171 # define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
172 # define MDIO_DATA(data) ((data) & 0xffff)
173 #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
174 # define PHYSEL_LINKSEL 0x00000040
175 # define PHYSEL_LINKINT 0x00000020
184 #define CPMAC_SOP 0x8000
185 #define CPMAC_EOP 0x4000
186 #define CPMAC_OWN 0x2000
187 #define CPMAC_EOQ 0x1000
189 struct cpmac_desc
*next
;
190 struct cpmac_desc
*prev
;
192 dma_addr_t data_mapping
;
198 struct cpmac_desc
*rx_head
;
200 struct cpmac_desc
*desc_ring
;
203 struct mii_bus
*mii_bus
;
204 struct phy_device
*phy
;
205 char phy_name
[MII_BUS_ID_SIZE
+ 3];
206 int oldlink
, oldspeed
, oldduplex
;
208 struct net_device
*dev
;
209 struct work_struct reset_work
;
210 struct platform_device
*pdev
;
211 struct napi_struct napi
;
212 atomic_t reset_pending
;
215 static irqreturn_t
cpmac_irq(int, void *);
216 static void cpmac_hw_start(struct net_device
*dev
);
217 static void cpmac_hw_stop(struct net_device
*dev
);
218 static int cpmac_stop(struct net_device
*dev
);
219 static int cpmac_open(struct net_device
*dev
);
221 static void cpmac_dump_regs(struct net_device
*dev
)
224 struct cpmac_priv
*priv
= netdev_priv(dev
);
225 for (i
= 0; i
< CPMAC_REG_END
; i
+= 4) {
229 printk(KERN_DEBUG
"%s: reg[%p]:", dev
->name
,
232 printk(" %08x", cpmac_read(priv
->regs
, i
));
237 static void cpmac_dump_desc(struct net_device
*dev
, struct cpmac_desc
*desc
)
240 printk(KERN_DEBUG
"%s: desc[%p]:", dev
->name
, desc
);
241 for (i
= 0; i
< sizeof(*desc
) / 4; i
++)
242 printk(" %08x", ((u32
*)desc
)[i
]);
246 static void cpmac_dump_all_desc(struct net_device
*dev
)
248 struct cpmac_priv
*priv
= netdev_priv(dev
);
249 struct cpmac_desc
*dump
= priv
->rx_head
;
251 cpmac_dump_desc(dev
, dump
);
253 } while (dump
!= priv
->rx_head
);
256 static void cpmac_dump_skb(struct net_device
*dev
, struct sk_buff
*skb
)
259 printk(KERN_DEBUG
"%s: skb 0x%p, len=%d\n", dev
->name
, skb
, skb
->len
);
260 for (i
= 0; i
< skb
->len
; i
++) {
264 printk(KERN_DEBUG
"%s: data[%p]:", dev
->name
,
267 printk(" %02x", ((u8
*)skb
->data
)[i
]);
272 static int cpmac_mdio_read(struct mii_bus
*bus
, int phy_id
, int reg
)
276 while (cpmac_read(bus
->priv
, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY
)
278 cpmac_write(bus
->priv
, CPMAC_MDIO_ACCESS(0), MDIO_BUSY
| MDIO_REG(reg
) |
280 while ((val
= cpmac_read(bus
->priv
, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY
)
282 return MDIO_DATA(val
);
285 static int cpmac_mdio_write(struct mii_bus
*bus
, int phy_id
,
288 while (cpmac_read(bus
->priv
, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY
)
290 cpmac_write(bus
->priv
, CPMAC_MDIO_ACCESS(0), MDIO_BUSY
| MDIO_WRITE
|
291 MDIO_REG(reg
) | MDIO_PHY(phy_id
) | MDIO_DATA(val
));
295 static int cpmac_mdio_reset(struct mii_bus
*bus
)
297 ar7_device_reset(AR7_RESET_BIT_MDIO
);
298 cpmac_write(bus
->priv
, CPMAC_MDIO_CONTROL
, MDIOC_ENABLE
|
299 MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
303 static int mii_irqs
[PHY_MAX_ADDR
] = { PHY_POLL
, };
305 static struct mii_bus
*cpmac_mii
;
307 static int cpmac_config(struct net_device
*dev
, struct ifmap
*map
)
309 if (dev
->flags
& IFF_UP
)
312 /* Don't allow changing the I/O address */
313 if (map
->base_addr
!= dev
->base_addr
)
316 /* ignore other fields */
320 static void cpmac_set_multicast_list(struct net_device
*dev
)
322 struct dev_mc_list
*iter
;
325 u32 mbp
, bit
, hash
[2] = { 0, };
326 struct cpmac_priv
*priv
= netdev_priv(dev
);
328 mbp
= cpmac_read(priv
->regs
, CPMAC_MBP
);
329 if (dev
->flags
& IFF_PROMISC
) {
330 cpmac_write(priv
->regs
, CPMAC_MBP
, (mbp
& ~MBP_PROMISCCHAN(0)) |
333 cpmac_write(priv
->regs
, CPMAC_MBP
, mbp
& ~MBP_RXPROMISC
);
334 if (dev
->flags
& IFF_ALLMULTI
) {
335 /* enable all multicast mode */
336 cpmac_write(priv
->regs
, CPMAC_MAC_HASH_LO
, 0xffffffff);
337 cpmac_write(priv
->regs
, CPMAC_MAC_HASH_HI
, 0xffffffff);
340 * cpmac uses some strange mac address hashing
343 for (i
= 0, iter
= dev
->mc_list
; i
< dev
->mc_count
;
344 i
++, iter
= iter
->next
) {
346 tmp
= iter
->dmi_addr
[0];
347 bit
^= (tmp
>> 2) ^ (tmp
<< 4);
348 tmp
= iter
->dmi_addr
[1];
349 bit
^= (tmp
>> 4) ^ (tmp
<< 2);
350 tmp
= iter
->dmi_addr
[2];
351 bit
^= (tmp
>> 6) ^ tmp
;
352 tmp
= iter
->dmi_addr
[3];
353 bit
^= (tmp
>> 2) ^ (tmp
<< 4);
354 tmp
= iter
->dmi_addr
[4];
355 bit
^= (tmp
>> 4) ^ (tmp
<< 2);
356 tmp
= iter
->dmi_addr
[5];
357 bit
^= (tmp
>> 6) ^ tmp
;
359 hash
[bit
/ 32] |= 1 << (bit
% 32);
362 cpmac_write(priv
->regs
, CPMAC_MAC_HASH_LO
, hash
[0]);
363 cpmac_write(priv
->regs
, CPMAC_MAC_HASH_HI
, hash
[1]);
368 static struct sk_buff
*cpmac_rx_one(struct cpmac_priv
*priv
,
369 struct cpmac_desc
*desc
)
371 struct sk_buff
*skb
, *result
= NULL
;
373 if (unlikely(netif_msg_hw(priv
)))
374 cpmac_dump_desc(priv
->dev
, desc
);
375 cpmac_write(priv
->regs
, CPMAC_RX_ACK(0), (u32
)desc
->mapping
);
376 if (unlikely(!desc
->datalen
)) {
377 if (netif_msg_rx_err(priv
) && net_ratelimit())
378 printk(KERN_WARNING
"%s: rx: spurious interrupt\n",
383 skb
= netdev_alloc_skb(priv
->dev
, CPMAC_SKB_SIZE
);
386 skb_put(desc
->skb
, desc
->datalen
);
387 desc
->skb
->protocol
= eth_type_trans(desc
->skb
, priv
->dev
);
388 desc
->skb
->ip_summed
= CHECKSUM_NONE
;
389 priv
->dev
->stats
.rx_packets
++;
390 priv
->dev
->stats
.rx_bytes
+= desc
->datalen
;
392 dma_unmap_single(&priv
->dev
->dev
, desc
->data_mapping
,
393 CPMAC_SKB_SIZE
, DMA_FROM_DEVICE
);
395 desc
->data_mapping
= dma_map_single(&priv
->dev
->dev
, skb
->data
,
398 desc
->hw_data
= (u32
)desc
->data_mapping
;
399 if (unlikely(netif_msg_pktdata(priv
))) {
400 printk(KERN_DEBUG
"%s: received packet:\n",
402 cpmac_dump_skb(priv
->dev
, result
);
405 if (netif_msg_rx_err(priv
) && net_ratelimit())
407 "%s: low on skbs, dropping packet\n",
409 priv
->dev
->stats
.rx_dropped
++;
412 desc
->buflen
= CPMAC_SKB_SIZE
;
413 desc
->dataflags
= CPMAC_OWN
;
418 static int cpmac_poll(struct napi_struct
*napi
, int budget
)
421 struct cpmac_desc
*desc
, *restart
;
422 struct cpmac_priv
*priv
= container_of(napi
, struct cpmac_priv
, napi
);
423 int received
= 0, processed
= 0;
425 spin_lock(&priv
->rx_lock
);
426 if (unlikely(!priv
->rx_head
)) {
427 if (netif_msg_rx_err(priv
) && net_ratelimit())
428 printk(KERN_WARNING
"%s: rx: polling, but no queue\n",
430 spin_unlock(&priv
->rx_lock
);
435 desc
= priv
->rx_head
;
437 while (((desc
->dataflags
& CPMAC_OWN
) == 0) && (received
< budget
)) {
440 if ((desc
->dataflags
& CPMAC_EOQ
) != 0) {
441 /* The last update to eoq->hw_next didn't happen
442 * soon enough, and the receiver stopped here.
443 *Remember this descriptor so we can restart
444 * the receiver after freeing some space.
446 if (unlikely(restart
)) {
447 if (netif_msg_rx_err(priv
))
448 printk(KERN_ERR
"%s: poll found a"
449 " duplicate EOQ: %p and %p\n",
450 priv
->dev
->name
, restart
, desc
);
454 restart
= desc
->next
;
457 skb
= cpmac_rx_one(priv
, desc
);
459 netif_receive_skb(skb
);
465 if (desc
!= priv
->rx_head
) {
466 /* We freed some buffers, but not the whole ring,
467 * add what we did free to the rx list */
468 desc
->prev
->hw_next
= (u32
)0;
469 priv
->rx_head
->prev
->hw_next
= priv
->rx_head
->mapping
;
472 /* Optimization: If we did not actually process an EOQ (perhaps because
473 * of quota limits), check to see if the tail of the queue has EOQ set.
474 * We should immediately restart in that case so that the receiver can
475 * restart and run in parallel with more packet processing.
476 * This lets us handle slightly larger bursts before running
477 * out of ring space (assuming dev->weight < ring_size) */
480 (priv
->rx_head
->prev
->dataflags
& (CPMAC_OWN
|CPMAC_EOQ
))
482 (priv
->rx_head
->dataflags
& CPMAC_OWN
) != 0) {
483 /* reset EOQ so the poll loop (above) doesn't try to
484 * restart this when it eventually gets to this descriptor.
486 priv
->rx_head
->prev
->dataflags
&= ~CPMAC_EOQ
;
487 restart
= priv
->rx_head
;
491 priv
->dev
->stats
.rx_errors
++;
492 priv
->dev
->stats
.rx_fifo_errors
++;
493 if (netif_msg_rx_err(priv
) && net_ratelimit())
494 printk(KERN_WARNING
"%s: rx dma ring overrun\n",
497 if (unlikely((restart
->dataflags
& CPMAC_OWN
) == 0)) {
498 if (netif_msg_drv(priv
))
499 printk(KERN_ERR
"%s: cpmac_poll is trying to "
500 "restart rx from a descriptor that's "
502 priv
->dev
->name
, restart
);
506 cpmac_write(priv
->regs
, CPMAC_RX_PTR(0), restart
->mapping
);
509 priv
->rx_head
= desc
;
510 spin_unlock(&priv
->rx_lock
);
511 if (unlikely(netif_msg_rx_status(priv
)))
512 printk(KERN_DEBUG
"%s: poll processed %d packets\n",
513 priv
->dev
->name
, received
);
514 if (processed
== 0) {
515 /* we ran out of packets to read,
516 * revert to interrupt-driven mode */
518 cpmac_write(priv
->regs
, CPMAC_RX_INT_ENABLE
, 1);
525 /* Something went horribly wrong.
526 * Reset hardware to try to recover rather than wedging. */
528 if (netif_msg_drv(priv
)) {
529 printk(KERN_ERR
"%s: cpmac_poll is confused. "
530 "Resetting hardware\n", priv
->dev
->name
);
531 cpmac_dump_all_desc(priv
->dev
);
532 printk(KERN_DEBUG
"%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
534 cpmac_read(priv
->regs
, CPMAC_RX_PTR(0)),
535 cpmac_read(priv
->regs
, CPMAC_RX_ACK(0)));
538 spin_unlock(&priv
->rx_lock
);
540 netif_tx_stop_all_queues(priv
->dev
);
541 napi_disable(&priv
->napi
);
543 atomic_inc(&priv
->reset_pending
);
544 cpmac_hw_stop(priv
->dev
);
545 if (!schedule_work(&priv
->reset_work
))
546 atomic_dec(&priv
->reset_pending
);
551 static int cpmac_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
554 struct cpmac_desc
*desc
;
555 struct cpmac_priv
*priv
= netdev_priv(dev
);
557 if (unlikely(atomic_read(&priv
->reset_pending
)))
558 return NETDEV_TX_BUSY
;
560 if (unlikely(skb_padto(skb
, ETH_ZLEN
)))
563 len
= max(skb
->len
, ETH_ZLEN
);
564 queue
= skb_get_queue_mapping(skb
);
565 netif_stop_subqueue(dev
, queue
);
567 desc
= &priv
->desc_ring
[queue
];
568 if (unlikely(desc
->dataflags
& CPMAC_OWN
)) {
569 if (netif_msg_tx_err(priv
) && net_ratelimit())
570 printk(KERN_WARNING
"%s: tx dma ring full\n",
572 return NETDEV_TX_BUSY
;
575 spin_lock(&priv
->lock
);
576 dev
->trans_start
= jiffies
;
577 spin_unlock(&priv
->lock
);
578 desc
->dataflags
= CPMAC_SOP
| CPMAC_EOP
| CPMAC_OWN
;
580 desc
->data_mapping
= dma_map_single(&dev
->dev
, skb
->data
, len
,
582 desc
->hw_data
= (u32
)desc
->data_mapping
;
585 if (unlikely(netif_msg_tx_queued(priv
)))
586 printk(KERN_DEBUG
"%s: sending 0x%p, len=%d\n", dev
->name
, skb
,
588 if (unlikely(netif_msg_hw(priv
)))
589 cpmac_dump_desc(dev
, desc
);
590 if (unlikely(netif_msg_pktdata(priv
)))
591 cpmac_dump_skb(dev
, skb
);
592 cpmac_write(priv
->regs
, CPMAC_TX_PTR(queue
), (u32
)desc
->mapping
);
597 static void cpmac_end_xmit(struct net_device
*dev
, int queue
)
599 struct cpmac_desc
*desc
;
600 struct cpmac_priv
*priv
= netdev_priv(dev
);
602 desc
= &priv
->desc_ring
[queue
];
603 cpmac_write(priv
->regs
, CPMAC_TX_ACK(queue
), (u32
)desc
->mapping
);
604 if (likely(desc
->skb
)) {
605 spin_lock(&priv
->lock
);
606 dev
->stats
.tx_packets
++;
607 dev
->stats
.tx_bytes
+= desc
->skb
->len
;
608 spin_unlock(&priv
->lock
);
609 dma_unmap_single(&dev
->dev
, desc
->data_mapping
, desc
->skb
->len
,
612 if (unlikely(netif_msg_tx_done(priv
)))
613 printk(KERN_DEBUG
"%s: sent 0x%p, len=%d\n", dev
->name
,
614 desc
->skb
, desc
->skb
->len
);
616 dev_kfree_skb_irq(desc
->skb
);
618 if (__netif_subqueue_stopped(dev
, queue
))
619 netif_wake_subqueue(dev
, queue
);
621 if (netif_msg_tx_err(priv
) && net_ratelimit())
623 "%s: end_xmit: spurious interrupt\n", dev
->name
);
624 if (__netif_subqueue_stopped(dev
, queue
))
625 netif_wake_subqueue(dev
, queue
);
629 static void cpmac_hw_stop(struct net_device
*dev
)
632 struct cpmac_priv
*priv
= netdev_priv(dev
);
633 struct plat_cpmac_data
*pdata
= priv
->pdev
->dev
.platform_data
;
635 ar7_device_reset(pdata
->reset_bit
);
636 cpmac_write(priv
->regs
, CPMAC_RX_CONTROL
,
637 cpmac_read(priv
->regs
, CPMAC_RX_CONTROL
) & ~1);
638 cpmac_write(priv
->regs
, CPMAC_TX_CONTROL
,
639 cpmac_read(priv
->regs
, CPMAC_TX_CONTROL
) & ~1);
640 for (i
= 0; i
< 8; i
++) {
641 cpmac_write(priv
->regs
, CPMAC_TX_PTR(i
), 0);
642 cpmac_write(priv
->regs
, CPMAC_RX_PTR(i
), 0);
644 cpmac_write(priv
->regs
, CPMAC_UNICAST_CLEAR
, 0xff);
645 cpmac_write(priv
->regs
, CPMAC_RX_INT_CLEAR
, 0xff);
646 cpmac_write(priv
->regs
, CPMAC_TX_INT_CLEAR
, 0xff);
647 cpmac_write(priv
->regs
, CPMAC_MAC_INT_CLEAR
, 0xff);
648 cpmac_write(priv
->regs
, CPMAC_MAC_CONTROL
,
649 cpmac_read(priv
->regs
, CPMAC_MAC_CONTROL
) & ~MAC_MII
);
652 static void cpmac_hw_start(struct net_device
*dev
)
655 struct cpmac_priv
*priv
= netdev_priv(dev
);
656 struct plat_cpmac_data
*pdata
= priv
->pdev
->dev
.platform_data
;
658 ar7_device_reset(pdata
->reset_bit
);
659 for (i
= 0; i
< 8; i
++) {
660 cpmac_write(priv
->regs
, CPMAC_TX_PTR(i
), 0);
661 cpmac_write(priv
->regs
, CPMAC_RX_PTR(i
), 0);
663 cpmac_write(priv
->regs
, CPMAC_RX_PTR(0), priv
->rx_head
->mapping
);
665 cpmac_write(priv
->regs
, CPMAC_MBP
, MBP_RXSHORT
| MBP_RXBCAST
|
667 cpmac_write(priv
->regs
, CPMAC_BUFFER_OFFSET
, 0);
668 for (i
= 0; i
< 8; i
++)
669 cpmac_write(priv
->regs
, CPMAC_MAC_ADDR_LO(i
), dev
->dev_addr
[5]);
670 cpmac_write(priv
->regs
, CPMAC_MAC_ADDR_MID
, dev
->dev_addr
[4]);
671 cpmac_write(priv
->regs
, CPMAC_MAC_ADDR_HI
, dev
->dev_addr
[0] |
672 (dev
->dev_addr
[1] << 8) | (dev
->dev_addr
[2] << 16) |
673 (dev
->dev_addr
[3] << 24));
674 cpmac_write(priv
->regs
, CPMAC_MAX_LENGTH
, CPMAC_SKB_SIZE
);
675 cpmac_write(priv
->regs
, CPMAC_UNICAST_CLEAR
, 0xff);
676 cpmac_write(priv
->regs
, CPMAC_RX_INT_CLEAR
, 0xff);
677 cpmac_write(priv
->regs
, CPMAC_TX_INT_CLEAR
, 0xff);
678 cpmac_write(priv
->regs
, CPMAC_MAC_INT_CLEAR
, 0xff);
679 cpmac_write(priv
->regs
, CPMAC_UNICAST_ENABLE
, 1);
680 cpmac_write(priv
->regs
, CPMAC_RX_INT_ENABLE
, 1);
681 cpmac_write(priv
->regs
, CPMAC_TX_INT_ENABLE
, 0xff);
682 cpmac_write(priv
->regs
, CPMAC_MAC_INT_ENABLE
, 3);
684 cpmac_write(priv
->regs
, CPMAC_RX_CONTROL
,
685 cpmac_read(priv
->regs
, CPMAC_RX_CONTROL
) | 1);
686 cpmac_write(priv
->regs
, CPMAC_TX_CONTROL
,
687 cpmac_read(priv
->regs
, CPMAC_TX_CONTROL
) | 1);
688 cpmac_write(priv
->regs
, CPMAC_MAC_CONTROL
,
689 cpmac_read(priv
->regs
, CPMAC_MAC_CONTROL
) | MAC_MII
|
693 static void cpmac_clear_rx(struct net_device
*dev
)
695 struct cpmac_priv
*priv
= netdev_priv(dev
);
696 struct cpmac_desc
*desc
;
698 if (unlikely(!priv
->rx_head
))
700 desc
= priv
->rx_head
;
701 for (i
= 0; i
< priv
->ring_size
; i
++) {
702 if ((desc
->dataflags
& CPMAC_OWN
) == 0) {
703 if (netif_msg_rx_err(priv
) && net_ratelimit())
704 printk(KERN_WARNING
"%s: packet dropped\n",
706 if (unlikely(netif_msg_hw(priv
)))
707 cpmac_dump_desc(dev
, desc
);
708 desc
->dataflags
= CPMAC_OWN
;
709 dev
->stats
.rx_dropped
++;
711 desc
->hw_next
= desc
->next
->mapping
;
714 priv
->rx_head
->prev
->hw_next
= 0;
717 static void cpmac_clear_tx(struct net_device
*dev
)
719 struct cpmac_priv
*priv
= netdev_priv(dev
);
721 if (unlikely(!priv
->desc_ring
))
723 for (i
= 0; i
< CPMAC_QUEUES
; i
++) {
724 priv
->desc_ring
[i
].dataflags
= 0;
725 if (priv
->desc_ring
[i
].skb
) {
726 dev_kfree_skb_any(priv
->desc_ring
[i
].skb
);
727 priv
->desc_ring
[i
].skb
= NULL
;
732 static void cpmac_hw_error(struct work_struct
*work
)
734 struct cpmac_priv
*priv
=
735 container_of(work
, struct cpmac_priv
, reset_work
);
737 spin_lock(&priv
->rx_lock
);
738 cpmac_clear_rx(priv
->dev
);
739 spin_unlock(&priv
->rx_lock
);
740 cpmac_clear_tx(priv
->dev
);
741 cpmac_hw_start(priv
->dev
);
743 atomic_dec(&priv
->reset_pending
);
745 netif_tx_wake_all_queues(priv
->dev
);
746 cpmac_write(priv
->regs
, CPMAC_MAC_INT_ENABLE
, 3);
749 static void cpmac_check_status(struct net_device
*dev
)
751 struct cpmac_priv
*priv
= netdev_priv(dev
);
753 u32 macstatus
= cpmac_read(priv
->regs
, CPMAC_MAC_STATUS
);
754 int rx_channel
= (macstatus
>> 8) & 7;
755 int rx_code
= (macstatus
>> 12) & 15;
756 int tx_channel
= (macstatus
>> 16) & 7;
757 int tx_code
= (macstatus
>> 20) & 15;
759 if (rx_code
|| tx_code
) {
760 if (netif_msg_drv(priv
) && net_ratelimit()) {
761 /* Can't find any documentation on what these
762 *error codes actually are. So just log them and hope..
765 printk(KERN_WARNING
"%s: host error %d on rx "
766 "channel %d (macstatus %08x), resetting\n",
767 dev
->name
, rx_code
, rx_channel
, macstatus
);
769 printk(KERN_WARNING
"%s: host error %d on tx "
770 "channel %d (macstatus %08x), resetting\n",
771 dev
->name
, tx_code
, tx_channel
, macstatus
);
774 netif_tx_stop_all_queues(dev
);
776 if (schedule_work(&priv
->reset_work
))
777 atomic_inc(&priv
->reset_pending
);
778 if (unlikely(netif_msg_hw(priv
)))
779 cpmac_dump_regs(dev
);
781 cpmac_write(priv
->regs
, CPMAC_MAC_INT_CLEAR
, 0xff);
784 static irqreturn_t
cpmac_irq(int irq
, void *dev_id
)
786 struct net_device
*dev
= dev_id
;
787 struct cpmac_priv
*priv
;
791 priv
= netdev_priv(dev
);
793 status
= cpmac_read(priv
->regs
, CPMAC_MAC_INT_VECTOR
);
795 if (unlikely(netif_msg_intr(priv
)))
796 printk(KERN_DEBUG
"%s: interrupt status: 0x%08x\n", dev
->name
,
799 if (status
& MAC_INT_TX
)
800 cpmac_end_xmit(dev
, (status
& 7));
802 if (status
& MAC_INT_RX
) {
803 queue
= (status
>> 8) & 7;
804 if (napi_schedule_prep(&priv
->napi
)) {
805 cpmac_write(priv
->regs
, CPMAC_RX_INT_CLEAR
, 1 << queue
);
806 __napi_schedule(&priv
->napi
);
810 cpmac_write(priv
->regs
, CPMAC_MAC_EOI_VECTOR
, 0);
812 if (unlikely(status
& (MAC_INT_HOST
| MAC_INT_STATUS
)))
813 cpmac_check_status(dev
);
818 static void cpmac_tx_timeout(struct net_device
*dev
)
820 struct cpmac_priv
*priv
= netdev_priv(dev
);
822 spin_lock(&priv
->lock
);
823 dev
->stats
.tx_errors
++;
824 spin_unlock(&priv
->lock
);
825 if (netif_msg_tx_err(priv
) && net_ratelimit())
826 printk(KERN_WARNING
"%s: transmit timeout\n", dev
->name
);
828 atomic_inc(&priv
->reset_pending
);
832 atomic_dec(&priv
->reset_pending
);
834 netif_tx_wake_all_queues(priv
->dev
);
837 static int cpmac_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
839 struct cpmac_priv
*priv
= netdev_priv(dev
);
840 if (!(netif_running(dev
)))
844 if ((cmd
== SIOCGMIIPHY
) || (cmd
== SIOCGMIIREG
) ||
845 (cmd
== SIOCSMIIREG
))
846 return phy_mii_ioctl(priv
->phy
, if_mii(ifr
), cmd
);
851 static int cpmac_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
853 struct cpmac_priv
*priv
= netdev_priv(dev
);
856 return phy_ethtool_gset(priv
->phy
, cmd
);
861 static int cpmac_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
863 struct cpmac_priv
*priv
= netdev_priv(dev
);
865 if (!capable(CAP_NET_ADMIN
))
869 return phy_ethtool_sset(priv
->phy
, cmd
);
874 static void cpmac_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
876 struct cpmac_priv
*priv
= netdev_priv(dev
);
878 ring
->rx_max_pending
= 1024;
879 ring
->rx_mini_max_pending
= 1;
880 ring
->rx_jumbo_max_pending
= 1;
881 ring
->tx_max_pending
= 1;
883 ring
->rx_pending
= priv
->ring_size
;
884 ring
->rx_mini_pending
= 1;
885 ring
->rx_jumbo_pending
= 1;
886 ring
->tx_pending
= 1;
889 static int cpmac_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
891 struct cpmac_priv
*priv
= netdev_priv(dev
);
893 if (netif_running(dev
))
895 priv
->ring_size
= ring
->rx_pending
;
899 static void cpmac_get_drvinfo(struct net_device
*dev
,
900 struct ethtool_drvinfo
*info
)
902 strcpy(info
->driver
, "cpmac");
903 strcpy(info
->version
, CPMAC_VERSION
);
904 info
->fw_version
[0] = '\0';
905 sprintf(info
->bus_info
, "%s", "cpmac");
906 info
->regdump_len
= 0;
909 static const struct ethtool_ops cpmac_ethtool_ops
= {
910 .get_settings
= cpmac_get_settings
,
911 .set_settings
= cpmac_set_settings
,
912 .get_drvinfo
= cpmac_get_drvinfo
,
913 .get_link
= ethtool_op_get_link
,
914 .get_ringparam
= cpmac_get_ringparam
,
915 .set_ringparam
= cpmac_set_ringparam
,
918 static void cpmac_adjust_link(struct net_device
*dev
)
920 struct cpmac_priv
*priv
= netdev_priv(dev
);
923 spin_lock(&priv
->lock
);
924 if (priv
->phy
->link
) {
925 netif_tx_start_all_queues(dev
);
926 if (priv
->phy
->duplex
!= priv
->oldduplex
) {
928 priv
->oldduplex
= priv
->phy
->duplex
;
931 if (priv
->phy
->speed
!= priv
->oldspeed
) {
933 priv
->oldspeed
= priv
->phy
->speed
;
936 if (!priv
->oldlink
) {
940 } else if (priv
->oldlink
) {
944 priv
->oldduplex
= -1;
947 if (new_state
&& netif_msg_link(priv
) && net_ratelimit())
948 phy_print_status(priv
->phy
);
950 spin_unlock(&priv
->lock
);
953 static int cpmac_open(struct net_device
*dev
)
956 struct cpmac_priv
*priv
= netdev_priv(dev
);
957 struct resource
*mem
;
958 struct cpmac_desc
*desc
;
961 mem
= platform_get_resource_byname(priv
->pdev
, IORESOURCE_MEM
, "regs");
962 if (!request_mem_region(mem
->start
, mem
->end
- mem
->start
, dev
->name
)) {
963 if (netif_msg_drv(priv
))
964 printk(KERN_ERR
"%s: failed to request registers\n",
970 priv
->regs
= ioremap(mem
->start
, mem
->end
- mem
->start
);
972 if (netif_msg_drv(priv
))
973 printk(KERN_ERR
"%s: failed to remap registers\n",
979 size
= priv
->ring_size
+ CPMAC_QUEUES
;
980 priv
->desc_ring
= dma_alloc_coherent(&dev
->dev
,
981 sizeof(struct cpmac_desc
) * size
,
984 if (!priv
->desc_ring
) {
989 for (i
= 0; i
< size
; i
++)
990 priv
->desc_ring
[i
].mapping
= priv
->dma_ring
+ sizeof(*desc
) * i
;
992 priv
->rx_head
= &priv
->desc_ring
[CPMAC_QUEUES
];
993 for (i
= 0, desc
= priv
->rx_head
; i
< priv
->ring_size
; i
++, desc
++) {
994 skb
= netdev_alloc_skb(dev
, CPMAC_SKB_SIZE
);
995 if (unlikely(!skb
)) {
1001 desc
->data_mapping
= dma_map_single(&dev
->dev
, skb
->data
,
1004 desc
->hw_data
= (u32
)desc
->data_mapping
;
1005 desc
->buflen
= CPMAC_SKB_SIZE
;
1006 desc
->dataflags
= CPMAC_OWN
;
1007 desc
->next
= &priv
->rx_head
[(i
+ 1) % priv
->ring_size
];
1008 desc
->next
->prev
= desc
;
1009 desc
->hw_next
= (u32
)desc
->next
->mapping
;
1012 priv
->rx_head
->prev
->hw_next
= (u32
)0;
1014 if ((res
= request_irq(dev
->irq
, cpmac_irq
, IRQF_SHARED
,
1016 if (netif_msg_drv(priv
))
1017 printk(KERN_ERR
"%s: failed to obtain irq\n",
1022 atomic_set(&priv
->reset_pending
, 0);
1023 INIT_WORK(&priv
->reset_work
, cpmac_hw_error
);
1024 cpmac_hw_start(dev
);
1026 napi_enable(&priv
->napi
);
1027 priv
->phy
->state
= PHY_CHANGELINK
;
1028 phy_start(priv
->phy
);
1034 for (i
= 0; i
< priv
->ring_size
; i
++) {
1035 if (priv
->rx_head
[i
].skb
) {
1036 dma_unmap_single(&dev
->dev
,
1037 priv
->rx_head
[i
].data_mapping
,
1040 kfree_skb(priv
->rx_head
[i
].skb
);
1044 kfree(priv
->desc_ring
);
1045 iounmap(priv
->regs
);
1048 release_mem_region(mem
->start
, mem
->end
- mem
->start
);
1054 static int cpmac_stop(struct net_device
*dev
)
1057 struct cpmac_priv
*priv
= netdev_priv(dev
);
1058 struct resource
*mem
;
1060 netif_tx_stop_all_queues(dev
);
1062 cancel_work_sync(&priv
->reset_work
);
1063 napi_disable(&priv
->napi
);
1064 phy_stop(priv
->phy
);
1068 for (i
= 0; i
< 8; i
++)
1069 cpmac_write(priv
->regs
, CPMAC_TX_PTR(i
), 0);
1070 cpmac_write(priv
->regs
, CPMAC_RX_PTR(0), 0);
1071 cpmac_write(priv
->regs
, CPMAC_MBP
, 0);
1073 free_irq(dev
->irq
, dev
);
1074 iounmap(priv
->regs
);
1075 mem
= platform_get_resource_byname(priv
->pdev
, IORESOURCE_MEM
, "regs");
1076 release_mem_region(mem
->start
, mem
->end
- mem
->start
);
1077 priv
->rx_head
= &priv
->desc_ring
[CPMAC_QUEUES
];
1078 for (i
= 0; i
< priv
->ring_size
; i
++) {
1079 if (priv
->rx_head
[i
].skb
) {
1080 dma_unmap_single(&dev
->dev
,
1081 priv
->rx_head
[i
].data_mapping
,
1084 kfree_skb(priv
->rx_head
[i
].skb
);
1088 dma_free_coherent(&dev
->dev
, sizeof(struct cpmac_desc
) *
1089 (CPMAC_QUEUES
+ priv
->ring_size
),
1090 priv
->desc_ring
, priv
->dma_ring
);
1094 static const struct net_device_ops cpmac_netdev_ops
= {
1095 .ndo_open
= cpmac_open
,
1096 .ndo_stop
= cpmac_stop
,
1097 .ndo_start_xmit
= cpmac_start_xmit
,
1098 .ndo_tx_timeout
= cpmac_tx_timeout
,
1099 .ndo_set_multicast_list
= cpmac_set_multicast_list
,
1100 .ndo_do_ioctl
= cpmac_ioctl
,
1101 .ndo_set_config
= cpmac_config
,
1102 .ndo_change_mtu
= eth_change_mtu
,
1103 .ndo_validate_addr
= eth_validate_addr
,
1104 .ndo_set_mac_address
= eth_mac_addr
,
1107 static int external_switch
;
1109 static int __devinit
cpmac_probe(struct platform_device
*pdev
)
1112 char mdio_bus_id
[BUS_ID_SIZE
];
1113 struct resource
*mem
;
1114 struct cpmac_priv
*priv
;
1115 struct net_device
*dev
;
1116 struct plat_cpmac_data
*pdata
;
1118 pdata
= pdev
->dev
.platform_data
;
1120 if (external_switch
|| dumb_switch
) {
1121 strncpy(mdio_bus_id
, "0", BUS_ID_SIZE
); /* fixed phys bus */
1124 for (phy_id
= 0; phy_id
< PHY_MAX_ADDR
; phy_id
++) {
1125 if (!(pdata
->phy_mask
& (1 << phy_id
)))
1127 if (!cpmac_mii
->phy_map
[phy_id
])
1129 strncpy(mdio_bus_id
, cpmac_mii
->id
, BUS_ID_SIZE
);
1134 if (phy_id
== PHY_MAX_ADDR
) {
1135 dev_err(&pdev
->dev
, "no PHY present\n");
1139 dev
= alloc_etherdev_mq(sizeof(*priv
), CPMAC_QUEUES
);
1142 printk(KERN_ERR
"cpmac: Unable to allocate net_device\n");
1146 platform_set_drvdata(pdev
, dev
);
1147 priv
= netdev_priv(dev
);
1150 mem
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "regs");
1156 dev
->irq
= platform_get_irq_byname(pdev
, "irq");
1158 dev
->netdev_ops
= &cpmac_netdev_ops
;
1159 dev
->ethtool_ops
= &cpmac_ethtool_ops
;
1161 netif_napi_add(dev
, &priv
->napi
, cpmac_poll
, 64);
1163 spin_lock_init(&priv
->lock
);
1164 spin_lock_init(&priv
->rx_lock
);
1166 priv
->ring_size
= 64;
1167 priv
->msg_enable
= netif_msg_init(debug_level
, 0xff);
1168 memcpy(dev
->dev_addr
, pdata
->dev_addr
, sizeof(dev
->dev_addr
));
1170 snprintf(priv
->phy_name
, BUS_ID_SIZE
, PHY_ID_FMT
, mdio_bus_id
, phy_id
);
1172 priv
->phy
= phy_connect(dev
, priv
->phy_name
, &cpmac_adjust_link
, 0,
1173 PHY_INTERFACE_MODE_MII
);
1175 if (IS_ERR(priv
->phy
)) {
1176 if (netif_msg_drv(priv
))
1177 printk(KERN_ERR
"%s: Could not attach to PHY\n",
1179 return PTR_ERR(priv
->phy
);
1182 if ((rc
= register_netdev(dev
))) {
1183 printk(KERN_ERR
"cpmac: error %i registering device %s\n", rc
,
1188 if (netif_msg_probe(priv
)) {
1190 "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1191 "mac: %pM)\n", dev
->name
, (void *)mem
->start
, dev
->irq
,
1192 priv
->phy_name
, dev
->dev_addr
);
1201 static int __devexit
cpmac_remove(struct platform_device
*pdev
)
1203 struct net_device
*dev
= platform_get_drvdata(pdev
);
1204 unregister_netdev(dev
);
1209 static struct platform_driver cpmac_driver
= {
1210 .driver
.name
= "cpmac",
1211 .driver
.owner
= THIS_MODULE
,
1212 .probe
= cpmac_probe
,
1213 .remove
= __devexit_p(cpmac_remove
),
1216 int __devinit
cpmac_init(void)
1221 cpmac_mii
= mdiobus_alloc();
1222 if (cpmac_mii
== NULL
)
1225 cpmac_mii
->name
= "cpmac-mii";
1226 cpmac_mii
->read
= cpmac_mdio_read
;
1227 cpmac_mii
->write
= cpmac_mdio_write
;
1228 cpmac_mii
->reset
= cpmac_mdio_reset
;
1229 cpmac_mii
->irq
= mii_irqs
;
1231 cpmac_mii
->priv
= ioremap(AR7_REGS_MDIO
, 256);
1233 if (!cpmac_mii
->priv
) {
1234 printk(KERN_ERR
"Can't ioremap mdio registers\n");
1239 #warning FIXME: unhardcode gpio&reset bits
1240 ar7_gpio_disable(26);
1241 ar7_gpio_disable(27);
1242 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO
);
1243 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI
);
1244 ar7_device_reset(AR7_RESET_BIT_EPHY
);
1246 cpmac_mii
->reset(cpmac_mii
);
1248 for (i
= 0; i
< 300000; i
++)
1249 if ((mask
= cpmac_read(cpmac_mii
->priv
, CPMAC_MDIO_ALIVE
)))
1255 if (mask
& (mask
- 1)) {
1256 external_switch
= 1;
1260 cpmac_mii
->phy_mask
= ~(mask
| 0x80000000);
1261 snprintf(cpmac_mii
->id
, MII_BUS_ID_SIZE
, "1");
1263 res
= mdiobus_register(cpmac_mii
);
1267 res
= platform_driver_register(&cpmac_driver
);
1274 mdiobus_unregister(cpmac_mii
);
1277 iounmap(cpmac_mii
->priv
);
1280 mdiobus_free(cpmac_mii
);
1285 void __devexit
cpmac_exit(void)
1287 platform_driver_unregister(&cpmac_driver
);
1288 mdiobus_unregister(cpmac_mii
);
1289 mdiobus_free(cpmac_mii
);
1290 iounmap(cpmac_mii
->priv
);
1293 module_init(cpmac_init
);
1294 module_exit(cpmac_exit
);