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Fix common misspellings
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / chelsio / sge.c
1 /*****************************************************************************
2 * *
3 * File: sge.c *
4 * $Revision: 1.26 $ *
5 * $Date: 2005/06/21 18:29:48 $ *
6 * Description: *
7 * DMA engine. *
8 * part of the Chelsio 10Gb Ethernet Driver. *
9 * *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License, version 2, as *
12 * published by the Free Software Foundation. *
13 * *
14 * You should have received a copy of the GNU General Public License along *
15 * with this program; if not, write to the Free Software Foundation, Inc., *
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
17 * *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
19 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
21 * *
22 * http://www.chelsio.com *
23 * *
24 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
25 * All rights reserved. *
26 * *
27 * Maintainers: maintainers@chelsio.com *
28 * *
29 * Authors: Dimitrios Michailidis <dm@chelsio.com> *
30 * Tina Yang <tainay@chelsio.com> *
31 * Felix Marti <felix@chelsio.com> *
32 * Scott Bardone <sbardone@chelsio.com> *
33 * Kurt Ottaway <kottaway@chelsio.com> *
34 * Frank DiMambro <frank@chelsio.com> *
35 * *
36 * History: *
37 * *
38 ****************************************************************************/
39
40 #include "common.h"
41
42 #include <linux/types.h>
43 #include <linux/errno.h>
44 #include <linux/pci.h>
45 #include <linux/ktime.h>
46 #include <linux/netdevice.h>
47 #include <linux/etherdevice.h>
48 #include <linux/if_vlan.h>
49 #include <linux/skbuff.h>
50 #include <linux/init.h>
51 #include <linux/mm.h>
52 #include <linux/tcp.h>
53 #include <linux/ip.h>
54 #include <linux/in.h>
55 #include <linux/if_arp.h>
56 #include <linux/slab.h>
57
58 #include "cpl5_cmd.h"
59 #include "sge.h"
60 #include "regs.h"
61 #include "espi.h"
62
63 /* This belongs in if_ether.h */
64 #define ETH_P_CPL5 0xf
65
66 #define SGE_CMDQ_N 2
67 #define SGE_FREELQ_N 2
68 #define SGE_CMDQ0_E_N 1024
69 #define SGE_CMDQ1_E_N 128
70 #define SGE_FREEL_SIZE 4096
71 #define SGE_JUMBO_FREEL_SIZE 512
72 #define SGE_FREEL_REFILL_THRESH 16
73 #define SGE_RESPQ_E_N 1024
74 #define SGE_INTRTIMER_NRES 1000
75 #define SGE_RX_SM_BUF_SIZE 1536
76 #define SGE_TX_DESC_MAX_PLEN 16384
77
78 #define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4)
79
80 /*
81 * Period of the TX buffer reclaim timer. This timer does not need to run
82 * frequently as TX buffers are usually reclaimed by new TX packets.
83 */
84 #define TX_RECLAIM_PERIOD (HZ / 4)
85
86 #define M_CMD_LEN 0x7fffffff
87 #define V_CMD_LEN(v) (v)
88 #define G_CMD_LEN(v) ((v) & M_CMD_LEN)
89 #define V_CMD_GEN1(v) ((v) << 31)
90 #define V_CMD_GEN2(v) (v)
91 #define F_CMD_DATAVALID (1 << 1)
92 #define F_CMD_SOP (1 << 2)
93 #define V_CMD_EOP(v) ((v) << 3)
94
95 /*
96 * Command queue, receive buffer list, and response queue descriptors.
97 */
98 #if defined(__BIG_ENDIAN_BITFIELD)
99 struct cmdQ_e {
100 u32 addr_lo;
101 u32 len_gen;
102 u32 flags;
103 u32 addr_hi;
104 };
105
106 struct freelQ_e {
107 u32 addr_lo;
108 u32 len_gen;
109 u32 gen2;
110 u32 addr_hi;
111 };
112
113 struct respQ_e {
114 u32 Qsleeping : 4;
115 u32 Cmdq1CreditReturn : 5;
116 u32 Cmdq1DmaComplete : 5;
117 u32 Cmdq0CreditReturn : 5;
118 u32 Cmdq0DmaComplete : 5;
119 u32 FreelistQid : 2;
120 u32 CreditValid : 1;
121 u32 DataValid : 1;
122 u32 Offload : 1;
123 u32 Eop : 1;
124 u32 Sop : 1;
125 u32 GenerationBit : 1;
126 u32 BufferLength;
127 };
128 #elif defined(__LITTLE_ENDIAN_BITFIELD)
129 struct cmdQ_e {
130 u32 len_gen;
131 u32 addr_lo;
132 u32 addr_hi;
133 u32 flags;
134 };
135
136 struct freelQ_e {
137 u32 len_gen;
138 u32 addr_lo;
139 u32 addr_hi;
140 u32 gen2;
141 };
142
143 struct respQ_e {
144 u32 BufferLength;
145 u32 GenerationBit : 1;
146 u32 Sop : 1;
147 u32 Eop : 1;
148 u32 Offload : 1;
149 u32 DataValid : 1;
150 u32 CreditValid : 1;
151 u32 FreelistQid : 2;
152 u32 Cmdq0DmaComplete : 5;
153 u32 Cmdq0CreditReturn : 5;
154 u32 Cmdq1DmaComplete : 5;
155 u32 Cmdq1CreditReturn : 5;
156 u32 Qsleeping : 4;
157 } ;
158 #endif
159
160 /*
161 * SW Context Command and Freelist Queue Descriptors
162 */
163 struct cmdQ_ce {
164 struct sk_buff *skb;
165 DEFINE_DMA_UNMAP_ADDR(dma_addr);
166 DEFINE_DMA_UNMAP_LEN(dma_len);
167 };
168
169 struct freelQ_ce {
170 struct sk_buff *skb;
171 DEFINE_DMA_UNMAP_ADDR(dma_addr);
172 DEFINE_DMA_UNMAP_LEN(dma_len);
173 };
174
175 /*
176 * SW command, freelist and response rings
177 */
178 struct cmdQ {
179 unsigned long status; /* HW DMA fetch status */
180 unsigned int in_use; /* # of in-use command descriptors */
181 unsigned int size; /* # of descriptors */
182 unsigned int processed; /* total # of descs HW has processed */
183 unsigned int cleaned; /* total # of descs SW has reclaimed */
184 unsigned int stop_thres; /* SW TX queue suspend threshold */
185 u16 pidx; /* producer index (SW) */
186 u16 cidx; /* consumer index (HW) */
187 u8 genbit; /* current generation (=valid) bit */
188 u8 sop; /* is next entry start of packet? */
189 struct cmdQ_e *entries; /* HW command descriptor Q */
190 struct cmdQ_ce *centries; /* SW command context descriptor Q */
191 dma_addr_t dma_addr; /* DMA addr HW command descriptor Q */
192 spinlock_t lock; /* Lock to protect cmdQ enqueuing */
193 };
194
195 struct freelQ {
196 unsigned int credits; /* # of available RX buffers */
197 unsigned int size; /* free list capacity */
198 u16 pidx; /* producer index (SW) */
199 u16 cidx; /* consumer index (HW) */
200 u16 rx_buffer_size; /* Buffer size on this free list */
201 u16 dma_offset; /* DMA offset to align IP headers */
202 u16 recycleq_idx; /* skb recycle q to use */
203 u8 genbit; /* current generation (=valid) bit */
204 struct freelQ_e *entries; /* HW freelist descriptor Q */
205 struct freelQ_ce *centries; /* SW freelist context descriptor Q */
206 dma_addr_t dma_addr; /* DMA addr HW freelist descriptor Q */
207 };
208
209 struct respQ {
210 unsigned int credits; /* credits to be returned to SGE */
211 unsigned int size; /* # of response Q descriptors */
212 u16 cidx; /* consumer index (SW) */
213 u8 genbit; /* current generation(=valid) bit */
214 struct respQ_e *entries; /* HW response descriptor Q */
215 dma_addr_t dma_addr; /* DMA addr HW response descriptor Q */
216 };
217
218 /* Bit flags for cmdQ.status */
219 enum {
220 CMDQ_STAT_RUNNING = 1, /* fetch engine is running */
221 CMDQ_STAT_LAST_PKT_DB = 2 /* last packet rung the doorbell */
222 };
223
224 /* T204 TX SW scheduler */
225
226 /* Per T204 TX port */
227 struct sched_port {
228 unsigned int avail; /* available bits - quota */
229 unsigned int drain_bits_per_1024ns; /* drain rate */
230 unsigned int speed; /* drain rate, mbps */
231 unsigned int mtu; /* mtu size */
232 struct sk_buff_head skbq; /* pending skbs */
233 };
234
235 /* Per T204 device */
236 struct sched {
237 ktime_t last_updated; /* last time quotas were computed */
238 unsigned int max_avail; /* max bits to be sent to any port */
239 unsigned int port; /* port index (round robin ports) */
240 unsigned int num; /* num skbs in per port queues */
241 struct sched_port p[MAX_NPORTS];
242 struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */
243 };
244 static void restart_sched(unsigned long);
245
246
247 /*
248 * Main SGE data structure
249 *
250 * Interrupts are handled by a single CPU and it is likely that on a MP system
251 * the application is migrated to another CPU. In that scenario, we try to
252 * separate the RX(in irq context) and TX state in order to decrease memory
253 * contention.
254 */
255 struct sge {
256 struct adapter *adapter; /* adapter backpointer */
257 struct net_device *netdev; /* netdevice backpointer */
258 struct freelQ freelQ[SGE_FREELQ_N]; /* buffer free lists */
259 struct respQ respQ; /* response Q */
260 unsigned long stopped_tx_queues; /* bitmap of suspended Tx queues */
261 unsigned int rx_pkt_pad; /* RX padding for L2 packets */
262 unsigned int jumbo_fl; /* jumbo freelist Q index */
263 unsigned int intrtimer_nres; /* no-resource interrupt timer */
264 unsigned int fixed_intrtimer;/* non-adaptive interrupt timer */
265 struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
266 struct timer_list espibug_timer;
267 unsigned long espibug_timeout;
268 struct sk_buff *espibug_skb[MAX_NPORTS];
269 u32 sge_control; /* shadow value of sge control reg */
270 struct sge_intr_counts stats;
271 struct sge_port_stats __percpu *port_stats[MAX_NPORTS];
272 struct sched *tx_sched;
273 struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp;
274 };
275
276 static const u8 ch_mac_addr[ETH_ALEN] = {
277 0x0, 0x7, 0x43, 0x0, 0x0, 0x0
278 };
279
280 /*
281 * stop tasklet and free all pending skb's
282 */
283 static void tx_sched_stop(struct sge *sge)
284 {
285 struct sched *s = sge->tx_sched;
286 int i;
287
288 tasklet_kill(&s->sched_tsk);
289
290 for (i = 0; i < MAX_NPORTS; i++)
291 __skb_queue_purge(&s->p[s->port].skbq);
292 }
293
294 /*
295 * t1_sched_update_parms() is called when the MTU or link speed changes. It
296 * re-computes scheduler parameters to scope with the change.
297 */
298 unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port,
299 unsigned int mtu, unsigned int speed)
300 {
301 struct sched *s = sge->tx_sched;
302 struct sched_port *p = &s->p[port];
303 unsigned int max_avail_segs;
304
305 pr_debug("t1_sched_update_params mtu=%d speed=%d\n", mtu, speed);
306 if (speed)
307 p->speed = speed;
308 if (mtu)
309 p->mtu = mtu;
310
311 if (speed || mtu) {
312 unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40);
313 do_div(drain, (p->mtu + 50) * 1000);
314 p->drain_bits_per_1024ns = (unsigned int) drain;
315
316 if (p->speed < 1000)
317 p->drain_bits_per_1024ns =
318 90 * p->drain_bits_per_1024ns / 100;
319 }
320
321 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) {
322 p->drain_bits_per_1024ns -= 16;
323 s->max_avail = max(4096U, p->mtu + 16 + 14 + 4);
324 max_avail_segs = max(1U, 4096 / (p->mtu - 40));
325 } else {
326 s->max_avail = 16384;
327 max_avail_segs = max(1U, 9000 / (p->mtu - 40));
328 }
329
330 pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u "
331 "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu,
332 p->speed, s->max_avail, max_avail_segs,
333 p->drain_bits_per_1024ns);
334
335 return max_avail_segs * (p->mtu - 40);
336 }
337
338 #if 0
339
340 /*
341 * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of
342 * data that can be pushed per port.
343 */
344 void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val)
345 {
346 struct sched *s = sge->tx_sched;
347 unsigned int i;
348
349 s->max_avail = val;
350 for (i = 0; i < MAX_NPORTS; i++)
351 t1_sched_update_parms(sge, i, 0, 0);
352 }
353
354 /*
355 * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port
356 * is draining.
357 */
358 void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port,
359 unsigned int val)
360 {
361 struct sched *s = sge->tx_sched;
362 struct sched_port *p = &s->p[port];
363 p->drain_bits_per_1024ns = val * 1024 / 1000;
364 t1_sched_update_parms(sge, port, 0, 0);
365 }
366
367 #endif /* 0 */
368
369
370 /*
371 * get_clock() implements a ns clock (see ktime_get)
372 */
373 static inline ktime_t get_clock(void)
374 {
375 struct timespec ts;
376
377 ktime_get_ts(&ts);
378 return timespec_to_ktime(ts);
379 }
380
381 /*
382 * tx_sched_init() allocates resources and does basic initialization.
383 */
384 static int tx_sched_init(struct sge *sge)
385 {
386 struct sched *s;
387 int i;
388
389 s = kzalloc(sizeof (struct sched), GFP_KERNEL);
390 if (!s)
391 return -ENOMEM;
392
393 pr_debug("tx_sched_init\n");
394 tasklet_init(&s->sched_tsk, restart_sched, (unsigned long) sge);
395 sge->tx_sched = s;
396
397 for (i = 0; i < MAX_NPORTS; i++) {
398 skb_queue_head_init(&s->p[i].skbq);
399 t1_sched_update_parms(sge, i, 1500, 1000);
400 }
401
402 return 0;
403 }
404
405 /*
406 * sched_update_avail() computes the delta since the last time it was called
407 * and updates the per port quota (number of bits that can be sent to the any
408 * port).
409 */
410 static inline int sched_update_avail(struct sge *sge)
411 {
412 struct sched *s = sge->tx_sched;
413 ktime_t now = get_clock();
414 unsigned int i;
415 long long delta_time_ns;
416
417 delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated));
418
419 pr_debug("sched_update_avail delta=%lld\n", delta_time_ns);
420 if (delta_time_ns < 15000)
421 return 0;
422
423 for (i = 0; i < MAX_NPORTS; i++) {
424 struct sched_port *p = &s->p[i];
425 unsigned int delta_avail;
426
427 delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13;
428 p->avail = min(p->avail + delta_avail, s->max_avail);
429 }
430
431 s->last_updated = now;
432
433 return 1;
434 }
435
436 /*
437 * sched_skb() is called from two different places. In the tx path, any
438 * packet generating load on an output port will call sched_skb()
439 * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq
440 * context (skb == NULL).
441 * The scheduler only returns a skb (which will then be sent) if the
442 * length of the skb is <= the current quota of the output port.
443 */
444 static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb,
445 unsigned int credits)
446 {
447 struct sched *s = sge->tx_sched;
448 struct sk_buff_head *skbq;
449 unsigned int i, len, update = 1;
450
451 pr_debug("sched_skb %p\n", skb);
452 if (!skb) {
453 if (!s->num)
454 return NULL;
455 } else {
456 skbq = &s->p[skb->dev->if_port].skbq;
457 __skb_queue_tail(skbq, skb);
458 s->num++;
459 skb = NULL;
460 }
461
462 if (credits < MAX_SKB_FRAGS + 1)
463 goto out;
464
465 again:
466 for (i = 0; i < MAX_NPORTS; i++) {
467 s->port = (s->port + 1) & (MAX_NPORTS - 1);
468 skbq = &s->p[s->port].skbq;
469
470 skb = skb_peek(skbq);
471
472 if (!skb)
473 continue;
474
475 len = skb->len;
476 if (len <= s->p[s->port].avail) {
477 s->p[s->port].avail -= len;
478 s->num--;
479 __skb_unlink(skb, skbq);
480 goto out;
481 }
482 skb = NULL;
483 }
484
485 if (update-- && sched_update_avail(sge))
486 goto again;
487
488 out:
489 /* If there are more pending skbs, we use the hardware to schedule us
490 * again.
491 */
492 if (s->num && !skb) {
493 struct cmdQ *q = &sge->cmdQ[0];
494 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
495 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
496 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
497 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
498 }
499 }
500 pr_debug("sched_skb ret %p\n", skb);
501
502 return skb;
503 }
504
505 /*
506 * PIO to indicate that memory mapped Q contains valid descriptor(s).
507 */
508 static inline void doorbell_pio(struct adapter *adapter, u32 val)
509 {
510 wmb();
511 writel(val, adapter->regs + A_SG_DOORBELL);
512 }
513
514 /*
515 * Frees all RX buffers on the freelist Q. The caller must make sure that
516 * the SGE is turned off before calling this function.
517 */
518 static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q)
519 {
520 unsigned int cidx = q->cidx;
521
522 while (q->credits--) {
523 struct freelQ_ce *ce = &q->centries[cidx];
524
525 pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr),
526 dma_unmap_len(ce, dma_len),
527 PCI_DMA_FROMDEVICE);
528 dev_kfree_skb(ce->skb);
529 ce->skb = NULL;
530 if (++cidx == q->size)
531 cidx = 0;
532 }
533 }
534
535 /*
536 * Free RX free list and response queue resources.
537 */
538 static void free_rx_resources(struct sge *sge)
539 {
540 struct pci_dev *pdev = sge->adapter->pdev;
541 unsigned int size, i;
542
543 if (sge->respQ.entries) {
544 size = sizeof(struct respQ_e) * sge->respQ.size;
545 pci_free_consistent(pdev, size, sge->respQ.entries,
546 sge->respQ.dma_addr);
547 }
548
549 for (i = 0; i < SGE_FREELQ_N; i++) {
550 struct freelQ *q = &sge->freelQ[i];
551
552 if (q->centries) {
553 free_freelQ_buffers(pdev, q);
554 kfree(q->centries);
555 }
556 if (q->entries) {
557 size = sizeof(struct freelQ_e) * q->size;
558 pci_free_consistent(pdev, size, q->entries,
559 q->dma_addr);
560 }
561 }
562 }
563
564 /*
565 * Allocates basic RX resources, consisting of memory mapped freelist Qs and a
566 * response queue.
567 */
568 static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
569 {
570 struct pci_dev *pdev = sge->adapter->pdev;
571 unsigned int size, i;
572
573 for (i = 0; i < SGE_FREELQ_N; i++) {
574 struct freelQ *q = &sge->freelQ[i];
575
576 q->genbit = 1;
577 q->size = p->freelQ_size[i];
578 q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN;
579 size = sizeof(struct freelQ_e) * q->size;
580 q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr);
581 if (!q->entries)
582 goto err_no_mem;
583
584 size = sizeof(struct freelQ_ce) * q->size;
585 q->centries = kzalloc(size, GFP_KERNEL);
586 if (!q->centries)
587 goto err_no_mem;
588 }
589
590 /*
591 * Calculate the buffer sizes for the two free lists. FL0 accommodates
592 * regular sized Ethernet frames, FL1 is sized not to exceed 16K,
593 * including all the sk_buff overhead.
594 *
595 * Note: For T2 FL0 and FL1 are reversed.
596 */
597 sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE +
598 sizeof(struct cpl_rx_data) +
599 sge->freelQ[!sge->jumbo_fl].dma_offset;
600
601 size = (16 * 1024) -
602 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
603
604 sge->freelQ[sge->jumbo_fl].rx_buffer_size = size;
605
606 /*
607 * Setup which skb recycle Q should be used when recycling buffers from
608 * each free list.
609 */
610 sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0;
611 sge->freelQ[sge->jumbo_fl].recycleq_idx = 1;
612
613 sge->respQ.genbit = 1;
614 sge->respQ.size = SGE_RESPQ_E_N;
615 sge->respQ.credits = 0;
616 size = sizeof(struct respQ_e) * sge->respQ.size;
617 sge->respQ.entries =
618 pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr);
619 if (!sge->respQ.entries)
620 goto err_no_mem;
621 return 0;
622
623 err_no_mem:
624 free_rx_resources(sge);
625 return -ENOMEM;
626 }
627
628 /*
629 * Reclaims n TX descriptors and frees the buffers associated with them.
630 */
631 static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n)
632 {
633 struct cmdQ_ce *ce;
634 struct pci_dev *pdev = sge->adapter->pdev;
635 unsigned int cidx = q->cidx;
636
637 q->in_use -= n;
638 ce = &q->centries[cidx];
639 while (n--) {
640 if (likely(dma_unmap_len(ce, dma_len))) {
641 pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr),
642 dma_unmap_len(ce, dma_len),
643 PCI_DMA_TODEVICE);
644 if (q->sop)
645 q->sop = 0;
646 }
647 if (ce->skb) {
648 dev_kfree_skb_any(ce->skb);
649 q->sop = 1;
650 }
651 ce++;
652 if (++cidx == q->size) {
653 cidx = 0;
654 ce = q->centries;
655 }
656 }
657 q->cidx = cidx;
658 }
659
660 /*
661 * Free TX resources.
662 *
663 * Assumes that SGE is stopped and all interrupts are disabled.
664 */
665 static void free_tx_resources(struct sge *sge)
666 {
667 struct pci_dev *pdev = sge->adapter->pdev;
668 unsigned int size, i;
669
670 for (i = 0; i < SGE_CMDQ_N; i++) {
671 struct cmdQ *q = &sge->cmdQ[i];
672
673 if (q->centries) {
674 if (q->in_use)
675 free_cmdQ_buffers(sge, q, q->in_use);
676 kfree(q->centries);
677 }
678 if (q->entries) {
679 size = sizeof(struct cmdQ_e) * q->size;
680 pci_free_consistent(pdev, size, q->entries,
681 q->dma_addr);
682 }
683 }
684 }
685
686 /*
687 * Allocates basic TX resources, consisting of memory mapped command Qs.
688 */
689 static int alloc_tx_resources(struct sge *sge, struct sge_params *p)
690 {
691 struct pci_dev *pdev = sge->adapter->pdev;
692 unsigned int size, i;
693
694 for (i = 0; i < SGE_CMDQ_N; i++) {
695 struct cmdQ *q = &sge->cmdQ[i];
696
697 q->genbit = 1;
698 q->sop = 1;
699 q->size = p->cmdQ_size[i];
700 q->in_use = 0;
701 q->status = 0;
702 q->processed = q->cleaned = 0;
703 q->stop_thres = 0;
704 spin_lock_init(&q->lock);
705 size = sizeof(struct cmdQ_e) * q->size;
706 q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr);
707 if (!q->entries)
708 goto err_no_mem;
709
710 size = sizeof(struct cmdQ_ce) * q->size;
711 q->centries = kzalloc(size, GFP_KERNEL);
712 if (!q->centries)
713 goto err_no_mem;
714 }
715
716 /*
717 * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE
718 * only. For queue 0 set the stop threshold so we can handle one more
719 * packet from each port, plus reserve an additional 24 entries for
720 * Ethernet packets only. Queue 1 never suspends nor do we reserve
721 * space for Ethernet packets.
722 */
723 sge->cmdQ[0].stop_thres = sge->adapter->params.nports *
724 (MAX_SKB_FRAGS + 1);
725 return 0;
726
727 err_no_mem:
728 free_tx_resources(sge);
729 return -ENOMEM;
730 }
731
732 static inline void setup_ring_params(struct adapter *adapter, u64 addr,
733 u32 size, int base_reg_lo,
734 int base_reg_hi, int size_reg)
735 {
736 writel((u32)addr, adapter->regs + base_reg_lo);
737 writel(addr >> 32, adapter->regs + base_reg_hi);
738 writel(size, adapter->regs + size_reg);
739 }
740
741 /*
742 * Enable/disable VLAN acceleration.
743 */
744 void t1_set_vlan_accel(struct adapter *adapter, int on_off)
745 {
746 struct sge *sge = adapter->sge;
747
748 sge->sge_control &= ~F_VLAN_XTRACT;
749 if (on_off)
750 sge->sge_control |= F_VLAN_XTRACT;
751 if (adapter->open_device_map) {
752 writel(sge->sge_control, adapter->regs + A_SG_CONTROL);
753 readl(adapter->regs + A_SG_CONTROL); /* flush */
754 }
755 }
756
757 /*
758 * Programs the various SGE registers. However, the engine is not yet enabled,
759 * but sge->sge_control is setup and ready to go.
760 */
761 static void configure_sge(struct sge *sge, struct sge_params *p)
762 {
763 struct adapter *ap = sge->adapter;
764
765 writel(0, ap->regs + A_SG_CONTROL);
766 setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size,
767 A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE);
768 setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size,
769 A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE);
770 setup_ring_params(ap, sge->freelQ[0].dma_addr,
771 sge->freelQ[0].size, A_SG_FL0BASELWR,
772 A_SG_FL0BASEUPR, A_SG_FL0SIZE);
773 setup_ring_params(ap, sge->freelQ[1].dma_addr,
774 sge->freelQ[1].size, A_SG_FL1BASELWR,
775 A_SG_FL1BASEUPR, A_SG_FL1SIZE);
776
777 /* The threshold comparison uses <. */
778 writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD);
779
780 setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size,
781 A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE);
782 writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT);
783
784 sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE |
785 F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE |
786 V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE |
787 V_RX_PKT_OFFSET(sge->rx_pkt_pad);
788
789 #if defined(__BIG_ENDIAN_BITFIELD)
790 sge->sge_control |= F_ENABLE_BIG_ENDIAN;
791 #endif
792
793 /* Initialize no-resource timer */
794 sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap);
795
796 t1_sge_set_coalesce_params(sge, p);
797 }
798
799 /*
800 * Return the payload capacity of the jumbo free-list buffers.
801 */
802 static inline unsigned int jumbo_payload_capacity(const struct sge *sge)
803 {
804 return sge->freelQ[sge->jumbo_fl].rx_buffer_size -
805 sge->freelQ[sge->jumbo_fl].dma_offset -
806 sizeof(struct cpl_rx_data);
807 }
808
809 /*
810 * Frees all SGE related resources and the sge structure itself
811 */
812 void t1_sge_destroy(struct sge *sge)
813 {
814 int i;
815
816 for_each_port(sge->adapter, i)
817 free_percpu(sge->port_stats[i]);
818
819 kfree(sge->tx_sched);
820 free_tx_resources(sge);
821 free_rx_resources(sge);
822 kfree(sge);
823 }
824
825 /*
826 * Allocates new RX buffers on the freelist Q (and tracks them on the freelist
827 * context Q) until the Q is full or alloc_skb fails.
828 *
829 * It is possible that the generation bits already match, indicating that the
830 * buffer is already valid and nothing needs to be done. This happens when we
831 * copied a received buffer into a new sk_buff during the interrupt processing.
832 *
833 * If the SGE doesn't automatically align packets properly (!sge->rx_pkt_pad),
834 * we specify a RX_OFFSET in order to make sure that the IP header is 4B
835 * aligned.
836 */
837 static void refill_free_list(struct sge *sge, struct freelQ *q)
838 {
839 struct pci_dev *pdev = sge->adapter->pdev;
840 struct freelQ_ce *ce = &q->centries[q->pidx];
841 struct freelQ_e *e = &q->entries[q->pidx];
842 unsigned int dma_len = q->rx_buffer_size - q->dma_offset;
843
844 while (q->credits < q->size) {
845 struct sk_buff *skb;
846 dma_addr_t mapping;
847
848 skb = alloc_skb(q->rx_buffer_size, GFP_ATOMIC);
849 if (!skb)
850 break;
851
852 skb_reserve(skb, q->dma_offset);
853 mapping = pci_map_single(pdev, skb->data, dma_len,
854 PCI_DMA_FROMDEVICE);
855 skb_reserve(skb, sge->rx_pkt_pad);
856
857 ce->skb = skb;
858 dma_unmap_addr_set(ce, dma_addr, mapping);
859 dma_unmap_len_set(ce, dma_len, dma_len);
860 e->addr_lo = (u32)mapping;
861 e->addr_hi = (u64)mapping >> 32;
862 e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit);
863 wmb();
864 e->gen2 = V_CMD_GEN2(q->genbit);
865
866 e++;
867 ce++;
868 if (++q->pidx == q->size) {
869 q->pidx = 0;
870 q->genbit ^= 1;
871 ce = q->centries;
872 e = q->entries;
873 }
874 q->credits++;
875 }
876 }
877
878 /*
879 * Calls refill_free_list for both free lists. If we cannot fill at least 1/4
880 * of both rings, we go into 'few interrupt mode' in order to give the system
881 * time to free up resources.
882 */
883 static void freelQs_empty(struct sge *sge)
884 {
885 struct adapter *adapter = sge->adapter;
886 u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE);
887 u32 irqholdoff_reg;
888
889 refill_free_list(sge, &sge->freelQ[0]);
890 refill_free_list(sge, &sge->freelQ[1]);
891
892 if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) &&
893 sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) {
894 irq_reg |= F_FL_EXHAUSTED;
895 irqholdoff_reg = sge->fixed_intrtimer;
896 } else {
897 /* Clear the F_FL_EXHAUSTED interrupts for now */
898 irq_reg &= ~F_FL_EXHAUSTED;
899 irqholdoff_reg = sge->intrtimer_nres;
900 }
901 writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER);
902 writel(irq_reg, adapter->regs + A_SG_INT_ENABLE);
903
904 /* We reenable the Qs to force a freelist GTS interrupt later */
905 doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE);
906 }
907
908 #define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA)
909 #define SGE_INT_FATAL (F_RESPQ_OVERFLOW | F_PACKET_TOO_BIG | F_PACKET_MISMATCH)
910 #define SGE_INT_ENABLE (F_RESPQ_EXHAUSTED | F_RESPQ_OVERFLOW | \
911 F_FL_EXHAUSTED | F_PACKET_TOO_BIG | F_PACKET_MISMATCH)
912
913 /*
914 * Disable SGE Interrupts
915 */
916 void t1_sge_intr_disable(struct sge *sge)
917 {
918 u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
919
920 writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
921 writel(0, sge->adapter->regs + A_SG_INT_ENABLE);
922 }
923
924 /*
925 * Enable SGE interrupts.
926 */
927 void t1_sge_intr_enable(struct sge *sge)
928 {
929 u32 en = SGE_INT_ENABLE;
930 u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
931
932 if (sge->adapter->flags & TSO_CAPABLE)
933 en &= ~F_PACKET_TOO_BIG;
934 writel(en, sge->adapter->regs + A_SG_INT_ENABLE);
935 writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
936 }
937
938 /*
939 * Clear SGE interrupts.
940 */
941 void t1_sge_intr_clear(struct sge *sge)
942 {
943 writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE);
944 writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE);
945 }
946
947 /*
948 * SGE 'Error' interrupt handler
949 */
950 int t1_sge_intr_error_handler(struct sge *sge)
951 {
952 struct adapter *adapter = sge->adapter;
953 u32 cause = readl(adapter->regs + A_SG_INT_CAUSE);
954
955 if (adapter->flags & TSO_CAPABLE)
956 cause &= ~F_PACKET_TOO_BIG;
957 if (cause & F_RESPQ_EXHAUSTED)
958 sge->stats.respQ_empty++;
959 if (cause & F_RESPQ_OVERFLOW) {
960 sge->stats.respQ_overflow++;
961 pr_alert("%s: SGE response queue overflow\n",
962 adapter->name);
963 }
964 if (cause & F_FL_EXHAUSTED) {
965 sge->stats.freelistQ_empty++;
966 freelQs_empty(sge);
967 }
968 if (cause & F_PACKET_TOO_BIG) {
969 sge->stats.pkt_too_big++;
970 pr_alert("%s: SGE max packet size exceeded\n",
971 adapter->name);
972 }
973 if (cause & F_PACKET_MISMATCH) {
974 sge->stats.pkt_mismatch++;
975 pr_alert("%s: SGE packet mismatch\n", adapter->name);
976 }
977 if (cause & SGE_INT_FATAL)
978 t1_fatal_err(adapter);
979
980 writel(cause, adapter->regs + A_SG_INT_CAUSE);
981 return 0;
982 }
983
984 const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge)
985 {
986 return &sge->stats;
987 }
988
989 void t1_sge_get_port_stats(const struct sge *sge, int port,
990 struct sge_port_stats *ss)
991 {
992 int cpu;
993
994 memset(ss, 0, sizeof(*ss));
995 for_each_possible_cpu(cpu) {
996 struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu);
997
998 ss->rx_cso_good += st->rx_cso_good;
999 ss->tx_cso += st->tx_cso;
1000 ss->tx_tso += st->tx_tso;
1001 ss->tx_need_hdrroom += st->tx_need_hdrroom;
1002 ss->vlan_xtract += st->vlan_xtract;
1003 ss->vlan_insert += st->vlan_insert;
1004 }
1005 }
1006
1007 /**
1008 * recycle_fl_buf - recycle a free list buffer
1009 * @fl: the free list
1010 * @idx: index of buffer to recycle
1011 *
1012 * Recycles the specified buffer on the given free list by adding it at
1013 * the next available slot on the list.
1014 */
1015 static void recycle_fl_buf(struct freelQ *fl, int idx)
1016 {
1017 struct freelQ_e *from = &fl->entries[idx];
1018 struct freelQ_e *to = &fl->entries[fl->pidx];
1019
1020 fl->centries[fl->pidx] = fl->centries[idx];
1021 to->addr_lo = from->addr_lo;
1022 to->addr_hi = from->addr_hi;
1023 to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit);
1024 wmb();
1025 to->gen2 = V_CMD_GEN2(fl->genbit);
1026 fl->credits++;
1027
1028 if (++fl->pidx == fl->size) {
1029 fl->pidx = 0;
1030 fl->genbit ^= 1;
1031 }
1032 }
1033
1034 static int copybreak __read_mostly = 256;
1035 module_param(copybreak, int, 0);
1036 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
1037
1038 /**
1039 * get_packet - return the next ingress packet buffer
1040 * @pdev: the PCI device that received the packet
1041 * @fl: the SGE free list holding the packet
1042 * @len: the actual packet length, excluding any SGE padding
1043 *
1044 * Get the next packet from a free list and complete setup of the
1045 * sk_buff. If the packet is small we make a copy and recycle the
1046 * original buffer, otherwise we use the original buffer itself. If a
1047 * positive drop threshold is supplied packets are dropped and their
1048 * buffers recycled if (a) the number of remaining buffers is under the
1049 * threshold and the packet is too big to copy, or (b) the packet should
1050 * be copied but there is no memory for the copy.
1051 */
1052 static inline struct sk_buff *get_packet(struct pci_dev *pdev,
1053 struct freelQ *fl, unsigned int len)
1054 {
1055 struct sk_buff *skb;
1056 const struct freelQ_ce *ce = &fl->centries[fl->cidx];
1057
1058 if (len < copybreak) {
1059 skb = alloc_skb(len + 2, GFP_ATOMIC);
1060 if (!skb)
1061 goto use_orig_buf;
1062
1063 skb_reserve(skb, 2); /* align IP header */
1064 skb_put(skb, len);
1065 pci_dma_sync_single_for_cpu(pdev,
1066 dma_unmap_addr(ce, dma_addr),
1067 dma_unmap_len(ce, dma_len),
1068 PCI_DMA_FROMDEVICE);
1069 skb_copy_from_linear_data(ce->skb, skb->data, len);
1070 pci_dma_sync_single_for_device(pdev,
1071 dma_unmap_addr(ce, dma_addr),
1072 dma_unmap_len(ce, dma_len),
1073 PCI_DMA_FROMDEVICE);
1074 recycle_fl_buf(fl, fl->cidx);
1075 return skb;
1076 }
1077
1078 use_orig_buf:
1079 if (fl->credits < 2) {
1080 recycle_fl_buf(fl, fl->cidx);
1081 return NULL;
1082 }
1083
1084 pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr),
1085 dma_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
1086 skb = ce->skb;
1087 prefetch(skb->data);
1088
1089 skb_put(skb, len);
1090 return skb;
1091 }
1092
1093 /**
1094 * unexpected_offload - handle an unexpected offload packet
1095 * @adapter: the adapter
1096 * @fl: the free list that received the packet
1097 *
1098 * Called when we receive an unexpected offload packet (e.g., the TOE
1099 * function is disabled or the card is a NIC). Prints a message and
1100 * recycles the buffer.
1101 */
1102 static void unexpected_offload(struct adapter *adapter, struct freelQ *fl)
1103 {
1104 struct freelQ_ce *ce = &fl->centries[fl->cidx];
1105 struct sk_buff *skb = ce->skb;
1106
1107 pci_dma_sync_single_for_cpu(adapter->pdev, dma_unmap_addr(ce, dma_addr),
1108 dma_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
1109 pr_err("%s: unexpected offload packet, cmd %u\n",
1110 adapter->name, *skb->data);
1111 recycle_fl_buf(fl, fl->cidx);
1112 }
1113
1114 /*
1115 * T1/T2 SGE limits the maximum DMA size per TX descriptor to
1116 * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the
1117 * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner.
1118 * Note that the *_large_page_tx_descs stuff will be optimized out when
1119 * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN.
1120 *
1121 * compute_large_page_descs() computes how many additional descriptors are
1122 * required to break down the stack's request.
1123 */
1124 static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb)
1125 {
1126 unsigned int count = 0;
1127
1128 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1129 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
1130 unsigned int i, len = skb_headlen(skb);
1131 while (len > SGE_TX_DESC_MAX_PLEN) {
1132 count++;
1133 len -= SGE_TX_DESC_MAX_PLEN;
1134 }
1135 for (i = 0; nfrags--; i++) {
1136 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1137 len = frag->size;
1138 while (len > SGE_TX_DESC_MAX_PLEN) {
1139 count++;
1140 len -= SGE_TX_DESC_MAX_PLEN;
1141 }
1142 }
1143 }
1144 return count;
1145 }
1146
1147 /*
1148 * Write a cmdQ entry.
1149 *
1150 * Since this function writes the 'flags' field, it must not be used to
1151 * write the first cmdQ entry.
1152 */
1153 static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping,
1154 unsigned int len, unsigned int gen,
1155 unsigned int eop)
1156 {
1157 BUG_ON(len > SGE_TX_DESC_MAX_PLEN);
1158
1159 e->addr_lo = (u32)mapping;
1160 e->addr_hi = (u64)mapping >> 32;
1161 e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen);
1162 e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen);
1163 }
1164
1165 /*
1166 * See comment for previous function.
1167 *
1168 * write_tx_descs_large_page() writes additional SGE tx descriptors if
1169 * *desc_len exceeds HW's capability.
1170 */
1171 static inline unsigned int write_large_page_tx_descs(unsigned int pidx,
1172 struct cmdQ_e **e,
1173 struct cmdQ_ce **ce,
1174 unsigned int *gen,
1175 dma_addr_t *desc_mapping,
1176 unsigned int *desc_len,
1177 unsigned int nfrags,
1178 struct cmdQ *q)
1179 {
1180 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1181 struct cmdQ_e *e1 = *e;
1182 struct cmdQ_ce *ce1 = *ce;
1183
1184 while (*desc_len > SGE_TX_DESC_MAX_PLEN) {
1185 *desc_len -= SGE_TX_DESC_MAX_PLEN;
1186 write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN,
1187 *gen, nfrags == 0 && *desc_len == 0);
1188 ce1->skb = NULL;
1189 dma_unmap_len_set(ce1, dma_len, 0);
1190 *desc_mapping += SGE_TX_DESC_MAX_PLEN;
1191 if (*desc_len) {
1192 ce1++;
1193 e1++;
1194 if (++pidx == q->size) {
1195 pidx = 0;
1196 *gen ^= 1;
1197 ce1 = q->centries;
1198 e1 = q->entries;
1199 }
1200 }
1201 }
1202 *e = e1;
1203 *ce = ce1;
1204 }
1205 return pidx;
1206 }
1207
1208 /*
1209 * Write the command descriptors to transmit the given skb starting at
1210 * descriptor pidx with the given generation.
1211 */
1212 static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb,
1213 unsigned int pidx, unsigned int gen,
1214 struct cmdQ *q)
1215 {
1216 dma_addr_t mapping, desc_mapping;
1217 struct cmdQ_e *e, *e1;
1218 struct cmdQ_ce *ce;
1219 unsigned int i, flags, first_desc_len, desc_len,
1220 nfrags = skb_shinfo(skb)->nr_frags;
1221
1222 e = e1 = &q->entries[pidx];
1223 ce = &q->centries[pidx];
1224
1225 mapping = pci_map_single(adapter->pdev, skb->data,
1226 skb_headlen(skb), PCI_DMA_TODEVICE);
1227
1228 desc_mapping = mapping;
1229 desc_len = skb_headlen(skb);
1230
1231 flags = F_CMD_DATAVALID | F_CMD_SOP |
1232 V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) |
1233 V_CMD_GEN2(gen);
1234 first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ?
1235 desc_len : SGE_TX_DESC_MAX_PLEN;
1236 e->addr_lo = (u32)desc_mapping;
1237 e->addr_hi = (u64)desc_mapping >> 32;
1238 e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen);
1239 ce->skb = NULL;
1240 dma_unmap_len_set(ce, dma_len, 0);
1241
1242 if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN &&
1243 desc_len > SGE_TX_DESC_MAX_PLEN) {
1244 desc_mapping += first_desc_len;
1245 desc_len -= first_desc_len;
1246 e1++;
1247 ce++;
1248 if (++pidx == q->size) {
1249 pidx = 0;
1250 gen ^= 1;
1251 e1 = q->entries;
1252 ce = q->centries;
1253 }
1254 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1255 &desc_mapping, &desc_len,
1256 nfrags, q);
1257
1258 if (likely(desc_len))
1259 write_tx_desc(e1, desc_mapping, desc_len, gen,
1260 nfrags == 0);
1261 }
1262
1263 ce->skb = NULL;
1264 dma_unmap_addr_set(ce, dma_addr, mapping);
1265 dma_unmap_len_set(ce, dma_len, skb_headlen(skb));
1266
1267 for (i = 0; nfrags--; i++) {
1268 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1269 e1++;
1270 ce++;
1271 if (++pidx == q->size) {
1272 pidx = 0;
1273 gen ^= 1;
1274 e1 = q->entries;
1275 ce = q->centries;
1276 }
1277
1278 mapping = pci_map_page(adapter->pdev, frag->page,
1279 frag->page_offset, frag->size,
1280 PCI_DMA_TODEVICE);
1281 desc_mapping = mapping;
1282 desc_len = frag->size;
1283
1284 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1285 &desc_mapping, &desc_len,
1286 nfrags, q);
1287 if (likely(desc_len))
1288 write_tx_desc(e1, desc_mapping, desc_len, gen,
1289 nfrags == 0);
1290 ce->skb = NULL;
1291 dma_unmap_addr_set(ce, dma_addr, mapping);
1292 dma_unmap_len_set(ce, dma_len, frag->size);
1293 }
1294 ce->skb = skb;
1295 wmb();
1296 e->flags = flags;
1297 }
1298
1299 /*
1300 * Clean up completed Tx buffers.
1301 */
1302 static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q)
1303 {
1304 unsigned int reclaim = q->processed - q->cleaned;
1305
1306 if (reclaim) {
1307 pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n",
1308 q->processed, q->cleaned);
1309 free_cmdQ_buffers(sge, q, reclaim);
1310 q->cleaned += reclaim;
1311 }
1312 }
1313
1314 /*
1315 * Called from tasklet. Checks the scheduler for any
1316 * pending skbs that can be sent.
1317 */
1318 static void restart_sched(unsigned long arg)
1319 {
1320 struct sge *sge = (struct sge *) arg;
1321 struct adapter *adapter = sge->adapter;
1322 struct cmdQ *q = &sge->cmdQ[0];
1323 struct sk_buff *skb;
1324 unsigned int credits, queued_skb = 0;
1325
1326 spin_lock(&q->lock);
1327 reclaim_completed_tx(sge, q);
1328
1329 credits = q->size - q->in_use;
1330 pr_debug("restart_sched credits=%d\n", credits);
1331 while ((skb = sched_skb(sge, NULL, credits)) != NULL) {
1332 unsigned int genbit, pidx, count;
1333 count = 1 + skb_shinfo(skb)->nr_frags;
1334 count += compute_large_page_tx_descs(skb);
1335 q->in_use += count;
1336 genbit = q->genbit;
1337 pidx = q->pidx;
1338 q->pidx += count;
1339 if (q->pidx >= q->size) {
1340 q->pidx -= q->size;
1341 q->genbit ^= 1;
1342 }
1343 write_tx_descs(adapter, skb, pidx, genbit, q);
1344 credits = q->size - q->in_use;
1345 queued_skb = 1;
1346 }
1347
1348 if (queued_skb) {
1349 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1350 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1351 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1352 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1353 }
1354 }
1355 spin_unlock(&q->lock);
1356 }
1357
1358 /**
1359 * sge_rx - process an ingress ethernet packet
1360 * @sge: the sge structure
1361 * @fl: the free list that contains the packet buffer
1362 * @len: the packet length
1363 *
1364 * Process an ingress ethernet pakcet and deliver it to the stack.
1365 */
1366 static void sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len)
1367 {
1368 struct sk_buff *skb;
1369 const struct cpl_rx_pkt *p;
1370 struct adapter *adapter = sge->adapter;
1371 struct sge_port_stats *st;
1372
1373 skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad);
1374 if (unlikely(!skb)) {
1375 sge->stats.rx_drops++;
1376 return;
1377 }
1378
1379 p = (const struct cpl_rx_pkt *) skb->data;
1380 if (p->iff >= adapter->params.nports) {
1381 kfree_skb(skb);
1382 return;
1383 }
1384 __skb_pull(skb, sizeof(*p));
1385
1386 st = this_cpu_ptr(sge->port_stats[p->iff]);
1387
1388 skb->protocol = eth_type_trans(skb, adapter->port[p->iff].dev);
1389 if ((adapter->flags & RX_CSUM_ENABLED) && p->csum == 0xffff &&
1390 skb->protocol == htons(ETH_P_IP) &&
1391 (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) {
1392 ++st->rx_cso_good;
1393 skb->ip_summed = CHECKSUM_UNNECESSARY;
1394 } else
1395 skb_checksum_none_assert(skb);
1396
1397 if (unlikely(adapter->vlan_grp && p->vlan_valid)) {
1398 st->vlan_xtract++;
1399 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp,
1400 ntohs(p->vlan));
1401 } else
1402 netif_receive_skb(skb);
1403 }
1404
1405 /*
1406 * Returns true if a command queue has enough available descriptors that
1407 * we can resume Tx operation after temporarily disabling its packet queue.
1408 */
1409 static inline int enough_free_Tx_descs(const struct cmdQ *q)
1410 {
1411 unsigned int r = q->processed - q->cleaned;
1412
1413 return q->in_use - r < (q->size >> 1);
1414 }
1415
1416 /*
1417 * Called when sufficient space has become available in the SGE command queues
1418 * after the Tx packet schedulers have been suspended to restart the Tx path.
1419 */
1420 static void restart_tx_queues(struct sge *sge)
1421 {
1422 struct adapter *adap = sge->adapter;
1423 int i;
1424
1425 if (!enough_free_Tx_descs(&sge->cmdQ[0]))
1426 return;
1427
1428 for_each_port(adap, i) {
1429 struct net_device *nd = adap->port[i].dev;
1430
1431 if (test_and_clear_bit(nd->if_port, &sge->stopped_tx_queues) &&
1432 netif_running(nd)) {
1433 sge->stats.cmdQ_restarted[2]++;
1434 netif_wake_queue(nd);
1435 }
1436 }
1437 }
1438
1439 /*
1440 * update_tx_info is called from the interrupt handler/NAPI to return cmdQ0
1441 * information.
1442 */
1443 static unsigned int update_tx_info(struct adapter *adapter,
1444 unsigned int flags,
1445 unsigned int pr0)
1446 {
1447 struct sge *sge = adapter->sge;
1448 struct cmdQ *cmdq = &sge->cmdQ[0];
1449
1450 cmdq->processed += pr0;
1451 if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) {
1452 freelQs_empty(sge);
1453 flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE);
1454 }
1455 if (flags & F_CMDQ0_ENABLE) {
1456 clear_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1457
1458 if (cmdq->cleaned + cmdq->in_use != cmdq->processed &&
1459 !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) {
1460 set_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1461 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1462 }
1463 if (sge->tx_sched)
1464 tasklet_hi_schedule(&sge->tx_sched->sched_tsk);
1465
1466 flags &= ~F_CMDQ0_ENABLE;
1467 }
1468
1469 if (unlikely(sge->stopped_tx_queues != 0))
1470 restart_tx_queues(sge);
1471
1472 return flags;
1473 }
1474
1475 /*
1476 * Process SGE responses, up to the supplied budget. Returns the number of
1477 * responses processed. A negative budget is effectively unlimited.
1478 */
1479 static int process_responses(struct adapter *adapter, int budget)
1480 {
1481 struct sge *sge = adapter->sge;
1482 struct respQ *q = &sge->respQ;
1483 struct respQ_e *e = &q->entries[q->cidx];
1484 int done = 0;
1485 unsigned int flags = 0;
1486 unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1487
1488 while (done < budget && e->GenerationBit == q->genbit) {
1489 flags |= e->Qsleeping;
1490
1491 cmdq_processed[0] += e->Cmdq0CreditReturn;
1492 cmdq_processed[1] += e->Cmdq1CreditReturn;
1493
1494 /* We batch updates to the TX side to avoid cacheline
1495 * ping-pong of TX state information on MP where the sender
1496 * might run on a different CPU than this function...
1497 */
1498 if (unlikely((flags & F_CMDQ0_ENABLE) || cmdq_processed[0] > 64)) {
1499 flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1500 cmdq_processed[0] = 0;
1501 }
1502
1503 if (unlikely(cmdq_processed[1] > 16)) {
1504 sge->cmdQ[1].processed += cmdq_processed[1];
1505 cmdq_processed[1] = 0;
1506 }
1507
1508 if (likely(e->DataValid)) {
1509 struct freelQ *fl = &sge->freelQ[e->FreelistQid];
1510
1511 BUG_ON(!e->Sop || !e->Eop);
1512 if (unlikely(e->Offload))
1513 unexpected_offload(adapter, fl);
1514 else
1515 sge_rx(sge, fl, e->BufferLength);
1516
1517 ++done;
1518
1519 /*
1520 * Note: this depends on each packet consuming a
1521 * single free-list buffer; cf. the BUG above.
1522 */
1523 if (++fl->cidx == fl->size)
1524 fl->cidx = 0;
1525 prefetch(fl->centries[fl->cidx].skb);
1526
1527 if (unlikely(--fl->credits <
1528 fl->size - SGE_FREEL_REFILL_THRESH))
1529 refill_free_list(sge, fl);
1530 } else
1531 sge->stats.pure_rsps++;
1532
1533 e++;
1534 if (unlikely(++q->cidx == q->size)) {
1535 q->cidx = 0;
1536 q->genbit ^= 1;
1537 e = q->entries;
1538 }
1539 prefetch(e);
1540
1541 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1542 writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1543 q->credits = 0;
1544 }
1545 }
1546
1547 flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1548 sge->cmdQ[1].processed += cmdq_processed[1];
1549
1550 return done;
1551 }
1552
1553 static inline int responses_pending(const struct adapter *adapter)
1554 {
1555 const struct respQ *Q = &adapter->sge->respQ;
1556 const struct respQ_e *e = &Q->entries[Q->cidx];
1557
1558 return e->GenerationBit == Q->genbit;
1559 }
1560
1561 /*
1562 * A simpler version of process_responses() that handles only pure (i.e.,
1563 * non data-carrying) responses. Such respones are too light-weight to justify
1564 * calling a softirq when using NAPI, so we handle them specially in hard
1565 * interrupt context. The function is called with a pointer to a response,
1566 * which the caller must ensure is a valid pure response. Returns 1 if it
1567 * encounters a valid data-carrying response, 0 otherwise.
1568 */
1569 static int process_pure_responses(struct adapter *adapter)
1570 {
1571 struct sge *sge = adapter->sge;
1572 struct respQ *q = &sge->respQ;
1573 struct respQ_e *e = &q->entries[q->cidx];
1574 const struct freelQ *fl = &sge->freelQ[e->FreelistQid];
1575 unsigned int flags = 0;
1576 unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1577
1578 prefetch(fl->centries[fl->cidx].skb);
1579 if (e->DataValid)
1580 return 1;
1581
1582 do {
1583 flags |= e->Qsleeping;
1584
1585 cmdq_processed[0] += e->Cmdq0CreditReturn;
1586 cmdq_processed[1] += e->Cmdq1CreditReturn;
1587
1588 e++;
1589 if (unlikely(++q->cidx == q->size)) {
1590 q->cidx = 0;
1591 q->genbit ^= 1;
1592 e = q->entries;
1593 }
1594 prefetch(e);
1595
1596 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1597 writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1598 q->credits = 0;
1599 }
1600 sge->stats.pure_rsps++;
1601 } while (e->GenerationBit == q->genbit && !e->DataValid);
1602
1603 flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1604 sge->cmdQ[1].processed += cmdq_processed[1];
1605
1606 return e->GenerationBit == q->genbit;
1607 }
1608
1609 /*
1610 * Handler for new data events when using NAPI. This does not need any locking
1611 * or protection from interrupts as data interrupts are off at this point and
1612 * other adapter interrupts do not interfere.
1613 */
1614 int t1_poll(struct napi_struct *napi, int budget)
1615 {
1616 struct adapter *adapter = container_of(napi, struct adapter, napi);
1617 int work_done = process_responses(adapter, budget);
1618
1619 if (likely(work_done < budget)) {
1620 napi_complete(napi);
1621 writel(adapter->sge->respQ.cidx,
1622 adapter->regs + A_SG_SLEEPING);
1623 }
1624 return work_done;
1625 }
1626
1627 irqreturn_t t1_interrupt(int irq, void *data)
1628 {
1629 struct adapter *adapter = data;
1630 struct sge *sge = adapter->sge;
1631 int handled;
1632
1633 if (likely(responses_pending(adapter))) {
1634 writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE);
1635
1636 if (napi_schedule_prep(&adapter->napi)) {
1637 if (process_pure_responses(adapter))
1638 __napi_schedule(&adapter->napi);
1639 else {
1640 /* no data, no NAPI needed */
1641 writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING);
1642 /* undo schedule_prep */
1643 napi_enable(&adapter->napi);
1644 }
1645 }
1646 return IRQ_HANDLED;
1647 }
1648
1649 spin_lock(&adapter->async_lock);
1650 handled = t1_slow_intr_handler(adapter);
1651 spin_unlock(&adapter->async_lock);
1652
1653 if (!handled)
1654 sge->stats.unhandled_irqs++;
1655
1656 return IRQ_RETVAL(handled != 0);
1657 }
1658
1659 /*
1660 * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it.
1661 *
1662 * The code figures out how many entries the sk_buff will require in the
1663 * cmdQ and updates the cmdQ data structure with the state once the enqueue
1664 * has complete. Then, it doesn't access the global structure anymore, but
1665 * uses the corresponding fields on the stack. In conjunction with a spinlock
1666 * around that code, we can make the function reentrant without holding the
1667 * lock when we actually enqueue (which might be expensive, especially on
1668 * architectures with IO MMUs).
1669 *
1670 * This runs with softirqs disabled.
1671 */
1672 static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1673 unsigned int qid, struct net_device *dev)
1674 {
1675 struct sge *sge = adapter->sge;
1676 struct cmdQ *q = &sge->cmdQ[qid];
1677 unsigned int credits, pidx, genbit, count, use_sched_skb = 0;
1678
1679 if (!spin_trylock(&q->lock))
1680 return NETDEV_TX_LOCKED;
1681
1682 reclaim_completed_tx(sge, q);
1683
1684 pidx = q->pidx;
1685 credits = q->size - q->in_use;
1686 count = 1 + skb_shinfo(skb)->nr_frags;
1687 count += compute_large_page_tx_descs(skb);
1688
1689 /* Ethernet packet */
1690 if (unlikely(credits < count)) {
1691 if (!netif_queue_stopped(dev)) {
1692 netif_stop_queue(dev);
1693 set_bit(dev->if_port, &sge->stopped_tx_queues);
1694 sge->stats.cmdQ_full[2]++;
1695 pr_err("%s: Tx ring full while queue awake!\n",
1696 adapter->name);
1697 }
1698 spin_unlock(&q->lock);
1699 return NETDEV_TX_BUSY;
1700 }
1701
1702 if (unlikely(credits - count < q->stop_thres)) {
1703 netif_stop_queue(dev);
1704 set_bit(dev->if_port, &sge->stopped_tx_queues);
1705 sge->stats.cmdQ_full[2]++;
1706 }
1707
1708 /* T204 cmdQ0 skbs that are destined for a certain port have to go
1709 * through the scheduler.
1710 */
1711 if (sge->tx_sched && !qid && skb->dev) {
1712 use_sched:
1713 use_sched_skb = 1;
1714 /* Note that the scheduler might return a different skb than
1715 * the one passed in.
1716 */
1717 skb = sched_skb(sge, skb, credits);
1718 if (!skb) {
1719 spin_unlock(&q->lock);
1720 return NETDEV_TX_OK;
1721 }
1722 pidx = q->pidx;
1723 count = 1 + skb_shinfo(skb)->nr_frags;
1724 count += compute_large_page_tx_descs(skb);
1725 }
1726
1727 q->in_use += count;
1728 genbit = q->genbit;
1729 pidx = q->pidx;
1730 q->pidx += count;
1731 if (q->pidx >= q->size) {
1732 q->pidx -= q->size;
1733 q->genbit ^= 1;
1734 }
1735 spin_unlock(&q->lock);
1736
1737 write_tx_descs(adapter, skb, pidx, genbit, q);
1738
1739 /*
1740 * We always ring the doorbell for cmdQ1. For cmdQ0, we only ring
1741 * the doorbell if the Q is asleep. There is a natural race, where
1742 * the hardware is going to sleep just after we checked, however,
1743 * then the interrupt handler will detect the outstanding TX packet
1744 * and ring the doorbell for us.
1745 */
1746 if (qid)
1747 doorbell_pio(adapter, F_CMDQ1_ENABLE);
1748 else {
1749 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1750 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1751 set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1752 writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1753 }
1754 }
1755
1756 if (use_sched_skb) {
1757 if (spin_trylock(&q->lock)) {
1758 credits = q->size - q->in_use;
1759 skb = NULL;
1760 goto use_sched;
1761 }
1762 }
1763 return NETDEV_TX_OK;
1764 }
1765
1766 #define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14))
1767
1768 /*
1769 * eth_hdr_len - return the length of an Ethernet header
1770 * @data: pointer to the start of the Ethernet header
1771 *
1772 * Returns the length of an Ethernet header, including optional VLAN tag.
1773 */
1774 static inline int eth_hdr_len(const void *data)
1775 {
1776 const struct ethhdr *e = data;
1777
1778 return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN;
1779 }
1780
1781 /*
1782 * Adds the CPL header to the sk_buff and passes it to t1_sge_tx.
1783 */
1784 netdev_tx_t t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1785 {
1786 struct adapter *adapter = dev->ml_priv;
1787 struct sge *sge = adapter->sge;
1788 struct sge_port_stats *st = this_cpu_ptr(sge->port_stats[dev->if_port]);
1789 struct cpl_tx_pkt *cpl;
1790 struct sk_buff *orig_skb = skb;
1791 int ret;
1792
1793 if (skb->protocol == htons(ETH_P_CPL5))
1794 goto send;
1795
1796 /*
1797 * We are using a non-standard hard_header_len.
1798 * Allocate more header room in the rare cases it is not big enough.
1799 */
1800 if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) {
1801 skb = skb_realloc_headroom(skb, sizeof(struct cpl_tx_pkt_lso));
1802 ++st->tx_need_hdrroom;
1803 dev_kfree_skb_any(orig_skb);
1804 if (!skb)
1805 return NETDEV_TX_OK;
1806 }
1807
1808 if (skb_shinfo(skb)->gso_size) {
1809 int eth_type;
1810 struct cpl_tx_pkt_lso *hdr;
1811
1812 ++st->tx_tso;
1813
1814 eth_type = skb_network_offset(skb) == ETH_HLEN ?
1815 CPL_ETH_II : CPL_ETH_II_VLAN;
1816
1817 hdr = (struct cpl_tx_pkt_lso *)skb_push(skb, sizeof(*hdr));
1818 hdr->opcode = CPL_TX_PKT_LSO;
1819 hdr->ip_csum_dis = hdr->l4_csum_dis = 0;
1820 hdr->ip_hdr_words = ip_hdr(skb)->ihl;
1821 hdr->tcp_hdr_words = tcp_hdr(skb)->doff;
1822 hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type,
1823 skb_shinfo(skb)->gso_size));
1824 hdr->len = htonl(skb->len - sizeof(*hdr));
1825 cpl = (struct cpl_tx_pkt *)hdr;
1826 } else {
1827 /*
1828 * Packets shorter than ETH_HLEN can break the MAC, drop them
1829 * early. Also, we may get oversized packets because some
1830 * parts of the kernel don't handle our unusual hard_header_len
1831 * right, drop those too.
1832 */
1833 if (unlikely(skb->len < ETH_HLEN ||
1834 skb->len > dev->mtu + eth_hdr_len(skb->data))) {
1835 pr_debug("%s: packet size %d hdr %d mtu%d\n", dev->name,
1836 skb->len, eth_hdr_len(skb->data), dev->mtu);
1837 dev_kfree_skb_any(skb);
1838 return NETDEV_TX_OK;
1839 }
1840
1841 if (!(adapter->flags & UDP_CSUM_CAPABLE) &&
1842 skb->ip_summed == CHECKSUM_PARTIAL &&
1843 ip_hdr(skb)->protocol == IPPROTO_UDP) {
1844 if (unlikely(skb_checksum_help(skb))) {
1845 pr_debug("%s: unable to do udp checksum\n", dev->name);
1846 dev_kfree_skb_any(skb);
1847 return NETDEV_TX_OK;
1848 }
1849 }
1850
1851 /* Hmmm, assuming to catch the gratious arp... and we'll use
1852 * it to flush out stuck espi packets...
1853 */
1854 if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) {
1855 if (skb->protocol == htons(ETH_P_ARP) &&
1856 arp_hdr(skb)->ar_op == htons(ARPOP_REQUEST)) {
1857 adapter->sge->espibug_skb[dev->if_port] = skb;
1858 /* We want to re-use this skb later. We
1859 * simply bump the reference count and it
1860 * will not be freed...
1861 */
1862 skb = skb_get(skb);
1863 }
1864 }
1865
1866 cpl = (struct cpl_tx_pkt *)__skb_push(skb, sizeof(*cpl));
1867 cpl->opcode = CPL_TX_PKT;
1868 cpl->ip_csum_dis = 1; /* SW calculates IP csum */
1869 cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_PARTIAL ? 0 : 1;
1870 /* the length field isn't used so don't bother setting it */
1871
1872 st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL);
1873 }
1874 cpl->iff = dev->if_port;
1875
1876 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
1877 if (vlan_tx_tag_present(skb)) {
1878 cpl->vlan_valid = 1;
1879 cpl->vlan = htons(vlan_tx_tag_get(skb));
1880 st->vlan_insert++;
1881 } else
1882 #endif
1883 cpl->vlan_valid = 0;
1884
1885 send:
1886 ret = t1_sge_tx(skb, adapter, 0, dev);
1887
1888 /* If transmit busy, and we reallocated skb's due to headroom limit,
1889 * then silently discard to avoid leak.
1890 */
1891 if (unlikely(ret != NETDEV_TX_OK && skb != orig_skb)) {
1892 dev_kfree_skb_any(skb);
1893 ret = NETDEV_TX_OK;
1894 }
1895 return ret;
1896 }
1897
1898 /*
1899 * Callback for the Tx buffer reclaim timer. Runs with softirqs disabled.
1900 */
1901 static void sge_tx_reclaim_cb(unsigned long data)
1902 {
1903 int i;
1904 struct sge *sge = (struct sge *)data;
1905
1906 for (i = 0; i < SGE_CMDQ_N; ++i) {
1907 struct cmdQ *q = &sge->cmdQ[i];
1908
1909 if (!spin_trylock(&q->lock))
1910 continue;
1911
1912 reclaim_completed_tx(sge, q);
1913 if (i == 0 && q->in_use) { /* flush pending credits */
1914 writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
1915 }
1916 spin_unlock(&q->lock);
1917 }
1918 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1919 }
1920
1921 /*
1922 * Propagate changes of the SGE coalescing parameters to the HW.
1923 */
1924 int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p)
1925 {
1926 sge->fixed_intrtimer = p->rx_coalesce_usecs *
1927 core_ticks_per_usec(sge->adapter);
1928 writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER);
1929 return 0;
1930 }
1931
1932 /*
1933 * Allocates both RX and TX resources and configures the SGE. However,
1934 * the hardware is not enabled yet.
1935 */
1936 int t1_sge_configure(struct sge *sge, struct sge_params *p)
1937 {
1938 if (alloc_rx_resources(sge, p))
1939 return -ENOMEM;
1940 if (alloc_tx_resources(sge, p)) {
1941 free_rx_resources(sge);
1942 return -ENOMEM;
1943 }
1944 configure_sge(sge, p);
1945
1946 /*
1947 * Now that we have sized the free lists calculate the payload
1948 * capacity of the large buffers. Other parts of the driver use
1949 * this to set the max offload coalescing size so that RX packets
1950 * do not overflow our large buffers.
1951 */
1952 p->large_buf_capacity = jumbo_payload_capacity(sge);
1953 return 0;
1954 }
1955
1956 /*
1957 * Disables the DMA engine.
1958 */
1959 void t1_sge_stop(struct sge *sge)
1960 {
1961 int i;
1962 writel(0, sge->adapter->regs + A_SG_CONTROL);
1963 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1964
1965 if (is_T2(sge->adapter))
1966 del_timer_sync(&sge->espibug_timer);
1967
1968 del_timer_sync(&sge->tx_reclaim_timer);
1969 if (sge->tx_sched)
1970 tx_sched_stop(sge);
1971
1972 for (i = 0; i < MAX_NPORTS; i++)
1973 kfree_skb(sge->espibug_skb[i]);
1974 }
1975
1976 /*
1977 * Enables the DMA engine.
1978 */
1979 void t1_sge_start(struct sge *sge)
1980 {
1981 refill_free_list(sge, &sge->freelQ[0]);
1982 refill_free_list(sge, &sge->freelQ[1]);
1983
1984 writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL);
1985 doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE);
1986 readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1987
1988 mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1989
1990 if (is_T2(sge->adapter))
1991 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
1992 }
1993
1994 /*
1995 * Callback for the T2 ESPI 'stuck packet feature' workaorund
1996 */
1997 static void espibug_workaround_t204(unsigned long data)
1998 {
1999 struct adapter *adapter = (struct adapter *)data;
2000 struct sge *sge = adapter->sge;
2001 unsigned int nports = adapter->params.nports;
2002 u32 seop[MAX_NPORTS];
2003
2004 if (adapter->open_device_map & PORT_MASK) {
2005 int i;
2006
2007 if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0)
2008 return;
2009
2010 for (i = 0; i < nports; i++) {
2011 struct sk_buff *skb = sge->espibug_skb[i];
2012
2013 if (!netif_running(adapter->port[i].dev) ||
2014 netif_queue_stopped(adapter->port[i].dev) ||
2015 !seop[i] || ((seop[i] & 0xfff) != 0) || !skb)
2016 continue;
2017
2018 if (!skb->cb[0]) {
2019 skb_copy_to_linear_data_offset(skb,
2020 sizeof(struct cpl_tx_pkt),
2021 ch_mac_addr,
2022 ETH_ALEN);
2023 skb_copy_to_linear_data_offset(skb,
2024 skb->len - 10,
2025 ch_mac_addr,
2026 ETH_ALEN);
2027 skb->cb[0] = 0xff;
2028 }
2029
2030 /* bump the reference count to avoid freeing of
2031 * the skb once the DMA has completed.
2032 */
2033 skb = skb_get(skb);
2034 t1_sge_tx(skb, adapter, 0, adapter->port[i].dev);
2035 }
2036 }
2037 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2038 }
2039
2040 static void espibug_workaround(unsigned long data)
2041 {
2042 struct adapter *adapter = (struct adapter *)data;
2043 struct sge *sge = adapter->sge;
2044
2045 if (netif_running(adapter->port[0].dev)) {
2046 struct sk_buff *skb = sge->espibug_skb[0];
2047 u32 seop = t1_espi_get_mon(adapter, 0x930, 0);
2048
2049 if ((seop & 0xfff0fff) == 0xfff && skb) {
2050 if (!skb->cb[0]) {
2051 skb_copy_to_linear_data_offset(skb,
2052 sizeof(struct cpl_tx_pkt),
2053 ch_mac_addr,
2054 ETH_ALEN);
2055 skb_copy_to_linear_data_offset(skb,
2056 skb->len - 10,
2057 ch_mac_addr,
2058 ETH_ALEN);
2059 skb->cb[0] = 0xff;
2060 }
2061
2062 /* bump the reference count to avoid freeing of the
2063 * skb once the DMA has completed.
2064 */
2065 skb = skb_get(skb);
2066 t1_sge_tx(skb, adapter, 0, adapter->port[0].dev);
2067 }
2068 }
2069 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2070 }
2071
2072 /*
2073 * Creates a t1_sge structure and returns suggested resource parameters.
2074 */
2075 struct sge * __devinit t1_sge_create(struct adapter *adapter,
2076 struct sge_params *p)
2077 {
2078 struct sge *sge = kzalloc(sizeof(*sge), GFP_KERNEL);
2079 int i;
2080
2081 if (!sge)
2082 return NULL;
2083
2084 sge->adapter = adapter;
2085 sge->netdev = adapter->port[0].dev;
2086 sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2;
2087 sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
2088
2089 for_each_port(adapter, i) {
2090 sge->port_stats[i] = alloc_percpu(struct sge_port_stats);
2091 if (!sge->port_stats[i])
2092 goto nomem_port;
2093 }
2094
2095 init_timer(&sge->tx_reclaim_timer);
2096 sge->tx_reclaim_timer.data = (unsigned long)sge;
2097 sge->tx_reclaim_timer.function = sge_tx_reclaim_cb;
2098
2099 if (is_T2(sge->adapter)) {
2100 init_timer(&sge->espibug_timer);
2101
2102 if (adapter->params.nports > 1) {
2103 tx_sched_init(sge);
2104 sge->espibug_timer.function = espibug_workaround_t204;
2105 } else
2106 sge->espibug_timer.function = espibug_workaround;
2107 sge->espibug_timer.data = (unsigned long)sge->adapter;
2108
2109 sge->espibug_timeout = 1;
2110 /* for T204, every 10ms */
2111 if (adapter->params.nports > 1)
2112 sge->espibug_timeout = HZ/100;
2113 }
2114
2115
2116 p->cmdQ_size[0] = SGE_CMDQ0_E_N;
2117 p->cmdQ_size[1] = SGE_CMDQ1_E_N;
2118 p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE;
2119 p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE;
2120 if (sge->tx_sched) {
2121 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204)
2122 p->rx_coalesce_usecs = 15;
2123 else
2124 p->rx_coalesce_usecs = 50;
2125 } else
2126 p->rx_coalesce_usecs = 50;
2127
2128 p->coalesce_enable = 0;
2129 p->sample_interval_usecs = 0;
2130
2131 return sge;
2132 nomem_port:
2133 while (i >= 0) {
2134 free_percpu(sge->port_stats[i]);
2135 --i;
2136 }
2137 kfree(sge);
2138 return NULL;
2139
2140 }
kernel source for telekom puls (alcatel/mediatek)