drivers/net/can/sja1000/plx_pci.c

   1 /*
   2  * Copyright (C) 2008-2010 Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>
   3  *
   4  * Derived from the ems_pci.c driver:
   5  *      Copyright (C) 2007 Wolfgang Grandegger <wg@grandegger.com>
   6  *      Copyright (C) 2008 Markus Plessing <plessing@ems-wuensche.com>
   7  *      Copyright (C) 2008 Sebastian Haas <haas@ems-wuensche.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the version 2 of the GNU General Public License
  11  * as published by the Free Software Foundation
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  21  */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/delay.h>
  28 #include <linux/slab.h>
  29 #include <linux/pci.h>
  30 #include <linux/can.h>
  31 #include <linux/can/dev.h>
  32 #include <linux/io.h>
  33
  34 #include "sja1000.h"
  35
  36 #define DRV_NAME  "sja1000_plx_pci"
  37
  38 MODULE_AUTHOR("Pavel Cheblakov <P.B.Cheblakov@inp.nsk.su>");
  39 MODULE_DESCRIPTION("Socket-CAN driver for PLX90xx PCI-bridge cards with "
  40                    "the SJA1000 chips");
  41 MODULE_SUPPORTED_DEVICE("Adlink PCI-7841/cPCI-7841, "
  42                         "Adlink PCI-7841/cPCI-7841 SE, "
  43                         "Marathon CAN-bus-PCI, "
  44                         "TEWS TECHNOLOGIES TPMC810");
  45 MODULE_LICENSE("GPL v2");
  46
  47 #define PLX_PCI_MAX_CHAN 2
  48
  49 struct plx_pci_card {
  50         int channels;                   /* detected channels count */
  51         struct net_device *net_dev[PLX_PCI_MAX_CHAN];
  52         void __iomem *conf_addr;
  53 };
  54
  55 #define PLX_PCI_CAN_CLOCK (16000000 / 2)
  56
  57 /* PLX90xx registers */
  58 #define PLX_INTCSR      0x4c            /* Interrupt Control/Status */
  59 #define PLX_CNTRL       0x50            /* User I/O, Direct Slave Response,
  60                                          * Serial EEPROM, and Initialization
  61                                          * Control register
  62                                          */
  63
  64 #define PLX_LINT1_EN    0x1             /* Local interrupt 1 enable */
  65 #define PLX_LINT2_EN    (1 << 3)        /* Local interrupt 2 enable */
  66 #define PLX_PCI_INT_EN  (1 << 6)        /* PCI Interrupt Enable */
  67 #define PLX_PCI_RESET   (1 << 30)       /* PCI Adapter Software Reset */
  68
  69 /*
  70  * The board configuration is probably following:
  71  * RX1 is connected to ground.
  72  * TX1 is not connected.
  73  * CLKO is not connected.
  74  * Setting the OCR register to 0xDA is a good idea.
  75  * This means normal output mode, push-pull and the correct polarity.
  76  */
  77 #define PLX_PCI_OCR     (OCR_TX0_PUSHPULL | OCR_TX1_PUSHPULL)
  78
  79 /*
  80  * In the CDR register, you should set CBP to 1.
  81  * You will probably also want to set the clock divider value to 7
  82  * (meaning direct oscillator output) because the second SJA1000 chip
  83  * is driven by the first one CLKOUT output.
  84  */
  85 #define PLX_PCI_CDR                     (CDR_CBP | CDR_CLKOUT_MASK)
  86
  87 /* SJA1000 Control Register in the BasicCAN Mode */
  88 #define REG_CR                          0x00
  89
  90 /* States of some SJA1000 registers after hardware reset in the BasicCAN mode*/
  91 #define REG_CR_BASICCAN_INITIAL         0x21
  92 #define REG_CR_BASICCAN_INITIAL_MASK    0xa1
  93 #define REG_SR_BASICCAN_INITIAL         0x0c
  94 #define REG_IR_BASICCAN_INITIAL         0xe0
  95
  96 /* States of some SJA1000 registers after hardware reset in the PeliCAN mode*/
  97 #define REG_MOD_PELICAN_INITIAL         0x01
  98 #define REG_SR_PELICAN_INITIAL          0x3c
  99 #define REG_IR_PELICAN_INITIAL          0x00
 100
 101 #define ADLINK_PCI_VENDOR_ID            0x144A
 102 #define ADLINK_PCI_DEVICE_ID            0x7841
 103
 104 #define MARATHON_PCI_DEVICE_ID          0x2715
 105
 106 #define TEWS_PCI_VENDOR_ID              0x1498
 107 #define TEWS_PCI_DEVICE_ID_TMPC810      0x032A
 108
 109 static void plx_pci_reset_common(struct pci_dev *pdev);
 110 static void plx_pci_reset_marathon(struct pci_dev *pdev);
 111
 112 struct plx_pci_channel_map {
 113         u32 bar;
 114         u32 offset;
 115         u32 size;               /* 0x00 - auto, e.g. length of entire bar */
 116 };
 117
 118 struct plx_pci_card_info {
 119         const char *name;
 120         int channel_count;
 121         u32 can_clock;
 122         u8 ocr;                 /* output control register */
 123         u8 cdr;                 /* clock divider register */
 124
 125         /* Parameters for mapping local configuration space */
 126         struct plx_pci_channel_map conf_map;
 127
 128         /* Parameters for mapping the SJA1000 chips */
 129         struct plx_pci_channel_map chan_map_tbl[PLX_PCI_MAX_CHAN];
 130
 131         /* Pointer to device-dependent reset function */
 132         void (*reset_func)(struct pci_dev *pdev);
 133 };
 134
 135 static struct plx_pci_card_info plx_pci_card_info_adlink __devinitdata = {
 136         "Adlink PCI-7841/cPCI-7841", 2,
 137         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 138         {1, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
 139         &plx_pci_reset_common
 140         /* based on PLX9052 */
 141 };
 142
 143 static struct plx_pci_card_info plx_pci_card_info_adlink_se __devinitdata = {
 144         "Adlink PCI-7841/cPCI-7841 SE", 2,
 145         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 146         {0, 0x00, 0x00}, { {2, 0x00, 0x80}, {2, 0x80, 0x80} },
 147         &plx_pci_reset_common
 148         /* based on PLX9052 */
 149 };
 150
 151 static struct plx_pci_card_info plx_pci_card_info_marathon __devinitdata = {
 152         "Marathon CAN-bus-PCI", 2,
 153         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 154         {0, 0x00, 0x00}, { {2, 0x00, 0x00}, {4, 0x00, 0x00} },
 155         &plx_pci_reset_marathon
 156         /* based on PLX9052 */
 157 };
 158
 159 static struct plx_pci_card_info plx_pci_card_info_tews __devinitdata = {
 160         "TEWS TECHNOLOGIES TPMC810", 2,
 161         PLX_PCI_CAN_CLOCK, PLX_PCI_OCR, PLX_PCI_CDR,
 162         {0, 0x00, 0x00}, { {2, 0x000, 0x80}, {2, 0x100, 0x80} },
 163         &plx_pci_reset_common
 164         /* based on PLX9030 */
 165 };
 166
 167 static DEFINE_PCI_DEVICE_TABLE(plx_pci_tbl) = {
 168         {
 169                 /* Adlink PCI-7841/cPCI-7841 */
 170                 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
 171                 PCI_ANY_ID, PCI_ANY_ID,
 172                 PCI_CLASS_NETWORK_OTHER << 8, ~0,
 173                 (kernel_ulong_t)&plx_pci_card_info_adlink
 174         },
 175         {
 176                 /* Adlink PCI-7841/cPCI-7841 SE */
 177                 ADLINK_PCI_VENDOR_ID, ADLINK_PCI_DEVICE_ID,
 178                 PCI_ANY_ID, PCI_ANY_ID,
 179                 PCI_CLASS_COMMUNICATION_OTHER << 8, ~0,
 180                 (kernel_ulong_t)&plx_pci_card_info_adlink_se
 181         },
 182         {
 183                 /* Marathon CAN-bus-PCI card */
 184                 PCI_VENDOR_ID_PLX, MARATHON_PCI_DEVICE_ID,
 185                 PCI_ANY_ID, PCI_ANY_ID,
 186                 0, 0,
 187                 (kernel_ulong_t)&plx_pci_card_info_marathon
 188         },
 189         {
 190                 /* TEWS TECHNOLOGIES TPMC810 card */
 191                 TEWS_PCI_VENDOR_ID, TEWS_PCI_DEVICE_ID_TMPC810,
 192                 PCI_ANY_ID, PCI_ANY_ID,
 193                 0, 0,
 194                 (kernel_ulong_t)&plx_pci_card_info_tews
 195         },
 196         { 0,}
 197 };
 198 MODULE_DEVICE_TABLE(pci, plx_pci_tbl);
 199
 200 static u8 plx_pci_read_reg(const struct sja1000_priv *priv, int port)
 201 {
 202         return ioread8(priv->reg_base + port);
 203 }
 204
 205 static void plx_pci_write_reg(const struct sja1000_priv *priv, int port, u8 val)
 206 {
 207         iowrite8(val, priv->reg_base + port);
 208 }
 209
 210 /*
 211  * Check if a CAN controller is present at the specified location
 212  * by trying to switch 'em from the Basic mode into the PeliCAN mode.
 213  * Also check states of some registers in reset mode.
 214  */
 215 static inline int plx_pci_check_sja1000(const struct sja1000_priv *priv)
 216 {
 217         int flag = 0;
 218
 219         /*
 220          * Check registers after hardware reset (the Basic mode)
 221          * See states on p. 10 of the Datasheet.
 222          */
 223         if ((priv->read_reg(priv, REG_CR) & REG_CR_BASICCAN_INITIAL_MASK) ==
 224             REG_CR_BASICCAN_INITIAL &&
 225             (priv->read_reg(priv, REG_SR) == REG_SR_BASICCAN_INITIAL) &&
 226             (priv->read_reg(priv, REG_IR) == REG_IR_BASICCAN_INITIAL))
 227                 flag = 1;
 228
 229         /* Bring the SJA1000 into the PeliCAN mode*/
 230         priv->write_reg(priv, REG_CDR, CDR_PELICAN);
 231
 232         /*
 233          * Check registers after reset in the PeliCAN mode.
 234          * See states on p. 23 of the Datasheet.
 235          */
 236         if (priv->read_reg(priv, REG_MOD) == REG_MOD_PELICAN_INITIAL &&
 237             priv->read_reg(priv, REG_SR) == REG_SR_PELICAN_INITIAL &&
 238             priv->read_reg(priv, REG_IR) == REG_IR_PELICAN_INITIAL)
 239                 return flag;
 240
 241         return 0;
 242 }
 243
 244 /*
 245  * PLX90xx software reset
 246  * Also LRESET# asserts and brings to reset device on the Local Bus (if wired).
 247  * For most cards it's enough for reset the SJA1000 chips.
 248  */
 249 static void plx_pci_reset_common(struct pci_dev *pdev)
 250 {
 251         struct plx_pci_card *card = pci_get_drvdata(pdev);
 252         u32 cntrl;
 253
 254         cntrl = ioread32(card->conf_addr + PLX_CNTRL);
 255         cntrl |= PLX_PCI_RESET;
 256         iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
 257         udelay(100);
 258         cntrl ^= PLX_PCI_RESET;
 259         iowrite32(cntrl, card->conf_addr + PLX_CNTRL);
 260 };
 261
 262 /* Special reset function for Marathon card */
 263 static void plx_pci_reset_marathon(struct pci_dev *pdev)
 264 {
 265         void __iomem *reset_addr;
 266         int i;
 267         int reset_bar[2] = {3, 5};
 268
 269         plx_pci_reset_common(pdev);
 270
 271         for (i = 0; i < 2; i++) {
 272                 reset_addr = pci_iomap(pdev, reset_bar[i], 0);
 273                 if (!reset_addr) {
 274                         dev_err(&pdev->dev, "Failed to remap reset "
 275                                 "space %d (BAR%d)\n", i, reset_bar[i]);
 276                 } else {
 277                         /* reset the SJA1000 chip */
 278                         iowrite8(0x1, reset_addr);
 279                         udelay(100);
 280                         pci_iounmap(pdev, reset_addr);
 281                 }
 282         }
 283 }
 284
 285 static void plx_pci_del_card(struct pci_dev *pdev)
 286 {
 287         struct plx_pci_card *card = pci_get_drvdata(pdev);
 288         struct net_device *dev;
 289         struct sja1000_priv *priv;
 290         int i = 0;
 291
 292         for (i = 0; i < card->channels; i++) {
 293                 dev = card->net_dev[i];
 294                 if (!dev)
 295                         continue;
 296
 297                 dev_info(&pdev->dev, "Removing %s\n", dev->name);
 298                 unregister_sja1000dev(dev);
 299                 priv = netdev_priv(dev);
 300                 if (priv->reg_base)
 301                         pci_iounmap(pdev, priv->reg_base);
 302                 free_sja1000dev(dev);
 303         }
 304
 305         plx_pci_reset_common(pdev);
 306
 307         /*
 308          * Disable interrupts from PCI-card (PLX90xx) and disable Local_1,
 309          * Local_2 interrupts
 310          */
 311         iowrite32(0x0, card->conf_addr + PLX_INTCSR);
 312
 313         if (card->conf_addr)
 314                 pci_iounmap(pdev, card->conf_addr);
 315
 316         kfree(card);
 317
 318         pci_disable_device(pdev);
 319         pci_set_drvdata(pdev, NULL);
 320 }
 321
 322 /*
 323  * Probe PLX90xx based device for the SJA1000 chips and register each
 324  * available CAN channel to SJA1000 Socket-CAN subsystem.
 325  */
 326 static int __devinit plx_pci_add_card(struct pci_dev *pdev,
 327                                       const struct pci_device_id *ent)
 328 {
 329         struct sja1000_priv *priv;
 330         struct net_device *dev;
 331         struct plx_pci_card *card;
 332         struct plx_pci_card_info *ci;
 333         int err, i;
 334         u32 val;
 335         void __iomem *addr;
 336
 337         ci = (struct plx_pci_card_info *)ent->driver_data;
 338
 339         if (pci_enable_device(pdev) < 0) {
 340                 dev_err(&pdev->dev, "Failed to enable PCI device\n");
 341                 return -ENODEV;
 342         }
 343
 344         dev_info(&pdev->dev, "Detected \"%s\" card at slot #%i\n",
 345                  ci->name, PCI_SLOT(pdev->devfn));
 346
 347         /* Allocate card structures to hold addresses, ... */
 348         card = kzalloc(sizeof(*card), GFP_KERNEL);
 349         if (!card) {
 350                 dev_err(&pdev->dev, "Unable to allocate memory\n");
 351                 pci_disable_device(pdev);
 352                 return -ENOMEM;
 353         }
 354
 355         pci_set_drvdata(pdev, card);
 356
 357         card->channels = 0;
 358
 359         /* Remap PLX90xx configuration space */
 360         addr = pci_iomap(pdev, ci->conf_map.bar, ci->conf_map.size);
 361         if (!addr) {
 362                 err = -ENOMEM;
 363                 dev_err(&pdev->dev, "Failed to remap configuration space "
 364                         "(BAR%d)\n", ci->conf_map.bar);
 365                 goto failure_cleanup;
 366         }
 367         card->conf_addr = addr + ci->conf_map.offset;
 368
 369         ci->reset_func(pdev);
 370
 371         /* Detect available channels */
 372         for (i = 0; i < ci->channel_count; i++) {
 373                 struct plx_pci_channel_map *cm = &ci->chan_map_tbl[i];
 374
 375                 dev = alloc_sja1000dev(0);
 376                 if (!dev) {
 377                         err = -ENOMEM;
 378                         goto failure_cleanup;
 379                 }
 380
 381                 card->net_dev[i] = dev;
 382                 priv = netdev_priv(dev);
 383                 priv->priv = card;
 384                 priv->irq_flags = IRQF_SHARED;
 385
 386                 dev->irq = pdev->irq;
 387
 388                 /*
 389                  * Remap IO space of the SJA1000 chips
 390                  * This is device-dependent mapping
 391                  */
 392                 addr = pci_iomap(pdev, cm->bar, cm->size);
 393                 if (!addr) {
 394                         err = -ENOMEM;
 395                         dev_err(&pdev->dev, "Failed to remap BAR%d\n", cm->bar);
 396                         goto failure_cleanup;
 397                 }
 398
 399                 priv->reg_base = addr + cm->offset;
 400                 priv->read_reg = plx_pci_read_reg;
 401                 priv->write_reg = plx_pci_write_reg;
 402
 403                 /* Check if channel is present */
 404                 if (plx_pci_check_sja1000(priv)) {
 405                         priv->can.clock.freq = ci->can_clock;
 406                         priv->ocr = ci->ocr;
 407                         priv->cdr = ci->cdr;
 408
 409                         SET_NETDEV_DEV(dev, &pdev->dev);
 410
 411                         /* Register SJA1000 device */
 412                         err = register_sja1000dev(dev);
 413                         if (err) {
 414                                 dev_err(&pdev->dev, "Registering device failed "
 415                                         "(err=%d)\n", err);
 416                                 free_sja1000dev(dev);
 417                                 goto failure_cleanup;
 418                         }
 419
 420                         card->channels++;
 421
 422                         dev_info(&pdev->dev, "Channel #%d at 0x%p, irq %d "
 423                                  "registered as %s\n", i + 1, priv->reg_base,
 424                                  dev->irq, dev->name);
 425                 } else {
 426                         dev_err(&pdev->dev, "Channel #%d not detected\n",
 427                                 i + 1);
 428                         free_sja1000dev(dev);
 429                 }
 430         }
 431
 432         if (!card->channels) {
 433                 err = -ENODEV;
 434                 goto failure_cleanup;
 435         }
 436
 437         /*
 438          * Enable interrupts from PCI-card (PLX90xx) and enable Local_1,
 439          * Local_2 interrupts from the SJA1000 chips
 440          */
 441         val = ioread32(card->conf_addr + PLX_INTCSR);
 442         val |= PLX_LINT1_EN | PLX_LINT2_EN | PLX_PCI_INT_EN;
 443         iowrite32(val, card->conf_addr + PLX_INTCSR);
 444
 445         return 0;
 446
 447 failure_cleanup:
 448         dev_err(&pdev->dev, "Error: %d. Cleaning Up.\n", err);
 449
 450         plx_pci_del_card(pdev);
 451
 452         return err;
 453 }
 454
 455 static struct pci_driver plx_pci_driver = {
 456         .name = DRV_NAME,
 457         .id_table = plx_pci_tbl,
 458         .probe = plx_pci_add_card,
 459         .remove = plx_pci_del_card,
 460 };
 461
 462 static int __init plx_pci_init(void)
 463 {
 464         return pci_register_driver(&plx_pci_driver);
 465 }
 466
 467 static void __exit plx_pci_exit(void)
 468 {
 469         pci_unregister_driver(&plx_pci_driver);
 470 }
 471
 472 module_init(plx_pci_init);
 473 module_exit(plx_pci_exit);