1 /* bnx2x_reg.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2009 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * The registers description starts with the register Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
14 * ST - Statistics register (clear on read)
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
23 /* [R 19] Interrupt register #0 read */
24 #define BRB1_REG_BRB1_INT_STS 0x6011c
25 /* [RW 4] Parity mask register #0 read/write */
26 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
27 /* [R 4] Parity register #0 read */
28 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
29 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
30 address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
31 BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */
32 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
33 /* [RW 10] The number of free blocks above which the High_llfc signal to
34 interface #n is de-asserted. */
35 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
36 /* [RW 10] The number of free blocks below which the High_llfc signal to
37 interface #n is asserted. */
38 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
39 /* [RW 23] LL RAM data. */
40 #define BRB1_REG_LL_RAM 0x61000
41 /* [RW 10] The number of free blocks above which the Low_llfc signal to
42 interface #n is de-asserted. */
43 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
44 /* [RW 10] The number of free blocks below which the Low_llfc signal to
45 interface #n is asserted. */
46 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
47 /* [R 24] The number of full blocks. */
48 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
49 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
51 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
52 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
53 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
54 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
56 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
57 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
58 /* [RW 10] Write client 0: De-assert pause threshold. */
59 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
60 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
61 /* [RW 10] Write client 0: Assert pause threshold. */
62 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
63 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
64 /* [R 24] The number of full blocks occupied by port. */
65 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
66 /* [RW 1] Reset the design by software. */
67 #define BRB1_REG_SOFT_RESET 0x600dc
68 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
69 #define CCM_REG_CAM_OCCUP 0xd0188
70 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
71 acknowledge output is deasserted; all other signals are treated as usual;
72 if 1 - normal activity. */
73 #define CCM_REG_CCM_CFC_IFEN 0xd003c
74 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
75 disregarded; valid is deasserted; all other signals are treated as usual;
76 if 1 - normal activity. */
77 #define CCM_REG_CCM_CQM_IFEN 0xd000c
78 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
79 Otherwise 0 is inserted. */
80 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
81 /* [RW 11] Interrupt mask register #0 read/write */
82 #define CCM_REG_CCM_INT_MASK 0xd01e4
83 /* [R 11] Interrupt register #0 read */
84 #define CCM_REG_CCM_INT_STS 0xd01d8
85 /* [R 27] Parity register #0 read */
86 #define CCM_REG_CCM_PRTY_STS 0xd01e8
87 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
88 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
89 Is used to determine the number of the AG context REG-pairs written back;
90 when the input message Reg1WbFlg isn't set. */
91 #define CCM_REG_CCM_REG0_SZ 0xd00c4
92 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
93 disregarded; valid is deasserted; all other signals are treated as usual;
94 if 1 - normal activity. */
95 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
96 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
97 disregarded; valid is deasserted; all other signals are treated as usual;
98 if 1 - normal activity. */
99 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
100 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
101 disregarded; valid output is deasserted; all other signals are treated as
102 usual; if 1 - normal activity. */
103 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
104 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
105 are disregarded; all other signals are treated as usual; if 1 - normal
107 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
108 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
109 disregarded; valid output is deasserted; all other signals are treated as
110 usual; if 1 - normal activity. */
111 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
112 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
113 input is disregarded; all other signals are treated as usual; if 1 -
115 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
116 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
117 the initial credit value; read returns the current value of the credit
118 counter. Must be initialized to 1 at start-up. */
119 #define CCM_REG_CFC_INIT_CRD 0xd0204
120 /* [RW 2] Auxillary counter flag Q number 1. */
121 #define CCM_REG_CNT_AUX1_Q 0xd00c8
122 /* [RW 2] Auxillary counter flag Q number 2. */
123 #define CCM_REG_CNT_AUX2_Q 0xd00cc
124 /* [RW 28] The CM header value for QM request (primary). */
125 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
126 /* [RW 28] The CM header value for QM request (secondary). */
127 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
128 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
129 acknowledge output is deasserted; all other signals are treated as usual;
130 if 1 - normal activity. */
131 #define CCM_REG_CQM_CCM_IFEN 0xd0014
132 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
133 the initial credit value; read returns the current value of the credit
134 counter. Must be initialized to 32 at start-up. */
135 #define CCM_REG_CQM_INIT_CRD 0xd020c
136 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
137 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
138 prioritised); 2 stands for weight 2; tc. */
139 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
140 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
141 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
142 prioritised); 2 stands for weight 2; tc. */
143 #define CCM_REG_CQM_S_WEIGHT 0xd00bc
144 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
145 acknowledge output is deasserted; all other signals are treated as usual;
146 if 1 - normal activity. */
147 #define CCM_REG_CSDM_IFEN 0xd0018
148 /* [RC 1] Set when the message length mismatch (relative to last indication)
149 at the SDM interface is detected. */
150 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
151 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
152 weight 8 (the most prioritised); 1 stands for weight 1(least
153 prioritised); 2 stands for weight 2; tc. */
154 #define CCM_REG_CSDM_WEIGHT 0xd00b4
155 /* [RW 28] The CM header for QM formatting in case of an error in the QM
157 #define CCM_REG_ERR_CCM_HDR 0xd0094
158 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
159 #define CCM_REG_ERR_EVNT_ID 0xd0098
160 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
161 writes the initial credit value; read returns the current value of the
162 credit counter. Must be initialized to 64 at start-up. */
163 #define CCM_REG_FIC0_INIT_CRD 0xd0210
164 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
165 writes the initial credit value; read returns the current value of the
166 credit counter. Must be initialized to 64 at start-up. */
167 #define CCM_REG_FIC1_INIT_CRD 0xd0214
168 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
169 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
170 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
171 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
172 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
173 #define CCM_REG_GR_ARB_TYPE 0xd015c
174 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
175 highest priority is 3. It is supposed; that the Store channel priority is
176 the compliment to 4 of the rest priorities - Aggregation channel; Load
177 (FIC0) channel and Load (FIC1). */
178 #define CCM_REG_GR_LD0_PR 0xd0164
179 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
180 highest priority is 3. It is supposed; that the Store channel priority is
181 the compliment to 4 of the rest priorities - Aggregation channel; Load
182 (FIC0) channel and Load (FIC1). */
183 #define CCM_REG_GR_LD1_PR 0xd0168
184 /* [RW 2] General flags index. */
185 #define CCM_REG_INV_DONE_Q 0xd0108
186 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
187 context and sent to STORM; for a specific connection type. The double
188 REG-pairs are used in order to align to STORM context row size of 128
189 bits. The offset of these data in the STORM context is always 0. Index
190 _(0..15) stands for the connection type (one of 16). */
191 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
192 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
193 #define CCM_REG_N_SM_CTX_LD_10 0xd0074
194 #define CCM_REG_N_SM_CTX_LD_11 0xd0078
195 #define CCM_REG_N_SM_CTX_LD_12 0xd007c
196 #define CCM_REG_N_SM_CTX_LD_13 0xd0080
197 #define CCM_REG_N_SM_CTX_LD_14 0xd0084
198 #define CCM_REG_N_SM_CTX_LD_15 0xd0088
199 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
200 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
201 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
202 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
203 acknowledge output is deasserted; all other signals are treated as usual;
204 if 1 - normal activity. */
205 #define CCM_REG_PBF_IFEN 0xd0028
206 /* [RC 1] Set when the message length mismatch (relative to last indication)
207 at the pbf interface is detected. */
208 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
209 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
210 weight 8 (the most prioritised); 1 stands for weight 1(least
211 prioritised); 2 stands for weight 2; tc. */
212 #define CCM_REG_PBF_WEIGHT 0xd00ac
213 #define CCM_REG_PHYS_QNUM1_0 0xd0134
214 #define CCM_REG_PHYS_QNUM1_1 0xd0138
215 #define CCM_REG_PHYS_QNUM2_0 0xd013c
216 #define CCM_REG_PHYS_QNUM2_1 0xd0140
217 #define CCM_REG_PHYS_QNUM3_0 0xd0144
218 #define CCM_REG_PHYS_QNUM3_1 0xd0148
219 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
220 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
221 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
222 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
223 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
224 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
225 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
226 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
227 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
228 disregarded; acknowledge output is deasserted; all other signals are
229 treated as usual; if 1 - normal activity. */
230 #define CCM_REG_STORM_CCM_IFEN 0xd0010
231 /* [RC 1] Set when the message length mismatch (relative to last indication)
232 at the STORM interface is detected. */
233 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
234 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
235 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
236 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
238 #define CCM_REG_STORM_WEIGHT 0xd009c
239 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
240 disregarded; acknowledge output is deasserted; all other signals are
241 treated as usual; if 1 - normal activity. */
242 #define CCM_REG_TSEM_IFEN 0xd001c
243 /* [RC 1] Set when the message length mismatch (relative to last indication)
244 at the tsem interface is detected. */
245 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
246 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
247 weight 8 (the most prioritised); 1 stands for weight 1(least
248 prioritised); 2 stands for weight 2; tc. */
249 #define CCM_REG_TSEM_WEIGHT 0xd00a0
250 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
251 disregarded; acknowledge output is deasserted; all other signals are
252 treated as usual; if 1 - normal activity. */
253 #define CCM_REG_USEM_IFEN 0xd0024
254 /* [RC 1] Set when message length mismatch (relative to last indication) at
255 the usem interface is detected. */
256 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
257 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
258 weight 8 (the most prioritised); 1 stands for weight 1(least
259 prioritised); 2 stands for weight 2; tc. */
260 #define CCM_REG_USEM_WEIGHT 0xd00a8
261 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
262 disregarded; acknowledge output is deasserted; all other signals are
263 treated as usual; if 1 - normal activity. */
264 #define CCM_REG_XSEM_IFEN 0xd0020
265 /* [RC 1] Set when the message length mismatch (relative to last indication)
266 at the xsem interface is detected. */
267 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
268 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
269 weight 8 (the most prioritised); 1 stands for weight 1(least
270 prioritised); 2 stands for weight 2; tc. */
271 #define CCM_REG_XSEM_WEIGHT 0xd00a4
272 /* [RW 19] Indirect access to the descriptor table of the XX protection
273 mechanism. The fields are: [5:0] - message length; [12:6] - message
274 pointer; 18:13] - next pointer. */
275 #define CCM_REG_XX_DESCR_TABLE 0xd0300
276 #define CCM_REG_XX_DESCR_TABLE_SIZE 36
277 /* [R 7] Used to read the value of XX protection Free counter. */
278 #define CCM_REG_XX_FREE 0xd0184
279 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
280 of the Input Stage XX protection buffer by the XX protection pending
281 messages. Max credit available - 127. Write writes the initial credit
282 value; read returns the current value of the credit counter. Must be
283 initialized to maximum XX protected message size - 2 at start-up. */
284 #define CCM_REG_XX_INIT_CRD 0xd0220
285 /* [RW 7] The maximum number of pending messages; which may be stored in XX
286 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
287 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
289 #define CCM_REG_XX_MSG_NUM 0xd0224
290 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
291 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
292 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
293 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
295 #define CCM_REG_XX_TABLE 0xd0280
296 #define CDU_REG_CDU_CHK_MASK0 0x101000
297 #define CDU_REG_CDU_CHK_MASK1 0x101004
298 #define CDU_REG_CDU_CONTROL0 0x101008
299 #define CDU_REG_CDU_DEBUG 0x101010
300 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
301 /* [RW 7] Interrupt mask register #0 read/write */
302 #define CDU_REG_CDU_INT_MASK 0x10103c
303 /* [R 7] Interrupt register #0 read */
304 #define CDU_REG_CDU_INT_STS 0x101030
305 /* [RW 5] Parity mask register #0 read/write */
306 #define CDU_REG_CDU_PRTY_MASK 0x10104c
307 /* [R 5] Parity register #0 read */
308 #define CDU_REG_CDU_PRTY_STS 0x101040
309 /* [RC 32] logging of error data in case of a CDU load error:
310 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
311 ype_error; ctual_active; ctual_compressed_context}; */
312 #define CDU_REG_ERROR_DATA 0x101014
313 /* [WB 216] L1TT ram access. each entry has the following format :
314 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
315 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
316 #define CDU_REG_L1TT 0x101800
317 /* [WB 24] MATT ram access. each entry has the following
318 format:{RegionLength[11:0]; egionOffset[11:0]} */
319 #define CDU_REG_MATT 0x101100
320 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */
321 #define CDU_REG_MF_MODE 0x101050
322 /* [R 1] indication the initializing the activity counter by the hardware
324 #define CFC_REG_AC_INIT_DONE 0x104078
325 /* [RW 13] activity counter ram access */
326 #define CFC_REG_ACTIVITY_COUNTER 0x104400
327 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
328 /* [R 1] indication the initializing the cams by the hardware was done. */
329 #define CFC_REG_CAM_INIT_DONE 0x10407c
330 /* [RW 2] Interrupt mask register #0 read/write */
331 #define CFC_REG_CFC_INT_MASK 0x104108
332 /* [R 2] Interrupt register #0 read */
333 #define CFC_REG_CFC_INT_STS 0x1040fc
334 /* [RC 2] Interrupt register #0 read clear */
335 #define CFC_REG_CFC_INT_STS_CLR 0x104100
336 /* [RW 4] Parity mask register #0 read/write */
337 #define CFC_REG_CFC_PRTY_MASK 0x104118
338 /* [R 4] Parity register #0 read */
339 #define CFC_REG_CFC_PRTY_STS 0x10410c
340 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
341 #define CFC_REG_CID_CAM 0x104800
342 #define CFC_REG_CONTROL0 0x104028
343 #define CFC_REG_DEBUG0 0x104050
344 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
345 vector) whether the cfc should be disabled upon it */
346 #define CFC_REG_DISABLE_ON_ERROR 0x104044
347 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
348 set one of these bits. the bit description can be found in CFC
350 #define CFC_REG_ERROR_VECTOR 0x10403c
351 /* [WB 93] LCID info ram access */
352 #define CFC_REG_INFO_RAM 0x105000
353 #define CFC_REG_INFO_RAM_SIZE 1024
354 #define CFC_REG_INIT_REG 0x10404c
355 #define CFC_REG_INTERFACES 0x104058
356 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
357 field allows changing the priorities of the weighted-round-robin arbiter
358 which selects which CFC load client should be served next */
359 #define CFC_REG_LCREQ_WEIGHTS 0x104084
360 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
361 #define CFC_REG_LINK_LIST 0x104c00
362 #define CFC_REG_LINK_LIST_SIZE 256
363 /* [R 1] indication the initializing the link list by the hardware was done. */
364 #define CFC_REG_LL_INIT_DONE 0x104074
365 /* [R 9] Number of allocated LCIDs which are at empty state */
366 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
367 /* [R 9] Number of Arriving LCIDs in Link List Block */
368 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
369 /* [R 9] Number of Leaving LCIDs in Link List Block */
370 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
371 /* [RW 8] The event id for aggregated interrupt 0 */
372 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
373 #define CSDM_REG_AGG_INT_EVENT_1 0xc203c
374 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060
375 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064
376 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068
377 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c
378 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070
379 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074
380 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078
381 #define CSDM_REG_AGG_INT_EVENT_17 0xc207c
382 #define CSDM_REG_AGG_INT_EVENT_18 0xc2080
383 #define CSDM_REG_AGG_INT_EVENT_19 0xc2084
384 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040
385 #define CSDM_REG_AGG_INT_EVENT_20 0xc2088
386 #define CSDM_REG_AGG_INT_EVENT_21 0xc208c
387 #define CSDM_REG_AGG_INT_EVENT_22 0xc2090
388 #define CSDM_REG_AGG_INT_EVENT_23 0xc2094
389 #define CSDM_REG_AGG_INT_EVENT_24 0xc2098
390 #define CSDM_REG_AGG_INT_EVENT_25 0xc209c
391 #define CSDM_REG_AGG_INT_EVENT_26 0xc20a0
392 #define CSDM_REG_AGG_INT_EVENT_27 0xc20a4
393 #define CSDM_REG_AGG_INT_EVENT_28 0xc20a8
394 #define CSDM_REG_AGG_INT_EVENT_29 0xc20ac
395 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044
396 #define CSDM_REG_AGG_INT_EVENT_30 0xc20b0
397 #define CSDM_REG_AGG_INT_EVENT_31 0xc20b4
398 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048
399 /* [RW 1] The T bit for aggregated interrupt 0 */
400 #define CSDM_REG_AGG_INT_T_0 0xc20b8
401 #define CSDM_REG_AGG_INT_T_1 0xc20bc
402 #define CSDM_REG_AGG_INT_T_10 0xc20e0
403 #define CSDM_REG_AGG_INT_T_11 0xc20e4
404 #define CSDM_REG_AGG_INT_T_12 0xc20e8
405 #define CSDM_REG_AGG_INT_T_13 0xc20ec
406 #define CSDM_REG_AGG_INT_T_14 0xc20f0
407 #define CSDM_REG_AGG_INT_T_15 0xc20f4
408 #define CSDM_REG_AGG_INT_T_16 0xc20f8
409 #define CSDM_REG_AGG_INT_T_17 0xc20fc
410 #define CSDM_REG_AGG_INT_T_18 0xc2100
411 #define CSDM_REG_AGG_INT_T_19 0xc2104
412 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
413 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
414 /* [RW 16] The maximum value of the competion counter #0 */
415 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
416 /* [RW 16] The maximum value of the competion counter #1 */
417 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
418 /* [RW 16] The maximum value of the competion counter #2 */
419 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
420 /* [RW 16] The maximum value of the competion counter #3 */
421 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
422 /* [RW 13] The start address in the internal RAM for the completion
424 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
425 /* [RW 32] Interrupt mask register #0 read/write */
426 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
427 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
428 /* [R 32] Interrupt register #0 read */
429 #define CSDM_REG_CSDM_INT_STS_0 0xc2290
430 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0
431 /* [RW 11] Parity mask register #0 read/write */
432 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
433 /* [R 11] Parity register #0 read */
434 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
435 #define CSDM_REG_ENABLE_IN1 0xc2238
436 #define CSDM_REG_ENABLE_IN2 0xc223c
437 #define CSDM_REG_ENABLE_OUT1 0xc2240
438 #define CSDM_REG_ENABLE_OUT2 0xc2244
439 /* [RW 4] The initial number of messages that can be sent to the pxp control
440 interface without receiving any ACK. */
441 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
442 /* [ST 32] The number of ACK after placement messages received */
443 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
444 /* [ST 32] The number of packet end messages received from the parser */
445 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
446 /* [ST 32] The number of requests received from the pxp async if */
447 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
448 /* [ST 32] The number of commands received in queue 0 */
449 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
450 /* [ST 32] The number of commands received in queue 10 */
451 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
452 /* [ST 32] The number of commands received in queue 11 */
453 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
454 /* [ST 32] The number of commands received in queue 1 */
455 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
456 /* [ST 32] The number of commands received in queue 3 */
457 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
458 /* [ST 32] The number of commands received in queue 4 */
459 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
460 /* [ST 32] The number of commands received in queue 5 */
461 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
462 /* [ST 32] The number of commands received in queue 6 */
463 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
464 /* [ST 32] The number of commands received in queue 7 */
465 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
466 /* [ST 32] The number of commands received in queue 8 */
467 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
468 /* [ST 32] The number of commands received in queue 9 */
469 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
470 /* [RW 13] The start address in the internal RAM for queue counters */
471 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
472 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
473 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
474 /* [R 1] parser fifo empty in sdm_sync block */
475 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
476 /* [R 1] parser serial fifo empty in sdm_sync block */
477 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
478 /* [RW 32] Tick for timer counter. Applicable only when
479 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
480 #define CSDM_REG_TIMER_TICK 0xc2000
481 /* [RW 5] The number of time_slots in the arbitration cycle */
482 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
483 /* [RW 3] The source that is associated with arbitration element 0. Source
484 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
485 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
486 #define CSEM_REG_ARB_ELEMENT0 0x200020
487 /* [RW 3] The source that is associated with arbitration element 1. Source
488 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
489 sleeping thread with priority 1; 4- sleeping thread with priority 2.
490 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
491 #define CSEM_REG_ARB_ELEMENT1 0x200024
492 /* [RW 3] The source that is associated with arbitration element 2. Source
493 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
494 sleeping thread with priority 1; 4- sleeping thread with priority 2.
495 Could not be equal to register ~csem_registers_arb_element0.arb_element0
496 and ~csem_registers_arb_element1.arb_element1 */
497 #define CSEM_REG_ARB_ELEMENT2 0x200028
498 /* [RW 3] The source that is associated with arbitration element 3. Source
499 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
500 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
501 not be equal to register ~csem_registers_arb_element0.arb_element0 and
502 ~csem_registers_arb_element1.arb_element1 and
503 ~csem_registers_arb_element2.arb_element2 */
504 #define CSEM_REG_ARB_ELEMENT3 0x20002c
505 /* [RW 3] The source that is associated with arbitration element 4. Source
506 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
507 sleeping thread with priority 1; 4- sleeping thread with priority 2.
508 Could not be equal to register ~csem_registers_arb_element0.arb_element0
509 and ~csem_registers_arb_element1.arb_element1 and
510 ~csem_registers_arb_element2.arb_element2 and
511 ~csem_registers_arb_element3.arb_element3 */
512 #define CSEM_REG_ARB_ELEMENT4 0x200030
513 /* [RW 32] Interrupt mask register #0 read/write */
514 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
515 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
516 /* [R 32] Interrupt register #0 read */
517 #define CSEM_REG_CSEM_INT_STS_0 0x200104
518 #define CSEM_REG_CSEM_INT_STS_1 0x200114
519 /* [RW 32] Parity mask register #0 read/write */
520 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
521 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
522 /* [R 32] Parity register #0 read */
523 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
524 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
525 #define CSEM_REG_ENABLE_IN 0x2000a4
526 #define CSEM_REG_ENABLE_OUT 0x2000a8
527 /* [RW 32] This address space contains all registers and memories that are
528 placed in SEM_FAST block. The SEM_FAST registers are described in
529 appendix B. In order to access the sem_fast registers the base address
530 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
531 #define CSEM_REG_FAST_MEMORY 0x220000
532 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
534 #define CSEM_REG_FIC0_DISABLE 0x200224
535 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
537 #define CSEM_REG_FIC1_DISABLE 0x200234
538 /* [RW 15] Interrupt table Read and write access to it is not possible in
539 the middle of the work */
540 #define CSEM_REG_INT_TABLE 0x200400
541 /* [ST 24] Statistics register. The number of messages that entered through
543 #define CSEM_REG_MSG_NUM_FIC0 0x200000
544 /* [ST 24] Statistics register. The number of messages that entered through
546 #define CSEM_REG_MSG_NUM_FIC1 0x200004
547 /* [ST 24] Statistics register. The number of messages that were sent to
549 #define CSEM_REG_MSG_NUM_FOC0 0x200008
550 /* [ST 24] Statistics register. The number of messages that were sent to
552 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
553 /* [ST 24] Statistics register. The number of messages that were sent to
555 #define CSEM_REG_MSG_NUM_FOC2 0x200010
556 /* [ST 24] Statistics register. The number of messages that were sent to
558 #define CSEM_REG_MSG_NUM_FOC3 0x200014
559 /* [RW 1] Disables input messages from the passive buffer May be updated
560 during run_time by the microcode */
561 #define CSEM_REG_PAS_DISABLE 0x20024c
562 /* [WB 128] Debug only. Passive buffer memory */
563 #define CSEM_REG_PASSIVE_BUFFER 0x202000
564 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
565 #define CSEM_REG_PRAM 0x240000
566 /* [R 16] Valid sleeping threads indication have bit per thread */
567 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
568 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
569 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
570 /* [RW 16] List of free threads . There is a bit per thread. */
571 #define CSEM_REG_THREADS_LIST 0x2002e4
572 /* [RW 3] The arbitration scheme of time_slot 0 */
573 #define CSEM_REG_TS_0_AS 0x200038
574 /* [RW 3] The arbitration scheme of time_slot 10 */
575 #define CSEM_REG_TS_10_AS 0x200060
576 /* [RW 3] The arbitration scheme of time_slot 11 */
577 #define CSEM_REG_TS_11_AS 0x200064
578 /* [RW 3] The arbitration scheme of time_slot 12 */
579 #define CSEM_REG_TS_12_AS 0x200068
580 /* [RW 3] The arbitration scheme of time_slot 13 */
581 #define CSEM_REG_TS_13_AS 0x20006c
582 /* [RW 3] The arbitration scheme of time_slot 14 */
583 #define CSEM_REG_TS_14_AS 0x200070
584 /* [RW 3] The arbitration scheme of time_slot 15 */
585 #define CSEM_REG_TS_15_AS 0x200074
586 /* [RW 3] The arbitration scheme of time_slot 16 */
587 #define CSEM_REG_TS_16_AS 0x200078
588 /* [RW 3] The arbitration scheme of time_slot 17 */
589 #define CSEM_REG_TS_17_AS 0x20007c
590 /* [RW 3] The arbitration scheme of time_slot 18 */
591 #define CSEM_REG_TS_18_AS 0x200080
592 /* [RW 3] The arbitration scheme of time_slot 1 */
593 #define CSEM_REG_TS_1_AS 0x20003c
594 /* [RW 3] The arbitration scheme of time_slot 2 */
595 #define CSEM_REG_TS_2_AS 0x200040
596 /* [RW 3] The arbitration scheme of time_slot 3 */
597 #define CSEM_REG_TS_3_AS 0x200044
598 /* [RW 3] The arbitration scheme of time_slot 4 */
599 #define CSEM_REG_TS_4_AS 0x200048
600 /* [RW 3] The arbitration scheme of time_slot 5 */
601 #define CSEM_REG_TS_5_AS 0x20004c
602 /* [RW 3] The arbitration scheme of time_slot 6 */
603 #define CSEM_REG_TS_6_AS 0x200050
604 /* [RW 3] The arbitration scheme of time_slot 7 */
605 #define CSEM_REG_TS_7_AS 0x200054
606 /* [RW 3] The arbitration scheme of time_slot 8 */
607 #define CSEM_REG_TS_8_AS 0x200058
608 /* [RW 3] The arbitration scheme of time_slot 9 */
609 #define CSEM_REG_TS_9_AS 0x20005c
610 /* [RW 1] Parity mask register #0 read/write */
611 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
612 /* [R 1] Parity register #0 read */
613 #define DBG_REG_DBG_PRTY_STS 0xc09c
614 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
616 #define DMAE_REG_CMD_MEM 0x102400
617 #define DMAE_REG_CMD_MEM_SIZE 224
618 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
619 initial value is all ones. */
620 #define DMAE_REG_CRC16C_INIT 0x10201c
621 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
622 CRC-16 T10 initial value is all ones. */
623 #define DMAE_REG_CRC16T10_INIT 0x102020
624 /* [RW 2] Interrupt mask register #0 read/write */
625 #define DMAE_REG_DMAE_INT_MASK 0x102054
626 /* [RW 4] Parity mask register #0 read/write */
627 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
628 /* [R 4] Parity register #0 read */
629 #define DMAE_REG_DMAE_PRTY_STS 0x102058
630 /* [RW 1] Command 0 go. */
631 #define DMAE_REG_GO_C0 0x102080
632 /* [RW 1] Command 1 go. */
633 #define DMAE_REG_GO_C1 0x102084
634 /* [RW 1] Command 10 go. */
635 #define DMAE_REG_GO_C10 0x102088
636 #define DMAE_REG_GO_C10_SIZE 1
637 /* [RW 1] Command 11 go. */
638 #define DMAE_REG_GO_C11 0x10208c
639 #define DMAE_REG_GO_C11_SIZE 1
640 /* [RW 1] Command 12 go. */
641 #define DMAE_REG_GO_C12 0x102090
642 #define DMAE_REG_GO_C12_SIZE 1
643 /* [RW 1] Command 13 go. */
644 #define DMAE_REG_GO_C13 0x102094
645 #define DMAE_REG_GO_C13_SIZE 1
646 /* [RW 1] Command 14 go. */
647 #define DMAE_REG_GO_C14 0x102098
648 #define DMAE_REG_GO_C14_SIZE 1
649 /* [RW 1] Command 15 go. */
650 #define DMAE_REG_GO_C15 0x10209c
651 #define DMAE_REG_GO_C15_SIZE 1
652 /* [RW 1] Command 10 go. */
653 #define DMAE_REG_GO_C10 0x102088
654 /* [RW 1] Command 11 go. */
655 #define DMAE_REG_GO_C11 0x10208c
656 /* [RW 1] Command 12 go. */
657 #define DMAE_REG_GO_C12 0x102090
658 /* [RW 1] Command 13 go. */
659 #define DMAE_REG_GO_C13 0x102094
660 /* [RW 1] Command 14 go. */
661 #define DMAE_REG_GO_C14 0x102098
662 /* [RW 1] Command 15 go. */
663 #define DMAE_REG_GO_C15 0x10209c
664 /* [RW 1] Command 2 go. */
665 #define DMAE_REG_GO_C2 0x1020a0
666 /* [RW 1] Command 3 go. */
667 #define DMAE_REG_GO_C3 0x1020a4
668 /* [RW 1] Command 4 go. */
669 #define DMAE_REG_GO_C4 0x1020a8
670 /* [RW 1] Command 5 go. */
671 #define DMAE_REG_GO_C5 0x1020ac
672 /* [RW 1] Command 6 go. */
673 #define DMAE_REG_GO_C6 0x1020b0
674 /* [RW 1] Command 7 go. */
675 #define DMAE_REG_GO_C7 0x1020b4
676 /* [RW 1] Command 8 go. */
677 #define DMAE_REG_GO_C8 0x1020b8
678 /* [RW 1] Command 9 go. */
679 #define DMAE_REG_GO_C9 0x1020bc
680 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
681 input is disregarded; valid is deasserted; all other signals are treated
682 as usual; if 1 - normal activity. */
683 #define DMAE_REG_GRC_IFEN 0x102008
684 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
685 acknowledge input is disregarded; valid is deasserted; full is asserted;
686 all other signals are treated as usual; if 1 - normal activity. */
687 #define DMAE_REG_PCI_IFEN 0x102004
688 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
689 initial value to the credit counter; related to the address. Read returns
690 the current value of the counter. */
691 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
692 /* [RW 8] Aggregation command. */
693 #define DORQ_REG_AGG_CMD0 0x170060
694 /* [RW 8] Aggregation command. */
695 #define DORQ_REG_AGG_CMD1 0x170064
696 /* [RW 8] Aggregation command. */
697 #define DORQ_REG_AGG_CMD2 0x170068
698 /* [RW 8] Aggregation command. */
699 #define DORQ_REG_AGG_CMD3 0x17006c
700 /* [RW 28] UCM Header. */
701 #define DORQ_REG_CMHEAD_RX 0x170050
702 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
703 #define DORQ_REG_DB_ADDR0 0x17008c
704 /* [RW 5] Interrupt mask register #0 read/write */
705 #define DORQ_REG_DORQ_INT_MASK 0x170180
706 /* [R 5] Interrupt register #0 read */
707 #define DORQ_REG_DORQ_INT_STS 0x170174
708 /* [RC 5] Interrupt register #0 read clear */
709 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
710 /* [RW 2] Parity mask register #0 read/write */
711 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
712 /* [R 2] Parity register #0 read */
713 #define DORQ_REG_DORQ_PRTY_STS 0x170184
714 /* [RW 8] The address to write the DPM CID to STORM. */
715 #define DORQ_REG_DPM_CID_ADDR 0x170044
716 /* [RW 5] The DPM mode CID extraction offset. */
717 #define DORQ_REG_DPM_CID_OFST 0x170030
718 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
719 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
720 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
721 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
722 /* [R 13] Current value of the DQ FIFO fill level according to following
723 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
725 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
726 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
727 equal to full threshold; reset on full clear. */
728 #define DORQ_REG_DQ_FULL_ST 0x1700c0
729 /* [RW 28] The value sent to CM header in the case of CFC load error. */
730 #define DORQ_REG_ERR_CMHEAD 0x170058
731 #define DORQ_REG_IF_EN 0x170004
732 #define DORQ_REG_MODE_ACT 0x170008
733 /* [RW 5] The normal mode CID extraction offset. */
734 #define DORQ_REG_NORM_CID_OFST 0x17002c
735 /* [RW 28] TCM Header when only TCP context is loaded. */
736 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
737 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
739 #define DORQ_REG_OUTST_REQ 0x17003c
740 #define DORQ_REG_REGN 0x170038
741 /* [R 4] Current value of response A counter credit. Initial credit is
742 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
744 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
745 /* [R 4] Current value of response B counter credit. Initial credit is
746 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
748 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
749 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
750 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
751 read reads this written value. */
752 #define DORQ_REG_RSP_INIT_CRD 0x170048
753 /* [RW 4] Initial activity counter value on the load request; when the
755 #define DORQ_REG_SHRT_ACT_CNT 0x170070
756 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
757 #define DORQ_REG_SHRT_CMHEAD 0x170054
758 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
759 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
760 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
761 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
762 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
763 #define HC_REG_AGG_INT_0 0x108050
764 #define HC_REG_AGG_INT_1 0x108054
765 #define HC_REG_ATTN_BIT 0x108120
766 #define HC_REG_ATTN_IDX 0x108100
767 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
768 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
769 #define HC_REG_ATTN_NUM_P0 0x108038
770 #define HC_REG_ATTN_NUM_P1 0x10803c
771 #define HC_REG_COMMAND_REG 0x108180
772 #define HC_REG_CONFIG_0 0x108000
773 #define HC_REG_CONFIG_1 0x108004
774 #define HC_REG_FUNC_NUM_P0 0x1080ac
775 #define HC_REG_FUNC_NUM_P1 0x1080b0
776 /* [RW 3] Parity mask register #0 read/write */
777 #define HC_REG_HC_PRTY_MASK 0x1080a0
778 /* [R 3] Parity register #0 read */
779 #define HC_REG_HC_PRTY_STS 0x108094
780 #define HC_REG_INT_MASK 0x108108
781 #define HC_REG_LEADING_EDGE_0 0x108040
782 #define HC_REG_LEADING_EDGE_1 0x108048
783 #define HC_REG_P0_PROD_CONS 0x108200
784 #define HC_REG_P1_PROD_CONS 0x108400
785 #define HC_REG_PBA_COMMAND 0x108140
786 #define HC_REG_PCI_CONFIG_0 0x108010
787 #define HC_REG_PCI_CONFIG_1 0x108014
788 #define HC_REG_STATISTIC_COUNTERS 0x109000
789 #define HC_REG_TRAILING_EDGE_0 0x108044
790 #define HC_REG_TRAILING_EDGE_1 0x10804c
791 #define HC_REG_UC_RAM_ADDR_0 0x108028
792 #define HC_REG_UC_RAM_ADDR_1 0x108030
793 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
794 #define HC_REG_VQID_0 0x108008
795 #define HC_REG_VQID_1 0x10800c
796 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
797 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
798 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
799 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
800 #define MCP_REG_MCPR_NVM_READ 0x86410
801 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
802 #define MCP_REG_MCPR_NVM_WRITE 0x86408
803 #define MCP_REG_MCPR_NVM_WRITE1 0x86428
804 #define MCP_REG_MCPR_SCRATCH 0xa0000
805 /* [R 32] read first 32 bit after inversion of function 0. mapped as
806 follows: [0] NIG attention for function0; [1] NIG attention for
807 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
808 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
809 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
810 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
811 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
812 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
813 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
814 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
815 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
816 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
817 Parity error; [31] PBF Hw interrupt; */
818 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
819 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
820 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
821 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
822 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
823 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
824 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
825 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
826 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
827 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
828 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
829 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
830 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
831 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
833 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
834 /* [R 32] read second 32 bit after inversion of function 0. mapped as
835 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
836 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
837 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
838 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
839 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
840 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
841 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
842 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
843 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
844 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
845 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
847 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
848 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
849 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
850 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
851 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
852 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
853 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
854 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
855 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
856 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
857 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
858 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
859 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
860 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
861 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
862 /* [R 32] read third 32 bit after inversion of function 0. mapped as
863 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
864 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
865 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
866 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
867 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
868 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
869 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
870 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
871 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
872 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
873 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
875 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
876 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
877 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
878 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
879 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
880 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
881 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
882 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
883 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
884 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
885 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
886 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
887 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
888 timers attn_4 func1; [30] General attn0; [31] General attn1; */
889 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
890 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
891 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
892 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
893 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
894 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
895 [14] General attn16; [15] General attn17; [16] General attn18; [17]
896 General attn19; [18] General attn20; [19] General attn21; [20] Main power
897 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
898 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
899 Latched timeout attention; [27] GRC Latched reserved access attention;
900 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
901 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
902 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
903 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
904 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
905 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
906 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
907 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
908 General attn13; [12] General attn14; [13] General attn15; [14] General
909 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
910 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
911 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
912 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
913 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
914 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
915 ump_tx_parity; [31] MCP Latched scpad_parity; */
916 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
917 /* [W 14] write to this register results with the clear of the latched
918 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
919 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
920 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
921 GRC Latched reserved access attention; one in d7 clears Latched
922 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
923 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
924 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
925 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
926 from this register return zero */
927 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
928 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
929 as follows: [0] NIG attention for function0; [1] NIG attention for
930 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
931 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
932 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
933 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
934 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
935 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
936 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
937 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
938 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
939 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
940 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
941 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
942 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
943 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
944 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
945 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
946 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
947 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
948 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
949 as follows: [0] NIG attention for function0; [1] NIG attention for
950 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
951 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
952 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
953 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
954 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
955 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
956 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
957 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
958 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
959 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
960 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
961 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
962 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
963 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
964 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
965 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
966 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
967 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
968 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped
969 as follows: [0] NIG attention for function0; [1] NIG attention for
970 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
971 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
972 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
973 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
974 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
975 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
976 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
977 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
978 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
979 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
980 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
981 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
982 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
983 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
984 as follows: [0] NIG attention for function0; [1] NIG attention for
985 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
986 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
987 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
988 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
989 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
990 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
991 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
992 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
993 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
994 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
995 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
996 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
997 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
998 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
999 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1000 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1001 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1002 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1003 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1004 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1005 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1006 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1007 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1008 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1009 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1011 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1012 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1013 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1014 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1015 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1016 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1017 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1018 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1019 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1020 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1021 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1022 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1023 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1024 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1026 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1027 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
1028 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1029 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1030 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1031 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1032 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1033 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1034 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1035 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1036 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1037 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1038 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1039 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1041 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1042 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1043 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1044 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1045 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1046 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1047 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1048 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1049 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1050 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1051 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1052 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1053 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1054 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1056 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1057 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1058 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1059 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1060 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1061 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1062 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1063 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1064 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1065 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1066 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1067 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1068 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1069 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1071 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1072 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1073 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1074 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1075 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1076 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1077 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1078 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1079 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1080 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1081 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1082 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1083 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1084 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1086 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1087 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1088 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1089 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1090 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1091 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1092 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1093 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1094 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1095 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1096 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1097 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1098 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1099 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1101 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1102 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1103 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1104 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1105 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1106 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1107 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1108 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1109 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1110 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1111 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1112 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1113 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1114 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1116 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1117 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1118 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1119 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1120 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1121 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1122 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1123 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1124 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1125 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1126 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1127 Latched timeout attention; [27] GRC Latched reserved access attention;
1128 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1129 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1130 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1131 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1132 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1133 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1134 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1135 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1136 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1137 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1138 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1139 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1140 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1141 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1142 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1143 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1144 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1145 Latched timeout attention; [27] GRC Latched reserved access attention;
1146 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1147 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1148 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1149 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1150 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1151 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1152 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1153 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1154 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1155 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1156 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1157 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1158 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1159 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1160 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1161 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1162 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1163 Latched timeout attention; [27] GRC Latched reserved access attention;
1164 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1165 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1166 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1167 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1168 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1169 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1170 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1171 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1172 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1173 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1174 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1175 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1176 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1177 Latched timeout attention; [27] GRC Latched reserved access attention;
1178 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1179 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1180 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1181 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1182 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1184 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1185 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1186 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1187 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1188 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1189 #define MISC_REG_AEU_GENERAL_ATTN_13 0xa034
1190 #define MISC_REG_AEU_GENERAL_ATTN_14 0xa038
1191 #define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c
1192 #define MISC_REG_AEU_GENERAL_ATTN_16 0xa040
1193 #define MISC_REG_AEU_GENERAL_ATTN_17 0xa044
1194 #define MISC_REG_AEU_GENERAL_ATTN_18 0xa048
1195 #define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c
1196 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1197 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1198 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1199 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1200 #define MISC_REG_AEU_GENERAL_ATTN_20 0xa050
1201 #define MISC_REG_AEU_GENERAL_ATTN_21 0xa054
1202 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1203 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1204 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1205 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1206 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1207 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1208 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1209 #define MISC_REG_AEU_GENERAL_MASK 0xa61c
1210 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1211 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1212 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1213 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1214 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1215 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1216 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1217 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1218 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1219 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1220 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1221 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1222 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1223 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1224 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1225 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1226 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1227 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1228 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1229 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1230 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1231 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1232 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1233 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1234 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1235 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1236 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1237 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1238 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1239 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1240 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1241 [9:8] = raserved. Zero = mask; one = unmask */
1242 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1243 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1244 /* [RW 1] If set a system kill occurred */
1245 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1246 /* [RW 32] Represent the status of the input vector to the AEU when a system
1247 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1248 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1249 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1250 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1251 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1252 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1253 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1254 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1255 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1256 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1257 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1258 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1260 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1261 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1262 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1263 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1264 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1266 #define MISC_REG_BOND_ID 0xa400
1267 /* [R 8] These bits indicate the metal revision of the chip. This value
1268 starts at 0x00 for each all-layer tape-out and increments by one for each
1270 #define MISC_REG_CHIP_METAL 0xa404
1271 /* [R 16] These bits indicate the part number for the chip. */
1272 #define MISC_REG_CHIP_NUM 0xa408
1273 /* [R 4] These bits indicate the base revision of the chip. This value
1274 starts at 0x0 for the A0 tape-out and increments by one for each
1275 all-layer tape-out. */
1276 #define MISC_REG_CHIP_REV 0xa40c
1277 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1278 32 clients. Each client can be controlled by one driver only. One in each
1279 bit represent that this driver control the appropriate client (Ex: bit 5
1280 is set means this driver control client number 5). addr1 = set; addr0 =
1281 clear; read from both addresses will give the same result = status. write
1282 to address 1 will set a request to control all the clients that their
1283 appropriate bit (in the write command) is set. if the client is free (the
1284 appropriate bit in all the other drivers is clear) one will be written to
1285 that driver register; if the client isn't free the bit will remain zero.
1286 if the appropriate bit is set (the driver request to gain control on a
1287 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1288 interrupt will be asserted). write to address 0 will set a request to
1289 free all the clients that their appropriate bit (in the write command) is
1290 set. if the appropriate bit is clear (the driver request to free a client
1291 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1293 #define MISC_REG_DRIVER_CONTROL_10 0xa3e0
1294 #define MISC_REG_DRIVER_CONTROL_10_SIZE 2
1295 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1296 32 clients. Each client can be controlled by one driver only. One in each
1297 bit represent that this driver control the appropriate client (Ex: bit 5
1298 is set means this driver control client number 5). addr1 = set; addr0 =
1299 clear; read from both addresses will give the same result = status. write
1300 to address 1 will set a request to control all the clients that their
1301 appropriate bit (in the write command) is set. if the client is free (the
1302 appropriate bit in all the other drivers is clear) one will be written to
1303 that driver register; if the client isn't free the bit will remain zero.
1304 if the appropriate bit is set (the driver request to gain control on a
1305 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1306 interrupt will be asserted). write to address 0 will set a request to
1307 free all the clients that their appropriate bit (in the write command) is
1308 set. if the appropriate bit is clear (the driver request to free a client
1309 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1311 #define MISC_REG_DRIVER_CONTROL_11 0xa3e8
1312 #define MISC_REG_DRIVER_CONTROL_11_SIZE 2
1313 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1314 32 clients. Each client can be controlled by one driver only. One in each
1315 bit represent that this driver control the appropriate client (Ex: bit 5
1316 is set means this driver control client number 5). addr1 = set; addr0 =
1317 clear; read from both addresses will give the same result = status. write
1318 to address 1 will set a request to control all the clients that their
1319 appropriate bit (in the write command) is set. if the client is free (the
1320 appropriate bit in all the other drivers is clear) one will be written to
1321 that driver register; if the client isn't free the bit will remain zero.
1322 if the appropriate bit is set (the driver request to gain control on a
1323 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1324 interrupt will be asserted). write to address 0 will set a request to
1325 free all the clients that their appropriate bit (in the write command) is
1326 set. if the appropriate bit is clear (the driver request to free a client
1327 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1329 #define MISC_REG_DRIVER_CONTROL_12 0xa3f0
1330 #define MISC_REG_DRIVER_CONTROL_12_SIZE 2
1331 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1332 32 clients. Each client can be controlled by one driver only. One in each
1333 bit represent that this driver control the appropriate client (Ex: bit 5
1334 is set means this driver control client number 5). addr1 = set; addr0 =
1335 clear; read from both addresses will give the same result = status. write
1336 to address 1 will set a request to control all the clients that their
1337 appropriate bit (in the write command) is set. if the client is free (the
1338 appropriate bit in all the other drivers is clear) one will be written to
1339 that driver register; if the client isn't free the bit will remain zero.
1340 if the appropriate bit is set (the driver request to gain control on a
1341 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1342 interrupt will be asserted). write to address 0 will set a request to
1343 free all the clients that their appropriate bit (in the write command) is
1344 set. if the appropriate bit is clear (the driver request to free a client
1345 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1347 #define MISC_REG_DRIVER_CONTROL_13 0xa3f8
1348 #define MISC_REG_DRIVER_CONTROL_13_SIZE 2
1349 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1350 32 clients. Each client can be controlled by one driver only. One in each
1351 bit represent that this driver control the appropriate client (Ex: bit 5
1352 is set means this driver control client number 5). addr1 = set; addr0 =
1353 clear; read from both addresses will give the same result = status. write
1354 to address 1 will set a request to control all the clients that their
1355 appropriate bit (in the write command) is set. if the client is free (the
1356 appropriate bit in all the other drivers is clear) one will be written to
1357 that driver register; if the client isn't free the bit will remain zero.
1358 if the appropriate bit is set (the driver request to gain control on a
1359 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1360 interrupt will be asserted). write to address 0 will set a request to
1361 free all the clients that their appropriate bit (in the write command) is
1362 set. if the appropriate bit is clear (the driver request to free a client
1363 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1365 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1366 #define MISC_REG_DRIVER_CONTROL_14 0xa5e0
1367 #define MISC_REG_DRIVER_CONTROL_14_SIZE 2
1368 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1369 32 clients. Each client can be controlled by one driver only. One in each
1370 bit represent that this driver control the appropriate client (Ex: bit 5
1371 is set means this driver control client number 5). addr1 = set; addr0 =
1372 clear; read from both addresses will give the same result = status. write
1373 to address 1 will set a request to control all the clients that their
1374 appropriate bit (in the write command) is set. if the client is free (the
1375 appropriate bit in all the other drivers is clear) one will be written to
1376 that driver register; if the client isn't free the bit will remain zero.
1377 if the appropriate bit is set (the driver request to gain control on a
1378 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1379 interrupt will be asserted). write to address 0 will set a request to
1380 free all the clients that their appropriate bit (in the write command) is
1381 set. if the appropriate bit is clear (the driver request to free a client
1382 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1384 #define MISC_REG_DRIVER_CONTROL_15 0xa5e8
1385 #define MISC_REG_DRIVER_CONTROL_15_SIZE 2
1386 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1387 32 clients. Each client can be controlled by one driver only. One in each
1388 bit represent that this driver control the appropriate client (Ex: bit 5
1389 is set means this driver control client number 5). addr1 = set; addr0 =
1390 clear; read from both addresses will give the same result = status. write
1391 to address 1 will set a request to control all the clients that their
1392 appropriate bit (in the write command) is set. if the client is free (the
1393 appropriate bit in all the other drivers is clear) one will be written to
1394 that driver register; if the client isn't free the bit will remain zero.
1395 if the appropriate bit is set (the driver request to gain control on a
1396 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1397 interrupt will be asserted). write to address 0 will set a request to
1398 free all the clients that their appropriate bit (in the write command) is
1399 set. if the appropriate bit is clear (the driver request to free a client
1400 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1402 #define MISC_REG_DRIVER_CONTROL_16 0xa5f0
1403 #define MISC_REG_DRIVER_CONTROL_16_SIZE 2
1404 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1405 32 clients. Each client can be controlled by one driver only. One in each
1406 bit represent that this driver control the appropriate client (Ex: bit 5
1407 is set means this driver control client number 5). addr1 = set; addr0 =
1408 clear; read from both addresses will give the same result = status. write
1409 to address 1 will set a request to control all the clients that their
1410 appropriate bit (in the write command) is set. if the client is free (the
1411 appropriate bit in all the other drivers is clear) one will be written to
1412 that driver register; if the client isn't free the bit will remain zero.
1413 if the appropriate bit is set (the driver request to gain control on a
1414 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1415 interrupt will be asserted). write to address 0 will set a request to
1416 free all the clients that their appropriate bit (in the write command) is
1417 set. if the appropriate bit is clear (the driver request to free a client
1418 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1420 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1421 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1423 #define MISC_REG_E1HMF_MODE 0xa5f8
1424 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1425 these bits is written as a '1'; the corresponding SPIO bit will turn off
1426 it's drivers and become an input. This is the reset state of all GPIO
1427 pins. The read value of these bits will be a '1' if that last command
1428 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1429 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1430 as a '1'; the corresponding GPIO bit will drive low. The read value of
1431 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1432 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1433 SET When any of these bits is written as a '1'; the corresponding GPIO
1434 bit will drive high (if it has that capability). The read value of these
1435 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1436 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1437 RO; These bits indicate the read value of each of the eight GPIO pins.
1438 This is the result value of the pin; not the drive value. Writing these
1439 bits will have not effect. */
1440 #define MISC_REG_GPIO 0xa490
1441 /* [RW 8] These bits enable the GPIO_INTs to signals event to the
1442 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1443 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1445 #define MISC_REG_GPIO_EVENT_EN 0xa2bc
1446 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1447 '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1448 This will acknowledge an interrupt on the falling edge of corresponding
1449 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1450 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1451 register. This will acknowledge an interrupt on the rising edge of
1452 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1453 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1454 value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1455 of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1456 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1457 is '1'; then the interrupt is due to a high to low edge (reset value 0).
1458 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1459 current GPIO interrupt state for each GPIO pin. This bit is cleared when
1460 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1461 set when the GPIO input does not match the current value in #OLD_VALUE
1463 #define MISC_REG_GPIO_INT 0xa494
1464 /* [R 28] this field hold the last information that caused reserved
1465 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1466 [27:24] the master that caused the attention - according to the following
1467 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1469 #define MISC_REG_GRC_RSV_ATTN 0xa3c0
1470 /* [R 28] this field hold the last information that caused timeout
1471 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1472 [27:24] the master that caused the attention - according to the following
1473 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1475 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1476 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1477 access that does not finish within
1478 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1479 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1480 assert it attention output. */
1481 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1482 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1483 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1484 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1485 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1486 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1487 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1488 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1489 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1490 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1491 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1492 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1493 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1494 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1495 connected to RESET input directly. [15] capRetry_en (reset value 0)
1496 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1497 value 0) bit to continuously monitor vco freq (inverted). [17]
1498 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1499 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1500 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1501 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1502 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1503 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1504 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1505 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1506 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1507 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1508 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1510 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1511 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1512 /* [RW 4] Interrupt mask register #0 read/write */
1513 #define MISC_REG_MISC_INT_MASK 0xa388
1514 /* [RW 1] Parity mask register #0 read/write */
1515 #define MISC_REG_MISC_PRTY_MASK 0xa398
1516 /* [R 1] Parity register #0 read */
1517 #define MISC_REG_MISC_PRTY_STS 0xa38c
1518 #define MISC_REG_NIG_WOL_P0 0xa270
1519 #define MISC_REG_NIG_WOL_P1 0xa274
1520 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1522 #define MISC_REG_PCIE_HOT_RESET 0xa618
1523 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1524 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1525 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1526 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1527 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1528 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1529 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1530 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1531 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1532 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1533 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1534 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1535 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1536 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1537 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1538 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1539 testa_en (reset value 0); */
1540 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1541 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1542 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1543 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1544 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1545 write/read zero = the specific block is in reset; addr 0-wr- the write
1546 value will be written to the register; addr 1-set - one will be written
1547 to all the bits that have the value of one in the data written (bits that
1548 have the value of zero will not be change) ; addr 2-clear - zero will be
1549 written to all the bits that have the value of one in the data written
1550 (bits that have the value of zero will not be change); addr 3-ignore;
1551 read ignore from all addr except addr 00; inside order of the bits is:
1552 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1553 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1554 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1555 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1556 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1557 rst_pxp_rq_rd_wr; 31:17] reserved */
1558 #define MISC_REG_RESET_REG_2 0xa590
1559 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1560 shared with the driver resides */
1561 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1562 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1563 the corresponding SPIO bit will turn off it's drivers and become an
1564 input. This is the reset state of all SPIO pins. The read value of these
1565 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1566 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1567 is written as a '1'; the corresponding SPIO bit will drive low. The read
1568 value of these bits will be a '1' if that last command (#SET; #CLR; or
1569 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1570 these bits is written as a '1'; the corresponding SPIO bit will drive
1571 high (if it has that capability). The read value of these bits will be a
1572 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1573 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1574 each of the eight SPIO pins. This is the result value of the pin; not the
1575 drive value. Writing these bits will have not effect. Each 8 bits field
1576 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1577 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1578 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1579 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1580 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1581 select VAUX supply. (This is an output pin only; it is not controlled by
1582 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1583 field is not applicable for this pin; only the VALUE fields is relevant -
1584 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1585 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1586 device ID select; read by UMP firmware. */
1587 #define MISC_REG_SPIO 0xa4fc
1588 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1589 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1591 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1592 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1593 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1594 interrupt on the falling edge of corresponding SPIO input (reset value
1595 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1596 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1597 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1598 RO; These bits indicate the old value of the SPIO input value. When the
1599 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1600 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1601 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1602 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1603 RO; These bits indicate the current SPIO interrupt state for each SPIO
1604 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1605 command bit is written. This bit is set when the SPIO input does not
1606 match the current value in #OLD_VALUE (reset value 0). */
1607 #define MISC_REG_SPIO_INT 0xa500
1608 /* [RW 32] reload value for counter 4 if reload; the value will be reload if
1609 the counter reached zero and the reload bit
1610 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1611 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1612 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1613 in this register. addres 0 - timer 1; address - timer 2�address 7 -
1615 #define MISC_REG_SW_TIMER_VAL 0xa5c0
1616 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1617 loaded; 0-prepare; -unprepare */
1618 #define MISC_REG_UNPREPARED 0xa424
1619 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1620 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1621 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1622 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1623 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1624 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1625 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1626 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1627 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1628 /* [RW 1] Input enable for RX_BMAC0 IF */
1629 #define NIG_REG_BMAC0_IN_EN 0x100ac
1630 /* [RW 1] output enable for TX_BMAC0 IF */
1631 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1632 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1633 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1634 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1635 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1636 /* [RW 1] output enable for RX BRB1 port0 IF */
1637 #define NIG_REG_BRB0_OUT_EN 0x100f8
1638 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1639 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1640 /* [RW 1] output enable for RX BRB1 port1 IF */
1641 #define NIG_REG_BRB1_OUT_EN 0x100fc
1642 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1643 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1644 /* [RW 1] output enable for RX BRB1 LP IF */
1645 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1646 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1647 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1648 72:73]-vnic_num; 81:74]-sideband_info */
1649 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1650 /* [RW 1] Input enable for TX Debug packet */
1651 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1652 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1653 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1654 First packet may be deleted from the middle. And last packet will be
1655 always deleted till the end. */
1656 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1657 /* [RW 1] Output enable to EMAC0 */
1658 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1659 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1660 to emac for port0; other way to bmac for port0 */
1661 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1662 /* [RW 32] TX_MNG_FIFO in NIG_TX_PORT0; data[31:0] written in FIFO order. */
1663 #define NIG_REG_EGRESS_MNG0_FIFO 0x1045c
1664 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1665 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1666 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1667 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1668 /* [RW 1] Input enable for TX UMP management packet port0 IF */
1669 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
1670 /* [RW 1] Input enable for RX_EMAC0 IF */
1671 #define NIG_REG_EMAC0_IN_EN 0x100a4
1672 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1673 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1674 /* [R 1] status from emac0. This bit is set when MDINT from either the
1675 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1676 be cleared in the attached PHY device that is driving the MINT pin. */
1677 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1678 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1679 are described in appendix A. In order to access the BMAC0 registers; the
1680 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1681 added to each BMAC register offset */
1682 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1683 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1684 are described in appendix A. In order to access the BMAC0 registers; the
1685 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1686 added to each BMAC register offset */
1687 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1688 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1689 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1690 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1691 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1692 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1693 /* [RW 1] led 10g for port 0 */
1694 #define NIG_REG_LED_10G_P0 0x10320
1695 /* [RW 1] led 10g for port 1 */
1696 #define NIG_REG_LED_10G_P1 0x10324
1697 /* [RW 1] Port0: This bit is set to enable the use of the
1698 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1699 defined below. If this bit is cleared; then the blink rate will be about
1701 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1702 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1703 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1704 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1705 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1706 /* [RW 1] Port0: If set along with the
1707 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1708 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1709 bit; the Traffic LED will blink with the blink rate specified in
1710 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1711 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1713 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1714 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1715 Traffic LED will then be controlled via bit ~nig_registers_
1716 led_control_traffic_p0.led_control_traffic_p0 and bit
1717 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1718 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1719 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1720 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1721 set; the LED will blink with blink rate specified in
1722 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1723 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1725 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1726 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1727 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1728 #define NIG_REG_LED_MODE_P0 0x102f0
1729 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
1730 tsdm enable; b2- usdm enable */
1731 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
1732 /* [RW 1] SAFC enable for port0. This register may get 1 only when
1733 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
1735 #define NIG_REG_LLFC_ENABLE_0 0x16208
1736 /* [RW 16] classes are high-priority for port0 */
1737 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
1738 /* [RW 16] classes are low-priority for port0 */
1739 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
1740 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
1741 #define NIG_REG_LLFC_OUT_EN_0 0x160c8
1742 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1743 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
1744 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1745 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
1746 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1747 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1748 /* [RW 2] Determine the classification participants. 0: no classification.1:
1749 classification upon VLAN id. 2: classification upon MAC address. 3:
1750 classification upon both VLAN id & MAC addr. */
1751 #define NIG_REG_LLH0_CLS_TYPE 0x16080
1752 /* [RW 32] cm header for llh0 */
1753 #define NIG_REG_LLH0_CM_HEADER 0x1007c
1754 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1755 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1756 /* [RW 16] destination TCP address 1. The LLH will look for this address in
1757 all incoming packets. */
1758 #define NIG_REG_LLH0_DEST_TCP_0 0x10220
1759 /* [RW 16] destination UDP address 1 The LLH will look for this address in
1760 all incoming packets. */
1761 #define NIG_REG_LLH0_DEST_UDP_0 0x10214
1762 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
1763 /* [RW 8] event id for llh0 */
1764 #define NIG_REG_LLH0_EVENT_ID 0x10084
1765 #define NIG_REG_LLH0_FUNC_EN 0x160fc
1766 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1767 /* [RW 1] Determine the IP version to look for in
1768 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1769 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1770 /* [RW 1] t bit for llh0 */
1771 #define NIG_REG_LLH0_T_BIT 0x10074
1772 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1773 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c
1774 /* [RW 8] init credit counter for port0 in LLH */
1775 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1776 #define NIG_REG_LLH0_XCM_MASK 0x10130
1777 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
1778 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1779 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1780 /* [RW 2] Determine the classification participants. 0: no classification.1:
1781 classification upon VLAN id. 2: classification upon MAC address. 3:
1782 classification upon both VLAN id & MAC addr. */
1783 #define NIG_REG_LLH1_CLS_TYPE 0x16084
1784 /* [RW 32] cm header for llh1 */
1785 #define NIG_REG_LLH1_CM_HEADER 0x10080
1786 #define NIG_REG_LLH1_ERROR_MASK 0x10090
1787 /* [RW 8] event id for llh1 */
1788 #define NIG_REG_LLH1_EVENT_ID 0x10088
1789 /* [RW 8] init credit counter for port1 in LLH */
1790 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1791 #define NIG_REG_LLH1_XCM_MASK 0x10134
1792 /* [RW 1] When this bit is set; the LLH will expect all packets to be with
1794 #define NIG_REG_LLH_E1HOV_MODE 0x160d8
1795 /* [RW 1] When this bit is set; the LLH will classify the packet before
1796 sending it to the BRB or calculating WoL on it. */
1797 #define NIG_REG_LLH_MF_MODE 0x16024
1798 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1799 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1800 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1801 #define NIG_REG_NIG_EMAC0_EN 0x1003c
1802 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1803 #define NIG_REG_NIG_EMAC1_EN 0x10040
1804 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1805 EMAC0 to strip the CRC from the ingress packets. */
1806 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1807 /* [R 32] Interrupt register #0 read */
1808 #define NIG_REG_NIG_INT_STS_0 0x103b0
1809 #define NIG_REG_NIG_INT_STS_1 0x103c0
1810 /* [R 32] Parity register #0 read */
1811 #define NIG_REG_NIG_PRTY_STS 0x103d0
1812 /* [RW 1] Pause enable for port0. This register may get 1 only when
1813 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
1815 #define NIG_REG_PAUSE_ENABLE_0 0x160c0
1816 /* [RW 1] Input enable for RX PBF LP IF */
1817 #define NIG_REG_PBF_LB_IN_EN 0x100b4
1818 /* [RW 1] Value of this register will be transmitted to port swap when
1819 ~nig_registers_strap_override.strap_override =1 */
1820 #define NIG_REG_PORT_SWAP 0x10394
1821 /* [RW 1] output enable for RX parser descriptor IF */
1822 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
1823 /* [RW 1] Input enable for RX parser request IF */
1824 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
1825 /* [RW 5] control to serdes - CL45 DEVAD */
1826 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
1827 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
1828 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
1829 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
1830 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
1831 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
1832 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
1833 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1835 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1836 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
1838 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
1839 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1840 between 1024 and 1522 bytes for port0 */
1841 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
1842 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
1843 between 1523 bytes and above for port0 */
1844 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
1845 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1847 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
1848 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1849 between 1024 and 1522 bytes for port1 */
1850 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
1851 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
1852 between 1523 bytes and above for port1 */
1853 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
1854 /* [WB_R 64] Rx statistics : User octets received for LP */
1855 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
1856 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
1857 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
1858 /* [RW 1] port swap mux selection. If this register equal to 0 then port
1859 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
1860 ort swap is equal to ~nig_registers_port_swap.port_swap */
1861 #define NIG_REG_STRAP_OVERRIDE 0x10398
1862 /* [RW 1] output enable for RX_XCM0 IF */
1863 #define NIG_REG_XCM0_OUT_EN 0x100f0
1864 /* [RW 1] output enable for RX_XCM1 IF */
1865 #define NIG_REG_XCM1_OUT_EN 0x100f4
1866 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
1867 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
1868 /* [RW 5] control to xgxs - CL45 DEVAD */
1869 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
1870 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
1871 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
1872 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
1873 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
1874 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
1875 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
1876 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
1877 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
1878 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
1879 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
1880 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
1881 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
1882 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
1883 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
1884 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
1885 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
1886 /* [RW 1] Disable processing further tasks from port 0 (after ending the
1887 current task in process). */
1888 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
1889 /* [RW 1] Disable processing further tasks from port 1 (after ending the
1890 current task in process). */
1891 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
1892 /* [RW 1] Disable processing further tasks from port 4 (after ending the
1893 current task in process). */
1894 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
1895 #define PBF_REG_IF_ENABLE_REG 0x140044
1896 /* [RW 1] Init bit. When set the initial credits are copied to the credit
1897 registers (except the port credits). Should be set and then reset after
1898 the configuration of the block has ended. */
1899 #define PBF_REG_INIT 0x140000
1900 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
1901 copied to the credit register. Should be set and then reset after the
1902 configuration of the port has ended. */
1903 #define PBF_REG_INIT_P0 0x140004
1904 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
1905 copied to the credit register. Should be set and then reset after the
1906 configuration of the port has ended. */
1907 #define PBF_REG_INIT_P1 0x140008
1908 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
1909 copied to the credit register. Should be set and then reset after the
1910 configuration of the port has ended. */
1911 #define PBF_REG_INIT_P4 0x14000c
1912 /* [RW 1] Enable for mac interface 0. */
1913 #define PBF_REG_MAC_IF0_ENABLE 0x140030
1914 /* [RW 1] Enable for mac interface 1. */
1915 #define PBF_REG_MAC_IF1_ENABLE 0x140034
1916 /* [RW 1] Enable for the loopback interface. */
1917 #define PBF_REG_MAC_LB_ENABLE 0x140040
1918 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
1920 #define PBF_REG_P0_ARB_THRSH 0x1400e4
1921 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
1922 #define PBF_REG_P0_CREDIT 0x140200
1923 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
1925 #define PBF_REG_P0_INIT_CRD 0x1400d0
1926 /* [RW 1] Indication that pause is enabled for port 0. */
1927 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
1928 /* [R 8] Number of tasks in port 0 task queue. */
1929 #define PBF_REG_P0_TASK_CNT 0x140204
1930 /* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
1931 #define PBF_REG_P1_CREDIT 0x140208
1932 /* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte
1934 #define PBF_REG_P1_INIT_CRD 0x1400d4
1935 /* [R 8] Number of tasks in port 1 task queue. */
1936 #define PBF_REG_P1_TASK_CNT 0x14020c
1937 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
1938 #define PBF_REG_P4_CREDIT 0x140210
1939 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
1941 #define PBF_REG_P4_INIT_CRD 0x1400e0
1942 /* [R 8] Number of tasks in port 4 task queue. */
1943 #define PBF_REG_P4_TASK_CNT 0x140214
1944 /* [RW 5] Interrupt mask register #0 read/write */
1945 #define PBF_REG_PBF_INT_MASK 0x1401d4
1946 /* [R 5] Interrupt register #0 read */
1947 #define PBF_REG_PBF_INT_STS 0x1401c8
1948 #define PB_REG_CONTROL 0
1949 /* [RW 2] Interrupt mask register #0 read/write */
1950 #define PB_REG_PB_INT_MASK 0x28
1951 /* [R 2] Interrupt register #0 read */
1952 #define PB_REG_PB_INT_STS 0x1c
1953 /* [RW 4] Parity mask register #0 read/write */
1954 #define PB_REG_PB_PRTY_MASK 0x38
1955 /* [R 4] Parity register #0 read */
1956 #define PB_REG_PB_PRTY_STS 0x2c
1957 #define PRS_REG_A_PRSU_20 0x40134
1958 /* [R 8] debug only: CFC load request current credit. Transaction based. */
1959 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
1960 /* [R 8] debug only: CFC search request current credit. Transaction based. */
1961 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
1962 /* [RW 6] The initial credit for the search message to the CFC interface.
1963 Credit is transaction based. */
1964 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
1965 /* [RW 24] CID for port 0 if no match */
1966 #define PRS_REG_CID_PORT_0 0x400fc
1967 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1968 load response is reset and packet type is 0. Used in packet start message
1970 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
1971 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
1972 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
1973 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
1974 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
1975 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
1976 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1977 load response is set and packet type is 0. Used in packet start message
1979 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
1980 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
1981 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
1982 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
1983 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
1984 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
1985 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
1986 Used in packet start message to TCM. */
1987 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
1988 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
1989 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
1990 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
1991 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
1993 #define PRS_REG_CM_HDR_TYPE_0 0x40078
1994 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
1995 #define PRS_REG_CM_HDR_TYPE_2 0x40080
1996 #define PRS_REG_CM_HDR_TYPE_3 0x40084
1997 #define PRS_REG_CM_HDR_TYPE_4 0x40088
1998 /* [RW 32] The CM header in case there was not a match on the connection */
1999 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
2000 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
2001 #define PRS_REG_E1HOV_MODE 0x401c8
2002 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
2003 start message to TCM. */
2004 #define PRS_REG_EVENT_ID_1 0x40054
2005 #define PRS_REG_EVENT_ID_2 0x40058
2006 #define PRS_REG_EVENT_ID_3 0x4005c
2007 /* [RW 16] The Ethernet type value for FCoE */
2008 #define PRS_REG_FCOE_TYPE 0x401d0
2009 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
2010 load request message. */
2011 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
2012 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
2013 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
2014 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
2015 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
2016 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
2017 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
2018 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
2019 /* [RW 4] The increment value to send in the CFC load request message */
2020 #define PRS_REG_INC_VALUE 0x40048
2021 /* [RW 1] If set indicates not to send messages to CFC on received packets */
2022 #define PRS_REG_NIC_MODE 0x40138
2023 /* [RW 8] The 8-bit event ID for cases where there is no match on the
2024 connection. Used in packet start message to TCM. */
2025 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
2026 /* [ST 24] The number of input CFC flush packets */
2027 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
2028 /* [ST 32] The number of cycles the Parser halted its operation since it
2029 could not allocate the next serial number */
2030 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
2031 /* [ST 24] The number of input packets */
2032 #define PRS_REG_NUM_OF_PACKETS 0x40124
2033 /* [ST 24] The number of input transparent flush packets */
2034 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
2035 /* [RW 8] Context region for received Ethernet packet with a match and
2036 packet type 0. Used in CFC load request message */
2037 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
2038 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
2039 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
2040 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
2041 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
2042 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
2043 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
2044 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
2045 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
2046 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
2047 /* [R 2] debug only: Number of pending requests for header parsing. */
2048 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
2049 /* [R 1] Interrupt register #0 read */
2050 #define PRS_REG_PRS_INT_STS 0x40188
2051 /* [RW 8] Parity mask register #0 read/write */
2052 #define PRS_REG_PRS_PRTY_MASK 0x401a4
2053 /* [R 8] Parity register #0 read */
2054 #define PRS_REG_PRS_PRTY_STS 0x40198
2055 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
2057 #define PRS_REG_PURE_REGIONS 0x40024
2058 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
2059 serail number was released by SDM but cannot be used because a previous
2060 serial number was not released. */
2061 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
2062 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
2063 serail number was released by SDM but cannot be used because a previous
2064 serial number was not released. */
2065 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
2066 /* [R 4] debug only: SRC current credit. Transaction based. */
2067 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
2068 /* [R 8] debug only: TCM current credit. Cycle based. */
2069 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
2070 /* [R 8] debug only: TSDM current credit. Transaction based. */
2071 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
2072 /* [R 6] Debug only: Number of used entries in the data FIFO */
2073 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
2074 /* [R 7] Debug only: Number of used entries in the header FIFO */
2075 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
2076 #define PXP2_REG_PGL_ADDR_88_F0 0x120534
2077 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538
2078 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c
2079 #define PXP2_REG_PGL_ADDR_94_F0 0x120540
2080 #define PXP2_REG_PGL_CONTROL0 0x120490
2081 #define PXP2_REG_PGL_CONTROL1 0x120514
2082 /* [RW 32] third dword data of expansion rom request. this register is
2083 special. reading from it provides a vector outstanding read requests. if
2084 a bit is zero it means that a read request on the corresponding tag did
2085 not finish yet (not all completions have arrived for it) */
2086 #define PXP2_REG_PGL_EXP_ROM2 0x120808
2087 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
2088 its[15:0]-address */
2089 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
2090 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
2091 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
2092 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
2093 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
2094 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
2095 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
2096 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
2097 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
2098 its[15:0]-address */
2099 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
2100 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
2101 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
2102 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
2103 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
2104 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
2105 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
2106 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
2107 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
2108 its[15:0]-address */
2109 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
2110 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
2111 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
2112 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
2113 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
2114 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
2115 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
2116 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
2117 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
2118 its[15:0]-address */
2119 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
2120 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
2121 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
2122 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
2123 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
2124 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
2125 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
2126 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
2127 /* [RW 3] this field allows one function to pretend being another function
2128 when accessing any BAR mapped resource within the device. the value of
2129 the field is the number of the function that will be accessed
2130 effectively. after software write to this bit it must read it in order to
2131 know that the new value is updated */
2132 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
2133 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
2134 #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
2135 #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
2136 #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
2137 #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
2138 #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
2139 #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
2140 /* [R 1] this bit indicates that a read request was blocked because of
2141 bus_master_en was deasserted */
2142 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
2143 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
2144 /* [R 18] debug only */
2145 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
2146 /* [R 1] this bit indicates that a write request was blocked because of
2147 bus_master_en was deasserted */
2148 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
2149 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
2150 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2151 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2152 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2153 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2154 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
2155 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2156 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2157 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
2158 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
2159 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
2160 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
2161 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
2162 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
2163 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
2164 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2165 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2166 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2167 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2168 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
2169 #define PXP2_REG_PSWRQ_BW_L28 0x120318
2170 #define PXP2_REG_PSWRQ_BW_L28 0x120318
2171 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
2172 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
2173 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
2174 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
2175 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
2176 #define PXP2_REG_PSWRQ_BW_RD 0x120324
2177 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
2178 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2179 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
2180 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2181 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
2182 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
2183 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2184 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2185 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
2186 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
2187 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
2188 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
2189 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
2190 #define PXP2_REG_PSWRQ_BW_WR 0x120328
2191 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
2192 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
2193 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
2194 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
2195 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
2196 /* [RW 32] Interrupt mask register #0 read/write */
2197 #define PXP2_REG_PXP2_INT_MASK_0 0x120578
2198 /* [R 32] Interrupt register #0 read */
2199 #define PXP2_REG_PXP2_INT_STS_0 0x12056c
2200 #define PXP2_REG_PXP2_INT_STS_1 0x120608
2201 /* [RC 32] Interrupt register #0 read clear */
2202 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
2203 /* [RW 32] Parity mask register #0 read/write */
2204 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
2205 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
2206 /* [R 32] Parity register #0 read */
2207 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
2208 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
2209 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
2210 indication about backpressure) */
2211 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
2212 /* [R 8] Debug only: The blocks counter - number of unused block ids */
2213 #define PXP2_REG_RD_BLK_CNT 0x120418
2214 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
2215 Must be bigger than 6. Normally should not be changed. */
2216 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
2217 /* [RW 2] CDU byte swapping mode configuration for master read requests */
2218 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
2219 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
2220 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
2221 /* [R 1] PSWRD internal memories initialization is done */
2222 #define PXP2_REG_RD_INIT_DONE 0x120370
2223 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2224 allocated for vq10 */
2225 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
2226 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2227 allocated for vq11 */
2228 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
2229 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2230 allocated for vq17 */
2231 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
2232 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2233 allocated for vq18 */
2234 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
2235 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2236 allocated for vq19 */
2237 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
2238 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2239 allocated for vq22 */
2240 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
2241 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2242 allocated for vq6 */
2243 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
2244 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2245 allocated for vq9 */
2246 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
2247 /* [RW 2] PBF byte swapping mode configuration for master read requests */
2248 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
2249 /* [R 1] Debug only: Indication if delivery ports are idle */
2250 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
2251 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
2252 /* [RW 2] QM byte swapping mode configuration for master read requests */
2253 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
2254 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
2255 #define PXP2_REG_RD_SR_CNT 0x120414
2256 /* [RW 2] SRC byte swapping mode configuration for master read requests */
2257 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
2258 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
2259 be bigger than 1. Normally should not be changed. */
2260 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
2261 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
2262 #define PXP2_REG_RD_START_INIT 0x12036c
2263 /* [RW 2] TM byte swapping mode configuration for master read requests */
2264 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
2265 /* [RW 10] Bandwidth addition to VQ0 write requests */
2266 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
2267 /* [RW 10] Bandwidth addition to VQ12 read requests */
2268 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
2269 /* [RW 10] Bandwidth addition to VQ13 read requests */
2270 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
2271 /* [RW 10] Bandwidth addition to VQ14 read requests */
2272 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
2273 /* [RW 10] Bandwidth addition to VQ15 read requests */
2274 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
2275 /* [RW 10] Bandwidth addition to VQ16 read requests */
2276 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
2277 /* [RW 10] Bandwidth addition to VQ17 read requests */
2278 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
2279 /* [RW 10] Bandwidth addition to VQ18 read requests */
2280 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
2281 /* [RW 10] Bandwidth addition to VQ19 read requests */
2282 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
2283 /* [RW 10] Bandwidth addition to VQ20 read requests */
2284 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
2285 /* [RW 10] Bandwidth addition to VQ22 read requests */
2286 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
2287 /* [RW 10] Bandwidth addition to VQ23 read requests */
2288 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
2289 /* [RW 10] Bandwidth addition to VQ24 read requests */
2290 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
2291 /* [RW 10] Bandwidth addition to VQ25 read requests */
2292 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
2293 /* [RW 10] Bandwidth addition to VQ26 read requests */
2294 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
2295 /* [RW 10] Bandwidth addition to VQ27 read requests */
2296 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
2297 /* [RW 10] Bandwidth addition to VQ4 read requests */
2298 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
2299 /* [RW 10] Bandwidth addition to VQ5 read requests */
2300 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
2301 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
2302 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
2303 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
2304 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
2305 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
2306 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
2307 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
2308 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
2309 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
2310 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
2311 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
2312 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
2313 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
2314 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
2315 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
2316 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
2317 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
2318 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
2319 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
2320 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
2321 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
2322 #define PXP2_REG_RQ_BW_RD_L22 0x120300
2323 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
2324 #define PXP2_REG_RQ_BW_RD_L23 0x120304
2325 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
2326 #define PXP2_REG_RQ_BW_RD_L24 0x120308
2327 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
2328 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
2329 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
2330 #define PXP2_REG_RQ_BW_RD_L26 0x120310
2331 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
2332 #define PXP2_REG_RQ_BW_RD_L27 0x120314
2333 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
2334 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
2335 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
2336 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
2337 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
2338 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
2339 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
2340 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
2341 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
2342 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
2343 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
2344 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
2345 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
2346 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
2347 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
2348 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
2349 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
2350 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
2351 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
2352 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
2353 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
2354 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
2355 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
2356 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
2357 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
2358 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
2359 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
2360 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
2361 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
2362 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
2363 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
2364 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
2365 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
2366 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
2367 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
2368 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
2369 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
2370 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
2371 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
2372 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
2373 /* [RW 10] Bandwidth addition to VQ29 write requests */
2374 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
2375 /* [RW 10] Bandwidth addition to VQ30 write requests */
2376 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
2377 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
2378 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
2379 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
2380 #define PXP2_REG_RQ_BW_WR_L30 0x120320
2381 /* [RW 7] Bandwidth upper bound for VQ29 */
2382 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
2383 /* [RW 7] Bandwidth upper bound for VQ30 */
2384 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
2385 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
2386 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
2387 /* [RW 2] Endian mode for cdu */
2388 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
2389 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
2390 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
2391 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
2393 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
2394 /* [R 1] 1' indicates that the requester has finished its internal
2396 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
2397 /* [RW 2] Endian mode for debug */
2398 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
2399 /* [RW 1] When '1'; requests will enter input buffers but wont get out
2401 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
2402 /* [RW 1] 1 - SR will be aligned by 64B; 0 - SR will be aligned by 8B */
2403 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
2404 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
2406 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c
2407 /* [RW 2] Endian mode for hc */
2408 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
2409 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
2410 compatibility needs; Note that different registers are used per mode */
2411 #define PXP2_REG_RQ_ILT_MODE 0x1205b4
2412 /* [WB 53] Onchip address table */
2413 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
2414 /* [WB 53] Onchip address table - B0 */
2415 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
2416 /* [RW 13] Pending read limiter threshold; in Dwords */
2417 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
2418 /* [RW 2] Endian mode for qm */
2419 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
2420 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
2421 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638
2422 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2424 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
2425 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
2426 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
2427 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
2428 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2429 #define PXP2_REG_RQ_RD_MBS0 0x120160
2430 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
2431 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2432 #define PXP2_REG_RQ_RD_MBS1 0x120168
2433 /* [RW 2] Endian mode for src */
2434 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
2435 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
2436 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
2437 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
2439 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
2440 /* [RW 2] Endian mode for tm */
2441 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
2442 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
2443 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648
2444 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
2446 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
2447 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
2448 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
2449 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
2450 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
2451 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
2452 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
2453 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
2454 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
2455 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
2456 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
2457 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
2458 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
2459 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
2460 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
2461 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
2462 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
2463 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
2464 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
2465 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
2466 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
2467 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
2468 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
2469 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
2470 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
2471 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
2472 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
2473 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
2474 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
2475 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
2476 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
2477 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
2478 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
2479 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
2480 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
2481 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
2482 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
2483 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
2484 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
2485 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
2486 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
2487 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
2488 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
2489 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
2490 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
2491 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
2492 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
2493 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
2494 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
2495 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
2496 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
2497 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
2498 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
2499 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
2500 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
2501 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
2502 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
2503 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
2504 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
2505 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
2506 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
2507 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
2508 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
2509 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
2510 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
2511 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
2512 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
2513 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
2514 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
2515 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
2516 001:256B; 010: 512B; */
2517 #define PXP2_REG_RQ_WR_MBS0 0x12015c
2518 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
2519 001:256B; 010: 512B; */
2520 #define PXP2_REG_RQ_WR_MBS1 0x120164
2521 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2522 buffer reaches this number has_payload will be asserted */
2523 #define PXP2_REG_WR_CDU_MPS 0x1205f0
2524 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2525 buffer reaches this number has_payload will be asserted */
2526 #define PXP2_REG_WR_CSDM_MPS 0x1205d0
2527 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2528 buffer reaches this number has_payload will be asserted */
2529 #define PXP2_REG_WR_DBG_MPS 0x1205e8
2530 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2531 buffer reaches this number has_payload will be asserted */
2532 #define PXP2_REG_WR_DMAE_MPS 0x1205ec
2533 /* [RW 10] if Number of entries in dmae fifo will be higher than this
2534 threshold then has_payload indication will be asserted; the default value
2535 should be equal to > write MBS size! */
2536 #define PXP2_REG_WR_DMAE_TH 0x120368
2537 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2538 buffer reaches this number has_payload will be asserted */
2539 #define PXP2_REG_WR_HC_MPS 0x1205c8
2540 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2541 buffer reaches this number has_payload will be asserted */
2542 #define PXP2_REG_WR_QM_MPS 0x1205dc
2543 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
2544 #define PXP2_REG_WR_REV_MODE 0x120670
2545 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2546 buffer reaches this number has_payload will be asserted */
2547 #define PXP2_REG_WR_SRC_MPS 0x1205e4
2548 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2549 buffer reaches this number has_payload will be asserted */
2550 #define PXP2_REG_WR_TM_MPS 0x1205e0
2551 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2552 buffer reaches this number has_payload will be asserted */
2553 #define PXP2_REG_WR_TSDM_MPS 0x1205d4
2554 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this
2555 threshold then has_payload indication will be asserted; the default value
2556 should be equal to > write MBS size! */
2557 #define PXP2_REG_WR_USDMDP_TH 0x120348
2558 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2559 buffer reaches this number has_payload will be asserted */
2560 #define PXP2_REG_WR_USDM_MPS 0x1205cc
2561 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
2562 buffer reaches this number has_payload will be asserted */
2563 #define PXP2_REG_WR_XSDM_MPS 0x1205d8
2564 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
2565 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
2566 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
2567 this client is waiting for the arbiter. */
2568 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
2569 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
2570 should update accoring to 'hst_discard_doorbells' register when the state
2572 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
2573 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
2574 means this PSWHST is discarding inputs from this client. Each bit should
2575 update accoring to 'hst_discard_internal_writes' register when the state
2577 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
2578 /* [WB 160] Used for initialization of the inbound interrupts memory */
2579 #define PXP_REG_HST_INBOUND_INT 0x103800
2580 /* [RW 32] Interrupt mask register #0 read/write */
2581 #define PXP_REG_PXP_INT_MASK_0 0x103074
2582 #define PXP_REG_PXP_INT_MASK_1 0x103084
2583 /* [R 32] Interrupt register #0 read */
2584 #define PXP_REG_PXP_INT_STS_0 0x103068
2585 #define PXP_REG_PXP_INT_STS_1 0x103078
2586 /* [RC 32] Interrupt register #0 read clear */
2587 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
2588 /* [RW 26] Parity mask register #0 read/write */
2589 #define PXP_REG_PXP_PRTY_MASK 0x103094
2590 /* [R 26] Parity register #0 read */
2591 #define PXP_REG_PXP_PRTY_STS 0x103088
2592 /* [RW 4] The activity counter initial increment value sent in the load
2594 #define QM_REG_ACTCTRINITVAL_0 0x168040
2595 #define QM_REG_ACTCTRINITVAL_1 0x168044
2596 #define QM_REG_ACTCTRINITVAL_2 0x168048
2597 #define QM_REG_ACTCTRINITVAL_3 0x16804c
2598 /* [RW 32] The base logical address (in bytes) of each physical queue. The
2599 index I represents the physical queue number. The 12 lsbs are ignore and
2600 considered zero so practically there are only 20 bits in this register;
2602 #define QM_REG_BASEADDR 0x168900
2603 /* [RW 32] The base logical address (in bytes) of each physical queue. The
2604 index I represents the physical queue number. The 12 lsbs are ignore and
2605 considered zero so practically there are only 20 bits in this register;
2607 #define QM_REG_BASEADDR_EXT_A 0x16e100
2608 /* [RW 16] The byte credit cost for each task. This value is for both ports */
2609 #define QM_REG_BYTECRDCOST 0x168234
2610 /* [RW 16] The initial byte credit value for both ports. */
2611 #define QM_REG_BYTECRDINITVAL 0x168238
2612 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2613 queue uses port 0 else it uses port 1; queues 31-0 */
2614 #define QM_REG_BYTECRDPORT_LSB 0x168228
2615 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2616 queue uses port 0 else it uses port 1; queues 95-64 */
2617 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
2618 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2619 queue uses port 0 else it uses port 1; queues 63-32 */
2620 #define QM_REG_BYTECRDPORT_MSB 0x168224
2621 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2622 queue uses port 0 else it uses port 1; queues 127-96 */
2623 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
2624 /* [RW 16] The byte credit value that if above the QM is considered almost
2626 #define QM_REG_BYTECREDITAFULLTHR 0x168094
2627 /* [RW 4] The initial credit for interface */
2628 #define QM_REG_CMINITCRD_0 0x1680cc
2629 #define QM_REG_CMINITCRD_1 0x1680d0
2630 #define QM_REG_CMINITCRD_2 0x1680d4
2631 #define QM_REG_CMINITCRD_3 0x1680d8
2632 #define QM_REG_CMINITCRD_4 0x1680dc
2633 #define QM_REG_CMINITCRD_5 0x1680e0
2634 #define QM_REG_CMINITCRD_6 0x1680e4
2635 #define QM_REG_CMINITCRD_7 0x1680e8
2636 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
2638 #define QM_REG_CMINTEN 0x1680ec
2639 /* [RW 12] A bit vector which indicates which one of the queues are tied to
2641 #define QM_REG_CMINTVOQMASK_0 0x1681f4
2642 #define QM_REG_CMINTVOQMASK_1 0x1681f8
2643 #define QM_REG_CMINTVOQMASK_2 0x1681fc
2644 #define QM_REG_CMINTVOQMASK_3 0x168200
2645 #define QM_REG_CMINTVOQMASK_4 0x168204
2646 #define QM_REG_CMINTVOQMASK_5 0x168208
2647 #define QM_REG_CMINTVOQMASK_6 0x16820c
2648 #define QM_REG_CMINTVOQMASK_7 0x168210
2649 /* [RW 20] The number of connections divided by 16 which dictates the size
2650 of each queue which belongs to even function number. */
2651 #define QM_REG_CONNNUM_0 0x168020
2652 /* [R 6] Keep the fill level of the fifo from write client 4 */
2653 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
2654 /* [RW 8] The context regions sent in the CFC load request */
2655 #define QM_REG_CTXREG_0 0x168030
2656 #define QM_REG_CTXREG_1 0x168034
2657 #define QM_REG_CTXREG_2 0x168038
2658 #define QM_REG_CTXREG_3 0x16803c
2659 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
2661 #define QM_REG_ENBYPVOQMASK 0x16823c
2662 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2663 physical queue uses the byte credit; queues 31-0 */
2664 #define QM_REG_ENBYTECRD_LSB 0x168220
2665 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2666 physical queue uses the byte credit; queues 95-64 */
2667 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
2668 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2669 physical queue uses the byte credit; queues 63-32 */
2670 #define QM_REG_ENBYTECRD_MSB 0x16821c
2671 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2672 physical queue uses the byte credit; queues 127-96 */
2673 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
2674 /* [RW 4] If cleared then the secondary interface will not be served by the
2676 #define QM_REG_ENSEC 0x1680f0
2678 #define QM_REG_FUNCNUMSEL_LSB 0x168230
2680 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
2681 /* [RW 32] A mask register to mask the Almost empty signals which will not
2682 be use for the almost empty indication to the HW block; queues 31:0 */
2683 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
2684 /* [RW 32] A mask register to mask the Almost empty signals which will not
2685 be use for the almost empty indication to the HW block; queues 95-64 */
2686 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
2687 /* [RW 32] A mask register to mask the Almost empty signals which will not
2688 be use for the almost empty indication to the HW block; queues 63:32 */
2689 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
2690 /* [RW 32] A mask register to mask the Almost empty signals which will not
2691 be use for the almost empty indication to the HW block; queues 127-96 */
2692 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
2693 /* [RW 4] The number of outstanding request to CFC */
2694 #define QM_REG_OUTLDREQ 0x168804
2695 /* [RC 1] A flag to indicate that overflow error occurred in one of the
2697 #define QM_REG_OVFERROR 0x16805c
2698 /* [RC 7] the Q were the qverflow occurs */
2699 #define QM_REG_OVFQNUM 0x168058
2700 /* [R 16] Pause state for physical queues 15-0 */
2701 #define QM_REG_PAUSESTATE0 0x168410
2702 /* [R 16] Pause state for physical queues 31-16 */
2703 #define QM_REG_PAUSESTATE1 0x168414
2704 /* [R 16] Pause state for physical queues 47-32 */
2705 #define QM_REG_PAUSESTATE2 0x16e684
2706 /* [R 16] Pause state for physical queues 63-48 */
2707 #define QM_REG_PAUSESTATE3 0x16e688
2708 /* [R 16] Pause state for physical queues 79-64 */
2709 #define QM_REG_PAUSESTATE4 0x16e68c
2710 /* [R 16] Pause state for physical queues 95-80 */
2711 #define QM_REG_PAUSESTATE5 0x16e690
2712 /* [R 16] Pause state for physical queues 111-96 */
2713 #define QM_REG_PAUSESTATE6 0x16e694
2714 /* [R 16] Pause state for physical queues 127-112 */
2715 #define QM_REG_PAUSESTATE7 0x16e698
2716 /* [RW 2] The PCI attributes field used in the PCI request. */
2717 #define QM_REG_PCIREQAT 0x168054
2718 /* [R 16] The byte credit of port 0 */
2719 #define QM_REG_PORT0BYTECRD 0x168300
2720 /* [R 16] The byte credit of port 1 */
2721 #define QM_REG_PORT1BYTECRD 0x168304
2722 /* [RW 3] pci function number of queues 15-0 */
2723 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc
2724 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0
2725 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4
2726 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8
2727 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc
2728 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0
2729 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4
2730 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8
2731 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
2732 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2733 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2734 #define QM_REG_PTRTBL 0x168a00
2735 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
2736 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
2737 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2738 #define QM_REG_PTRTBL_EXT_A 0x16e200
2739 /* [RW 2] Interrupt mask register #0 read/write */
2740 #define QM_REG_QM_INT_MASK 0x168444
2741 /* [R 2] Interrupt register #0 read */
2742 #define QM_REG_QM_INT_STS 0x168438
2743 /* [RW 12] Parity mask register #0 read/write */
2744 #define QM_REG_QM_PRTY_MASK 0x168454
2745 /* [R 12] Parity register #0 read */
2746 #define QM_REG_QM_PRTY_STS 0x168448
2747 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
2748 #define QM_REG_QSTATUS_HIGH 0x16802c
2749 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
2750 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
2751 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
2752 #define QM_REG_QSTATUS_LOW 0x168028
2753 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */
2754 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
2755 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
2756 #define QM_REG_QTASKCTR_0 0x168308
2757 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
2758 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584
2759 /* [RW 4] Queue tied to VOQ */
2760 #define QM_REG_QVOQIDX_0 0x1680f4
2761 #define QM_REG_QVOQIDX_10 0x16811c
2762 #define QM_REG_QVOQIDX_100 0x16e49c
2763 #define QM_REG_QVOQIDX_101 0x16e4a0
2764 #define QM_REG_QVOQIDX_102 0x16e4a4
2765 #define QM_REG_QVOQIDX_103 0x16e4a8
2766 #define QM_REG_QVOQIDX_104 0x16e4ac
2767 #define QM_REG_QVOQIDX_105 0x16e4b0
2768 #define QM_REG_QVOQIDX_106 0x16e4b4
2769 #define QM_REG_QVOQIDX_107 0x16e4b8
2770 #define QM_REG_QVOQIDX_108 0x16e4bc
2771 #define QM_REG_QVOQIDX_109 0x16e4c0
2772 #define QM_REG_QVOQIDX_100 0x16e49c
2773 #define QM_REG_QVOQIDX_101 0x16e4a0
2774 #define QM_REG_QVOQIDX_102 0x16e4a4
2775 #define QM_REG_QVOQIDX_103 0x16e4a8
2776 #define QM_REG_QVOQIDX_104 0x16e4ac
2777 #define QM_REG_QVOQIDX_105 0x16e4b0
2778 #define QM_REG_QVOQIDX_106 0x16e4b4
2779 #define QM_REG_QVOQIDX_107 0x16e4b8
2780 #define QM_REG_QVOQIDX_108 0x16e4bc
2781 #define QM_REG_QVOQIDX_109 0x16e4c0
2782 #define QM_REG_QVOQIDX_11 0x168120
2783 #define QM_REG_QVOQIDX_110 0x16e4c4
2784 #define QM_REG_QVOQIDX_111 0x16e4c8
2785 #define QM_REG_QVOQIDX_112 0x16e4cc
2786 #define QM_REG_QVOQIDX_113 0x16e4d0
2787 #define QM_REG_QVOQIDX_114 0x16e4d4
2788 #define QM_REG_QVOQIDX_115 0x16e4d8
2789 #define QM_REG_QVOQIDX_116 0x16e4dc
2790 #define QM_REG_QVOQIDX_117 0x16e4e0
2791 #define QM_REG_QVOQIDX_118 0x16e4e4
2792 #define QM_REG_QVOQIDX_119 0x16e4e8
2793 #define QM_REG_QVOQIDX_110 0x16e4c4
2794 #define QM_REG_QVOQIDX_111 0x16e4c8
2795 #define QM_REG_QVOQIDX_112 0x16e4cc
2796 #define QM_REG_QVOQIDX_113 0x16e4d0
2797 #define QM_REG_QVOQIDX_114 0x16e4d4
2798 #define QM_REG_QVOQIDX_115 0x16e4d8
2799 #define QM_REG_QVOQIDX_116 0x16e4dc
2800 #define QM_REG_QVOQIDX_117 0x16e4e0
2801 #define QM_REG_QVOQIDX_118 0x16e4e4
2802 #define QM_REG_QVOQIDX_119 0x16e4e8
2803 #define QM_REG_QVOQIDX_12 0x168124
2804 #define QM_REG_QVOQIDX_120 0x16e4ec
2805 #define QM_REG_QVOQIDX_121 0x16e4f0
2806 #define QM_REG_QVOQIDX_122 0x16e4f4
2807 #define QM_REG_QVOQIDX_123 0x16e4f8
2808 #define QM_REG_QVOQIDX_124 0x16e4fc
2809 #define QM_REG_QVOQIDX_125 0x16e500
2810 #define QM_REG_QVOQIDX_126 0x16e504
2811 #define QM_REG_QVOQIDX_127 0x16e508
2812 #define QM_REG_QVOQIDX_120 0x16e4ec
2813 #define QM_REG_QVOQIDX_121 0x16e4f0
2814 #define QM_REG_QVOQIDX_122 0x16e4f4
2815 #define QM_REG_QVOQIDX_123 0x16e4f8
2816 #define QM_REG_QVOQIDX_124 0x16e4fc
2817 #define QM_REG_QVOQIDX_125 0x16e500
2818 #define QM_REG_QVOQIDX_126 0x16e504
2819 #define QM_REG_QVOQIDX_127 0x16e508
2820 #define QM_REG_QVOQIDX_13 0x168128
2821 #define QM_REG_QVOQIDX_14 0x16812c
2822 #define QM_REG_QVOQIDX_15 0x168130
2823 #define QM_REG_QVOQIDX_16 0x168134
2824 #define QM_REG_QVOQIDX_17 0x168138
2825 #define QM_REG_QVOQIDX_21 0x168148
2826 #define QM_REG_QVOQIDX_22 0x16814c
2827 #define QM_REG_QVOQIDX_23 0x168150
2828 #define QM_REG_QVOQIDX_24 0x168154
2829 #define QM_REG_QVOQIDX_25 0x168158
2830 #define QM_REG_QVOQIDX_26 0x16815c
2831 #define QM_REG_QVOQIDX_27 0x168160
2832 #define QM_REG_QVOQIDX_28 0x168164
2833 #define QM_REG_QVOQIDX_29 0x168168
2834 #define QM_REG_QVOQIDX_30 0x16816c
2835 #define QM_REG_QVOQIDX_31 0x168170
2836 #define QM_REG_QVOQIDX_32 0x168174
2837 #define QM_REG_QVOQIDX_33 0x168178
2838 #define QM_REG_QVOQIDX_34 0x16817c
2839 #define QM_REG_QVOQIDX_35 0x168180
2840 #define QM_REG_QVOQIDX_36 0x168184
2841 #define QM_REG_QVOQIDX_37 0x168188
2842 #define QM_REG_QVOQIDX_38 0x16818c
2843 #define QM_REG_QVOQIDX_39 0x168190
2844 #define QM_REG_QVOQIDX_40 0x168194
2845 #define QM_REG_QVOQIDX_41 0x168198
2846 #define QM_REG_QVOQIDX_42 0x16819c
2847 #define QM_REG_QVOQIDX_43 0x1681a0
2848 #define QM_REG_QVOQIDX_44 0x1681a4
2849 #define QM_REG_QVOQIDX_45 0x1681a8
2850 #define QM_REG_QVOQIDX_46 0x1681ac
2851 #define QM_REG_QVOQIDX_47 0x1681b0
2852 #define QM_REG_QVOQIDX_48 0x1681b4
2853 #define QM_REG_QVOQIDX_49 0x1681b8
2854 #define QM_REG_QVOQIDX_5 0x168108
2855 #define QM_REG_QVOQIDX_50 0x1681bc
2856 #define QM_REG_QVOQIDX_51 0x1681c0
2857 #define QM_REG_QVOQIDX_52 0x1681c4
2858 #define QM_REG_QVOQIDX_53 0x1681c8
2859 #define QM_REG_QVOQIDX_54 0x1681cc
2860 #define QM_REG_QVOQIDX_55 0x1681d0
2861 #define QM_REG_QVOQIDX_56 0x1681d4
2862 #define QM_REG_QVOQIDX_57 0x1681d8
2863 #define QM_REG_QVOQIDX_58 0x1681dc
2864 #define QM_REG_QVOQIDX_59 0x1681e0
2865 #define QM_REG_QVOQIDX_50 0x1681bc
2866 #define QM_REG_QVOQIDX_51 0x1681c0
2867 #define QM_REG_QVOQIDX_52 0x1681c4
2868 #define QM_REG_QVOQIDX_53 0x1681c8
2869 #define QM_REG_QVOQIDX_54 0x1681cc
2870 #define QM_REG_QVOQIDX_55 0x1681d0
2871 #define QM_REG_QVOQIDX_56 0x1681d4
2872 #define QM_REG_QVOQIDX_57 0x1681d8
2873 #define QM_REG_QVOQIDX_58 0x1681dc
2874 #define QM_REG_QVOQIDX_59 0x1681e0
2875 #define QM_REG_QVOQIDX_6 0x16810c
2876 #define QM_REG_QVOQIDX_60 0x1681e4
2877 #define QM_REG_QVOQIDX_61 0x1681e8
2878 #define QM_REG_QVOQIDX_62 0x1681ec
2879 #define QM_REG_QVOQIDX_63 0x1681f0
2880 #define QM_REG_QVOQIDX_64 0x16e40c
2881 #define QM_REG_QVOQIDX_65 0x16e410
2882 #define QM_REG_QVOQIDX_66 0x16e414
2883 #define QM_REG_QVOQIDX_67 0x16e418
2884 #define QM_REG_QVOQIDX_68 0x16e41c
2885 #define QM_REG_QVOQIDX_69 0x16e420
2886 #define QM_REG_QVOQIDX_60 0x1681e4
2887 #define QM_REG_QVOQIDX_61 0x1681e8
2888 #define QM_REG_QVOQIDX_62 0x1681ec
2889 #define QM_REG_QVOQIDX_63 0x1681f0
2890 #define QM_REG_QVOQIDX_64 0x16e40c
2891 #define QM_REG_QVOQIDX_65 0x16e410
2892 #define QM_REG_QVOQIDX_69 0x16e420
2893 #define QM_REG_QVOQIDX_7 0x168110
2894 #define QM_REG_QVOQIDX_70 0x16e424
2895 #define QM_REG_QVOQIDX_71 0x16e428
2896 #define QM_REG_QVOQIDX_72 0x16e42c
2897 #define QM_REG_QVOQIDX_73 0x16e430
2898 #define QM_REG_QVOQIDX_74 0x16e434
2899 #define QM_REG_QVOQIDX_75 0x16e438
2900 #define QM_REG_QVOQIDX_76 0x16e43c
2901 #define QM_REG_QVOQIDX_77 0x16e440
2902 #define QM_REG_QVOQIDX_78 0x16e444
2903 #define QM_REG_QVOQIDX_79 0x16e448
2904 #define QM_REG_QVOQIDX_70 0x16e424
2905 #define QM_REG_QVOQIDX_71 0x16e428
2906 #define QM_REG_QVOQIDX_72 0x16e42c
2907 #define QM_REG_QVOQIDX_73 0x16e430
2908 #define QM_REG_QVOQIDX_74 0x16e434
2909 #define QM_REG_QVOQIDX_75 0x16e438
2910 #define QM_REG_QVOQIDX_76 0x16e43c
2911 #define QM_REG_QVOQIDX_77 0x16e440
2912 #define QM_REG_QVOQIDX_78 0x16e444
2913 #define QM_REG_QVOQIDX_79 0x16e448
2914 #define QM_REG_QVOQIDX_8 0x168114
2915 #define QM_REG_QVOQIDX_80 0x16e44c
2916 #define QM_REG_QVOQIDX_81 0x16e450
2917 #define QM_REG_QVOQIDX_82 0x16e454
2918 #define QM_REG_QVOQIDX_83 0x16e458
2919 #define QM_REG_QVOQIDX_84 0x16e45c
2920 #define QM_REG_QVOQIDX_85 0x16e460
2921 #define QM_REG_QVOQIDX_86 0x16e464
2922 #define QM_REG_QVOQIDX_87 0x16e468
2923 #define QM_REG_QVOQIDX_88 0x16e46c
2924 #define QM_REG_QVOQIDX_89 0x16e470
2925 #define QM_REG_QVOQIDX_80 0x16e44c
2926 #define QM_REG_QVOQIDX_81 0x16e450
2927 #define QM_REG_QVOQIDX_85 0x16e460
2928 #define QM_REG_QVOQIDX_86 0x16e464
2929 #define QM_REG_QVOQIDX_87 0x16e468
2930 #define QM_REG_QVOQIDX_88 0x16e46c
2931 #define QM_REG_QVOQIDX_89 0x16e470
2932 #define QM_REG_QVOQIDX_9 0x168118
2933 #define QM_REG_QVOQIDX_90 0x16e474
2934 #define QM_REG_QVOQIDX_91 0x16e478
2935 #define QM_REG_QVOQIDX_92 0x16e47c
2936 #define QM_REG_QVOQIDX_93 0x16e480
2937 #define QM_REG_QVOQIDX_94 0x16e484
2938 #define QM_REG_QVOQIDX_95 0x16e488
2939 #define QM_REG_QVOQIDX_96 0x16e48c
2940 #define QM_REG_QVOQIDX_97 0x16e490
2941 #define QM_REG_QVOQIDX_98 0x16e494
2942 #define QM_REG_QVOQIDX_99 0x16e498
2943 #define QM_REG_QVOQIDX_90 0x16e474
2944 #define QM_REG_QVOQIDX_91 0x16e478
2945 #define QM_REG_QVOQIDX_92 0x16e47c
2946 #define QM_REG_QVOQIDX_93 0x16e480
2947 #define QM_REG_QVOQIDX_94 0x16e484
2948 #define QM_REG_QVOQIDX_95 0x16e488
2949 #define QM_REG_QVOQIDX_96 0x16e48c
2950 #define QM_REG_QVOQIDX_97 0x16e490
2951 #define QM_REG_QVOQIDX_98 0x16e494
2952 #define QM_REG_QVOQIDX_99 0x16e498
2953 /* [RW 1] Initialization bit command */
2954 #define QM_REG_SOFT_RESET 0x168428
2955 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
2956 #define QM_REG_TASKCRDCOST_0 0x16809c
2957 #define QM_REG_TASKCRDCOST_1 0x1680a0
2958 #define QM_REG_TASKCRDCOST_10 0x1680c4
2959 #define QM_REG_TASKCRDCOST_11 0x1680c8
2960 #define QM_REG_TASKCRDCOST_2 0x1680a4
2961 #define QM_REG_TASKCRDCOST_4 0x1680ac
2962 #define QM_REG_TASKCRDCOST_5 0x1680b0
2963 /* [R 6] Keep the fill level of the fifo from write client 3 */
2964 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
2965 /* [R 6] Keep the fill level of the fifo from write client 2 */
2966 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
2967 /* [RC 32] Credit update error register */
2968 #define QM_REG_VOQCRDERRREG 0x168408
2969 /* [R 16] The credit value for each VOQ */
2970 #define QM_REG_VOQCREDIT_0 0x1682d0
2971 #define QM_REG_VOQCREDIT_1 0x1682d4
2972 #define QM_REG_VOQCREDIT_10 0x1682f8
2973 #define QM_REG_VOQCREDIT_11 0x1682fc
2974 #define QM_REG_VOQCREDIT_4 0x1682e0
2975 /* [RW 16] The credit value that if above the QM is considered almost full */
2976 #define QM_REG_VOQCREDITAFULLTHR 0x168090
2977 /* [RW 16] The init and maximum credit for each VoQ */
2978 #define QM_REG_VOQINITCREDIT_0 0x168060
2979 #define QM_REG_VOQINITCREDIT_1 0x168064
2980 #define QM_REG_VOQINITCREDIT_10 0x168088
2981 #define QM_REG_VOQINITCREDIT_11 0x16808c
2982 #define QM_REG_VOQINITCREDIT_2 0x168068
2983 #define QM_REG_VOQINITCREDIT_4 0x168070
2984 #define QM_REG_VOQINITCREDIT_5 0x168074
2985 /* [RW 1] The port of which VOQ belongs */
2986 #define QM_REG_VOQPORT_0 0x1682a0
2987 #define QM_REG_VOQPORT_1 0x1682a4
2988 #define QM_REG_VOQPORT_10 0x1682c8
2989 #define QM_REG_VOQPORT_11 0x1682cc
2990 #define QM_REG_VOQPORT_2 0x1682a8
2991 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
2992 #define QM_REG_VOQQMASK_0_LSB 0x168240
2993 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
2994 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
2995 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
2996 #define QM_REG_VOQQMASK_0_MSB 0x168244
2997 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
2998 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
2999 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3000 #define QM_REG_VOQQMASK_10_LSB 0x168290
3001 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3002 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
3003 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3004 #define QM_REG_VOQQMASK_10_MSB 0x168294
3005 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3006 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
3007 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3008 #define QM_REG_VOQQMASK_11_LSB 0x168298
3009 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3010 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
3011 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3012 #define QM_REG_VOQQMASK_11_MSB 0x16829c
3013 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3014 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
3015 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3016 #define QM_REG_VOQQMASK_1_LSB 0x168248
3017 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3018 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
3019 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3020 #define QM_REG_VOQQMASK_1_MSB 0x16824c
3021 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3022 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
3023 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3024 #define QM_REG_VOQQMASK_2_LSB 0x168250
3025 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3026 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
3027 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3028 #define QM_REG_VOQQMASK_2_MSB 0x168254
3029 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3030 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
3031 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3032 #define QM_REG_VOQQMASK_3_LSB 0x168258
3033 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3034 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
3035 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3036 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
3037 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3038 #define QM_REG_VOQQMASK_4_LSB 0x168260
3039 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3040 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
3041 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3042 #define QM_REG_VOQQMASK_4_MSB 0x168264
3043 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3044 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
3045 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3046 #define QM_REG_VOQQMASK_5_LSB 0x168268
3047 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3048 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
3049 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3050 #define QM_REG_VOQQMASK_5_MSB 0x16826c
3051 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3052 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
3053 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3054 #define QM_REG_VOQQMASK_6_LSB 0x168270
3055 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3056 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
3057 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3058 #define QM_REG_VOQQMASK_6_MSB 0x168274
3059 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3060 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
3061 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3062 #define QM_REG_VOQQMASK_7_LSB 0x168278
3063 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3064 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
3065 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3066 #define QM_REG_VOQQMASK_7_MSB 0x16827c
3067 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3068 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
3069 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3070 #define QM_REG_VOQQMASK_8_LSB 0x168280
3071 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3072 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
3073 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3074 #define QM_REG_VOQQMASK_8_MSB 0x168284
3075 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3076 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
3077 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3078 #define QM_REG_VOQQMASK_9_LSB 0x168288
3079 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3080 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
3081 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3082 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
3083 /* [RW 32] Wrr weights */
3084 #define QM_REG_WRRWEIGHTS_0 0x16880c
3085 #define QM_REG_WRRWEIGHTS_1 0x168810
3086 #define QM_REG_WRRWEIGHTS_10 0x168814
3087 #define QM_REG_WRRWEIGHTS_10_SIZE 1
3088 /* [RW 32] Wrr weights */
3089 #define QM_REG_WRRWEIGHTS_11 0x168818
3090 #define QM_REG_WRRWEIGHTS_11_SIZE 1
3091 /* [RW 32] Wrr weights */
3092 #define QM_REG_WRRWEIGHTS_12 0x16881c
3093 #define QM_REG_WRRWEIGHTS_12_SIZE 1
3094 /* [RW 32] Wrr weights */
3095 #define QM_REG_WRRWEIGHTS_13 0x168820
3096 #define QM_REG_WRRWEIGHTS_13_SIZE 1
3097 /* [RW 32] Wrr weights */
3098 #define QM_REG_WRRWEIGHTS_14 0x168824
3099 #define QM_REG_WRRWEIGHTS_14_SIZE 1
3100 /* [RW 32] Wrr weights */
3101 #define QM_REG_WRRWEIGHTS_15 0x168828
3102 #define QM_REG_WRRWEIGHTS_15_SIZE 1
3103 /* [RW 32] Wrr weights */
3104 #define QM_REG_WRRWEIGHTS_16 0x16e000
3105 #define QM_REG_WRRWEIGHTS_16_SIZE 1
3106 /* [RW 32] Wrr weights */
3107 #define QM_REG_WRRWEIGHTS_17 0x16e004
3108 #define QM_REG_WRRWEIGHTS_17_SIZE 1
3109 /* [RW 32] Wrr weights */
3110 #define QM_REG_WRRWEIGHTS_18 0x16e008
3111 #define QM_REG_WRRWEIGHTS_18_SIZE 1
3112 /* [RW 32] Wrr weights */
3113 #define QM_REG_WRRWEIGHTS_19 0x16e00c
3114 #define QM_REG_WRRWEIGHTS_19_SIZE 1
3115 /* [RW 32] Wrr weights */
3116 #define QM_REG_WRRWEIGHTS_10 0x168814
3117 #define QM_REG_WRRWEIGHTS_11 0x168818
3118 #define QM_REG_WRRWEIGHTS_12 0x16881c
3119 #define QM_REG_WRRWEIGHTS_13 0x168820
3120 #define QM_REG_WRRWEIGHTS_14 0x168824
3121 #define QM_REG_WRRWEIGHTS_15 0x168828
3122 #define QM_REG_WRRWEIGHTS_16 0x16e000
3123 #define QM_REG_WRRWEIGHTS_17 0x16e004
3124 #define QM_REG_WRRWEIGHTS_18 0x16e008
3125 #define QM_REG_WRRWEIGHTS_19 0x16e00c
3126 #define QM_REG_WRRWEIGHTS_2 0x16882c
3127 #define QM_REG_WRRWEIGHTS_20 0x16e010
3128 #define QM_REG_WRRWEIGHTS_20_SIZE 1
3129 /* [RW 32] Wrr weights */
3130 #define QM_REG_WRRWEIGHTS_21 0x16e014
3131 #define QM_REG_WRRWEIGHTS_21_SIZE 1
3132 /* [RW 32] Wrr weights */
3133 #define QM_REG_WRRWEIGHTS_22 0x16e018
3134 #define QM_REG_WRRWEIGHTS_22_SIZE 1
3135 /* [RW 32] Wrr weights */
3136 #define QM_REG_WRRWEIGHTS_23 0x16e01c
3137 #define QM_REG_WRRWEIGHTS_23_SIZE 1
3138 /* [RW 32] Wrr weights */
3139 #define QM_REG_WRRWEIGHTS_24 0x16e020
3140 #define QM_REG_WRRWEIGHTS_24_SIZE 1
3141 /* [RW 32] Wrr weights */
3142 #define QM_REG_WRRWEIGHTS_25 0x16e024
3143 #define QM_REG_WRRWEIGHTS_25_SIZE 1
3144 /* [RW 32] Wrr weights */
3145 #define QM_REG_WRRWEIGHTS_26 0x16e028
3146 #define QM_REG_WRRWEIGHTS_26_SIZE 1
3147 /* [RW 32] Wrr weights */
3148 #define QM_REG_WRRWEIGHTS_27 0x16e02c
3149 #define QM_REG_WRRWEIGHTS_27_SIZE 1
3150 /* [RW 32] Wrr weights */
3151 #define QM_REG_WRRWEIGHTS_28 0x16e030
3152 #define QM_REG_WRRWEIGHTS_28_SIZE 1
3153 /* [RW 32] Wrr weights */
3154 #define QM_REG_WRRWEIGHTS_29 0x16e034
3155 #define QM_REG_WRRWEIGHTS_29_SIZE 1
3156 /* [RW 32] Wrr weights */
3157 #define QM_REG_WRRWEIGHTS_20 0x16e010
3158 #define QM_REG_WRRWEIGHTS_21 0x16e014
3159 #define QM_REG_WRRWEIGHTS_22 0x16e018
3160 #define QM_REG_WRRWEIGHTS_23 0x16e01c
3161 #define QM_REG_WRRWEIGHTS_24 0x16e020
3162 #define QM_REG_WRRWEIGHTS_25 0x16e024
3163 #define QM_REG_WRRWEIGHTS_26 0x16e028
3164 #define QM_REG_WRRWEIGHTS_27 0x16e02c
3165 #define QM_REG_WRRWEIGHTS_28 0x16e030
3166 #define QM_REG_WRRWEIGHTS_29 0x16e034
3167 #define QM_REG_WRRWEIGHTS_3 0x168830
3168 #define QM_REG_WRRWEIGHTS_30 0x16e038
3169 #define QM_REG_WRRWEIGHTS_30_SIZE 1
3170 /* [RW 32] Wrr weights */
3171 #define QM_REG_WRRWEIGHTS_31 0x16e03c
3172 #define QM_REG_WRRWEIGHTS_31_SIZE 1
3173 /* [RW 32] Wrr weights */
3174 #define QM_REG_WRRWEIGHTS_30 0x16e038
3175 #define QM_REG_WRRWEIGHTS_31 0x16e03c
3176 #define QM_REG_WRRWEIGHTS_4 0x168834
3177 #define QM_REG_WRRWEIGHTS_5 0x168838
3178 #define QM_REG_WRRWEIGHTS_6 0x16883c
3179 #define QM_REG_WRRWEIGHTS_7 0x168840
3180 #define QM_REG_WRRWEIGHTS_8 0x168844
3181 #define QM_REG_WRRWEIGHTS_9 0x168848
3182 /* [R 6] Keep the fill level of the fifo from write client 1 */
3183 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
3184 #define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3185 #define BRB1_BRB1_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3186 #define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3187 #define BRB1_BRB1_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3188 #define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3189 #define BRB1_BRB1_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3190 #define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3191 #define BRB1_BRB1_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3192 #define CCM_CCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3193 #define CCM_CCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3194 #define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3195 #define CCM_CCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3196 #define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3197 #define CCM_CCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3198 #define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3199 #define CCM_CCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3200 #define CDU_CDU_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3201 #define CDU_CDU_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3202 #define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3203 #define CDU_CDU_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3204 #define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3205 #define CDU_CDU_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3206 #define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3207 #define CDU_CDU_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3208 #define CFC_CFC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3209 #define CFC_CFC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3210 #define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3211 #define CFC_CFC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3212 #define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3213 #define CFC_CFC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3214 #define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3215 #define CFC_CFC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3216 #define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3217 #define CSDM_CSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3218 #define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3219 #define CSDM_CSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3220 #define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3221 #define CSDM_CSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3222 #define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3223 #define CSDM_CSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3224 #define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3225 #define CSEM_CSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3226 #define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3227 #define CSEM_CSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3228 #define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3229 #define CSEM_CSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3230 #define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3231 #define CSEM_CSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3232 #define DBG_DBG_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3233 #define DBG_DBG_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3234 #define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3235 #define DBG_DBG_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3236 #define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3237 #define DBG_DBG_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3238 #define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3239 #define DBG_DBG_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3240 #define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3241 #define DMAE_DMAE_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3242 #define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3243 #define DMAE_DMAE_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3244 #define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3245 #define DMAE_DMAE_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3246 #define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3247 #define DMAE_DMAE_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3248 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3249 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3250 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3251 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3252 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3253 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3254 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3255 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3256 #define HC_HC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3257 #define HC_HC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3258 #define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3259 #define HC_HC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3260 #define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3261 #define HC_HC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3262 #define HC_HC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3263 #define HC_HC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3264 #define MISC_MISC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3265 #define MISC_MISC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3266 #define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3267 #define MISC_MISC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3268 #define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3269 #define MISC_MISC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3270 #define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3271 #define MISC_MISC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3272 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3273 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3274 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3275 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3276 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3277 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3278 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3279 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3280 #define PBF_PBF_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3281 #define PBF_PBF_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3282 #define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3283 #define PBF_PBF_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3284 #define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3285 #define PBF_PBF_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3286 #define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3287 #define PBF_PBF_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3288 #define PB_PB_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3289 #define PB_PB_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3290 #define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3291 #define PB_PB_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3292 #define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3293 #define PB_PB_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3294 #define PB_PB_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3295 #define PB_PB_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3296 #define PRS_PRS_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3297 #define PRS_PRS_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3298 #define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3299 #define PRS_PRS_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3300 #define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3301 #define PRS_PRS_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3302 #define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3303 #define PRS_PRS_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3304 #define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3305 #define PXP2_PXP2_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3306 #define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3307 #define PXP2_PXP2_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3308 #define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3309 #define PXP2_PXP2_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3310 #define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3311 #define PXP2_PXP2_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3312 #define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3313 #define PXP_PXP_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3314 #define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3315 #define PXP_PXP_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3316 #define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3317 #define PXP_PXP_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3318 #define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3319 #define PXP_PXP_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3320 #define QM_QM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3321 #define QM_QM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3322 #define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3323 #define QM_QM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3324 #define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3325 #define QM_QM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3326 #define QM_QM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3327 #define QM_QM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3328 #define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3329 #define SEM_FAST_SEM_FAST_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3330 #define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3331 #define SEM_FAST_SEM_FAST_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3332 #define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3333 #define SEM_FAST_SEM_FAST_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3334 #define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3335 #define SEM_FAST_SEM_FAST_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3336 #define SRC_SRC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3337 #define SRC_SRC_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3338 #define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3339 #define SRC_SRC_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3340 #define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3341 #define SRC_SRC_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3342 #define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3343 #define SRC_SRC_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3344 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3345 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3346 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3347 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3348 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3349 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3350 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3351 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3352 #define TM_TM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3353 #define TM_TM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3354 #define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3355 #define TM_TM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3356 #define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3357 #define TM_TM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3358 #define TM_TM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3359 #define TM_TM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3360 #define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3361 #define TSDM_TSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3362 #define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3363 #define TSDM_TSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3364 #define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3365 #define TSDM_TSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3366 #define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3367 #define TSDM_TSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3368 #define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3369 #define TSEM_TSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3370 #define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3371 #define TSEM_TSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3372 #define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3373 #define TSEM_TSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3374 #define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3375 #define TSEM_TSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3376 #define UCM_UCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3377 #define UCM_UCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3378 #define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3379 #define UCM_UCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3380 #define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3381 #define UCM_UCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3382 #define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3383 #define UCM_UCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3384 #define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3385 #define USDM_USDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3386 #define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3387 #define USDM_USDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3388 #define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3389 #define USDM_USDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3390 #define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3391 #define USDM_USDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3392 #define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3393 #define USEM_USEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3394 #define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3395 #define USEM_USEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3396 #define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3397 #define USEM_USEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3398 #define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3399 #define USEM_USEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3400 #define XCM_XCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
3401 #define XCM_XCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
3402 #define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
3403 #define XCM_XCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
3404 #define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
3405 #define XCM_XCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
3406 #define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
3407 #define XCM_XCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
3408 #define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3409 #define XSDM_XSDM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3410 #define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3411 #define XSDM_XSDM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3412 #define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3413 #define XSDM_XSDM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3414 #define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3415 #define XSDM_XSDM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3416 #define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
3417 #define XSEM_XSEM_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
3418 #define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
3419 #define XSEM_XSEM_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
3420 #define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
3421 #define XSEM_XSEM_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
3422 #define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
3423 #define XSEM_XSEM_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
3424 #define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
3425 #define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
3426 /* [R 1] debug only: This bit indicates whether indicates that external
3427 buffer was wrapped (oldest data was thrown); Relevant only when
3428 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */
3429 #define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124
3430 #define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
3431 /* [R 1] debug only: This bit indicates whether the internal buffer was
3432 wrapped (oldest data was thrown) Relevant only when
3433 ~dbg_registers_debug_target=0 (internal buffer) */
3434 #define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
3435 #define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
3436 #define QM_QM_PRTY_STS_REG_WRBUFF (0x1<<8)
3437 #define QM_QM_PRTY_STS_REG_WRBUFF_SIZE 8
3438 #define QM_QM_PRTY_STS_CLR_REG_WRBUFF (0x1<<8)
3439 #define QM_QM_PRTY_STS_CLR_REG_WRBUFF_SIZE 8
3440 #define QM_QM_PRTY_STS_WR_REG_WRBUFF (0x1<<8)
3441 #define QM_QM_PRTY_STS_WR_REG_WRBUFF_SIZE 8
3442 #define QM_QM_PRTY_MASK_REG_WRBUFF (0x1<<8)
3443 #define QM_QM_PRTY_MASK_REG_WRBUFF_SIZE 8
3444 /* [RW 32] Wrr weights */
3445 #define QM_REG_WRRWEIGHTS_0 0x16880c
3446 #define QM_REG_WRRWEIGHTS_0_SIZE 1
3447 /* [RW 32] Wrr weights */
3448 #define QM_REG_WRRWEIGHTS_1 0x168810
3449 #define QM_REG_WRRWEIGHTS_1_SIZE 1
3450 /* [RW 32] Wrr weights */
3451 #define QM_REG_WRRWEIGHTS_10 0x168814
3452 #define QM_REG_WRRWEIGHTS_10_SIZE 1
3453 /* [RW 32] Wrr weights */
3454 #define QM_REG_WRRWEIGHTS_11 0x168818
3455 #define QM_REG_WRRWEIGHTS_11_SIZE 1
3456 /* [RW 32] Wrr weights */
3457 #define QM_REG_WRRWEIGHTS_12 0x16881c
3458 #define QM_REG_WRRWEIGHTS_12_SIZE 1
3459 /* [RW 32] Wrr weights */
3460 #define QM_REG_WRRWEIGHTS_13 0x168820
3461 #define QM_REG_WRRWEIGHTS_13_SIZE 1
3462 /* [RW 32] Wrr weights */
3463 #define QM_REG_WRRWEIGHTS_14 0x168824
3464 #define QM_REG_WRRWEIGHTS_14_SIZE 1
3465 /* [RW 32] Wrr weights */
3466 #define QM_REG_WRRWEIGHTS_15 0x168828
3467 #define QM_REG_WRRWEIGHTS_15_SIZE 1
3468 /* [RW 32] Wrr weights */
3469 #define QM_REG_WRRWEIGHTS_2 0x16882c
3470 #define QM_REG_WRRWEIGHTS_2_SIZE 1
3471 /* [RW 32] Wrr weights */
3472 #define QM_REG_WRRWEIGHTS_3 0x168830
3473 #define QM_REG_WRRWEIGHTS_3_SIZE 1
3474 /* [RW 32] Wrr weights */
3475 #define QM_REG_WRRWEIGHTS_4 0x168834
3476 #define QM_REG_WRRWEIGHTS_4_SIZE 1
3477 /* [RW 32] Wrr weights */
3478 #define QM_REG_WRRWEIGHTS_5 0x168838
3479 #define QM_REG_WRRWEIGHTS_5_SIZE 1
3480 /* [RW 32] Wrr weights */
3481 #define QM_REG_WRRWEIGHTS_6 0x16883c
3482 #define QM_REG_WRRWEIGHTS_6_SIZE 1
3483 /* [RW 32] Wrr weights */
3484 #define QM_REG_WRRWEIGHTS_7 0x168840
3485 #define QM_REG_WRRWEIGHTS_7_SIZE 1
3486 /* [RW 32] Wrr weights */
3487 #define QM_REG_WRRWEIGHTS_8 0x168844
3488 #define QM_REG_WRRWEIGHTS_8_SIZE 1
3489 /* [RW 32] Wrr weights */
3490 #define QM_REG_WRRWEIGHTS_9 0x168848
3491 #define QM_REG_WRRWEIGHTS_9_SIZE 1
3492 /* [RW 32] Wrr weights */
3493 #define QM_REG_WRRWEIGHTS_16 0x16e000
3494 #define QM_REG_WRRWEIGHTS_16_SIZE 1
3495 /* [RW 32] Wrr weights */
3496 #define QM_REG_WRRWEIGHTS_17 0x16e004
3497 #define QM_REG_WRRWEIGHTS_17_SIZE 1
3498 /* [RW 32] Wrr weights */
3499 #define QM_REG_WRRWEIGHTS_18 0x16e008
3500 #define QM_REG_WRRWEIGHTS_18_SIZE 1
3501 /* [RW 32] Wrr weights */
3502 #define QM_REG_WRRWEIGHTS_19 0x16e00c
3503 #define QM_REG_WRRWEIGHTS_19_SIZE 1
3504 /* [RW 32] Wrr weights */
3505 #define QM_REG_WRRWEIGHTS_20 0x16e010
3506 #define QM_REG_WRRWEIGHTS_20_SIZE 1
3507 /* [RW 32] Wrr weights */
3508 #define QM_REG_WRRWEIGHTS_21 0x16e014
3509 #define QM_REG_WRRWEIGHTS_21_SIZE 1
3510 /* [RW 32] Wrr weights */
3511 #define QM_REG_WRRWEIGHTS_22 0x16e018
3512 #define QM_REG_WRRWEIGHTS_22_SIZE 1
3513 /* [RW 32] Wrr weights */
3514 #define QM_REG_WRRWEIGHTS_23 0x16e01c
3515 #define QM_REG_WRRWEIGHTS_23_SIZE 1
3516 /* [RW 32] Wrr weights */
3517 #define QM_REG_WRRWEIGHTS_24 0x16e020
3518 #define QM_REG_WRRWEIGHTS_24_SIZE 1
3519 /* [RW 32] Wrr weights */
3520 #define QM_REG_WRRWEIGHTS_25 0x16e024
3521 #define QM_REG_WRRWEIGHTS_25_SIZE 1
3522 /* [RW 32] Wrr weights */
3523 #define QM_REG_WRRWEIGHTS_26 0x16e028
3524 #define QM_REG_WRRWEIGHTS_26_SIZE 1
3525 /* [RW 32] Wrr weights */
3526 #define QM_REG_WRRWEIGHTS_27 0x16e02c
3527 #define QM_REG_WRRWEIGHTS_27_SIZE 1
3528 /* [RW 32] Wrr weights */
3529 #define QM_REG_WRRWEIGHTS_28 0x16e030
3530 #define QM_REG_WRRWEIGHTS_28_SIZE 1
3531 /* [RW 32] Wrr weights */
3532 #define QM_REG_WRRWEIGHTS_29 0x16e034
3533 #define QM_REG_WRRWEIGHTS_29_SIZE 1
3534 /* [RW 32] Wrr weights */
3535 #define QM_REG_WRRWEIGHTS_30 0x16e038
3536 #define QM_REG_WRRWEIGHTS_30_SIZE 1
3537 /* [RW 32] Wrr weights */
3538 #define QM_REG_WRRWEIGHTS_31 0x16e03c
3539 #define QM_REG_WRRWEIGHTS_31_SIZE 1
3540 #define SRC_REG_COUNTFREE0 0x40500
3541 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3542 ports. If set the searcher support 8 functions. */
3543 #define SRC_REG_E1HMF_ENABLE 0x404cc
3544 #define SRC_REG_FIRSTFREE0 0x40510
3545 #define SRC_REG_KEYRSS0_0 0x40408
3546 #define SRC_REG_KEYRSS0_7 0x40424
3547 #define SRC_REG_KEYRSS1_9 0x40454
3548 #define SRC_REG_KEYSEARCH_0 0x40458
3549 #define SRC_REG_KEYSEARCH_1 0x4045c
3550 #define SRC_REG_KEYSEARCH_2 0x40460
3551 #define SRC_REG_KEYSEARCH_3 0x40464
3552 #define SRC_REG_KEYSEARCH_4 0x40468
3553 #define SRC_REG_KEYSEARCH_5 0x4046c
3554 #define SRC_REG_KEYSEARCH_6 0x40470
3555 #define SRC_REG_KEYSEARCH_7 0x40474
3556 #define SRC_REG_KEYSEARCH_8 0x40478
3557 #define SRC_REG_KEYSEARCH_9 0x4047c
3558 #define SRC_REG_LASTFREE0 0x40530
3559 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
3560 /* [RW 1] Reset internal state machines. */
3561 #define SRC_REG_SOFT_RST 0x4049c
3562 /* [R 3] Interrupt register #0 read */
3563 #define SRC_REG_SRC_INT_STS 0x404ac
3564 /* [RW 3] Parity mask register #0 read/write */
3565 #define SRC_REG_SRC_PRTY_MASK 0x404c8
3566 /* [R 3] Parity register #0 read */
3567 #define SRC_REG_SRC_PRTY_STS 0x404bc
3568 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
3569 #define TCM_REG_CAM_OCCUP 0x5017c
3570 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3571 disregarded; valid output is deasserted; all other signals are treated as
3572 usual; if 1 - normal activity. */
3573 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
3574 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3575 are disregarded; all other signals are treated as usual; if 1 - normal
3577 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
3578 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3579 disregarded; valid output is deasserted; all other signals are treated as
3580 usual; if 1 - normal activity. */
3581 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
3582 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3583 input is disregarded; all other signals are treated as usual; if 1 -
3585 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
3586 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3587 the initial credit value; read returns the current value of the credit
3588 counter. Must be initialized to 1 at start-up. */
3589 #define TCM_REG_CFC_INIT_CRD 0x50204
3590 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3591 weight 8 (the most prioritised); 1 stands for weight 1(least
3592 prioritised); 2 stands for weight 2; tc. */
3593 #define TCM_REG_CP_WEIGHT 0x500c0
3594 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3595 disregarded; acknowledge output is deasserted; all other signals are
3596 treated as usual; if 1 - normal activity. */
3597 #define TCM_REG_CSEM_IFEN 0x5002c
3598 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
3600 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
3601 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3602 weight 8 (the most prioritised); 1 stands for weight 1(least
3603 prioritised); 2 stands for weight 2; tc. */
3604 #define TCM_REG_CSEM_WEIGHT 0x500bc
3605 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
3606 #define TCM_REG_ERR_EVNT_ID 0x500a0
3607 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3608 #define TCM_REG_ERR_TCM_HDR 0x5009c
3609 /* [RW 8] The Event ID for Timers expiration. */
3610 #define TCM_REG_EXPR_EVNT_ID 0x500a4
3611 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3612 writes the initial credit value; read returns the current value of the
3613 credit counter. Must be initialized to 64 at start-up. */
3614 #define TCM_REG_FIC0_INIT_CRD 0x5020c
3615 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3616 writes the initial credit value; read returns the current value of the
3617 credit counter. Must be initialized to 64 at start-up. */
3618 #define TCM_REG_FIC1_INIT_CRD 0x50210
3619 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
3620 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
3621 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
3622 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
3623 #define TCM_REG_GR_ARB_TYPE 0x50114
3624 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3625 highest priority is 3. It is supposed that the Store channel is the
3626 compliment of the other 3 groups. */
3627 #define TCM_REG_GR_LD0_PR 0x5011c
3628 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3629 highest priority is 3. It is supposed that the Store channel is the
3630 compliment of the other 3 groups. */
3631 #define TCM_REG_GR_LD1_PR 0x50120
3632 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
3633 sent to STORM; for a specific connection type. The double REG-pairs are
3634 used to align to STORM context row size of 128 bits. The offset of these
3635 data in the STORM context is always 0. Index _i stands for the connection
3636 type (one of 16). */
3637 #define TCM_REG_N_SM_CTX_LD_0 0x50050
3638 #define TCM_REG_N_SM_CTX_LD_1 0x50054
3639 #define TCM_REG_N_SM_CTX_LD_10 0x50078
3640 #define TCM_REG_N_SM_CTX_LD_11 0x5007c
3641 #define TCM_REG_N_SM_CTX_LD_12 0x50080
3642 #define TCM_REG_N_SM_CTX_LD_13 0x50084
3643 #define TCM_REG_N_SM_CTX_LD_14 0x50088
3644 #define TCM_REG_N_SM_CTX_LD_15 0x5008c
3645 #define TCM_REG_N_SM_CTX_LD_2 0x50058
3646 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
3647 #define TCM_REG_N_SM_CTX_LD_4 0x50060
3648 #define TCM_REG_N_SM_CTX_LD_5 0x50064
3649 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3650 acknowledge output is deasserted; all other signals are treated as usual;
3651 if 1 - normal activity. */
3652 #define TCM_REG_PBF_IFEN 0x50024
3653 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
3655 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
3656 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3657 weight 8 (the most prioritised); 1 stands for weight 1(least
3658 prioritised); 2 stands for weight 2; tc. */
3659 #define TCM_REG_PBF_WEIGHT 0x500b4
3660 #define TCM_REG_PHYS_QNUM0_0 0x500e0
3661 #define TCM_REG_PHYS_QNUM0_1 0x500e4
3662 #define TCM_REG_PHYS_QNUM1_0 0x500e8
3663 #define TCM_REG_PHYS_QNUM1_1 0x500ec
3664 #define TCM_REG_PHYS_QNUM2_0 0x500f0
3665 #define TCM_REG_PHYS_QNUM2_1 0x500f4
3666 #define TCM_REG_PHYS_QNUM3_0 0x500f8
3667 #define TCM_REG_PHYS_QNUM3_1 0x500fc
3668 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
3669 acknowledge output is deasserted; all other signals are treated as usual;
3670 if 1 - normal activity. */
3671 #define TCM_REG_PRS_IFEN 0x50020
3672 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
3674 #define TCM_REG_PRS_LENGTH_MIS 0x50168
3675 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
3676 weight 8 (the most prioritised); 1 stands for weight 1(least
3677 prioritised); 2 stands for weight 2; tc. */
3678 #define TCM_REG_PRS_WEIGHT 0x500b0
3679 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3680 #define TCM_REG_STOP_EVNT_ID 0x500a8
3681 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
3683 #define TCM_REG_STORM_LENGTH_MIS 0x50160
3684 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3685 disregarded; acknowledge output is deasserted; all other signals are
3686 treated as usual; if 1 - normal activity. */
3687 #define TCM_REG_STORM_TCM_IFEN 0x50010
3688 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3689 weight 8 (the most prioritised); 1 stands for weight 1(least
3690 prioritised); 2 stands for weight 2; tc. */
3691 #define TCM_REG_STORM_WEIGHT 0x500ac
3692 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3693 acknowledge output is deasserted; all other signals are treated as usual;
3694 if 1 - normal activity. */
3695 #define TCM_REG_TCM_CFC_IFEN 0x50040
3696 /* [RW 11] Interrupt mask register #0 read/write */
3697 #define TCM_REG_TCM_INT_MASK 0x501dc
3698 /* [R 11] Interrupt register #0 read */
3699 #define TCM_REG_TCM_INT_STS 0x501d0
3700 /* [R 27] Parity register #0 read */
3701 #define TCM_REG_TCM_PRTY_STS 0x501e0
3702 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
3703 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3704 Is used to determine the number of the AG context REG-pairs written back;
3705 when the input message Reg1WbFlg isn't set. */
3706 #define TCM_REG_TCM_REG0_SZ 0x500d8
3707 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3708 disregarded; valid is deasserted; all other signals are treated as usual;
3709 if 1 - normal activity. */
3710 #define TCM_REG_TCM_STORM0_IFEN 0x50004
3711 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3712 disregarded; valid is deasserted; all other signals are treated as usual;
3713 if 1 - normal activity. */
3714 #define TCM_REG_TCM_STORM1_IFEN 0x50008
3715 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3716 disregarded; valid is deasserted; all other signals are treated as usual;
3717 if 1 - normal activity. */
3718 #define TCM_REG_TCM_TQM_IFEN 0x5000c
3719 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3720 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
3721 /* [RW 28] The CM header for Timers expiration command. */
3722 #define TCM_REG_TM_TCM_HDR 0x50098
3723 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3724 disregarded; acknowledge output is deasserted; all other signals are
3725 treated as usual; if 1 - normal activity. */
3726 #define TCM_REG_TM_TCM_IFEN 0x5001c
3727 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
3728 weight 8 (the most prioritised); 1 stands for weight 1(least
3729 prioritised); 2 stands for weight 2; tc. */
3730 #define TCM_REG_TM_WEIGHT 0x500d0
3731 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3732 the initial credit value; read returns the current value of the credit
3733 counter. Must be initialized to 32 at start-up. */
3734 #define TCM_REG_TQM_INIT_CRD 0x5021c
3735 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3736 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3737 prioritised); 2 stands for weight 2; tc. */
3738 #define TCM_REG_TQM_P_WEIGHT 0x500c8
3739 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
3740 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3741 prioritised); 2 stands for weight 2; tc. */
3742 #define TCM_REG_TQM_S_WEIGHT 0x500cc
3743 /* [RW 28] The CM header value for QM request (primary). */
3744 #define TCM_REG_TQM_TCM_HDR_P 0x50090
3745 /* [RW 28] The CM header value for QM request (secondary). */
3746 #define TCM_REG_TQM_TCM_HDR_S 0x50094
3747 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3748 acknowledge output is deasserted; all other signals are treated as usual;
3749 if 1 - normal activity. */
3750 #define TCM_REG_TQM_TCM_IFEN 0x50014
3751 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3752 acknowledge output is deasserted; all other signals are treated as usual;
3753 if 1 - normal activity. */
3754 #define TCM_REG_TSDM_IFEN 0x50018
3755 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
3757 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
3758 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3759 weight 8 (the most prioritised); 1 stands for weight 1(least
3760 prioritised); 2 stands for weight 2; tc. */
3761 #define TCM_REG_TSDM_WEIGHT 0x500c4
3762 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
3763 disregarded; acknowledge output is deasserted; all other signals are
3764 treated as usual; if 1 - normal activity. */
3765 #define TCM_REG_USEM_IFEN 0x50028
3766 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
3768 #define TCM_REG_USEM_LENGTH_MIS 0x50170
3769 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
3770 weight 8 (the most prioritised); 1 stands for weight 1(least
3771 prioritised); 2 stands for weight 2; tc. */
3772 #define TCM_REG_USEM_WEIGHT 0x500b8
3773 /* [RW 21] Indirect access to the descriptor table of the XX protection
3774 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
3775 pointer; 20:16] - next pointer. */
3776 #define TCM_REG_XX_DESCR_TABLE 0x50280
3777 #define TCM_REG_XX_DESCR_TABLE_SIZE 32
3778 /* [R 6] Use to read the value of XX protection Free counter. */
3779 #define TCM_REG_XX_FREE 0x50178
3780 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3781 of the Input Stage XX protection buffer by the XX protection pending
3782 messages. Max credit available - 127.Write writes the initial credit
3783 value; read returns the current value of the credit counter. Must be
3784 initialized to 19 at start-up. */
3785 #define TCM_REG_XX_INIT_CRD 0x50220
3786 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
3788 #define TCM_REG_XX_MAX_LL_SZ 0x50044
3789 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3790 protection. ~tcm_registers_xx_free.xx_free is read on read. */
3791 #define TCM_REG_XX_MSG_NUM 0x50224
3792 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3793 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
3794 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3795 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
3797 #define TCM_REG_XX_TABLE 0x50240
3798 /* [RW 4] Load value for for cfc ac credit cnt. */
3799 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
3800 /* [RW 4] Load value for cfc cld credit cnt. */
3801 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
3802 /* [RW 8] Client0 context region. */
3803 #define TM_REG_CL0_CONT_REGION 0x164030
3804 /* [RW 8] Client1 context region. */
3805 #define TM_REG_CL1_CONT_REGION 0x164034
3806 /* [RW 8] Client2 context region. */
3807 #define TM_REG_CL2_CONT_REGION 0x164038
3808 /* [RW 2] Client in High priority client number. */
3809 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
3810 /* [RW 4] Load value for clout0 cred cnt. */
3811 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
3812 /* [RW 4] Load value for clout1 cred cnt. */
3813 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
3814 /* [RW 4] Load value for clout2 cred cnt. */
3815 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
3816 /* [RW 1] Enable client0 input. */
3817 #define TM_REG_EN_CL0_INPUT 0x164008
3818 /* [RW 1] Enable client1 input. */
3819 #define TM_REG_EN_CL1_INPUT 0x16400c
3820 /* [RW 1] Enable client2 input. */
3821 #define TM_REG_EN_CL2_INPUT 0x164010
3822 #define TM_REG_EN_LINEAR0_TIMER 0x164014
3823 /* [RW 1] Enable real time counter. */
3824 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
3825 /* [RW 1] Enable for Timers state machines. */
3826 #define TM_REG_EN_TIMERS 0x164000
3827 /* [RW 4] Load value for expiration credit cnt. CFC max number of
3828 outstanding load requests for timers (expiration) context loading. */
3829 #define TM_REG_EXP_CRDCNT_VAL 0x164238
3830 /* [RW 32] Linear0 logic address. */
3831 #define TM_REG_LIN0_LOGIC_ADDR 0x164240
3832 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
3833 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
3834 /* [WB 64] Linear0 phy address. */
3835 #define TM_REG_LIN0_PHY_ADDR 0x164270
3836 /* [RW 1] Linear0 physical address valid. */
3837 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
3838 /* [RW 24] Linear0 array scan timeout. */
3839 #define TM_REG_LIN0_SCAN_TIME 0x16403c
3840 /* [RW 32] Linear1 logic address. */
3841 #define TM_REG_LIN1_LOGIC_ADDR 0x164250
3842 /* [WB 64] Linear1 phy address. */
3843 #define TM_REG_LIN1_PHY_ADDR 0x164280
3844 /* [RW 1] Linear1 physical address valid. */
3845 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
3846 /* [RW 6] Linear timer set_clear fifo threshold. */
3847 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
3848 /* [RW 2] Load value for pci arbiter credit cnt. */
3849 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
3850 /* [RW 1] Timer software reset - active high. */
3851 #define TM_REG_TIMER_SOFT_RST 0x164004
3852 /* [RW 20] The amount of hardware cycles for each timer tick. */
3853 #define TM_REG_TIMER_TICK_SIZE 0x16401c
3854 /* [RW 8] Timers Context region. */
3855 #define TM_REG_TM_CONTEXT_REGION 0x164044
3856 /* [RW 1] Interrupt mask register #0 read/write */
3857 #define TM_REG_TM_INT_MASK 0x1640fc
3858 /* [R 1] Interrupt register #0 read */
3859 #define TM_REG_TM_INT_STS 0x1640f0
3860 /* [RW 8] The event id for aggregated interrupt 0 */
3861 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
3862 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c
3863 #define TSDM_REG_AGG_INT_EVENT_10 0x42060
3864 #define TSDM_REG_AGG_INT_EVENT_11 0x42064
3865 #define TSDM_REG_AGG_INT_EVENT_12 0x42068
3866 #define TSDM_REG_AGG_INT_EVENT_13 0x4206c
3867 #define TSDM_REG_AGG_INT_EVENT_14 0x42070
3868 #define TSDM_REG_AGG_INT_EVENT_15 0x42074
3869 #define TSDM_REG_AGG_INT_EVENT_16 0x42078
3870 #define TSDM_REG_AGG_INT_EVENT_17 0x4207c
3871 #define TSDM_REG_AGG_INT_EVENT_18 0x42080
3872 #define TSDM_REG_AGG_INT_EVENT_19 0x42084
3873 #define TSDM_REG_AGG_INT_EVENT_2 0x42040
3874 #define TSDM_REG_AGG_INT_EVENT_20 0x42088
3875 #define TSDM_REG_AGG_INT_EVENT_21 0x4208c
3876 #define TSDM_REG_AGG_INT_EVENT_22 0x42090
3877 #define TSDM_REG_AGG_INT_EVENT_23 0x42094
3878 #define TSDM_REG_AGG_INT_EVENT_24 0x42098
3879 #define TSDM_REG_AGG_INT_EVENT_25 0x4209c
3880 #define TSDM_REG_AGG_INT_EVENT_26 0x420a0
3881 #define TSDM_REG_AGG_INT_EVENT_27 0x420a4
3882 #define TSDM_REG_AGG_INT_EVENT_28 0x420a8
3883 #define TSDM_REG_AGG_INT_EVENT_29 0x420ac
3884 #define TSDM_REG_AGG_INT_EVENT_3 0x42044
3885 #define TSDM_REG_AGG_INT_EVENT_30 0x420b0
3886 #define TSDM_REG_AGG_INT_EVENT_31 0x420b4
3887 #define TSDM_REG_AGG_INT_EVENT_4 0x42048
3888 /* [RW 1] The T bit for aggregated interrupt 0 */
3889 #define TSDM_REG_AGG_INT_T_0 0x420b8
3890 #define TSDM_REG_AGG_INT_T_1 0x420bc
3891 #define TSDM_REG_AGG_INT_T_10 0x420e0
3892 #define TSDM_REG_AGG_INT_T_11 0x420e4
3893 #define TSDM_REG_AGG_INT_T_12 0x420e8
3894 #define TSDM_REG_AGG_INT_T_13 0x420ec
3895 #define TSDM_REG_AGG_INT_T_14 0x420f0
3896 #define TSDM_REG_AGG_INT_T_15 0x420f4
3897 #define TSDM_REG_AGG_INT_T_16 0x420f8
3898 #define TSDM_REG_AGG_INT_T_17 0x420fc
3899 #define TSDM_REG_AGG_INT_T_18 0x42100
3900 #define TSDM_REG_AGG_INT_T_19 0x42104
3901 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3902 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
3903 /* [RW 16] The maximum value of the competion counter #0 */
3904 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
3905 /* [RW 16] The maximum value of the competion counter #1 */
3906 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
3907 /* [RW 16] The maximum value of the competion counter #2 */
3908 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
3909 /* [RW 16] The maximum value of the competion counter #3 */
3910 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
3911 /* [RW 13] The start address in the internal RAM for the completion
3913 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
3914 #define TSDM_REG_ENABLE_IN1 0x42238
3915 #define TSDM_REG_ENABLE_IN2 0x4223c
3916 #define TSDM_REG_ENABLE_OUT1 0x42240
3917 #define TSDM_REG_ENABLE_OUT2 0x42244
3918 /* [RW 4] The initial number of messages that can be sent to the pxp control
3919 interface without receiving any ACK. */
3920 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
3921 /* [ST 32] The number of ACK after placement messages received */
3922 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
3923 /* [ST 32] The number of packet end messages received from the parser */
3924 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
3925 /* [ST 32] The number of requests received from the pxp async if */
3926 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
3927 /* [ST 32] The number of commands received in queue 0 */
3928 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
3929 /* [ST 32] The number of commands received in queue 10 */
3930 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
3931 /* [ST 32] The number of commands received in queue 11 */
3932 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
3933 /* [ST 32] The number of commands received in queue 1 */
3934 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
3935 /* [ST 32] The number of commands received in queue 3 */
3936 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
3937 /* [ST 32] The number of commands received in queue 4 */
3938 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
3939 /* [ST 32] The number of commands received in queue 5 */
3940 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
3941 /* [ST 32] The number of commands received in queue 6 */
3942 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
3943 /* [ST 32] The number of commands received in queue 7 */
3944 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
3945 /* [ST 32] The number of commands received in queue 8 */
3946 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
3947 /* [ST 32] The number of commands received in queue 9 */
3948 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
3949 /* [RW 13] The start address in the internal RAM for the packet end message */
3950 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
3951 /* [RW 13] The start address in the internal RAM for queue counters */
3952 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
3953 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3954 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
3955 /* [R 1] parser fifo empty in sdm_sync block */
3956 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
3957 /* [R 1] parser serial fifo empty in sdm_sync block */
3958 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
3959 /* [RW 32] Tick for timer counter. Applicable only when
3960 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
3961 #define TSDM_REG_TIMER_TICK 0x42000
3962 /* [RW 32] Interrupt mask register #0 read/write */
3963 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
3964 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
3965 /* [R 32] Interrupt register #0 read */
3966 #define TSDM_REG_TSDM_INT_STS_0 0x42290
3967 #define TSDM_REG_TSDM_INT_STS_1 0x422a0
3968 /* [RW 11] Parity mask register #0 read/write */
3969 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
3970 /* [R 11] Parity register #0 read */
3971 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
3972 /* [RW 5] The number of time_slots in the arbitration cycle */
3973 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
3974 /* [RW 3] The source that is associated with arbitration element 0. Source
3975 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3976 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3977 #define TSEM_REG_ARB_ELEMENT0 0x180020
3978 /* [RW 3] The source that is associated with arbitration element 1. Source
3979 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3980 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3981 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
3982 #define TSEM_REG_ARB_ELEMENT1 0x180024
3983 /* [RW 3] The source that is associated with arbitration element 2. Source
3984 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3985 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3986 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
3987 and ~tsem_registers_arb_element1.arb_element1 */
3988 #define TSEM_REG_ARB_ELEMENT2 0x180028
3989 /* [RW 3] The source that is associated with arbitration element 3. Source
3990 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3991 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3992 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
3993 ~tsem_registers_arb_element1.arb_element1 and
3994 ~tsem_registers_arb_element2.arb_element2 */
3995 #define TSEM_REG_ARB_ELEMENT3 0x18002c
3996 /* [RW 3] The source that is associated with arbitration element 4. Source
3997 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3998 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3999 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4000 and ~tsem_registers_arb_element1.arb_element1 and
4001 ~tsem_registers_arb_element2.arb_element2 and
4002 ~tsem_registers_arb_element3.arb_element3 */
4003 #define TSEM_REG_ARB_ELEMENT4 0x180030
4004 #define TSEM_REG_ENABLE_IN 0x1800a4
4005 #define TSEM_REG_ENABLE_OUT 0x1800a8
4006 /* [RW 32] This address space contains all registers and memories that are
4007 placed in SEM_FAST block. The SEM_FAST registers are described in
4008 appendix B. In order to access the sem_fast registers the base address
4009 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4010 #define TSEM_REG_FAST_MEMORY 0x1a0000
4011 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4013 #define TSEM_REG_FIC0_DISABLE 0x180224
4014 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4016 #define TSEM_REG_FIC1_DISABLE 0x180234
4017 /* [RW 15] Interrupt table Read and write access to it is not possible in
4018 the middle of the work */
4019 #define TSEM_REG_INT_TABLE 0x180400
4020 /* [ST 24] Statistics register. The number of messages that entered through
4022 #define TSEM_REG_MSG_NUM_FIC0 0x180000
4023 /* [ST 24] Statistics register. The number of messages that entered through
4025 #define TSEM_REG_MSG_NUM_FIC1 0x180004
4026 /* [ST 24] Statistics register. The number of messages that were sent to
4028 #define TSEM_REG_MSG_NUM_FOC0 0x180008
4029 /* [ST 24] Statistics register. The number of messages that were sent to
4031 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
4032 /* [ST 24] Statistics register. The number of messages that were sent to
4034 #define TSEM_REG_MSG_NUM_FOC2 0x180010
4035 /* [ST 24] Statistics register. The number of messages that were sent to
4037 #define TSEM_REG_MSG_NUM_FOC3 0x180014
4038 /* [RW 1] Disables input messages from the passive buffer May be updated
4039 during run_time by the microcode */
4040 #define TSEM_REG_PAS_DISABLE 0x18024c
4041 /* [WB 128] Debug only. Passive buffer memory */
4042 #define TSEM_REG_PASSIVE_BUFFER 0x181000
4043 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4044 #define TSEM_REG_PRAM 0x1c0000
4045 /* [R 8] Valid sleeping threads indication have bit per thread */
4046 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
4047 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4048 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
4049 /* [RW 8] List of free threads . There is a bit per thread. */
4050 #define TSEM_REG_THREADS_LIST 0x1802e4
4051 /* [RW 3] The arbitration scheme of time_slot 0 */
4052 #define TSEM_REG_TS_0_AS 0x180038
4053 /* [RW 3] The arbitration scheme of time_slot 10 */
4054 #define TSEM_REG_TS_10_AS 0x180060
4055 /* [RW 3] The arbitration scheme of time_slot 11 */
4056 #define TSEM_REG_TS_11_AS 0x180064
4057 /* [RW 3] The arbitration scheme of time_slot 12 */
4058 #define TSEM_REG_TS_12_AS 0x180068
4059 /* [RW 3] The arbitration scheme of time_slot 13 */
4060 #define TSEM_REG_TS_13_AS 0x18006c
4061 /* [RW 3] The arbitration scheme of time_slot 14 */
4062 #define TSEM_REG_TS_14_AS 0x180070
4063 /* [RW 3] The arbitration scheme of time_slot 15 */
4064 #define TSEM_REG_TS_15_AS 0x180074
4065 /* [RW 3] The arbitration scheme of time_slot 16 */
4066 #define TSEM_REG_TS_16_AS 0x180078
4067 /* [RW 3] The arbitration scheme of time_slot 17 */
4068 #define TSEM_REG_TS_17_AS 0x18007c
4069 /* [RW 3] The arbitration scheme of time_slot 18 */
4070 #define TSEM_REG_TS_18_AS 0x180080
4071 /* [RW 3] The arbitration scheme of time_slot 1 */
4072 #define TSEM_REG_TS_1_AS 0x18003c
4073 /* [RW 3] The arbitration scheme of time_slot 2 */
4074 #define TSEM_REG_TS_2_AS 0x180040
4075 /* [RW 3] The arbitration scheme of time_slot 3 */
4076 #define TSEM_REG_TS_3_AS 0x180044
4077 /* [RW 3] The arbitration scheme of time_slot 4 */
4078 #define TSEM_REG_TS_4_AS 0x180048
4079 /* [RW 3] The arbitration scheme of time_slot 5 */
4080 #define TSEM_REG_TS_5_AS 0x18004c
4081 /* [RW 3] The arbitration scheme of time_slot 6 */
4082 #define TSEM_REG_TS_6_AS 0x180050
4083 /* [RW 3] The arbitration scheme of time_slot 7 */
4084 #define TSEM_REG_TS_7_AS 0x180054
4085 /* [RW 3] The arbitration scheme of time_slot 8 */
4086 #define TSEM_REG_TS_8_AS 0x180058
4087 /* [RW 3] The arbitration scheme of time_slot 9 */
4088 #define TSEM_REG_TS_9_AS 0x18005c
4089 /* [RW 32] Interrupt mask register #0 read/write */
4090 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
4091 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
4092 /* [R 32] Interrupt register #0 read */
4093 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4094 #define TSEM_REG_TSEM_INT_STS_1 0x180104
4095 /* [RW 32] Parity mask register #0 read/write */
4096 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
4097 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
4098 /* [R 32] Parity register #0 read */
4099 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114
4100 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124
4101 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4102 #define UCM_REG_CAM_OCCUP 0xe0170
4103 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4104 disregarded; valid output is deasserted; all other signals are treated as
4105 usual; if 1 - normal activity. */
4106 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
4107 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4108 are disregarded; all other signals are treated as usual; if 1 - normal
4110 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
4111 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4112 disregarded; valid output is deasserted; all other signals are treated as
4113 usual; if 1 - normal activity. */
4114 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
4115 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4116 input is disregarded; all other signals are treated as usual; if 1 -
4118 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
4119 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4120 the initial credit value; read returns the current value of the credit
4121 counter. Must be initialized to 1 at start-up. */
4122 #define UCM_REG_CFC_INIT_CRD 0xe0204
4123 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4124 weight 8 (the most prioritised); 1 stands for weight 1(least
4125 prioritised); 2 stands for weight 2; tc. */
4126 #define UCM_REG_CP_WEIGHT 0xe00c4
4127 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4128 disregarded; acknowledge output is deasserted; all other signals are
4129 treated as usual; if 1 - normal activity. */
4130 #define UCM_REG_CSEM_IFEN 0xe0028
4131 /* [RC 1] Set when the message length mismatch (relative to last indication)
4132 at the csem interface is detected. */
4133 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4134 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4135 weight 8 (the most prioritised); 1 stands for weight 1(least
4136 prioritised); 2 stands for weight 2; tc. */
4137 #define UCM_REG_CSEM_WEIGHT 0xe00b8
4138 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4139 disregarded; acknowledge output is deasserted; all other signals are
4140 treated as usual; if 1 - normal activity. */
4141 #define UCM_REG_DORQ_IFEN 0xe0030
4142 /* [RC 1] Set when the message length mismatch (relative to last indication)
4143 at the dorq interface is detected. */
4144 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
4145 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4146 weight 8 (the most prioritised); 1 stands for weight 1(least
4147 prioritised); 2 stands for weight 2; tc. */
4148 #define UCM_REG_DORQ_WEIGHT 0xe00c0
4149 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4150 #define UCM_REG_ERR_EVNT_ID 0xe00a4
4151 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4152 #define UCM_REG_ERR_UCM_HDR 0xe00a0
4153 /* [RW 8] The Event ID for Timers expiration. */
4154 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
4155 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4156 writes the initial credit value; read returns the current value of the
4157 credit counter. Must be initialized to 64 at start-up. */
4158 #define UCM_REG_FIC0_INIT_CRD 0xe020c
4159 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4160 writes the initial credit value; read returns the current value of the
4161 credit counter. Must be initialized to 64 at start-up. */
4162 #define UCM_REG_FIC1_INIT_CRD 0xe0210
4163 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4164 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
4165 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
4166 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
4167 #define UCM_REG_GR_ARB_TYPE 0xe0144
4168 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4169 highest priority is 3. It is supposed that the Store channel group is
4170 compliment to the others. */
4171 #define UCM_REG_GR_LD0_PR 0xe014c
4172 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4173 highest priority is 3. It is supposed that the Store channel group is
4174 compliment to the others. */
4175 #define UCM_REG_GR_LD1_PR 0xe0150
4176 /* [RW 2] The queue index for invalidate counter flag decision. */
4177 #define UCM_REG_INV_CFLG_Q 0xe00e4
4178 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4179 sent to STORM; for a specific connection type. the double REG-pairs are
4180 used in order to align to STORM context row size of 128 bits. The offset
4181 of these data in the STORM context is always 0. Index _i stands for the
4182 connection type (one of 16). */
4183 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
4184 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
4185 #define UCM_REG_N_SM_CTX_LD_10 0xe007c
4186 #define UCM_REG_N_SM_CTX_LD_11 0xe0080
4187 #define UCM_REG_N_SM_CTX_LD_12 0xe0084
4188 #define UCM_REG_N_SM_CTX_LD_13 0xe0088
4189 #define UCM_REG_N_SM_CTX_LD_14 0xe008c
4190 #define UCM_REG_N_SM_CTX_LD_15 0xe0090
4191 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
4192 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
4193 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
4194 #define UCM_REG_N_SM_CTX_LD_5 0xe0068
4195 #define UCM_REG_PHYS_QNUM0_0 0xe0110
4196 #define UCM_REG_PHYS_QNUM0_1 0xe0114
4197 #define UCM_REG_PHYS_QNUM1_0 0xe0118
4198 #define UCM_REG_PHYS_QNUM1_1 0xe011c
4199 #define UCM_REG_PHYS_QNUM2_0 0xe0120
4200 #define UCM_REG_PHYS_QNUM2_1 0xe0124
4201 #define UCM_REG_PHYS_QNUM3_0 0xe0128
4202 #define UCM_REG_PHYS_QNUM3_1 0xe012c
4203 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4204 #define UCM_REG_STOP_EVNT_ID 0xe00ac
4205 /* [RC 1] Set when the message length mismatch (relative to last indication)
4206 at the STORM interface is detected. */
4207 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
4208 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4209 disregarded; acknowledge output is deasserted; all other signals are
4210 treated as usual; if 1 - normal activity. */
4211 #define UCM_REG_STORM_UCM_IFEN 0xe0010
4212 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4213 weight 8 (the most prioritised); 1 stands for weight 1(least
4214 prioritised); 2 stands for weight 2; tc. */
4215 #define UCM_REG_STORM_WEIGHT 0xe00b0
4216 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4217 writes the initial credit value; read returns the current value of the
4218 credit counter. Must be initialized to 4 at start-up. */
4219 #define UCM_REG_TM_INIT_CRD 0xe021c
4220 /* [RW 28] The CM header for Timers expiration command. */
4221 #define UCM_REG_TM_UCM_HDR 0xe009c
4222 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4223 disregarded; acknowledge output is deasserted; all other signals are
4224 treated as usual; if 1 - normal activity. */
4225 #define UCM_REG_TM_UCM_IFEN 0xe001c
4226 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4227 weight 8 (the most prioritised); 1 stands for weight 1(least
4228 prioritised); 2 stands for weight 2; tc. */
4229 #define UCM_REG_TM_WEIGHT 0xe00d4
4230 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4231 disregarded; acknowledge output is deasserted; all other signals are
4232 treated as usual; if 1 - normal activity. */
4233 #define UCM_REG_TSEM_IFEN 0xe0024
4234 /* [RC 1] Set when the message length mismatch (relative to last indication)
4235 at the tsem interface is detected. */
4236 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
4237 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4238 weight 8 (the most prioritised); 1 stands for weight 1(least
4239 prioritised); 2 stands for weight 2; tc. */
4240 #define UCM_REG_TSEM_WEIGHT 0xe00b4
4241 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4242 acknowledge output is deasserted; all other signals are treated as usual;
4243 if 1 - normal activity. */
4244 #define UCM_REG_UCM_CFC_IFEN 0xe0044
4245 /* [RW 11] Interrupt mask register #0 read/write */
4246 #define UCM_REG_UCM_INT_MASK 0xe01d4
4247 /* [R 11] Interrupt register #0 read */
4248 #define UCM_REG_UCM_INT_STS 0xe01c8
4249 /* [R 27] Parity register #0 read */
4250 #define UCM_REG_UCM_PRTY_STS 0xe01d8
4251 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4252 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4253 Is used to determine the number of the AG context REG-pairs written back;
4254 when the Reg1WbFlg isn't set. */
4255 #define UCM_REG_UCM_REG0_SZ 0xe00dc
4256 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4257 disregarded; valid is deasserted; all other signals are treated as usual;
4258 if 1 - normal activity. */
4259 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
4260 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4261 disregarded; valid is deasserted; all other signals are treated as usual;
4262 if 1 - normal activity. */
4263 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
4264 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4265 disregarded; acknowledge output is deasserted; all other signals are
4266 treated as usual; if 1 - normal activity. */
4267 #define UCM_REG_UCM_TM_IFEN 0xe0020
4268 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4269 disregarded; valid is deasserted; all other signals are treated as usual;
4270 if 1 - normal activity. */
4271 #define UCM_REG_UCM_UQM_IFEN 0xe000c
4272 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4273 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
4274 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4275 the initial credit value; read returns the current value of the credit
4276 counter. Must be initialized to 32 at start-up. */
4277 #define UCM_REG_UQM_INIT_CRD 0xe0220
4278 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4279 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4280 prioritised); 2 stands for weight 2; tc. */
4281 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
4282 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4283 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4284 prioritised); 2 stands for weight 2; tc. */
4285 #define UCM_REG_UQM_S_WEIGHT 0xe00d0
4286 /* [RW 28] The CM header value for QM request (primary). */
4287 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
4288 /* [RW 28] The CM header value for QM request (secondary). */
4289 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
4290 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4291 acknowledge output is deasserted; all other signals are treated as usual;
4292 if 1 - normal activity. */
4293 #define UCM_REG_UQM_UCM_IFEN 0xe0014
4294 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4295 acknowledge output is deasserted; all other signals are treated as usual;
4296 if 1 - normal activity. */
4297 #define UCM_REG_USDM_IFEN 0xe0018
4298 /* [RC 1] Set when the message length mismatch (relative to last indication)
4299 at the SDM interface is detected. */
4300 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
4301 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4302 weight 8 (the most prioritised); 1 stands for weight 1(least
4303 prioritised); 2 stands for weight 2; tc. */
4304 #define UCM_REG_USDM_WEIGHT 0xe00c8
4305 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4306 disregarded; acknowledge output is deasserted; all other signals are
4307 treated as usual; if 1 - normal activity. */
4308 #define UCM_REG_XSEM_IFEN 0xe002c
4309 /* [RC 1] Set when the message length mismatch (relative to last indication)
4310 at the xsem interface isdetected. */
4311 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
4312 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
4313 weight 8 (the most prioritised); 1 stands for weight 1(least
4314 prioritised); 2 stands for weight 2; tc. */
4315 #define UCM_REG_XSEM_WEIGHT 0xe00bc
4316 /* [RW 20] Indirect access to the descriptor table of the XX protection
4317 mechanism. The fields are:[5:0] - message length; 14:6] - message
4318 pointer; 19:15] - next pointer. */
4319 #define UCM_REG_XX_DESCR_TABLE 0xe0280
4320 #define UCM_REG_XX_DESCR_TABLE_SIZE 32
4321 /* [R 6] Use to read the XX protection Free counter. */
4322 #define UCM_REG_XX_FREE 0xe016c
4323 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4324 of the Input Stage XX protection buffer by the XX protection pending
4325 messages. Write writes the initial credit value; read returns the current
4326 value of the credit counter. Must be initialized to 12 at start-up. */
4327 #define UCM_REG_XX_INIT_CRD 0xe0224
4328 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4329 protection. ~ucm_registers_xx_free.xx_free read on read. */
4330 #define UCM_REG_XX_MSG_NUM 0xe0228
4331 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4332 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
4333 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4334 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4336 #define UCM_REG_XX_TABLE 0xe0300
4337 /* [RW 8] The event id for aggregated interrupt 0 */
4338 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
4339 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
4340 #define USDM_REG_AGG_INT_EVENT_10 0xc4060
4341 #define USDM_REG_AGG_INT_EVENT_11 0xc4064
4342 #define USDM_REG_AGG_INT_EVENT_12 0xc4068
4343 #define USDM_REG_AGG_INT_EVENT_13 0xc406c
4344 #define USDM_REG_AGG_INT_EVENT_14 0xc4070
4345 #define USDM_REG_AGG_INT_EVENT_15 0xc4074
4346 #define USDM_REG_AGG_INT_EVENT_16 0xc4078
4347 #define USDM_REG_AGG_INT_EVENT_17 0xc407c
4348 #define USDM_REG_AGG_INT_EVENT_18 0xc4080
4349 #define USDM_REG_AGG_INT_EVENT_19 0xc4084
4350 #define USDM_REG_AGG_INT_EVENT_2 0xc4040
4351 #define USDM_REG_AGG_INT_EVENT_20 0xc4088
4352 #define USDM_REG_AGG_INT_EVENT_21 0xc408c
4353 #define USDM_REG_AGG_INT_EVENT_22 0xc4090
4354 #define USDM_REG_AGG_INT_EVENT_23 0xc4094
4355 #define USDM_REG_AGG_INT_EVENT_24 0xc4098
4356 #define USDM_REG_AGG_INT_EVENT_25 0xc409c
4357 #define USDM_REG_AGG_INT_EVENT_26 0xc40a0
4358 #define USDM_REG_AGG_INT_EVENT_27 0xc40a4
4359 #define USDM_REG_AGG_INT_EVENT_28 0xc40a8
4360 #define USDM_REG_AGG_INT_EVENT_29 0xc40ac
4361 #define USDM_REG_AGG_INT_EVENT_3 0xc4044
4362 #define USDM_REG_AGG_INT_EVENT_30 0xc40b0
4363 #define USDM_REG_AGG_INT_EVENT_31 0xc40b4
4364 #define USDM_REG_AGG_INT_EVENT_4 0xc4048
4365 #define USDM_REG_AGG_INT_EVENT_5 0xc404c
4366 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4367 or auto-mask-mode (1) */
4368 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
4369 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
4370 #define USDM_REG_AGG_INT_MODE_10 0xc41e0
4371 #define USDM_REG_AGG_INT_MODE_11 0xc41e4
4372 #define USDM_REG_AGG_INT_MODE_12 0xc41e8
4373 #define USDM_REG_AGG_INT_MODE_13 0xc41ec
4374 #define USDM_REG_AGG_INT_MODE_14 0xc41f0
4375 #define USDM_REG_AGG_INT_MODE_15 0xc41f4
4376 #define USDM_REG_AGG_INT_MODE_16 0xc41f8
4377 #define USDM_REG_AGG_INT_MODE_17 0xc41fc
4378 #define USDM_REG_AGG_INT_MODE_18 0xc4200
4379 #define USDM_REG_AGG_INT_MODE_19 0xc4204
4380 #define USDM_REG_AGG_INT_MODE_4 0xc41c8
4381 #define USDM_REG_AGG_INT_MODE_5 0xc41cc
4382 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4383 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
4384 /* [RW 16] The maximum value of the competion counter #0 */
4385 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
4386 /* [RW 16] The maximum value of the competion counter #1 */
4387 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
4388 /* [RW 16] The maximum value of the competion counter #2 */
4389 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
4390 /* [RW 16] The maximum value of the competion counter #3 */
4391 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
4392 /* [RW 13] The start address in the internal RAM for the completion
4394 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
4395 #define USDM_REG_ENABLE_IN1 0xc4238
4396 #define USDM_REG_ENABLE_IN2 0xc423c
4397 #define USDM_REG_ENABLE_OUT1 0xc4240
4398 #define USDM_REG_ENABLE_OUT2 0xc4244
4399 /* [RW 4] The initial number of messages that can be sent to the pxp control
4400 interface without receiving any ACK. */
4401 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
4402 /* [ST 32] The number of ACK after placement messages received */
4403 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
4404 /* [ST 32] The number of packet end messages received from the parser */
4405 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
4406 /* [ST 32] The number of requests received from the pxp async if */
4407 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
4408 /* [ST 32] The number of commands received in queue 0 */
4409 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
4410 /* [ST 32] The number of commands received in queue 10 */
4411 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
4412 /* [ST 32] The number of commands received in queue 11 */
4413 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
4414 /* [ST 32] The number of commands received in queue 1 */
4415 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
4416 /* [ST 32] The number of commands received in queue 2 */
4417 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
4418 /* [ST 32] The number of commands received in queue 3 */
4419 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
4420 /* [ST 32] The number of commands received in queue 4 */
4421 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
4422 /* [ST 32] The number of commands received in queue 5 */
4423 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
4424 /* [ST 32] The number of commands received in queue 6 */
4425 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
4426 /* [ST 32] The number of commands received in queue 7 */
4427 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
4428 /* [ST 32] The number of commands received in queue 8 */
4429 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
4430 /* [ST 32] The number of commands received in queue 9 */
4431 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
4432 /* [RW 13] The start address in the internal RAM for the packet end message */
4433 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
4434 /* [RW 13] The start address in the internal RAM for queue counters */
4435 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
4436 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4437 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
4438 /* [R 1] parser fifo empty in sdm_sync block */
4439 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
4440 /* [R 1] parser serial fifo empty in sdm_sync block */
4441 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
4442 /* [RW 32] Tick for timer counter. Applicable only when
4443 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
4444 #define USDM_REG_TIMER_TICK 0xc4000
4445 /* [RW 32] Interrupt mask register #0 read/write */
4446 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
4447 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
4448 /* [R 32] Interrupt register #0 read */
4449 #define USDM_REG_USDM_INT_STS_0 0xc4294
4450 #define USDM_REG_USDM_INT_STS_1 0xc42a4
4451 /* [RW 11] Parity mask register #0 read/write */
4452 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
4453 /* [R 11] Parity register #0 read */
4454 #define USDM_REG_USDM_PRTY_STS 0xc42b4
4455 /* [RW 5] The number of time_slots in the arbitration cycle */
4456 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
4457 /* [RW 3] The source that is associated with arbitration element 0. Source
4458 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4459 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4460 #define USEM_REG_ARB_ELEMENT0 0x300020
4461 /* [RW 3] The source that is associated with arbitration element 1. Source
4462 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4463 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4464 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
4465 #define USEM_REG_ARB_ELEMENT1 0x300024
4466 /* [RW 3] The source that is associated with arbitration element 2. Source
4467 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4468 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4469 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4470 and ~usem_registers_arb_element1.arb_element1 */
4471 #define USEM_REG_ARB_ELEMENT2 0x300028
4472 /* [RW 3] The source that is associated with arbitration element 3. Source
4473 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4474 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4475 not be equal to register ~usem_registers_arb_element0.arb_element0 and
4476 ~usem_registers_arb_element1.arb_element1 and
4477 ~usem_registers_arb_element2.arb_element2 */
4478 #define USEM_REG_ARB_ELEMENT3 0x30002c
4479 /* [RW 3] The source that is associated with arbitration element 4. Source
4480 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4481 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4482 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4483 and ~usem_registers_arb_element1.arb_element1 and
4484 ~usem_registers_arb_element2.arb_element2 and
4485 ~usem_registers_arb_element3.arb_element3 */
4486 #define USEM_REG_ARB_ELEMENT4 0x300030
4487 #define USEM_REG_ENABLE_IN 0x3000a4
4488 #define USEM_REG_ENABLE_OUT 0x3000a8
4489 /* [RW 32] This address space contains all registers and memories that are
4490 placed in SEM_FAST block. The SEM_FAST registers are described in
4491 appendix B. In order to access the sem_fast registers the base address
4492 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4493 #define USEM_REG_FAST_MEMORY 0x320000
4494 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4496 #define USEM_REG_FIC0_DISABLE 0x300224
4497 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4499 #define USEM_REG_FIC1_DISABLE 0x300234
4500 /* [RW 15] Interrupt table Read and write access to it is not possible in
4501 the middle of the work */
4502 #define USEM_REG_INT_TABLE 0x300400
4503 /* [ST 24] Statistics register. The number of messages that entered through
4505 #define USEM_REG_MSG_NUM_FIC0 0x300000
4506 /* [ST 24] Statistics register. The number of messages that entered through
4508 #define USEM_REG_MSG_NUM_FIC1 0x300004
4509 /* [ST 24] Statistics register. The number of messages that were sent to
4511 #define USEM_REG_MSG_NUM_FOC0 0x300008
4512 /* [ST 24] Statistics register. The number of messages that were sent to
4514 #define USEM_REG_MSG_NUM_FOC1 0x30000c
4515 /* [ST 24] Statistics register. The number of messages that were sent to
4517 #define USEM_REG_MSG_NUM_FOC2 0x300010
4518 /* [ST 24] Statistics register. The number of messages that were sent to
4520 #define USEM_REG_MSG_NUM_FOC3 0x300014
4521 /* [RW 1] Disables input messages from the passive buffer May be updated
4522 during run_time by the microcode */
4523 #define USEM_REG_PAS_DISABLE 0x30024c
4524 /* [WB 128] Debug only. Passive buffer memory */
4525 #define USEM_REG_PASSIVE_BUFFER 0x302000
4526 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4527 #define USEM_REG_PRAM 0x340000
4528 /* [R 16] Valid sleeping threads indication have bit per thread */
4529 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
4530 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4531 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
4532 /* [RW 16] List of free threads . There is a bit per thread. */
4533 #define USEM_REG_THREADS_LIST 0x3002e4
4534 /* [RW 3] The arbitration scheme of time_slot 0 */
4535 #define USEM_REG_TS_0_AS 0x300038
4536 /* [RW 3] The arbitration scheme of time_slot 10 */
4537 #define USEM_REG_TS_10_AS 0x300060
4538 /* [RW 3] The arbitration scheme of time_slot 11 */
4539 #define USEM_REG_TS_11_AS 0x300064
4540 /* [RW 3] The arbitration scheme of time_slot 12 */
4541 #define USEM_REG_TS_12_AS 0x300068
4542 /* [RW 3] The arbitration scheme of time_slot 13 */
4543 #define USEM_REG_TS_13_AS 0x30006c
4544 /* [RW 3] The arbitration scheme of time_slot 14 */
4545 #define USEM_REG_TS_14_AS 0x300070
4546 /* [RW 3] The arbitration scheme of time_slot 15 */
4547 #define USEM_REG_TS_15_AS 0x300074
4548 /* [RW 3] The arbitration scheme of time_slot 16 */
4549 #define USEM_REG_TS_16_AS 0x300078
4550 /* [RW 3] The arbitration scheme of time_slot 17 */
4551 #define USEM_REG_TS_17_AS 0x30007c
4552 /* [RW 3] The arbitration scheme of time_slot 18 */
4553 #define USEM_REG_TS_18_AS 0x300080
4554 /* [RW 3] The arbitration scheme of time_slot 1 */
4555 #define USEM_REG_TS_1_AS 0x30003c
4556 /* [RW 3] The arbitration scheme of time_slot 2 */
4557 #define USEM_REG_TS_2_AS 0x300040
4558 /* [RW 3] The arbitration scheme of time_slot 3 */
4559 #define USEM_REG_TS_3_AS 0x300044
4560 /* [RW 3] The arbitration scheme of time_slot 4 */
4561 #define USEM_REG_TS_4_AS 0x300048
4562 /* [RW 3] The arbitration scheme of time_slot 5 */
4563 #define USEM_REG_TS_5_AS 0x30004c
4564 /* [RW 3] The arbitration scheme of time_slot 6 */
4565 #define USEM_REG_TS_6_AS 0x300050
4566 /* [RW 3] The arbitration scheme of time_slot 7 */
4567 #define USEM_REG_TS_7_AS 0x300054
4568 /* [RW 3] The arbitration scheme of time_slot 8 */
4569 #define USEM_REG_TS_8_AS 0x300058
4570 /* [RW 3] The arbitration scheme of time_slot 9 */
4571 #define USEM_REG_TS_9_AS 0x30005c
4572 /* [RW 32] Interrupt mask register #0 read/write */
4573 #define USEM_REG_USEM_INT_MASK_0 0x300110
4574 #define USEM_REG_USEM_INT_MASK_1 0x300120
4575 /* [R 32] Interrupt register #0 read */
4576 #define USEM_REG_USEM_INT_STS_0 0x300104
4577 #define USEM_REG_USEM_INT_STS_1 0x300114
4578 /* [RW 32] Parity mask register #0 read/write */
4579 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
4580 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
4581 /* [R 32] Parity register #0 read */
4582 #define USEM_REG_USEM_PRTY_STS_0 0x300124
4583 #define USEM_REG_USEM_PRTY_STS_1 0x300134
4584 /* [RW 2] The queue index for registration on Aux1 counter flag. */
4585 #define XCM_REG_AUX1_Q 0x20134
4586 /* [RW 2] Per each decision rule the queue index to register to. */
4587 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
4588 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4589 #define XCM_REG_CAM_OCCUP 0x20244
4590 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4591 disregarded; valid output is deasserted; all other signals are treated as
4592 usual; if 1 - normal activity. */
4593 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
4594 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4595 are disregarded; all other signals are treated as usual; if 1 - normal
4597 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
4598 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4599 disregarded; valid output is deasserted; all other signals are treated as
4600 usual; if 1 - normal activity. */
4601 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
4602 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4603 input is disregarded; all other signals are treated as usual; if 1 -
4605 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
4606 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4607 the initial credit value; read returns the current value of the credit
4608 counter. Must be initialized to 1 at start-up. */
4609 #define XCM_REG_CFC_INIT_CRD 0x20404
4610 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4611 weight 8 (the most prioritised); 1 stands for weight 1(least
4612 prioritised); 2 stands for weight 2; tc. */
4613 #define XCM_REG_CP_WEIGHT 0x200dc
4614 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4615 disregarded; acknowledge output is deasserted; all other signals are
4616 treated as usual; if 1 - normal activity. */
4617 #define XCM_REG_CSEM_IFEN 0x20028
4618 /* [RC 1] Set at message length mismatch (relative to last indication) at
4619 the csem interface. */
4620 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
4621 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4622 weight 8 (the most prioritised); 1 stands for weight 1(least
4623 prioritised); 2 stands for weight 2; tc. */
4624 #define XCM_REG_CSEM_WEIGHT 0x200c4
4625 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4626 disregarded; acknowledge output is deasserted; all other signals are
4627 treated as usual; if 1 - normal activity. */
4628 #define XCM_REG_DORQ_IFEN 0x20030
4629 /* [RC 1] Set at message length mismatch (relative to last indication) at
4630 the dorq interface. */
4631 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
4632 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4633 weight 8 (the most prioritised); 1 stands for weight 1(least
4634 prioritised); 2 stands for weight 2; tc. */
4635 #define XCM_REG_DORQ_WEIGHT 0x200cc
4636 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
4637 #define XCM_REG_ERR_EVNT_ID 0x200b0
4638 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4639 #define XCM_REG_ERR_XCM_HDR 0x200ac
4640 /* [RW 8] The Event ID for Timers expiration. */
4641 #define XCM_REG_EXPR_EVNT_ID 0x200b4
4642 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4643 writes the initial credit value; read returns the current value of the
4644 credit counter. Must be initialized to 64 at start-up. */
4645 #define XCM_REG_FIC0_INIT_CRD 0x2040c
4646 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4647 writes the initial credit value; read returns the current value of the
4648 credit counter. Must be initialized to 64 at start-up. */
4649 #define XCM_REG_FIC1_INIT_CRD 0x20410
4650 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
4651 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
4652 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
4653 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
4654 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
4655 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
4656 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
4657 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
4658 #define XCM_REG_GR_ARB_TYPE 0x2020c
4659 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4660 highest priority is 3. It is supposed that the Channel group is the
4661 compliment of the other 3 groups. */
4662 #define XCM_REG_GR_LD0_PR 0x20214
4663 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4664 highest priority is 3. It is supposed that the Channel group is the
4665 compliment of the other 3 groups. */
4666 #define XCM_REG_GR_LD1_PR 0x20218
4667 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
4668 disregarded; acknowledge output is deasserted; all other signals are
4669 treated as usual; if 1 - normal activity. */
4670 #define XCM_REG_NIG0_IFEN 0x20038
4671 /* [RC 1] Set at message length mismatch (relative to last indication) at
4672 the nig0 interface. */
4673 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
4674 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
4675 weight 8 (the most prioritised); 1 stands for weight 1(least
4676 prioritised); 2 stands for weight 2; tc. */
4677 #define XCM_REG_NIG0_WEIGHT 0x200d4
4678 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
4679 disregarded; acknowledge output is deasserted; all other signals are
4680 treated as usual; if 1 - normal activity. */
4681 #define XCM_REG_NIG1_IFEN 0x2003c
4682 /* [RC 1] Set at message length mismatch (relative to last indication) at
4683 the nig1 interface. */
4684 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
4685 /* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for
4686 weight 8 (the most prioritised); 1 stands for weight 1(least
4687 prioritised); 2 stands for weight 2; tc. */
4688 #define XCM_REG_NIG1_WEIGHT 0x200d8
4689 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4690 sent to STORM; for a specific connection type. The double REG-pairs are
4691 used in order to align to STORM context row size of 128 bits. The offset
4692 of these data in the STORM context is always 0. Index _i stands for the
4693 connection type (one of 16). */
4694 #define XCM_REG_N_SM_CTX_LD_0 0x20060
4695 #define XCM_REG_N_SM_CTX_LD_1 0x20064
4696 #define XCM_REG_N_SM_CTX_LD_10 0x20088
4697 #define XCM_REG_N_SM_CTX_LD_11 0x2008c
4698 #define XCM_REG_N_SM_CTX_LD_12 0x20090
4699 #define XCM_REG_N_SM_CTX_LD_13 0x20094
4700 #define XCM_REG_N_SM_CTX_LD_14 0x20098
4701 #define XCM_REG_N_SM_CTX_LD_15 0x2009c
4702 #define XCM_REG_N_SM_CTX_LD_2 0x20068
4703 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
4704 #define XCM_REG_N_SM_CTX_LD_4 0x20070
4705 #define XCM_REG_N_SM_CTX_LD_5 0x20074
4706 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4707 acknowledge output is deasserted; all other signals are treated as usual;
4708 if 1 - normal activity. */
4709 #define XCM_REG_PBF_IFEN 0x20034
4710 /* [RC 1] Set at message length mismatch (relative to last indication) at
4711 the pbf interface. */
4712 #define XCM_REG_PBF_LENGTH_MIS 0x20234
4713 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4714 weight 8 (the most prioritised); 1 stands for weight 1(least
4715 prioritised); 2 stands for weight 2; tc. */
4716 #define XCM_REG_PBF_WEIGHT 0x200d0
4717 #define XCM_REG_PHYS_QNUM3_0 0x20100
4718 #define XCM_REG_PHYS_QNUM3_1 0x20104
4719 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4720 #define XCM_REG_STOP_EVNT_ID 0x200b8
4721 /* [RC 1] Set at message length mismatch (relative to last indication) at
4722 the STORM interface. */
4723 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
4724 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4725 weight 8 (the most prioritised); 1 stands for weight 1(least
4726 prioritised); 2 stands for weight 2; tc. */
4727 #define XCM_REG_STORM_WEIGHT 0x200bc
4728 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4729 disregarded; acknowledge output is deasserted; all other signals are
4730 treated as usual; if 1 - normal activity. */
4731 #define XCM_REG_STORM_XCM_IFEN 0x20010
4732 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4733 writes the initial credit value; read returns the current value of the
4734 credit counter. Must be initialized to 4 at start-up. */
4735 #define XCM_REG_TM_INIT_CRD 0x2041c
4736 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4737 weight 8 (the most prioritised); 1 stands for weight 1(least
4738 prioritised); 2 stands for weight 2; tc. */
4739 #define XCM_REG_TM_WEIGHT 0x200ec
4740 /* [RW 28] The CM header for Timers expiration command. */
4741 #define XCM_REG_TM_XCM_HDR 0x200a8
4742 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4743 disregarded; acknowledge output is deasserted; all other signals are
4744 treated as usual; if 1 - normal activity. */
4745 #define XCM_REG_TM_XCM_IFEN 0x2001c
4746 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4747 disregarded; acknowledge output is deasserted; all other signals are
4748 treated as usual; if 1 - normal activity. */
4749 #define XCM_REG_TSEM_IFEN 0x20024
4750 /* [RC 1] Set at message length mismatch (relative to last indication) at
4751 the tsem interface. */
4752 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
4753 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4754 weight 8 (the most prioritised); 1 stands for weight 1(least
4755 prioritised); 2 stands for weight 2; tc. */
4756 #define XCM_REG_TSEM_WEIGHT 0x200c0
4757 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
4758 #define XCM_REG_UNA_GT_NXT_Q 0x20120
4759 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4760 disregarded; acknowledge output is deasserted; all other signals are
4761 treated as usual; if 1 - normal activity. */
4762 #define XCM_REG_USEM_IFEN 0x2002c
4763 /* [RC 1] Message length mismatch (relative to last indication) at the usem
4765 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
4766 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4767 weight 8 (the most prioritised); 1 stands for weight 1(least
4768 prioritised); 2 stands for weight 2; tc. */
4769 #define XCM_REG_USEM_WEIGHT 0x200c8
4770 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
4771 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
4772 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
4773 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
4774 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
4775 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
4776 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
4777 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
4778 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
4779 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
4780 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
4781 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
4782 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4783 acknowledge output is deasserted; all other signals are treated as usual;
4784 if 1 - normal activity. */
4785 #define XCM_REG_XCM_CFC_IFEN 0x20050
4786 /* [RW 14] Interrupt mask register #0 read/write */
4787 #define XCM_REG_XCM_INT_MASK 0x202b4
4788 /* [R 14] Interrupt register #0 read */
4789 #define XCM_REG_XCM_INT_STS 0x202a8
4790 /* [R 30] Parity register #0 read */
4791 #define XCM_REG_XCM_PRTY_STS 0x202b8
4792 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
4793 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4794 Is used to determine the number of the AG context REG-pairs written back;
4795 when the Reg1WbFlg isn't set. */
4796 #define XCM_REG_XCM_REG0_SZ 0x200f4
4797 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4798 disregarded; valid is deasserted; all other signals are treated as usual;
4799 if 1 - normal activity. */
4800 #define XCM_REG_XCM_STORM0_IFEN 0x20004
4801 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4802 disregarded; valid is deasserted; all other signals are treated as usual;
4803 if 1 - normal activity. */
4804 #define XCM_REG_XCM_STORM1_IFEN 0x20008
4805 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4806 disregarded; acknowledge output is deasserted; all other signals are
4807 treated as usual; if 1 - normal activity. */
4808 #define XCM_REG_XCM_TM_IFEN 0x20020
4809 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4810 disregarded; valid is deasserted; all other signals are treated as usual;
4811 if 1 - normal activity. */
4812 #define XCM_REG_XCM_XQM_IFEN 0x2000c
4813 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4814 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
4815 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
4816 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
4817 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4818 the initial credit value; read returns the current value of the credit
4819 counter. Must be initialized to 32 at start-up. */
4820 #define XCM_REG_XQM_INIT_CRD 0x20420
4821 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4822 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4823 prioritised); 2 stands for weight 2; tc. */
4824 #define XCM_REG_XQM_P_WEIGHT 0x200e4
4825 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4826 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4827 prioritised); 2 stands for weight 2; tc. */
4828 #define XCM_REG_XQM_S_WEIGHT 0x200e8
4829 /* [RW 28] The CM header value for QM request (primary). */
4830 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
4831 /* [RW 28] The CM header value for QM request (secondary). */
4832 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
4833 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4834 acknowledge output is deasserted; all other signals are treated as usual;
4835 if 1 - normal activity. */
4836 #define XCM_REG_XQM_XCM_IFEN 0x20014
4837 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4838 acknowledge output is deasserted; all other signals are treated as usual;
4839 if 1 - normal activity. */
4840 #define XCM_REG_XSDM_IFEN 0x20018
4841 /* [RC 1] Set at message length mismatch (relative to last indication) at
4842 the SDM interface. */
4843 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
4844 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4845 weight 8 (the most prioritised); 1 stands for weight 1(least
4846 prioritised); 2 stands for weight 2; tc. */
4847 #define XCM_REG_XSDM_WEIGHT 0x200e0
4848 /* [RW 17] Indirect access to the descriptor table of the XX protection
4849 mechanism. The fields are: [5:0] - message length; 11:6] - message
4850 pointer; 16:12] - next pointer. */
4851 #define XCM_REG_XX_DESCR_TABLE 0x20480
4852 #define XCM_REG_XX_DESCR_TABLE_SIZE 32
4853 /* [R 6] Used to read the XX protection Free counter. */
4854 #define XCM_REG_XX_FREE 0x20240
4855 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4856 of the Input Stage XX protection buffer by the XX protection pending
4857 messages. Max credit available - 3.Write writes the initial credit value;
4858 read returns the current value of the credit counter. Must be initialized
4859 to 2 at start-up. */
4860 #define XCM_REG_XX_INIT_CRD 0x20424
4861 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4862 protection. ~xcm_registers_xx_free.xx_free read on read. */
4863 #define XCM_REG_XX_MSG_NUM 0x20428
4864 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4865 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
4866 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4867 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
4869 #define XCM_REG_XX_TABLE 0x20500
4870 /* [RW 8] The event id for aggregated interrupt 0 */
4871 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
4872 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
4873 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
4874 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
4875 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
4876 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4877 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
4878 #define XSDM_REG_AGG_INT_EVENT_15 0x166074
4879 #define XSDM_REG_AGG_INT_EVENT_16 0x166078
4880 #define XSDM_REG_AGG_INT_EVENT_17 0x16607c
4881 #define XSDM_REG_AGG_INT_EVENT_18 0x166080
4882 #define XSDM_REG_AGG_INT_EVENT_19 0x166084
4883 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
4884 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
4885 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
4886 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4887 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
4888 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
4889 #define XSDM_REG_AGG_INT_EVENT_20 0x166088
4890 #define XSDM_REG_AGG_INT_EVENT_21 0x16608c
4891 #define XSDM_REG_AGG_INT_EVENT_22 0x166090
4892 #define XSDM_REG_AGG_INT_EVENT_23 0x166094
4893 #define XSDM_REG_AGG_INT_EVENT_24 0x166098
4894 #define XSDM_REG_AGG_INT_EVENT_25 0x16609c
4895 #define XSDM_REG_AGG_INT_EVENT_26 0x1660a0
4896 #define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
4897 #define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
4898 #define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
4899 #define XSDM_REG_AGG_INT_EVENT_3 0x166044
4900 #define XSDM_REG_AGG_INT_EVENT_30 0x1660b0
4901 #define XSDM_REG_AGG_INT_EVENT_31 0x1660b4
4902 #define XSDM_REG_AGG_INT_EVENT_4 0x166048
4903 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c
4904 #define XSDM_REG_AGG_INT_EVENT_6 0x166050
4905 #define XSDM_REG_AGG_INT_EVENT_7 0x166054
4906 #define XSDM_REG_AGG_INT_EVENT_8 0x166058
4907 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c
4908 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4909 or auto-mask-mode (1) */
4910 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
4911 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
4912 #define XSDM_REG_AGG_INT_MODE_10 0x1661e0
4913 #define XSDM_REG_AGG_INT_MODE_11 0x1661e4
4914 #define XSDM_REG_AGG_INT_MODE_12 0x1661e8
4915 #define XSDM_REG_AGG_INT_MODE_13 0x1661ec
4916 #define XSDM_REG_AGG_INT_MODE_14 0x1661f0
4917 #define XSDM_REG_AGG_INT_MODE_15 0x1661f4
4918 #define XSDM_REG_AGG_INT_MODE_16 0x1661f8
4919 #define XSDM_REG_AGG_INT_MODE_17 0x1661fc
4920 #define XSDM_REG_AGG_INT_MODE_18 0x166200
4921 #define XSDM_REG_AGG_INT_MODE_19 0x166204
4922 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4923 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
4924 /* [RW 16] The maximum value of the competion counter #0 */
4925 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
4926 /* [RW 16] The maximum value of the competion counter #1 */
4927 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
4928 /* [RW 16] The maximum value of the competion counter #2 */
4929 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
4930 /* [RW 16] The maximum value of the competion counter #3 */
4931 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
4932 /* [RW 13] The start address in the internal RAM for the completion
4934 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
4935 #define XSDM_REG_ENABLE_IN1 0x166238
4936 #define XSDM_REG_ENABLE_IN2 0x16623c
4937 #define XSDM_REG_ENABLE_OUT1 0x166240
4938 #define XSDM_REG_ENABLE_OUT2 0x166244
4939 /* [RW 4] The initial number of messages that can be sent to the pxp control
4940 interface without receiving any ACK. */
4941 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
4942 /* [ST 32] The number of ACK after placement messages received */
4943 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
4944 /* [ST 32] The number of packet end messages received from the parser */
4945 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
4946 /* [ST 32] The number of requests received from the pxp async if */
4947 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
4948 /* [ST 32] The number of commands received in queue 0 */
4949 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
4950 /* [ST 32] The number of commands received in queue 10 */
4951 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
4952 /* [ST 32] The number of commands received in queue 11 */
4953 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
4954 /* [ST 32] The number of commands received in queue 1 */
4955 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
4956 /* [ST 32] The number of commands received in queue 3 */
4957 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
4958 /* [ST 32] The number of commands received in queue 4 */
4959 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
4960 /* [ST 32] The number of commands received in queue 5 */
4961 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
4962 /* [ST 32] The number of commands received in queue 6 */
4963 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
4964 /* [ST 32] The number of commands received in queue 7 */
4965 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
4966 /* [ST 32] The number of commands received in queue 8 */
4967 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
4968 /* [ST 32] The number of commands received in queue 9 */
4969 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
4970 /* [RW 13] The start address in the internal RAM for queue counters */
4971 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
4972 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4973 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
4974 /* [R 1] parser fifo empty in sdm_sync block */
4975 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
4976 /* [R 1] parser serial fifo empty in sdm_sync block */
4977 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
4978 /* [RW 32] Tick for timer counter. Applicable only when
4979 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4980 #define XSDM_REG_TIMER_TICK 0x166000
4981 /* [RW 32] Interrupt mask register #0 read/write */
4982 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
4983 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
4984 /* [R 32] Interrupt register #0 read */
4985 #define XSDM_REG_XSDM_INT_STS_0 0x166290
4986 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0
4987 /* [RW 11] Parity mask register #0 read/write */
4988 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
4989 /* [R 11] Parity register #0 read */
4990 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0
4991 /* [RW 5] The number of time_slots in the arbitration cycle */
4992 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
4993 /* [RW 3] The source that is associated with arbitration element 0. Source
4994 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4995 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4996 #define XSEM_REG_ARB_ELEMENT0 0x280020
4997 /* [RW 3] The source that is associated with arbitration element 1. Source
4998 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4999 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5000 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
5001 #define XSEM_REG_ARB_ELEMENT1 0x280024
5002 /* [RW 3] The source that is associated with arbitration element 2. Source
5003 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5004 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5005 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5006 and ~xsem_registers_arb_element1.arb_element1 */
5007 #define XSEM_REG_ARB_ELEMENT2 0x280028
5008 /* [RW 3] The source that is associated with arbitration element 3. Source
5009 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5010 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5011 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
5012 ~xsem_registers_arb_element1.arb_element1 and
5013 ~xsem_registers_arb_element2.arb_element2 */
5014 #define XSEM_REG_ARB_ELEMENT3 0x28002c
5015 /* [RW 3] The source that is associated with arbitration element 4. Source
5016 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5017 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5018 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5019 and ~xsem_registers_arb_element1.arb_element1 and
5020 ~xsem_registers_arb_element2.arb_element2 and
5021 ~xsem_registers_arb_element3.arb_element3 */
5022 #define XSEM_REG_ARB_ELEMENT4 0x280030
5023 #define XSEM_REG_ENABLE_IN 0x2800a4
5024 #define XSEM_REG_ENABLE_OUT 0x2800a8
5025 /* [RW 32] This address space contains all registers and memories that are
5026 placed in SEM_FAST block. The SEM_FAST registers are described in
5027 appendix B. In order to access the sem_fast registers the base address
5028 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
5029 #define XSEM_REG_FAST_MEMORY 0x2a0000
5030 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
5032 #define XSEM_REG_FIC0_DISABLE 0x280224
5033 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
5035 #define XSEM_REG_FIC1_DISABLE 0x280234
5036 /* [RW 15] Interrupt table Read and write access to it is not possible in
5037 the middle of the work */
5038 #define XSEM_REG_INT_TABLE 0x280400
5039 /* [ST 24] Statistics register. The number of messages that entered through
5041 #define XSEM_REG_MSG_NUM_FIC0 0x280000
5042 /* [ST 24] Statistics register. The number of messages that entered through
5044 #define XSEM_REG_MSG_NUM_FIC1 0x280004
5045 /* [ST 24] Statistics register. The number of messages that were sent to
5047 #define XSEM_REG_MSG_NUM_FOC0 0x280008
5048 /* [ST 24] Statistics register. The number of messages that were sent to
5050 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
5051 /* [ST 24] Statistics register. The number of messages that were sent to
5053 #define XSEM_REG_MSG_NUM_FOC2 0x280010
5054 /* [ST 24] Statistics register. The number of messages that were sent to
5056 #define XSEM_REG_MSG_NUM_FOC3 0x280014
5057 /* [RW 1] Disables input messages from the passive buffer May be updated
5058 during run_time by the microcode */
5059 #define XSEM_REG_PAS_DISABLE 0x28024c
5060 /* [WB 128] Debug only. Passive buffer memory */
5061 #define XSEM_REG_PASSIVE_BUFFER 0x282000
5062 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5063 #define XSEM_REG_PRAM 0x2c0000
5064 /* [R 16] Valid sleeping threads indication have bit per thread */
5065 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
5066 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5067 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
5068 /* [RW 16] List of free threads . There is a bit per thread. */
5069 #define XSEM_REG_THREADS_LIST 0x2802e4
5070 /* [RW 3] The arbitration scheme of time_slot 0 */
5071 #define XSEM_REG_TS_0_AS 0x280038
5072 /* [RW 3] The arbitration scheme of time_slot 10 */
5073 #define XSEM_REG_TS_10_AS 0x280060
5074 /* [RW 3] The arbitration scheme of time_slot 11 */
5075 #define XSEM_REG_TS_11_AS 0x280064
5076 /* [RW 3] The arbitration scheme of time_slot 12 */
5077 #define XSEM_REG_TS_12_AS 0x280068
5078 /* [RW 3] The arbitration scheme of time_slot 13 */
5079 #define XSEM_REG_TS_13_AS 0x28006c
5080 /* [RW 3] The arbitration scheme of time_slot 14 */
5081 #define XSEM_REG_TS_14_AS 0x280070
5082 /* [RW 3] The arbitration scheme of time_slot 15 */
5083 #define XSEM_REG_TS_15_AS 0x280074
5084 /* [RW 3] The arbitration scheme of time_slot 16 */
5085 #define XSEM_REG_TS_16_AS 0x280078
5086 /* [RW 3] The arbitration scheme of time_slot 17 */
5087 #define XSEM_REG_TS_17_AS 0x28007c
5088 /* [RW 3] The arbitration scheme of time_slot 18 */
5089 #define XSEM_REG_TS_18_AS 0x280080
5090 /* [RW 3] The arbitration scheme of time_slot 1 */
5091 #define XSEM_REG_TS_1_AS 0x28003c
5092 /* [RW 3] The arbitration scheme of time_slot 2 */
5093 #define XSEM_REG_TS_2_AS 0x280040
5094 /* [RW 3] The arbitration scheme of time_slot 3 */
5095 #define XSEM_REG_TS_3_AS 0x280044
5096 /* [RW 3] The arbitration scheme of time_slot 4 */
5097 #define XSEM_REG_TS_4_AS 0x280048
5098 /* [RW 3] The arbitration scheme of time_slot 5 */
5099 #define XSEM_REG_TS_5_AS 0x28004c
5100 /* [RW 3] The arbitration scheme of time_slot 6 */
5101 #define XSEM_REG_TS_6_AS 0x280050
5102 /* [RW 3] The arbitration scheme of time_slot 7 */
5103 #define XSEM_REG_TS_7_AS 0x280054
5104 /* [RW 3] The arbitration scheme of time_slot 8 */
5105 #define XSEM_REG_TS_8_AS 0x280058
5106 /* [RW 3] The arbitration scheme of time_slot 9 */
5107 #define XSEM_REG_TS_9_AS 0x28005c
5108 /* [RW 32] Interrupt mask register #0 read/write */
5109 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
5110 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
5111 /* [R 32] Interrupt register #0 read */
5112 #define XSEM_REG_XSEM_INT_STS_0 0x280104
5113 #define XSEM_REG_XSEM_INT_STS_1 0x280114
5114 /* [RW 32] Parity mask register #0 read/write */
5115 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
5116 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
5117 /* [R 32] Parity register #0 read */
5118 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124
5119 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134
5120 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5121 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
5122 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
5123 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
5124 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
5125 #define MCPR_NVM_COMMAND_DONE (1L<<3)
5126 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
5127 #define MCPR_NVM_COMMAND_LAST (1L<<8)
5128 #define MCPR_NVM_COMMAND_WR (1L<<5)
5129 #define MCPR_NVM_COMMAND_WREN (1L<<16)
5130 #define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
5131 #define MCPR_NVM_COMMAND_WRDI (1L<<17)
5132 #define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
5133 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
5134 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
5135 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
5136 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
5137 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5138 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
5139 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
5140 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
5141 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
5142 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
5143 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
5144 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
5145 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
5146 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
5147 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
5148 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
5149 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
5150 #define EMAC_LED_1000MB_OVERRIDE (1L<<1)
5151 #define EMAC_LED_100MB_OVERRIDE (1L<<2)
5152 #define EMAC_LED_10MB_OVERRIDE (1L<<3)
5153 #define EMAC_LED_2500MB_OVERRIDE (1L<<12)
5154 #define EMAC_LED_OVERRIDE (1L<<0)
5155 #define EMAC_LED_TRAFFIC (1L<<6)
5156 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
5157 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
5158 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
5159 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
5160 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
5161 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
5162 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
5163 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
5164 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
5165 #define EMAC_MODE_25G_MODE (1L<<5)
5166 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
5167 #define EMAC_MODE_PORT_GMII (2L<<2)
5168 #define EMAC_MODE_PORT_MII (1L<<2)
5169 #define EMAC_MODE_PORT_MII_10M (3L<<2)
5170 #define EMAC_MODE_RESET (1L<<0)
5171 #define EMAC_REG_EMAC_LED 0xc
5172 #define EMAC_REG_EMAC_MAC_MATCH 0x10
5173 #define EMAC_REG_EMAC_MDIO_COMM 0xac
5174 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
5175 #define EMAC_REG_EMAC_MODE 0x0
5176 #define EMAC_REG_EMAC_RX_MODE 0xc8
5177 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
5178 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
5179 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
5180 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
5181 #define EMAC_REG_EMAC_TX_MODE 0xbc
5182 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
5183 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
5184 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
5185 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
5186 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
5187 #define EMAC_RX_MODE_RESET (1L<<0)
5188 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
5189 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
5190 #define EMAC_TX_MODE_FLOW_EN (1L<<4)
5191 #define EMAC_TX_MODE_RESET (1L<<0)
5192 #define MISC_REGISTERS_GPIO_0 0
5193 #define MISC_REGISTERS_GPIO_1 1
5194 #define MISC_REGISTERS_GPIO_2 2
5195 #define MISC_REGISTERS_GPIO_3 3
5196 #define MISC_REGISTERS_GPIO_CLR_POS 16
5197 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
5198 #define MISC_REGISTERS_GPIO_FLOAT_POS 24
5199 #define MISC_REGISTERS_GPIO_HIGH 1
5200 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
5201 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24
5202 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
5203 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
5204 #define MISC_REGISTERS_GPIO_INT_SET_POS 16
5205 #define MISC_REGISTERS_GPIO_LOW 0
5206 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
5207 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
5208 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4
5209 #define MISC_REGISTERS_GPIO_SET_POS 8
5210 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
5211 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
5212 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
5213 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
5214 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
5215 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
5216 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
5217 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5218 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5219 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
5220 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
5221 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
5222 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
5223 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
5224 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
5225 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
5226 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
5227 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
5228 #define MISC_REGISTERS_SPIO_4 4
5229 #define MISC_REGISTERS_SPIO_5 5
5230 #define MISC_REGISTERS_SPIO_7 7
5231 #define MISC_REGISTERS_SPIO_CLR_POS 16
5232 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
5233 #define GRC_MISC_REGISTERS_SPIO_FLOAT7 0x80000000
5234 #define GRC_MISC_REGISTERS_SPIO_FLOAT6 0x40000000
5235 #define GRC_MISC_REGISTERS_SPIO_FLOAT5 0x20000000
5236 #define GRC_MISC_REGISTERS_SPIO_FLOAT4 0x10000000
5237 #define MISC_REGISTERS_SPIO_FLOAT_POS 24
5238 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5239 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
5240 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5241 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5242 #define MISC_REGISTERS_SPIO_SET_POS 8
5243 #define HW_LOCK_MAX_RESOURCE_VALUE 31
5244 #define HW_LOCK_RESOURCE_GPIO 1
5245 #define HW_LOCK_RESOURCE_MDIO 0
5246 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5247 #define HW_LOCK_RESOURCE_SPIO 2
5248 #define HW_LOCK_RESOURCE_UNDI 5
5249 #define PRS_FLAG_OVERETH_IPV4 1
5250 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
5251 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
5252 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
5253 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
5254 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
5255 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
5256 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
5257 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
5258 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
5259 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
5260 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
5261 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
5262 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
5263 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
5264 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1<<5)
5265 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1<<9)
5266 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
5267 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
5268 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
5269 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
5270 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
5271 #define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
5272 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
5273 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
5274 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
5275 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
5276 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
5277 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
5278 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
5279 #define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15)
5280 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
5281 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
5282 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
5283 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
5284 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
5285 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
5286 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
5287 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
5288 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
5289 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
5290 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
5291 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
5292 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
5293 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
5294 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
5295 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
5296 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
5297 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
5298 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
5299 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
5301 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0
5302 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5304 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
5305 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
5306 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
5307 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
5308 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
5309 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
5310 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
5311 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
5312 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
5313 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
5314 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
5315 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
5316 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
5317 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
5318 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
5319 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
5321 /* storm asserts attention bits */
5322 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
5323 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
5324 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
5325 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
5327 /* mcp error attention bit */
5328 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
5330 /*E1H NIG status sync attention mapped to group 4-7*/
5331 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5332 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5333 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5334 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5335 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5336 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5337 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5338 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5341 #define LATCHED_ATTN_RBCR 23
5342 #define LATCHED_ATTN_RBCT 24
5343 #define LATCHED_ATTN_RBCN 25
5344 #define LATCHED_ATTN_RBCU 26
5345 #define LATCHED_ATTN_RBCP 27
5346 #define LATCHED_ATTN_TIMEOUT_GRC 28
5347 #define LATCHED_ATTN_RSVD_GRC 29
5348 #define LATCHED_ATTN_ROM_PARITY_MCP 30
5349 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
5350 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
5351 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
5353 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
5354 #define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32))
5356 * This file defines GRC base address for every block.
5357 * This file is included by chipsim, asm microcode and cpp microcode.
5358 * These values are used in Design.xml on regBase attribute
5359 * Use the base with the generated offsets of specific registers.
5362 #define GRCBASE_PXPCS 0x000000
5363 #define GRCBASE_PCICONFIG 0x002000
5364 #define GRCBASE_PCIREG 0x002400
5365 #define GRCBASE_EMAC0 0x008000
5366 #define GRCBASE_EMAC1 0x008400
5367 #define GRCBASE_DBU 0x008800
5368 #define GRCBASE_MISC 0x00A000
5369 #define GRCBASE_DBG 0x00C000
5370 #define GRCBASE_NIG 0x010000
5371 #define GRCBASE_XCM 0x020000
5372 #define GRCBASE_PRS 0x040000
5373 #define GRCBASE_SRCH 0x040400
5374 #define GRCBASE_TSDM 0x042000
5375 #define GRCBASE_TCM 0x050000
5376 #define GRCBASE_BRB1 0x060000
5377 #define GRCBASE_MCP 0x080000
5378 #define GRCBASE_UPB 0x0C1000
5379 #define GRCBASE_CSDM 0x0C2000
5380 #define GRCBASE_USDM 0x0C4000
5381 #define GRCBASE_CCM 0x0D0000
5382 #define GRCBASE_UCM 0x0E0000
5383 #define GRCBASE_CDU 0x101000
5384 #define GRCBASE_DMAE 0x102000
5385 #define GRCBASE_PXP 0x103000
5386 #define GRCBASE_CFC 0x104000
5387 #define GRCBASE_HC 0x108000
5388 #define GRCBASE_PXP2 0x120000
5389 #define GRCBASE_PBF 0x140000
5390 #define GRCBASE_XPB 0x161000
5391 #define GRCBASE_TIMERS 0x164000
5392 #define GRCBASE_XSDM 0x166000
5393 #define GRCBASE_QM 0x168000
5394 #define GRCBASE_DQ 0x170000
5395 #define GRCBASE_TSEM 0x180000
5396 #define GRCBASE_CSEM 0x200000
5397 #define GRCBASE_XSEM 0x280000
5398 #define GRCBASE_USEM 0x300000
5399 #define GRCBASE_MISC_AEU GRCBASE_MISC
5402 /* offset of configuration space in the pci core register */
5403 #define PCICFG_OFFSET 0x2000
5404 #define PCICFG_VENDOR_ID_OFFSET 0x00
5405 #define PCICFG_DEVICE_ID_OFFSET 0x02
5406 #define PCICFG_COMMAND_OFFSET 0x04
5407 #define PCICFG_COMMAND_IO_SPACE (1<<0)
5408 #define PCICFG_COMMAND_MEM_SPACE (1<<1)
5409 #define PCICFG_COMMAND_BUS_MASTER (1<<2)
5410 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5411 #define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5412 #define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5413 #define PCICFG_COMMAND_PERR_ENA (1<<6)
5414 #define PCICFG_COMMAND_STEPPING (1<<7)
5415 #define PCICFG_COMMAND_SERR_ENA (1<<8)
5416 #define PCICFG_COMMAND_FAST_B2B (1<<9)
5417 #define PCICFG_COMMAND_INT_DISABLE (1<<10)
5418 #define PCICFG_COMMAND_RESERVED (0x1f<<11)
5419 #define PCICFG_STATUS_OFFSET 0x06
5420 #define PCICFG_REVESION_ID_OFFSET 0x08
5421 #define PCICFG_CACHE_LINE_SIZE 0x0c
5422 #define PCICFG_LATENCY_TIMER 0x0d
5423 #define PCICFG_BAR_1_LOW 0x10
5424 #define PCICFG_BAR_1_HIGH 0x14
5425 #define PCICFG_BAR_2_LOW 0x18
5426 #define PCICFG_BAR_2_HIGH 0x1c
5427 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
5428 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
5429 #define PCICFG_INT_LINE 0x3c
5430 #define PCICFG_INT_PIN 0x3d
5431 #define PCICFG_PM_CAPABILITY 0x48
5432 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
5433 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
5434 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
5435 #define PCICFG_PM_CAPABILITY_DSI (1<<21)
5436 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
5437 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
5438 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
5439 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
5440 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
5441 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
5442 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
5443 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
5444 #define PCICFG_PM_CSR_OFFSET 0x4c
5445 #define PCICFG_PM_CSR_STATE (0x3<<0)
5446 #define PCICFG_PM_CSR_PME_ENABLE (1<<8)
5447 #define PCICFG_PM_CSR_PME_STATUS (1<<15)
5448 #define PCICFG_MSI_CAP_ID_OFFSET 0x58
5449 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
5450 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
5451 #define PCICFG_MSI_CONTROL_MENA (0x7<<20)
5452 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
5453 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
5454 #define PCICFG_GRC_ADDRESS 0x78
5455 #define PCICFG_GRC_DATA 0x80
5456 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
5457 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
5458 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
5459 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
5460 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
5462 #define PCICFG_DEVICE_CONTROL 0xb4
5463 #define PCICFG_DEVICE_STATUS 0xb6
5464 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
5465 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
5466 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
5467 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
5468 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
5469 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
5470 #define PCICFG_LINK_CONTROL 0xbc
5473 #define BAR_USTRORM_INTMEM 0x400000
5474 #define BAR_CSTRORM_INTMEM 0x410000
5475 #define BAR_XSTRORM_INTMEM 0x420000
5476 #define BAR_TSTRORM_INTMEM 0x430000
5478 /* for accessing the IGU in case of status block ACK */
5479 #define BAR_IGU_INTMEM 0x440000
5481 #define BAR_DOORBELL_OFFSET 0x800000
5483 #define BAR_ME_REGISTER 0x450000
5485 /* config_2 offset */
5486 #define GRC_CONFIG_2_SIZE_REG 0x408
5487 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
5488 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
5489 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
5490 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
5491 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
5492 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
5493 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
5494 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
5495 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
5496 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
5497 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
5498 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
5499 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
5500 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
5501 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
5502 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
5503 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
5504 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
5505 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
5506 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
5507 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
5508 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
5509 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
5510 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
5511 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
5512 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
5513 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
5514 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
5515 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
5516 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
5517 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
5518 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
5519 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
5520 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
5521 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
5522 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
5523 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
5524 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
5525 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
5526 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
5528 /* config_3 offset */
5529 #define GRC_CONFIG_3_SIZE_REG 0x40c
5530 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
5531 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
5532 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
5533 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
5534 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
5535 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
5536 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
5538 #define GRC_BAR2_CONFIG 0x4e0
5539 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
5540 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
5541 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
5542 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
5543 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
5544 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
5545 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
5546 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
5547 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
5548 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
5549 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
5550 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
5551 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
5552 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
5553 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
5554 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
5555 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
5556 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
5558 #define PCI_PM_DATA_A 0x410
5559 #define PCI_PM_DATA_B 0x414
5560 #define PCI_ID_VAL1 0x434
5561 #define PCI_ID_VAL2 0x438
5564 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
5565 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
5566 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
5567 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
5568 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
5570 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
5571 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
5572 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
5573 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
5574 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
5575 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
5577 #define MDIO_REG_BANK_RX0 0x80b0
5578 #define MDIO_RX0_RX_EQ_BOOST 0x1c
5579 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5580 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
5582 #define MDIO_REG_BANK_RX1 0x80c0
5583 #define MDIO_RX1_RX_EQ_BOOST 0x1c
5584 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5585 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
5587 #define MDIO_REG_BANK_RX2 0x80d0
5588 #define MDIO_RX2_RX_EQ_BOOST 0x1c
5589 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5590 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
5592 #define MDIO_REG_BANK_RX3 0x80e0
5593 #define MDIO_RX3_RX_EQ_BOOST 0x1c
5594 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5595 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
5597 #define MDIO_REG_BANK_RX_ALL 0x80f0
5598 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
5599 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5600 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
5602 #define MDIO_REG_BANK_TX0 0x8060
5603 #define MDIO_TX0_TX_DRIVER 0x17
5604 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5605 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5606 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5607 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5608 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5609 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5610 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5611 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5612 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5614 #define MDIO_REG_BANK_TX1 0x8070
5615 #define MDIO_TX1_TX_DRIVER 0x17
5616 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5617 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5618 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5619 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5620 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5621 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5622 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5623 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5624 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5626 #define MDIO_REG_BANK_TX2 0x8080
5627 #define MDIO_TX2_TX_DRIVER 0x17
5628 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5629 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5630 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5631 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5632 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5633 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5634 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5635 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5636 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5638 #define MDIO_REG_BANK_TX3 0x8090
5639 #define MDIO_TX3_TX_DRIVER 0x17
5640 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5641 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5642 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5643 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5644 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5645 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5646 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5647 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5648 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5650 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
5651 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
5653 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
5654 #define MDIO_BLOCK1_LANE_CTRL0 0x15
5655 #define MDIO_BLOCK1_LANE_CTRL1 0x16
5656 #define MDIO_BLOCK1_LANE_CTRL2 0x17
5657 #define MDIO_BLOCK1_LANE_PRBS 0x19
5659 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
5660 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
5661 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
5662 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
5663 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
5664 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
5665 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
5666 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
5667 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
5668 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
5670 #define MDIO_REG_BANK_GP_STATUS 0x8120
5671 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
5672 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
5673 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
5674 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
5675 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
5676 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
5677 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
5678 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
5679 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
5680 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
5681 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
5682 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
5683 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
5684 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
5685 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
5686 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
5687 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
5688 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
5689 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
5690 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
5691 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
5692 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
5693 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
5694 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
5695 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
5698 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
5699 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
5700 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
5701 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
5702 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
5704 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
5705 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
5706 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
5707 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
5708 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
5709 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
5710 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
5711 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
5712 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
5713 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
5714 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
5715 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
5716 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
5717 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
5718 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
5719 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
5720 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
5721 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
5722 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
5723 #define MDIO_SERDES_DIGITAL_MISC1 0x18
5724 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
5725 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
5726 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
5727 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
5728 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
5729 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
5730 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
5731 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
5732 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
5733 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
5734 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
5735 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
5736 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
5737 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
5738 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
5739 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
5740 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
5741 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
5743 #define MDIO_REG_BANK_OVER_1G 0x8320
5744 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
5745 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
5746 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
5747 #define MDIO_OVER_1G_UP1 0x19
5748 #define MDIO_OVER_1G_UP1_2_5G 0x0001
5749 #define MDIO_OVER_1G_UP1_5G 0x0002
5750 #define MDIO_OVER_1G_UP1_6G 0x0004
5751 #define MDIO_OVER_1G_UP1_10G 0x0010
5752 #define MDIO_OVER_1G_UP1_10GH 0x0008
5753 #define MDIO_OVER_1G_UP1_12G 0x0020
5754 #define MDIO_OVER_1G_UP1_12_5G 0x0040
5755 #define MDIO_OVER_1G_UP1_13G 0x0080
5756 #define MDIO_OVER_1G_UP1_15G 0x0100
5757 #define MDIO_OVER_1G_UP1_16G 0x0200
5758 #define MDIO_OVER_1G_UP2 0x1A
5759 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
5760 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
5761 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
5762 #define MDIO_OVER_1G_UP3 0x1B
5763 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
5764 #define MDIO_OVER_1G_LP_UP1 0x1C
5765 #define MDIO_OVER_1G_LP_UP2 0x1D
5766 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
5767 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
5768 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
5769 #define MDIO_OVER_1G_LP_UP3 0x1E
5771 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
5772 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
5773 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
5774 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
5776 #define MDIO_REG_BANK_CL73_USERB0 0x8370
5777 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
5778 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
5779 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
5780 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
5781 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
5782 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
5784 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
5785 #define MDIO_AER_BLOCK_AER_REG 0x1E
5787 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
5788 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
5789 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
5790 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
5791 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
5792 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
5793 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
5794 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
5795 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
5796 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
5797 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
5798 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
5799 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
5800 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
5801 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
5802 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
5803 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
5804 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
5805 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
5806 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
5807 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
5808 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
5809 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
5810 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
5811 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
5812 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
5813 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
5814 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
5815 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
5816 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
5817 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
5818 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
5819 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
5820 Theotherbitsarereservedandshouldbezero*/
5821 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
5824 #define MDIO_PMA_DEVAD 0x1
5826 #define MDIO_PMA_REG_CTRL 0x0
5827 #define MDIO_PMA_REG_STATUS 0x1
5828 #define MDIO_PMA_REG_10G_CTRL2 0x7
5829 #define MDIO_PMA_REG_RX_SD 0xa
5831 #define MDIO_PMA_REG_BCM_CTRL 0x0096
5832 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
5833 #define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000
5834 #define MDIO_PMA_REG_LASI_CTRL 0x9002
5835 #define MDIO_PMA_REG_RX_ALARM 0x9003
5836 #define MDIO_PMA_REG_TX_ALARM 0x9004
5837 #define MDIO_PMA_REG_LASI_STATUS 0x9005
5838 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
5839 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
5840 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
5841 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
5842 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
5843 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
5844 #define MDIO_PMA_REG_GEN_CTRL 0xca10
5845 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
5846 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
5847 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
5848 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
5849 #define MDIO_PMA_REG_ROM_VER1 0xca19
5850 #define MDIO_PMA_REG_ROM_VER2 0xca1a
5851 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
5852 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
5853 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
5854 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
5855 #define MDIO_PMA_REG_LRM_MODE 0xca3f
5856 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
5857 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
5859 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
5860 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
5861 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
5862 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
5863 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
5864 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
5865 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
5866 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
5867 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
5868 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
5869 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
5870 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
5872 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
5873 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
5874 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
5875 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
5876 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
5877 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
5878 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
5879 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
5881 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
5882 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
5883 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
5885 #define MDIO_PMA_REG_7101_RESET 0xc000
5886 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
5887 #define MDIO_PMA_REG_7101_VER1 0xc026
5888 #define MDIO_PMA_REG_7101_VER2 0xc027
5891 #define MDIO_WIS_DEVAD 0x2
5893 #define MDIO_WIS_REG_LASI_CNTL 0x9002
5894 #define MDIO_WIS_REG_LASI_STATUS 0x9005
5896 #define MDIO_PCS_DEVAD 0x3
5897 #define MDIO_PCS_REG_STATUS 0x0020
5898 #define MDIO_PCS_REG_LASI_STATUS 0x9005
5899 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
5900 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
5901 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
5902 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
5903 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
5904 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
5905 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
5906 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
5907 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
5910 #define MDIO_XS_DEVAD 0x4
5911 #define MDIO_XS_PLL_SEQUENCER 0x8000
5912 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
5914 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
5915 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
5916 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
5917 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
5918 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
5920 #define MDIO_AN_DEVAD 0x7
5922 #define MDIO_AN_REG_CTRL 0x0000
5923 #define MDIO_AN_REG_STATUS 0x0001
5924 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
5925 #define MDIO_AN_REG_ADV_PAUSE 0x0010
5926 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
5927 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
5928 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
5929 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
5930 #define MDIO_AN_REG_ADV 0x0011
5931 #define MDIO_AN_REG_ADV2 0x0012
5932 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
5933 #define MDIO_AN_REG_MASTER_STATUS 0x0021
5935 #define MDIO_AN_REG_LINK_STATUS 0x8304
5936 #define MDIO_AN_REG_CL37_CL73 0x8370
5937 #define MDIO_AN_REG_CL37_AN 0xffe0
5938 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
5939 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
5941 #define MDIO_AN_REG_8073_2_5G 0x8329
5944 #define IGU_FUNC_BASE 0x0400
5946 #define IGU_ADDR_MSIX 0x0000
5947 #define IGU_ADDR_INT_ACK 0x0200
5948 #define IGU_ADDR_PROD_UPD 0x0201
5949 #define IGU_ADDR_ATTN_BITS_UPD 0x0202
5950 #define IGU_ADDR_ATTN_BITS_SET 0x0203
5951 #define IGU_ADDR_ATTN_BITS_CLR 0x0204
5952 #define IGU_ADDR_COALESCE_NOW 0x0205
5953 #define IGU_ADDR_SIMD_MASK 0x0206
5954 #define IGU_ADDR_SIMD_NOMASK 0x0207
5955 #define IGU_ADDR_MSI_CTL 0x0210
5956 #define IGU_ADDR_MSI_ADDR_LO 0x0211
5957 #define IGU_ADDR_MSI_ADDR_HI 0x0212
5958 #define IGU_ADDR_MSI_DATA 0x0213
5960 #define IGU_INT_ENABLE 0
5961 #define IGU_INT_DISABLE 1
5962 #define IGU_INT_NOP 2
5963 #define IGU_INT_NOP2 3
5965 #define COMMAND_REG_INT_ACK 0x0
5966 #define COMMAND_REG_PROD_UPD 0x4
5967 #define COMMAND_REG_ATTN_BITS_UPD 0x8
5968 #define COMMAND_REG_ATTN_BITS_SET 0xc
5969 #define COMMAND_REG_ATTN_BITS_CLR 0x10
5970 #define COMMAND_REG_COALESCE_NOW 0x14
5971 #define COMMAND_REG_SIMD_MASK 0x18
5972 #define COMMAND_REG_SIMD_NOMASK 0x1c
projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob