1 /* Copyright 2008-2009 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/delay.h>
22 #include <linux/ethtool.h>
23 #include <linux/mutex.h>
27 /********************************************************/
29 #define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
30 #define ETH_MIN_PACKET_SIZE 60
31 #define ETH_MAX_PACKET_SIZE 1500
32 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
33 #define MDIO_ACCESS_TIMEOUT 1000
34 #define BMAC_CONTROL_RX_ENABLE 2
36 /***********************************************************/
37 /* Shortcut definitions */
38 /***********************************************************/
40 #define NIG_LATCH_BC_ENABLE_MI_INT 0
42 #define NIG_STATUS_EMAC0_MI_INT \
43 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
44 #define NIG_STATUS_XGXS0_LINK10G \
45 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
46 #define NIG_STATUS_XGXS0_LINK_STATUS \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
48 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
50 #define NIG_STATUS_SERDES0_LINK_STATUS \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
52 #define NIG_MASK_MI_INT \
53 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
54 #define NIG_MASK_XGXS0_LINK10G \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
56 #define NIG_MASK_XGXS0_LINK_STATUS \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
58 #define NIG_MASK_SERDES0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
61 #define MDIO_AN_CL73_OR_37_COMPLETE \
62 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
63 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
65 #define XGXS_RESET_BITS \
66 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
67 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
68 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
72 #define SERDES_RESET_BITS \
73 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
74 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
75 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
78 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
79 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
80 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
81 #define AUTONEG_PARALLEL \
82 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
83 #define AUTONEG_SGMII_FIBER_AUTODET \
84 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
85 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
87 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
88 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
89 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
91 #define GP_STATUS_SPEED_MASK \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
93 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
94 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
95 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
96 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
97 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
98 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
99 #define GP_STATUS_10G_HIG \
100 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
101 #define GP_STATUS_10G_CX4 \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
103 #define GP_STATUS_12G_HIG \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
105 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
106 #define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
107 #define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
108 #define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
109 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
110 #define GP_STATUS_10G_KX4 \
111 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
113 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
114 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
115 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
116 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
117 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
118 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
119 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
120 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
121 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
122 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
123 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
124 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
125 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
126 #define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
127 #define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
128 #define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
129 #define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
130 #define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
131 #define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
132 #define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
133 #define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
134 #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
135 #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
137 #define PHY_XGXS_FLAG 0x1
138 #define PHY_SGMII_FLAG 0x2
139 #define PHY_SERDES_FLAG 0x4
142 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
148 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
149 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
150 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
152 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
156 #define SFP_EEPROM_OPTIONS_ADDR 0x40
157 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
158 #define SFP_EEPROM_OPTIONS_SIZE 2
160 #define EDC_MODE_LINEAR 0x0022
161 #define EDC_MODE_LIMITING 0x0044
162 #define EDC_MODE_PASSIVE_DAC 0x0055
166 /**********************************************************/
168 /**********************************************************/
169 #define CL45_WR_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
170 bnx2x_cl45_write(_bp, _port, 0, _phy_addr, \
171 DEFAULT_PHY_DEV_ADDR, \
172 (_bank + (_addr & 0xf)), \
175 #define CL45_RD_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
176 bnx2x_cl45_read(_bp, _port, 0, _phy_addr, \
177 DEFAULT_PHY_DEV_ADDR, \
178 (_bank + (_addr & 0xf)), \
181 static void bnx2x_set_serdes_access(struct link_params
*params
)
183 struct bnx2x
*bp
= params
->bp
;
184 u32 emac_base
= (params
->port
) ? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
186 REG_WR(bp
, NIG_REG_SERDES0_CTRL_MD_ST
+ params
->port
*0x10, 1);
187 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_MDIO_COMM
, 0x245f8000);
189 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_MDIO_COMM
, 0x245d000f);
192 REG_WR(bp
, NIG_REG_SERDES0_CTRL_MD_ST
+ params
->port
*0x10, 0);
194 static void bnx2x_set_phy_mdio(struct link_params
*params
, u8 phy_flags
)
196 struct bnx2x
*bp
= params
->bp
;
197 if (phy_flags
& PHY_XGXS_FLAG
) {
198 REG_WR(bp
, NIG_REG_XGXS0_CTRL_MD_ST
+
199 params
->port
*0x18, 0);
200 REG_WR(bp
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ params
->port
*0x18,
201 DEFAULT_PHY_DEV_ADDR
);
203 bnx2x_set_serdes_access(params
);
205 REG_WR(bp
, NIG_REG_SERDES0_CTRL_MD_DEVAD
+
207 DEFAULT_PHY_DEV_ADDR
);
211 static u32
bnx2x_bits_en(struct bnx2x
*bp
, u32 reg
, u32 bits
)
213 u32 val
= REG_RD(bp
, reg
);
216 REG_WR(bp
, reg
, val
);
220 static u32
bnx2x_bits_dis(struct bnx2x
*bp
, u32 reg
, u32 bits
)
222 u32 val
= REG_RD(bp
, reg
);
225 REG_WR(bp
, reg
, val
);
229 static void bnx2x_emac_init(struct link_params
*params
,
230 struct link_vars
*vars
)
232 /* reset and unreset the emac core */
233 struct bnx2x
*bp
= params
->bp
;
234 u8 port
= params
->port
;
235 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
239 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
240 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
<< port
));
242 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
243 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
<< port
));
245 /* init emac - use read-modify-write */
246 /* self clear reset */
247 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_MODE
);
248 EMAC_WR(bp
, EMAC_REG_EMAC_MODE
, (val
| EMAC_MODE_RESET
));
252 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_MODE
);
253 DP(NETIF_MSG_LINK
, "EMAC reset reg is %u\n", val
);
255 DP(NETIF_MSG_LINK
, "EMAC timeout!\n");
259 } while (val
& EMAC_MODE_RESET
);
261 /* Set mac address */
262 val
= ((params
->mac_addr
[0] << 8) |
263 params
->mac_addr
[1]);
264 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
, val
);
266 val
= ((params
->mac_addr
[2] << 24) |
267 (params
->mac_addr
[3] << 16) |
268 (params
->mac_addr
[4] << 8) |
269 params
->mac_addr
[5]);
270 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ 4, val
);
273 static u8
bnx2x_emac_enable(struct link_params
*params
,
274 struct link_vars
*vars
, u8 lb
)
276 struct bnx2x
*bp
= params
->bp
;
277 u8 port
= params
->port
;
278 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
281 DP(NETIF_MSG_LINK
, "enabling EMAC\n");
283 /* enable emac and not bmac */
284 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_PORT
+ port
*4, 1);
287 if (CHIP_REV_IS_EMUL(bp
)) {
288 /* Use lane 1 (of lanes 0-3) */
289 REG_WR(bp
, NIG_REG_XGXS_LANE_SEL_P0
+ port
*4, 1);
290 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+
296 if (CHIP_REV_IS_FPGA(bp
)) {
297 /* Use lane 1 (of lanes 0-3) */
298 DP(NETIF_MSG_LINK
, "bnx2x_emac_enable: Setting FPGA\n");
300 REG_WR(bp
, NIG_REG_XGXS_LANE_SEL_P0
+ port
*4, 1);
301 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4,
305 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
306 u32 ser_lane
= ((params
->lane_config
&
307 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
308 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
310 DP(NETIF_MSG_LINK
, "XGXS\n");
311 /* select the master lanes (out of 0-3) */
312 REG_WR(bp
, NIG_REG_XGXS_LANE_SEL_P0
+
315 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+
318 } else { /* SerDes */
319 DP(NETIF_MSG_LINK
, "SerDes\n");
321 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+
325 bnx2x_bits_en(bp
, emac_base
+ EMAC_REG_EMAC_RX_MODE
,
327 bnx2x_bits_en(bp
, emac_base
+ EMAC_REG_EMAC_TX_MODE
,
330 if (CHIP_REV_IS_SLOW(bp
)) {
331 /* config GMII mode */
332 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_MODE
);
333 EMAC_WR(bp
, EMAC_REG_EMAC_MODE
,
334 (val
| EMAC_MODE_PORT_GMII
));
336 /* pause enable/disable */
337 bnx2x_bits_dis(bp
, emac_base
+ EMAC_REG_EMAC_RX_MODE
,
338 EMAC_RX_MODE_FLOW_EN
);
339 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_RX
)
340 bnx2x_bits_en(bp
, emac_base
+
341 EMAC_REG_EMAC_RX_MODE
,
342 EMAC_RX_MODE_FLOW_EN
);
344 bnx2x_bits_dis(bp
, emac_base
+ EMAC_REG_EMAC_TX_MODE
,
345 (EMAC_TX_MODE_EXT_PAUSE_EN
|
346 EMAC_TX_MODE_FLOW_EN
));
347 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
348 bnx2x_bits_en(bp
, emac_base
+
349 EMAC_REG_EMAC_TX_MODE
,
350 (EMAC_TX_MODE_EXT_PAUSE_EN
|
351 EMAC_TX_MODE_FLOW_EN
));
354 /* KEEP_VLAN_TAG, promiscuous */
355 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_RX_MODE
);
356 val
|= EMAC_RX_MODE_KEEP_VLAN_TAG
| EMAC_RX_MODE_PROMISCUOUS
;
357 EMAC_WR(bp
, EMAC_REG_EMAC_RX_MODE
, val
);
360 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_MODE
);
365 EMAC_WR(bp
, EMAC_REG_EMAC_MODE
, val
);
368 REG_WR(bp
, NIG_REG_NIG_EMAC0_EN
+ port
*4, 1);
370 /* enable emac for jumbo packets */
371 EMAC_WR(bp
, EMAC_REG_EMAC_RX_MTU_SIZE
,
372 (EMAC_RX_MTU_SIZE_JUMBO_ENA
|
373 (ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
)));
376 REG_WR(bp
, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC
+ port
*4, 0x1);
378 /* disable the NIG in/out to the bmac */
379 REG_WR(bp
, NIG_REG_BMAC0_IN_EN
+ port
*4, 0x0);
380 REG_WR(bp
, NIG_REG_BMAC0_PAUSE_OUT_EN
+ port
*4, 0x0);
381 REG_WR(bp
, NIG_REG_BMAC0_OUT_EN
+ port
*4, 0x0);
383 /* enable the NIG in/out to the emac */
384 REG_WR(bp
, NIG_REG_EMAC0_IN_EN
+ port
*4, 0x1);
386 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
389 REG_WR(bp
, NIG_REG_EMAC0_PAUSE_OUT_EN
+ port
*4, val
);
390 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
*4, 0x1);
392 if (CHIP_REV_IS_EMUL(bp
)) {
393 /* take the BigMac out of reset */
395 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
396 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
398 /* enable access for bmac registers */
399 REG_WR(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
*4, 0x1);
401 REG_WR(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
*4, 0x0);
403 vars
->mac_type
= MAC_TYPE_EMAC
;
409 static u8
bnx2x_bmac_enable(struct link_params
*params
, struct link_vars
*vars
,
412 struct bnx2x
*bp
= params
->bp
;
413 u8 port
= params
->port
;
414 u32 bmac_addr
= port
? NIG_REG_INGRESS_BMAC1_MEM
:
415 NIG_REG_INGRESS_BMAC0_MEM
;
419 DP(NETIF_MSG_LINK
, "Enabling BigMAC\n");
420 /* reset and unreset the BigMac */
421 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
422 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
425 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
426 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
428 /* enable access for bmac registers */
429 REG_WR(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
*4, 0x1);
434 REG_WR_DMAE(bp
, bmac_addr
+
435 BIGMAC_REGISTER_BMAC_XGXS_CONTROL
,
439 wb_data
[0] = ((params
->mac_addr
[2] << 24) |
440 (params
->mac_addr
[3] << 16) |
441 (params
->mac_addr
[4] << 8) |
442 params
->mac_addr
[5]);
443 wb_data
[1] = ((params
->mac_addr
[0] << 8) |
444 params
->mac_addr
[1]);
445 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_TX_SOURCE_ADDR
,
450 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
454 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_TX_CONTROL
,
461 DP(NETIF_MSG_LINK
, "enable bmac loopback\n");
465 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_BMAC_CONTROL
,
470 wb_data
[0] = ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
;
472 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_RX_MAX_SIZE
,
475 /* rx control set to don't strip crc */
477 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_RX
)
481 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_RX_CONTROL
,
485 wb_data
[0] = ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
;
487 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_TX_MAX_SIZE
,
490 /* set cnt max size */
491 wb_data
[0] = ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
;
493 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_CNT_MAX_SIZE
,
497 wb_data
[0] = 0x1000200;
499 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_RX_LLFC_MSG_FLDS
,
501 /* fix for emulation */
502 if (CHIP_REV_IS_EMUL(bp
)) {
506 bmac_addr
+ BIGMAC_REGISTER_TX_PAUSE_THRESHOLD
,
510 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 0x1);
511 REG_WR(bp
, NIG_REG_XGXS_LANE_SEL_P0
+ port
*4, 0x0);
512 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_PORT
+ port
*4, 0x0);
514 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
516 REG_WR(bp
, NIG_REG_BMAC0_PAUSE_OUT_EN
+ port
*4, val
);
517 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
*4, 0x0);
518 REG_WR(bp
, NIG_REG_EMAC0_IN_EN
+ port
*4, 0x0);
519 REG_WR(bp
, NIG_REG_EMAC0_PAUSE_OUT_EN
+ port
*4, 0x0);
520 REG_WR(bp
, NIG_REG_BMAC0_IN_EN
+ port
*4, 0x1);
521 REG_WR(bp
, NIG_REG_BMAC0_OUT_EN
+ port
*4, 0x1);
523 vars
->mac_type
= MAC_TYPE_BMAC
;
527 static void bnx2x_phy_deassert(struct link_params
*params
, u8 phy_flags
)
529 struct bnx2x
*bp
= params
->bp
;
532 if (phy_flags
& PHY_XGXS_FLAG
) {
533 DP(NETIF_MSG_LINK
, "bnx2x_phy_deassert:XGXS\n");
534 val
= XGXS_RESET_BITS
;
536 } else { /* SerDes */
537 DP(NETIF_MSG_LINK
, "bnx2x_phy_deassert:SerDes\n");
538 val
= SERDES_RESET_BITS
;
541 val
= val
<< (params
->port
*16);
543 /* reset and unreset the SerDes/XGXS */
544 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_CLEAR
,
547 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_SET
,
549 bnx2x_set_phy_mdio(params
, phy_flags
);
552 void bnx2x_link_status_update(struct link_params
*params
,
553 struct link_vars
*vars
)
555 struct bnx2x
*bp
= params
->bp
;
557 u8 port
= params
->port
;
559 if (params
->switch_cfg
== SWITCH_CFG_1G
)
560 vars
->phy_flags
= PHY_SERDES_FLAG
;
562 vars
->phy_flags
= PHY_XGXS_FLAG
;
563 vars
->link_status
= REG_RD(bp
, params
->shmem_base
+
564 offsetof(struct shmem_region
,
565 port_mb
[port
].link_status
));
567 vars
->link_up
= (vars
->link_status
& LINK_STATUS_LINK_UP
);
570 DP(NETIF_MSG_LINK
, "phy link up\n");
572 vars
->phy_link_up
= 1;
573 vars
->duplex
= DUPLEX_FULL
;
574 switch (vars
->link_status
&
575 LINK_STATUS_SPEED_AND_DUPLEX_MASK
) {
577 vars
->duplex
= DUPLEX_HALF
;
580 vars
->line_speed
= SPEED_10
;
584 vars
->duplex
= DUPLEX_HALF
;
588 vars
->line_speed
= SPEED_100
;
592 vars
->duplex
= DUPLEX_HALF
;
595 vars
->line_speed
= SPEED_1000
;
599 vars
->duplex
= DUPLEX_HALF
;
602 vars
->line_speed
= SPEED_2500
;
606 vars
->line_speed
= SPEED_10000
;
610 vars
->line_speed
= SPEED_12000
;
614 vars
->line_speed
= SPEED_12500
;
618 vars
->line_speed
= SPEED_13000
;
622 vars
->line_speed
= SPEED_15000
;
626 vars
->line_speed
= SPEED_16000
;
633 if (vars
->link_status
& LINK_STATUS_TX_FLOW_CONTROL_ENABLED
)
634 vars
->flow_ctrl
|= BNX2X_FLOW_CTRL_TX
;
636 vars
->flow_ctrl
&= ~BNX2X_FLOW_CTRL_TX
;
638 if (vars
->link_status
& LINK_STATUS_RX_FLOW_CONTROL_ENABLED
)
639 vars
->flow_ctrl
|= BNX2X_FLOW_CTRL_RX
;
641 vars
->flow_ctrl
&= ~BNX2X_FLOW_CTRL_RX
;
643 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
644 if (vars
->line_speed
&&
645 ((vars
->line_speed
== SPEED_10
) ||
646 (vars
->line_speed
== SPEED_100
))) {
647 vars
->phy_flags
|= PHY_SGMII_FLAG
;
649 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
653 /* anything 10 and over uses the bmac */
654 link_10g
= ((vars
->line_speed
== SPEED_10000
) ||
655 (vars
->line_speed
== SPEED_12000
) ||
656 (vars
->line_speed
== SPEED_12500
) ||
657 (vars
->line_speed
== SPEED_13000
) ||
658 (vars
->line_speed
== SPEED_15000
) ||
659 (vars
->line_speed
== SPEED_16000
));
661 vars
->mac_type
= MAC_TYPE_BMAC
;
663 vars
->mac_type
= MAC_TYPE_EMAC
;
665 } else { /* link down */
666 DP(NETIF_MSG_LINK
, "phy link down\n");
668 vars
->phy_link_up
= 0;
670 vars
->line_speed
= 0;
671 vars
->duplex
= DUPLEX_FULL
;
672 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
674 /* indicate no mac active */
675 vars
->mac_type
= MAC_TYPE_NONE
;
678 DP(NETIF_MSG_LINK
, "link_status 0x%x phy_link_up %x\n",
679 vars
->link_status
, vars
->phy_link_up
);
680 DP(NETIF_MSG_LINK
, "line_speed %x duplex %x flow_ctrl 0x%x\n",
681 vars
->line_speed
, vars
->duplex
, vars
->flow_ctrl
);
684 static void bnx2x_update_mng(struct link_params
*params
, u32 link_status
)
686 struct bnx2x
*bp
= params
->bp
;
687 REG_WR(bp
, params
->shmem_base
+
688 offsetof(struct shmem_region
,
689 port_mb
[params
->port
].link_status
),
693 static void bnx2x_bmac_rx_disable(struct bnx2x
*bp
, u8 port
)
695 u32 bmac_addr
= port
? NIG_REG_INGRESS_BMAC1_MEM
:
696 NIG_REG_INGRESS_BMAC0_MEM
;
698 u32 nig_bmac_enable
= REG_RD(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
*4);
700 /* Only if the bmac is out of reset */
701 if (REG_RD(bp
, MISC_REG_RESET_REG_2
) &
702 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
) &&
705 /* Clear Rx Enable bit in BMAC_CONTROL register */
706 REG_RD_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_BMAC_CONTROL
,
708 wb_data
[0] &= ~BMAC_CONTROL_RX_ENABLE
;
709 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_BMAC_CONTROL
,
716 static u8
bnx2x_pbf_update(struct link_params
*params
, u32 flow_ctrl
,
719 struct bnx2x
*bp
= params
->bp
;
720 u8 port
= params
->port
;
725 REG_WR(bp
, PBF_REG_DISABLE_NEW_TASK_PROC_P0
+ port
*4, 0x1);
727 /* wait for init credit */
728 init_crd
= REG_RD(bp
, PBF_REG_P0_INIT_CRD
+ port
*4);
729 crd
= REG_RD(bp
, PBF_REG_P0_CREDIT
+ port
*8);
730 DP(NETIF_MSG_LINK
, "init_crd 0x%x crd 0x%x\n", init_crd
, crd
);
732 while ((init_crd
!= crd
) && count
) {
735 crd
= REG_RD(bp
, PBF_REG_P0_CREDIT
+ port
*8);
738 crd
= REG_RD(bp
, PBF_REG_P0_CREDIT
+ port
*8);
739 if (init_crd
!= crd
) {
740 DP(NETIF_MSG_LINK
, "BUG! init_crd 0x%x != crd 0x%x\n",
745 if (flow_ctrl
& BNX2X_FLOW_CTRL_RX
||
746 line_speed
== SPEED_10
||
747 line_speed
== SPEED_100
||
748 line_speed
== SPEED_1000
||
749 line_speed
== SPEED_2500
) {
750 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 1);
751 /* update threshold */
752 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, 0);
753 /* update init credit */
754 init_crd
= 778; /* (800-18-4) */
757 u32 thresh
= (ETH_MAX_JUMBO_PACKET_SIZE
+
759 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 0);
760 /* update threshold */
761 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, thresh
);
762 /* update init credit */
763 switch (line_speed
) {
765 init_crd
= thresh
+ 553 - 22;
769 init_crd
= thresh
+ 664 - 22;
773 init_crd
= thresh
+ 742 - 22;
777 init_crd
= thresh
+ 778 - 22;
780 DP(NETIF_MSG_LINK
, "Invalid line_speed 0x%x\n",
786 REG_WR(bp
, PBF_REG_P0_INIT_CRD
+ port
*4, init_crd
);
787 DP(NETIF_MSG_LINK
, "PBF updated to speed %d credit %d\n",
788 line_speed
, init_crd
);
790 /* probe the credit changes */
791 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0x1);
793 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0x0);
796 REG_WR(bp
, PBF_REG_DISABLE_NEW_TASK_PROC_P0
+ port
*4, 0x0);
800 static u32
bnx2x_get_emac_base(struct bnx2x
*bp
, u32 ext_phy_type
, u8 port
)
803 switch (ext_phy_type
) {
804 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
805 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
806 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
807 /* All MDC/MDIO is directed through single EMAC */
808 if (REG_RD(bp
, NIG_REG_PORT_SWAP
))
809 emac_base
= GRCBASE_EMAC0
;
811 emac_base
= GRCBASE_EMAC1
;
813 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
814 emac_base
= (port
) ? GRCBASE_EMAC0
: GRCBASE_EMAC1
;
817 emac_base
= (port
) ? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
824 u8
bnx2x_cl45_write(struct bnx2x
*bp
, u8 port
, u32 ext_phy_type
,
825 u8 phy_addr
, u8 devad
, u16 reg
, u16 val
)
829 u32 mdio_ctrl
= bnx2x_get_emac_base(bp
, ext_phy_type
, port
);
831 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
832 * (a value of 49==0x31) and make sure that the AUTO poll is off
835 saved_mode
= REG_RD(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
836 tmp
= saved_mode
& ~(EMAC_MDIO_MODE_AUTO_POLL
|
837 EMAC_MDIO_MODE_CLOCK_CNT
);
838 tmp
|= (EMAC_MDIO_MODE_CLAUSE_45
|
839 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT
));
840 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, tmp
);
841 REG_RD(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
846 tmp
= ((phy_addr
<< 21) | (devad
<< 16) | reg
|
847 EMAC_MDIO_COMM_COMMAND_ADDRESS
|
848 EMAC_MDIO_COMM_START_BUSY
);
849 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, tmp
);
851 for (i
= 0; i
< 50; i
++) {
854 tmp
= REG_RD(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
855 if (!(tmp
& EMAC_MDIO_COMM_START_BUSY
)) {
860 if (tmp
& EMAC_MDIO_COMM_START_BUSY
) {
861 DP(NETIF_MSG_LINK
, "write phy register failed\n");
865 tmp
= ((phy_addr
<< 21) | (devad
<< 16) | val
|
866 EMAC_MDIO_COMM_COMMAND_WRITE_45
|
867 EMAC_MDIO_COMM_START_BUSY
);
868 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, tmp
);
870 for (i
= 0; i
< 50; i
++) {
873 tmp
= REG_RD(bp
, mdio_ctrl
+
874 EMAC_REG_EMAC_MDIO_COMM
);
875 if (!(tmp
& EMAC_MDIO_COMM_START_BUSY
)) {
880 if (tmp
& EMAC_MDIO_COMM_START_BUSY
) {
881 DP(NETIF_MSG_LINK
, "write phy register failed\n");
886 /* Restore the saved mode */
887 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, saved_mode
);
892 u8
bnx2x_cl45_read(struct bnx2x
*bp
, u8 port
, u32 ext_phy_type
,
893 u8 phy_addr
, u8 devad
, u16 reg
, u16
*ret_val
)
899 u32 mdio_ctrl
= bnx2x_get_emac_base(bp
, ext_phy_type
, port
);
900 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
901 * (a value of 49==0x31) and make sure that the AUTO poll is off
904 saved_mode
= REG_RD(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
905 val
= saved_mode
& ((EMAC_MDIO_MODE_AUTO_POLL
|
906 EMAC_MDIO_MODE_CLOCK_CNT
));
907 val
|= (EMAC_MDIO_MODE_CLAUSE_45
|
908 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT
));
909 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, val
);
910 REG_RD(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
914 val
= ((phy_addr
<< 21) | (devad
<< 16) | reg
|
915 EMAC_MDIO_COMM_COMMAND_ADDRESS
|
916 EMAC_MDIO_COMM_START_BUSY
);
917 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, val
);
919 for (i
= 0; i
< 50; i
++) {
922 val
= REG_RD(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
923 if (!(val
& EMAC_MDIO_COMM_START_BUSY
)) {
928 if (val
& EMAC_MDIO_COMM_START_BUSY
) {
929 DP(NETIF_MSG_LINK
, "read phy register failed\n");
936 val
= ((phy_addr
<< 21) | (devad
<< 16) |
937 EMAC_MDIO_COMM_COMMAND_READ_45
|
938 EMAC_MDIO_COMM_START_BUSY
);
939 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, val
);
941 for (i
= 0; i
< 50; i
++) {
944 val
= REG_RD(bp
, mdio_ctrl
+
945 EMAC_REG_EMAC_MDIO_COMM
);
946 if (!(val
& EMAC_MDIO_COMM_START_BUSY
)) {
947 *ret_val
= (u16
)(val
& EMAC_MDIO_COMM_DATA
);
951 if (val
& EMAC_MDIO_COMM_START_BUSY
) {
952 DP(NETIF_MSG_LINK
, "read phy register failed\n");
959 /* Restore the saved mode */
960 REG_WR(bp
, mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, saved_mode
);
965 static void bnx2x_set_aer_mmd(struct link_params
*params
,
966 struct link_vars
*vars
)
968 struct bnx2x
*bp
= params
->bp
;
972 ser_lane
= ((params
->lane_config
&
973 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
974 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
976 offset
= (vars
->phy_flags
& PHY_XGXS_FLAG
) ?
977 (params
->phy_addr
+ ser_lane
) : 0;
979 CL45_WR_OVER_CL22(bp
, params
->port
,
981 MDIO_REG_BANK_AER_BLOCK
,
982 MDIO_AER_BLOCK_AER_REG
, 0x3800 + offset
);
985 static void bnx2x_set_master_ln(struct link_params
*params
)
987 struct bnx2x
*bp
= params
->bp
;
988 u16 new_master_ln
, ser_lane
;
989 ser_lane
= ((params
->lane_config
&
990 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
991 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
993 /* set the master_ln for AN */
994 CL45_RD_OVER_CL22(bp
, params
->port
,
996 MDIO_REG_BANK_XGXS_BLOCK2
,
997 MDIO_XGXS_BLOCK2_TEST_MODE_LANE
,
1000 CL45_WR_OVER_CL22(bp
, params
->port
,
1002 MDIO_REG_BANK_XGXS_BLOCK2
,
1003 MDIO_XGXS_BLOCK2_TEST_MODE_LANE
,
1004 (new_master_ln
| ser_lane
));
1007 static u8
bnx2x_reset_unicore(struct link_params
*params
)
1009 struct bnx2x
*bp
= params
->bp
;
1013 CL45_RD_OVER_CL22(bp
, params
->port
,
1015 MDIO_REG_BANK_COMBO_IEEE0
,
1016 MDIO_COMBO_IEEE0_MII_CONTROL
, &mii_control
);
1018 /* reset the unicore */
1019 CL45_WR_OVER_CL22(bp
, params
->port
,
1021 MDIO_REG_BANK_COMBO_IEEE0
,
1022 MDIO_COMBO_IEEE0_MII_CONTROL
,
1024 MDIO_COMBO_IEEO_MII_CONTROL_RESET
));
1025 if (params
->switch_cfg
== SWITCH_CFG_1G
)
1026 bnx2x_set_serdes_access(params
);
1028 /* wait for the reset to self clear */
1029 for (i
= 0; i
< MDIO_ACCESS_TIMEOUT
; i
++) {
1032 /* the reset erased the previous bank value */
1033 CL45_RD_OVER_CL22(bp
, params
->port
,
1035 MDIO_REG_BANK_COMBO_IEEE0
,
1036 MDIO_COMBO_IEEE0_MII_CONTROL
,
1039 if (!(mii_control
& MDIO_COMBO_IEEO_MII_CONTROL_RESET
)) {
1045 DP(NETIF_MSG_LINK
, "BUG! XGXS is still in reset!\n");
1050 static void bnx2x_set_swap_lanes(struct link_params
*params
)
1052 struct bnx2x
*bp
= params
->bp
;
1053 /* Each two bits represents a lane number:
1054 No swap is 0123 => 0x1b no need to enable the swap */
1055 u16 ser_lane
, rx_lane_swap
, tx_lane_swap
;
1057 ser_lane
= ((params
->lane_config
&
1058 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
1059 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
1060 rx_lane_swap
= ((params
->lane_config
&
1061 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK
) >>
1062 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT
);
1063 tx_lane_swap
= ((params
->lane_config
&
1064 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK
) >>
1065 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT
);
1067 if (rx_lane_swap
!= 0x1b) {
1068 CL45_WR_OVER_CL22(bp
, params
->port
,
1070 MDIO_REG_BANK_XGXS_BLOCK2
,
1071 MDIO_XGXS_BLOCK2_RX_LN_SWAP
,
1073 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE
|
1074 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE
));
1076 CL45_WR_OVER_CL22(bp
, params
->port
,
1078 MDIO_REG_BANK_XGXS_BLOCK2
,
1079 MDIO_XGXS_BLOCK2_RX_LN_SWAP
, 0);
1082 if (tx_lane_swap
!= 0x1b) {
1083 CL45_WR_OVER_CL22(bp
, params
->port
,
1085 MDIO_REG_BANK_XGXS_BLOCK2
,
1086 MDIO_XGXS_BLOCK2_TX_LN_SWAP
,
1088 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE
));
1090 CL45_WR_OVER_CL22(bp
, params
->port
,
1092 MDIO_REG_BANK_XGXS_BLOCK2
,
1093 MDIO_XGXS_BLOCK2_TX_LN_SWAP
, 0);
1097 static void bnx2x_set_parallel_detection(struct link_params
*params
,
1100 struct bnx2x
*bp
= params
->bp
;
1103 CL45_RD_OVER_CL22(bp
, params
->port
,
1105 MDIO_REG_BANK_SERDES_DIGITAL
,
1106 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2
,
1110 control2
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN
;
1113 CL45_WR_OVER_CL22(bp
, params
->port
,
1115 MDIO_REG_BANK_SERDES_DIGITAL
,
1116 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2
,
1119 if (phy_flags
& PHY_XGXS_FLAG
) {
1120 DP(NETIF_MSG_LINK
, "XGXS\n");
1122 CL45_WR_OVER_CL22(bp
, params
->port
,
1124 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
1125 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK
,
1126 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT
);
1128 CL45_RD_OVER_CL22(bp
, params
->port
,
1130 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
1131 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL
,
1136 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN
;
1138 CL45_WR_OVER_CL22(bp
, params
->port
,
1140 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
1141 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL
,
1144 /* Disable parallel detection of HiG */
1145 CL45_WR_OVER_CL22(bp
, params
->port
,
1147 MDIO_REG_BANK_XGXS_BLOCK2
,
1148 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G
,
1149 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS
|
1150 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS
);
1154 static void bnx2x_set_autoneg(struct link_params
*params
,
1155 struct link_vars
*vars
,
1158 struct bnx2x
*bp
= params
->bp
;
1163 CL45_RD_OVER_CL22(bp
, params
->port
,
1165 MDIO_REG_BANK_COMBO_IEEE0
,
1166 MDIO_COMBO_IEEE0_MII_CONTROL
, ®_val
);
1168 /* CL37 Autoneg Enabled */
1169 if (vars
->line_speed
== SPEED_AUTO_NEG
)
1170 reg_val
|= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
;
1171 else /* CL37 Autoneg Disabled */
1172 reg_val
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
1173 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN
);
1175 CL45_WR_OVER_CL22(bp
, params
->port
,
1177 MDIO_REG_BANK_COMBO_IEEE0
,
1178 MDIO_COMBO_IEEE0_MII_CONTROL
, reg_val
);
1180 /* Enable/Disable Autodetection */
1182 CL45_RD_OVER_CL22(bp
, params
->port
,
1184 MDIO_REG_BANK_SERDES_DIGITAL
,
1185 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, ®_val
);
1186 reg_val
&= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN
|
1187 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT
);
1188 reg_val
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE
;
1189 if (vars
->line_speed
== SPEED_AUTO_NEG
)
1190 reg_val
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
;
1192 reg_val
&= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
;
1194 CL45_WR_OVER_CL22(bp
, params
->port
,
1196 MDIO_REG_BANK_SERDES_DIGITAL
,
1197 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, reg_val
);
1199 /* Enable TetonII and BAM autoneg */
1200 CL45_RD_OVER_CL22(bp
, params
->port
,
1202 MDIO_REG_BANK_BAM_NEXT_PAGE
,
1203 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL
,
1205 if (vars
->line_speed
== SPEED_AUTO_NEG
) {
1206 /* Enable BAM aneg Mode and TetonII aneg Mode */
1207 reg_val
|= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE
|
1208 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN
);
1210 /* TetonII and BAM Autoneg Disabled */
1211 reg_val
&= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE
|
1212 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN
);
1214 CL45_WR_OVER_CL22(bp
, params
->port
,
1216 MDIO_REG_BANK_BAM_NEXT_PAGE
,
1217 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL
,
1221 /* Enable Cl73 FSM status bits */
1222 CL45_WR_OVER_CL22(bp
, params
->port
,
1224 MDIO_REG_BANK_CL73_USERB0
,
1225 MDIO_CL73_USERB0_CL73_UCTRL
,
1226 MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL
);
1228 /* Enable BAM Station Manager*/
1229 CL45_WR_OVER_CL22(bp
, params
->port
,
1231 MDIO_REG_BANK_CL73_USERB0
,
1232 MDIO_CL73_USERB0_CL73_BAM_CTRL1
,
1233 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN
|
1234 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN
|
1235 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN
);
1237 /* Merge CL73 and CL37 aneg resolution */
1238 CL45_RD_OVER_CL22(bp
, params
->port
,
1240 MDIO_REG_BANK_CL73_USERB0
,
1241 MDIO_CL73_USERB0_CL73_BAM_CTRL3
,
1244 if (params
->speed_cap_mask
&
1245 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
) {
1246 /* Set the CL73 AN speed */
1247 CL45_RD_OVER_CL22(bp
, params
->port
,
1249 MDIO_REG_BANK_CL73_IEEEB1
,
1250 MDIO_CL73_IEEEB1_AN_ADV2
,
1253 CL45_WR_OVER_CL22(bp
, params
->port
,
1255 MDIO_REG_BANK_CL73_IEEEB1
,
1256 MDIO_CL73_IEEEB1_AN_ADV2
,
1257 reg_val
| MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4
);
1260 /* CL73 Autoneg Enabled */
1261 reg_val
= MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
;
1263 } else /* CL73 Autoneg Disabled */
1266 CL45_WR_OVER_CL22(bp
, params
->port
,
1268 MDIO_REG_BANK_CL73_IEEEB0
,
1269 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
, reg_val
);
1272 /* program SerDes, forced speed */
1273 static void bnx2x_program_serdes(struct link_params
*params
,
1274 struct link_vars
*vars
)
1276 struct bnx2x
*bp
= params
->bp
;
1279 /* program duplex, disable autoneg and sgmii*/
1280 CL45_RD_OVER_CL22(bp
, params
->port
,
1282 MDIO_REG_BANK_COMBO_IEEE0
,
1283 MDIO_COMBO_IEEE0_MII_CONTROL
, ®_val
);
1284 reg_val
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
|
1285 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
1286 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK
);
1287 if (params
->req_duplex
== DUPLEX_FULL
)
1288 reg_val
|= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
;
1289 CL45_WR_OVER_CL22(bp
, params
->port
,
1291 MDIO_REG_BANK_COMBO_IEEE0
,
1292 MDIO_COMBO_IEEE0_MII_CONTROL
, reg_val
);
1295 - needed only if the speed is greater than 1G (2.5G or 10G) */
1296 CL45_RD_OVER_CL22(bp
, params
->port
,
1298 MDIO_REG_BANK_SERDES_DIGITAL
,
1299 MDIO_SERDES_DIGITAL_MISC1
, ®_val
);
1300 /* clearing the speed value before setting the right speed */
1301 DP(NETIF_MSG_LINK
, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val
);
1303 reg_val
&= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK
|
1304 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL
);
1306 if (!((vars
->line_speed
== SPEED_1000
) ||
1307 (vars
->line_speed
== SPEED_100
) ||
1308 (vars
->line_speed
== SPEED_10
))) {
1310 reg_val
|= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M
|
1311 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL
);
1312 if (vars
->line_speed
== SPEED_10000
)
1314 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4
;
1315 if (vars
->line_speed
== SPEED_13000
)
1317 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G
;
1320 CL45_WR_OVER_CL22(bp
, params
->port
,
1322 MDIO_REG_BANK_SERDES_DIGITAL
,
1323 MDIO_SERDES_DIGITAL_MISC1
, reg_val
);
1327 static void bnx2x_set_brcm_cl37_advertisment(struct link_params
*params
)
1329 struct bnx2x
*bp
= params
->bp
;
1332 /* configure the 48 bits for BAM AN */
1334 /* set extended capabilities */
1335 if (params
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
)
1336 val
|= MDIO_OVER_1G_UP1_2_5G
;
1337 if (params
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
1338 val
|= MDIO_OVER_1G_UP1_10G
;
1339 CL45_WR_OVER_CL22(bp
, params
->port
,
1341 MDIO_REG_BANK_OVER_1G
,
1342 MDIO_OVER_1G_UP1
, val
);
1344 CL45_WR_OVER_CL22(bp
, params
->port
,
1346 MDIO_REG_BANK_OVER_1G
,
1347 MDIO_OVER_1G_UP3
, 0x400);
1350 static void bnx2x_calc_ieee_aneg_adv(struct link_params
*params
, u16
*ieee_fc
)
1352 *ieee_fc
= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX
;
1353 /* resolve pause mode and advertisement
1354 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1356 switch (params
->req_flow_ctrl
) {
1357 case BNX2X_FLOW_CTRL_AUTO
:
1358 if (params
->req_fc_auto_adv
== BNX2X_FLOW_CTRL_BOTH
) {
1360 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
1363 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
1366 case BNX2X_FLOW_CTRL_TX
:
1368 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
1371 case BNX2X_FLOW_CTRL_RX
:
1372 case BNX2X_FLOW_CTRL_BOTH
:
1373 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
1376 case BNX2X_FLOW_CTRL_NONE
:
1378 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE
;
1383 static void bnx2x_set_ieee_aneg_advertisment(struct link_params
*params
,
1386 struct bnx2x
*bp
= params
->bp
;
1387 /* for AN, we are always publishing full duplex */
1389 CL45_WR_OVER_CL22(bp
, params
->port
,
1391 MDIO_REG_BANK_COMBO_IEEE0
,
1392 MDIO_COMBO_IEEE0_AUTO_NEG_ADV
, ieee_fc
);
1395 static void bnx2x_restart_autoneg(struct link_params
*params
, u8 enable_cl73
)
1397 struct bnx2x
*bp
= params
->bp
;
1400 DP(NETIF_MSG_LINK
, "bnx2x_restart_autoneg\n");
1401 /* Enable and restart BAM/CL37 aneg */
1404 CL45_RD_OVER_CL22(bp
, params
->port
,
1406 MDIO_REG_BANK_CL73_IEEEB0
,
1407 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
1410 CL45_WR_OVER_CL22(bp
, params
->port
,
1412 MDIO_REG_BANK_CL73_IEEEB0
,
1413 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
1415 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
|
1416 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN
));
1419 CL45_RD_OVER_CL22(bp
, params
->port
,
1421 MDIO_REG_BANK_COMBO_IEEE0
,
1422 MDIO_COMBO_IEEE0_MII_CONTROL
,
1425 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1427 CL45_WR_OVER_CL22(bp
, params
->port
,
1429 MDIO_REG_BANK_COMBO_IEEE0
,
1430 MDIO_COMBO_IEEE0_MII_CONTROL
,
1432 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
1433 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN
));
1437 static void bnx2x_initialize_sgmii_process(struct link_params
*params
,
1438 struct link_vars
*vars
)
1440 struct bnx2x
*bp
= params
->bp
;
1443 /* in SGMII mode, the unicore is always slave */
1445 CL45_RD_OVER_CL22(bp
, params
->port
,
1447 MDIO_REG_BANK_SERDES_DIGITAL
,
1448 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
,
1450 control1
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT
;
1451 /* set sgmii mode (and not fiber) */
1452 control1
&= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE
|
1453 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
|
1454 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE
);
1455 CL45_WR_OVER_CL22(bp
, params
->port
,
1457 MDIO_REG_BANK_SERDES_DIGITAL
,
1458 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
,
1461 /* if forced speed */
1462 if (!(vars
->line_speed
== SPEED_AUTO_NEG
)) {
1463 /* set speed, disable autoneg */
1466 CL45_RD_OVER_CL22(bp
, params
->port
,
1468 MDIO_REG_BANK_COMBO_IEEE0
,
1469 MDIO_COMBO_IEEE0_MII_CONTROL
,
1471 mii_control
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
1472 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK
|
1473 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
);
1475 switch (vars
->line_speed
) {
1478 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100
;
1482 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000
;
1485 /* there is nothing to set for 10M */
1488 /* invalid speed for SGMII */
1489 DP(NETIF_MSG_LINK
, "Invalid line_speed 0x%x\n",
1494 /* setting the full duplex */
1495 if (params
->req_duplex
== DUPLEX_FULL
)
1497 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
;
1498 CL45_WR_OVER_CL22(bp
, params
->port
,
1500 MDIO_REG_BANK_COMBO_IEEE0
,
1501 MDIO_COMBO_IEEE0_MII_CONTROL
,
1504 } else { /* AN mode */
1505 /* enable and restart AN */
1506 bnx2x_restart_autoneg(params
, 0);
1515 static void bnx2x_pause_resolve(struct link_vars
*vars
, u32 pause_result
)
1517 switch (pause_result
) { /* ASYM P ASYM P */
1518 case 0xb: /* 1 0 1 1 */
1519 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_TX
;
1522 case 0xe: /* 1 1 1 0 */
1523 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_RX
;
1526 case 0x5: /* 0 1 0 1 */
1527 case 0x7: /* 0 1 1 1 */
1528 case 0xd: /* 1 1 0 1 */
1529 case 0xf: /* 1 1 1 1 */
1530 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_BOTH
;
1538 static u8
bnx2x_ext_phy_resove_fc(struct link_params
*params
,
1539 struct link_vars
*vars
)
1541 struct bnx2x
*bp
= params
->bp
;
1543 u16 ld_pause
; /* local */
1544 u16 lp_pause
; /* link partner */
1545 u16 an_complete
; /* AN complete */
1549 u8 port
= params
->port
;
1550 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
1551 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
1554 bnx2x_cl45_read(bp
, port
,
1558 MDIO_AN_REG_STATUS
, &an_complete
);
1559 bnx2x_cl45_read(bp
, port
,
1563 MDIO_AN_REG_STATUS
, &an_complete
);
1565 if (an_complete
& MDIO_AN_REG_STATUS_AN_COMPLETE
) {
1567 bnx2x_cl45_read(bp
, port
,
1571 MDIO_AN_REG_ADV_PAUSE
, &ld_pause
);
1572 bnx2x_cl45_read(bp
, port
,
1576 MDIO_AN_REG_LP_AUTO_NEG
, &lp_pause
);
1577 pause_result
= (ld_pause
&
1578 MDIO_AN_REG_ADV_PAUSE_MASK
) >> 8;
1579 pause_result
|= (lp_pause
&
1580 MDIO_AN_REG_ADV_PAUSE_MASK
) >> 10;
1581 DP(NETIF_MSG_LINK
, "Ext PHY pause result 0x%x \n",
1583 bnx2x_pause_resolve(vars
, pause_result
);
1584 if (vars
->flow_ctrl
== BNX2X_FLOW_CTRL_NONE
&&
1585 ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
) {
1586 bnx2x_cl45_read(bp
, port
,
1590 MDIO_AN_REG_CL37_FC_LD
, &ld_pause
);
1592 bnx2x_cl45_read(bp
, port
,
1596 MDIO_AN_REG_CL37_FC_LP
, &lp_pause
);
1597 pause_result
= (ld_pause
&
1598 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) >> 5;
1599 pause_result
|= (lp_pause
&
1600 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) >> 7;
1602 bnx2x_pause_resolve(vars
, pause_result
);
1603 DP(NETIF_MSG_LINK
, "Ext PHY CL37 pause result 0x%x \n",
1611 static void bnx2x_flow_ctrl_resolve(struct link_params
*params
,
1612 struct link_vars
*vars
,
1615 struct bnx2x
*bp
= params
->bp
;
1616 u16 ld_pause
; /* local driver */
1617 u16 lp_pause
; /* link partner */
1620 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
1622 /* resolve from gp_status in case of AN complete and not sgmii */
1623 if ((params
->req_flow_ctrl
== BNX2X_FLOW_CTRL_AUTO
) &&
1624 (gp_status
& MDIO_AN_CL73_OR_37_COMPLETE
) &&
1625 (!(vars
->phy_flags
& PHY_SGMII_FLAG
)) &&
1626 (XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
1627 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)) {
1628 CL45_RD_OVER_CL22(bp
, params
->port
,
1630 MDIO_REG_BANK_COMBO_IEEE0
,
1631 MDIO_COMBO_IEEE0_AUTO_NEG_ADV
,
1633 CL45_RD_OVER_CL22(bp
, params
->port
,
1635 MDIO_REG_BANK_COMBO_IEEE0
,
1636 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1
,
1638 pause_result
= (ld_pause
&
1639 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
)>>5;
1640 pause_result
|= (lp_pause
&
1641 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
)>>7;
1642 DP(NETIF_MSG_LINK
, "pause_result 0x%x\n", pause_result
);
1643 bnx2x_pause_resolve(vars
, pause_result
);
1644 } else if ((params
->req_flow_ctrl
== BNX2X_FLOW_CTRL_AUTO
) &&
1645 (bnx2x_ext_phy_resove_fc(params
, vars
))) {
1648 if (params
->req_flow_ctrl
== BNX2X_FLOW_CTRL_AUTO
)
1649 vars
->flow_ctrl
= params
->req_fc_auto_adv
;
1651 vars
->flow_ctrl
= params
->req_flow_ctrl
;
1653 DP(NETIF_MSG_LINK
, "flow_ctrl 0x%x\n", vars
->flow_ctrl
);
1656 static void bnx2x_check_fallback_to_cl37(struct link_params
*params
)
1658 struct bnx2x
*bp
= params
->bp
;
1659 u16 rx_status
, ustat_val
, cl37_fsm_recieved
;
1660 DP(NETIF_MSG_LINK
, "bnx2x_check_fallback_to_cl37\n");
1661 /* Step 1: Make sure signal is detected */
1662 CL45_RD_OVER_CL22(bp
, params
->port
,
1667 if ((rx_status
& MDIO_RX0_RX_STATUS_SIGDET
) !=
1668 (MDIO_RX0_RX_STATUS_SIGDET
)) {
1669 DP(NETIF_MSG_LINK
, "Signal is not detected. Restoring CL73."
1670 "rx_status(0x80b0) = 0x%x\n", rx_status
);
1671 CL45_WR_OVER_CL22(bp
, params
->port
,
1673 MDIO_REG_BANK_CL73_IEEEB0
,
1674 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
1675 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
);
1678 /* Step 2: Check CL73 state machine */
1679 CL45_RD_OVER_CL22(bp
, params
->port
,
1681 MDIO_REG_BANK_CL73_USERB0
,
1682 MDIO_CL73_USERB0_CL73_USTAT1
,
1685 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK
|
1686 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37
)) !=
1687 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK
|
1688 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37
)) {
1689 DP(NETIF_MSG_LINK
, "CL73 state-machine is not stable. "
1690 "ustat_val(0x8371) = 0x%x\n", ustat_val
);
1693 /* Step 3: Check CL37 Message Pages received to indicate LP
1694 supports only CL37 */
1695 CL45_RD_OVER_CL22(bp
, params
->port
,
1697 MDIO_REG_BANK_REMOTE_PHY
,
1698 MDIO_REMOTE_PHY_MISC_RX_STATUS
,
1699 &cl37_fsm_recieved
);
1700 if ((cl37_fsm_recieved
&
1701 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG
|
1702 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG
)) !=
1703 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG
|
1704 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG
)) {
1705 DP(NETIF_MSG_LINK
, "No CL37 FSM were received. "
1706 "misc_rx_status(0x8330) = 0x%x\n",
1710 /* The combined cl37/cl73 fsm state information indicating that we are
1711 connected to a device which does not support cl73, but does support
1712 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
1714 CL45_WR_OVER_CL22(bp
, params
->port
,
1716 MDIO_REG_BANK_CL73_IEEEB0
,
1717 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
1719 /* Restart CL37 autoneg */
1720 bnx2x_restart_autoneg(params
, 0);
1721 DP(NETIF_MSG_LINK
, "Disabling CL73, and restarting CL37 autoneg\n");
1723 static u8
bnx2x_link_settings_status(struct link_params
*params
,
1724 struct link_vars
*vars
,
1728 struct bnx2x
*bp
= params
->bp
;
1731 vars
->link_status
= 0;
1733 if (gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS
) {
1734 DP(NETIF_MSG_LINK
, "phy link up gp_status=0x%x\n",
1737 vars
->phy_link_up
= 1;
1738 vars
->link_status
|= LINK_STATUS_LINK_UP
;
1740 if (gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS
)
1741 vars
->duplex
= DUPLEX_FULL
;
1743 vars
->duplex
= DUPLEX_HALF
;
1745 bnx2x_flow_ctrl_resolve(params
, vars
, gp_status
);
1747 switch (gp_status
& GP_STATUS_SPEED_MASK
) {
1749 new_line_speed
= SPEED_10
;
1750 if (vars
->duplex
== DUPLEX_FULL
)
1751 vars
->link_status
|= LINK_10TFD
;
1753 vars
->link_status
|= LINK_10THD
;
1756 case GP_STATUS_100M
:
1757 new_line_speed
= SPEED_100
;
1758 if (vars
->duplex
== DUPLEX_FULL
)
1759 vars
->link_status
|= LINK_100TXFD
;
1761 vars
->link_status
|= LINK_100TXHD
;
1765 case GP_STATUS_1G_KX
:
1766 new_line_speed
= SPEED_1000
;
1767 if (vars
->duplex
== DUPLEX_FULL
)
1768 vars
->link_status
|= LINK_1000TFD
;
1770 vars
->link_status
|= LINK_1000THD
;
1773 case GP_STATUS_2_5G
:
1774 new_line_speed
= SPEED_2500
;
1775 if (vars
->duplex
== DUPLEX_FULL
)
1776 vars
->link_status
|= LINK_2500TFD
;
1778 vars
->link_status
|= LINK_2500THD
;
1784 "link speed unsupported gp_status 0x%x\n",
1788 case GP_STATUS_10G_KX4
:
1789 case GP_STATUS_10G_HIG
:
1790 case GP_STATUS_10G_CX4
:
1791 new_line_speed
= SPEED_10000
;
1792 vars
->link_status
|= LINK_10GTFD
;
1795 case GP_STATUS_12G_HIG
:
1796 new_line_speed
= SPEED_12000
;
1797 vars
->link_status
|= LINK_12GTFD
;
1800 case GP_STATUS_12_5G
:
1801 new_line_speed
= SPEED_12500
;
1802 vars
->link_status
|= LINK_12_5GTFD
;
1806 new_line_speed
= SPEED_13000
;
1807 vars
->link_status
|= LINK_13GTFD
;
1811 new_line_speed
= SPEED_15000
;
1812 vars
->link_status
|= LINK_15GTFD
;
1816 new_line_speed
= SPEED_16000
;
1817 vars
->link_status
|= LINK_16GTFD
;
1822 "link speed unsupported gp_status 0x%x\n",
1828 /* Upon link speed change set the NIG into drain mode.
1829 Comes to deals with possible FIFO glitch due to clk change
1830 when speed is decreased without link down indicator */
1831 if (new_line_speed
!= vars
->line_speed
) {
1832 if (XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) !=
1833 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
&&
1835 DP(NETIF_MSG_LINK
, "Internal link speed %d is"
1836 " different than the external"
1837 " link speed %d\n", new_line_speed
,
1839 vars
->phy_link_up
= 0;
1842 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
1843 + params
->port
*4, 0);
1846 vars
->line_speed
= new_line_speed
;
1847 vars
->link_status
|= LINK_STATUS_SERDES_LINK
;
1849 if ((params
->req_line_speed
== SPEED_AUTO_NEG
) &&
1850 ((XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
1851 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) ||
1852 (XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
1853 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
) ||
1854 (XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
1855 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
))) {
1856 vars
->autoneg
= AUTO_NEG_ENABLED
;
1858 if (gp_status
& MDIO_AN_CL73_OR_37_COMPLETE
) {
1859 vars
->autoneg
|= AUTO_NEG_COMPLETE
;
1860 vars
->link_status
|=
1861 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
1864 vars
->autoneg
|= AUTO_NEG_PARALLEL_DETECTION_USED
;
1865 vars
->link_status
|=
1866 LINK_STATUS_PARALLEL_DETECTION_USED
;
1869 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
1870 vars
->link_status
|=
1871 LINK_STATUS_TX_FLOW_CONTROL_ENABLED
;
1873 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_RX
)
1874 vars
->link_status
|=
1875 LINK_STATUS_RX_FLOW_CONTROL_ENABLED
;
1877 } else { /* link_down */
1878 DP(NETIF_MSG_LINK
, "phy link down\n");
1880 vars
->phy_link_up
= 0;
1882 vars
->duplex
= DUPLEX_FULL
;
1883 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
1884 vars
->autoneg
= AUTO_NEG_DISABLED
;
1885 vars
->mac_type
= MAC_TYPE_NONE
;
1887 if ((params
->req_line_speed
== SPEED_AUTO_NEG
) &&
1888 ((XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
1889 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
))) {
1890 /* Check signal is detected */
1891 bnx2x_check_fallback_to_cl37(params
);
1895 DP(NETIF_MSG_LINK
, "gp_status 0x%x phy_link_up %x line_speed %x \n",
1896 gp_status
, vars
->phy_link_up
, vars
->line_speed
);
1897 DP(NETIF_MSG_LINK
, "duplex %x flow_ctrl 0x%x"
1900 vars
->flow_ctrl
, vars
->autoneg
);
1901 DP(NETIF_MSG_LINK
, "link_status 0x%x\n", vars
->link_status
);
1906 static void bnx2x_set_gmii_tx_driver(struct link_params
*params
)
1908 struct bnx2x
*bp
= params
->bp
;
1914 CL45_RD_OVER_CL22(bp
, params
->port
,
1916 MDIO_REG_BANK_OVER_1G
,
1917 MDIO_OVER_1G_LP_UP2
, &lp_up2
);
1919 /* bits [10:7] at lp_up2, positioned at [15:12] */
1920 lp_up2
= (((lp_up2
& MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK
) >>
1921 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT
) <<
1922 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT
);
1927 for (bank
= MDIO_REG_BANK_TX0
; bank
<= MDIO_REG_BANK_TX3
;
1928 bank
+= (MDIO_REG_BANK_TX1
- MDIO_REG_BANK_TX0
)) {
1929 CL45_RD_OVER_CL22(bp
, params
->port
,
1932 MDIO_TX0_TX_DRIVER
, &tx_driver
);
1934 /* replace tx_driver bits [15:12] */
1936 (tx_driver
& MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK
)) {
1937 tx_driver
&= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK
;
1938 tx_driver
|= lp_up2
;
1939 CL45_WR_OVER_CL22(bp
, params
->port
,
1942 MDIO_TX0_TX_DRIVER
, tx_driver
);
1947 static u8
bnx2x_emac_program(struct link_params
*params
,
1948 u32 line_speed
, u32 duplex
)
1950 struct bnx2x
*bp
= params
->bp
;
1951 u8 port
= params
->port
;
1954 DP(NETIF_MSG_LINK
, "setting link speed & duplex\n");
1955 bnx2x_bits_dis(bp
, GRCBASE_EMAC0
+ port
*0x400 +
1957 (EMAC_MODE_25G_MODE
|
1958 EMAC_MODE_PORT_MII_10M
|
1959 EMAC_MODE_HALF_DUPLEX
));
1960 switch (line_speed
) {
1962 mode
|= EMAC_MODE_PORT_MII_10M
;
1966 mode
|= EMAC_MODE_PORT_MII
;
1970 mode
|= EMAC_MODE_PORT_GMII
;
1974 mode
|= (EMAC_MODE_25G_MODE
| EMAC_MODE_PORT_GMII
);
1978 /* 10G not valid for EMAC */
1979 DP(NETIF_MSG_LINK
, "Invalid line_speed 0x%x\n", line_speed
);
1983 if (duplex
== DUPLEX_HALF
)
1984 mode
|= EMAC_MODE_HALF_DUPLEX
;
1986 GRCBASE_EMAC0
+ port
*0x400 + EMAC_REG_EMAC_MODE
,
1989 bnx2x_set_led(bp
, params
->port
, LED_MODE_OPER
,
1990 line_speed
, params
->hw_led_mode
, params
->chip_id
);
1994 /*****************************************************************************/
1995 /* External Phy section */
1996 /*****************************************************************************/
1997 void bnx2x_ext_phy_hw_reset(struct bnx2x
*bp
, u8 port
)
1999 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
2000 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
2002 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
2003 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, port
);
2006 static void bnx2x_ext_phy_reset(struct link_params
*params
,
2007 struct link_vars
*vars
)
2009 struct bnx2x
*bp
= params
->bp
;
2011 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2013 DP(NETIF_MSG_LINK
, "Port %x: bnx2x_ext_phy_reset\n", params
->port
);
2014 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
2015 /* The PHY reset is controled by GPIO 1
2016 * Give it 1ms of reset pulse
2018 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
2020 switch (ext_phy_type
) {
2021 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
2022 DP(NETIF_MSG_LINK
, "XGXS Direct\n");
2025 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
:
2026 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
:
2027 DP(NETIF_MSG_LINK
, "XGXS 8705/8706\n");
2029 /* Restore normal power mode*/
2030 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
2031 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2035 bnx2x_ext_phy_hw_reset(bp
, params
->port
);
2037 bnx2x_cl45_write(bp
, params
->port
,
2041 MDIO_PMA_REG_CTRL
, 0xa040);
2044 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
2047 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
2049 /* Restore normal power mode*/
2050 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
2051 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2054 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
2055 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2058 bnx2x_cl45_write(bp
, params
->port
,
2066 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
2067 /* Unset Low Power Mode and SW reset */
2068 /* Restore normal power mode*/
2069 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
2070 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2073 DP(NETIF_MSG_LINK
, "XGXS 8072\n");
2074 bnx2x_cl45_write(bp
, params
->port
,
2081 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
2084 /* Restore normal power mode*/
2085 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
2086 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2089 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
2090 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2093 DP(NETIF_MSG_LINK
, "XGXS 8073\n");
2097 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
2098 DP(NETIF_MSG_LINK
, "XGXS SFX7101\n");
2100 /* Restore normal power mode*/
2101 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
2102 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2106 bnx2x_ext_phy_hw_reset(bp
, params
->port
);
2109 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
:
2111 /* Restore normal power mode*/
2112 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
2113 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
2117 bnx2x_ext_phy_hw_reset(bp
, params
->port
);
2119 bnx2x_cl45_write(bp
, params
->port
,
2126 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
2127 DP(NETIF_MSG_LINK
, "XGXS PHY Failure detected\n");
2131 DP(NETIF_MSG_LINK
, "BAD XGXS ext_phy_config 0x%x\n",
2132 params
->ext_phy_config
);
2136 } else { /* SerDes */
2137 ext_phy_type
= SERDES_EXT_PHY_TYPE(params
->ext_phy_config
);
2138 switch (ext_phy_type
) {
2139 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
:
2140 DP(NETIF_MSG_LINK
, "SerDes Direct\n");
2143 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482
:
2144 DP(NETIF_MSG_LINK
, "SerDes 5482\n");
2145 bnx2x_ext_phy_hw_reset(bp
, params
->port
);
2150 "BAD SerDes ext_phy_config 0x%x\n",
2151 params
->ext_phy_config
);
2158 static void bnx2x_save_spirom_version(struct bnx2x
*bp
, u8 port
,
2159 u32 shmem_base
, u32 spirom_ver
)
2161 DP(NETIF_MSG_LINK
, "FW version 0x%x:0x%x\n",
2162 (u16
)(spirom_ver
>>16), (u16
)spirom_ver
);
2163 REG_WR(bp
, shmem_base
+
2164 offsetof(struct shmem_region
,
2165 port_mb
[port
].ext_phy_fw_version
),
2169 static void bnx2x_save_bcm_spirom_ver(struct bnx2x
*bp
, u8 port
,
2170 u32 ext_phy_type
, u8 ext_phy_addr
,
2173 u16 fw_ver1
, fw_ver2
;
2174 bnx2x_cl45_read(bp
, port
, ext_phy_type
, ext_phy_addr
, MDIO_PMA_DEVAD
,
2175 MDIO_PMA_REG_ROM_VER1
, &fw_ver1
);
2176 bnx2x_cl45_read(bp
, port
, ext_phy_type
, ext_phy_addr
, MDIO_PMA_DEVAD
,
2177 MDIO_PMA_REG_ROM_VER2
, &fw_ver2
);
2178 bnx2x_save_spirom_version(bp
, port
, shmem_base
,
2179 (u32
)(fw_ver1
<<16 | fw_ver2
));
2183 static void bnx2x_save_8481_spirom_version(struct bnx2x
*bp
, u8 port
,
2184 u8 ext_phy_addr
, u32 shmem_base
)
2186 u16 val
, fw_ver1
, fw_ver2
, cnt
;
2187 /* For the 32 bits registers in 8481, access via MDIO2ARM interface.*/
2188 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
2189 bnx2x_cl45_write(bp
, port
,
2190 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2191 ext_phy_addr
, MDIO_PMA_DEVAD
,
2193 bnx2x_cl45_write(bp
, port
,
2194 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2199 bnx2x_cl45_write(bp
, port
,
2200 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2205 bnx2x_cl45_write(bp
, port
,
2206 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2211 bnx2x_cl45_write(bp
, port
,
2212 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2218 for (cnt
= 0; cnt
< 100; cnt
++) {
2219 bnx2x_cl45_read(bp
, port
,
2220 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2230 DP(NETIF_MSG_LINK
, "Unable to read 8481 phy fw version(1)\n");
2231 bnx2x_save_spirom_version(bp
, port
,
2237 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
2238 bnx2x_cl45_write(bp
, port
,
2239 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2240 ext_phy_addr
, MDIO_PMA_DEVAD
,
2242 bnx2x_cl45_write(bp
, port
,
2243 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2244 ext_phy_addr
, MDIO_PMA_DEVAD
,
2246 bnx2x_cl45_write(bp
, port
,
2247 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2248 ext_phy_addr
, MDIO_PMA_DEVAD
,
2250 for (cnt
= 0; cnt
< 100; cnt
++) {
2251 bnx2x_cl45_read(bp
, port
,
2252 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2262 DP(NETIF_MSG_LINK
, "Unable to read 8481 phy fw version(2)\n");
2263 bnx2x_save_spirom_version(bp
, port
,
2268 /* lower 16 bits of the register SPI_FW_STATUS */
2269 bnx2x_cl45_read(bp
, port
,
2270 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2275 /* upper 16 bits of register SPI_FW_STATUS */
2276 bnx2x_cl45_read(bp
, port
,
2277 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
2283 bnx2x_save_spirom_version(bp
, port
,
2284 shmem_base
, (fw_ver2
<<16) | fw_ver1
);
2287 static void bnx2x_bcm8072_external_rom_boot(struct link_params
*params
)
2289 struct bnx2x
*bp
= params
->bp
;
2290 u8 port
= params
->port
;
2291 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2292 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
2294 /* Need to wait 200ms after reset */
2296 /* Boot port from external ROM
2297 * Set ser_boot_ctl bit in the MISC_CTRL1 register
2299 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2301 MDIO_PMA_REG_MISC_CTRL1
, 0x0001);
2303 /* Reset internal microprocessor */
2304 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2306 MDIO_PMA_REG_GEN_CTRL
,
2307 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
2308 /* set micro reset = 0 */
2309 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2311 MDIO_PMA_REG_GEN_CTRL
,
2312 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET
);
2313 /* Reset internal microprocessor */
2314 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2316 MDIO_PMA_REG_GEN_CTRL
,
2317 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
2318 /* wait for 100ms for code download via SPI port */
2321 /* Clear ser_boot_ctl bit */
2322 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2324 MDIO_PMA_REG_MISC_CTRL1
, 0x0000);
2328 bnx2x_save_bcm_spirom_ver(bp
, port
,
2331 params
->shmem_base
);
2334 static u8
bnx2x_8073_is_snr_needed(struct link_params
*params
)
2336 /* This is only required for 8073A1, version 102 only */
2338 struct bnx2x
*bp
= params
->bp
;
2339 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2342 /* Read 8073 HW revision*/
2343 bnx2x_cl45_read(bp
, params
->port
,
2344 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
2347 MDIO_PMA_REG_8073_CHIP_REV
, &val
);
2350 /* No need to workaround in 8073 A1 */
2354 bnx2x_cl45_read(bp
, params
->port
,
2355 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
2358 MDIO_PMA_REG_ROM_VER2
, &val
);
2360 /* SNR should be applied only for version 0x102 */
2367 static u8
bnx2x_bcm8073_xaui_wa(struct link_params
*params
)
2369 struct bnx2x
*bp
= params
->bp
;
2370 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2371 u16 val
, cnt
, cnt1
;
2373 bnx2x_cl45_read(bp
, params
->port
,
2374 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
2377 MDIO_PMA_REG_8073_CHIP_REV
, &val
);
2380 /* No need to workaround in 8073 A1 */
2383 /* XAUI workaround in 8073 A0: */
2385 /* After loading the boot ROM and restarting Autoneg,
2386 poll Dev1, Reg $C820: */
2388 for (cnt
= 0; cnt
< 1000; cnt
++) {
2389 bnx2x_cl45_read(bp
, params
->port
,
2390 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
2393 MDIO_PMA_REG_8073_SPEED_LINK_STATUS
,
2395 /* If bit [14] = 0 or bit [13] = 0, continue on with
2396 system initialization (XAUI work-around not required,
2397 as these bits indicate 2.5G or 1G link up). */
2398 if (!(val
& (1<<14)) || !(val
& (1<<13))) {
2399 DP(NETIF_MSG_LINK
, "XAUI work-around not required\n");
2401 } else if (!(val
& (1<<15))) {
2402 DP(NETIF_MSG_LINK
, "clc bit 15 went off\n");
2403 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
2404 it's MSB (bit 15) goes to 1 (indicating that the
2405 XAUI workaround has completed),
2406 then continue on with system initialization.*/
2407 for (cnt1
= 0; cnt1
< 1000; cnt1
++) {
2408 bnx2x_cl45_read(bp
, params
->port
,
2409 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
2412 MDIO_PMA_REG_8073_XAUI_WA
, &val
);
2413 if (val
& (1<<15)) {
2415 "XAUI workaround has completed\n");
2424 DP(NETIF_MSG_LINK
, "Warning: XAUI work-around timeout !!!\n");
2429 static void bnx2x_bcm8073_bcm8727_external_rom_boot(struct bnx2x
*bp
, u8 port
,
2434 /* Boot port from external ROM */
2436 bnx2x_cl45_write(bp
, port
,
2440 MDIO_PMA_REG_GEN_CTRL
,
2443 /* ucode reboot and rst */
2444 bnx2x_cl45_write(bp
, port
,
2448 MDIO_PMA_REG_GEN_CTRL
,
2451 bnx2x_cl45_write(bp
, port
,
2455 MDIO_PMA_REG_MISC_CTRL1
, 0x0001);
2457 /* Reset internal microprocessor */
2458 bnx2x_cl45_write(bp
, port
,
2462 MDIO_PMA_REG_GEN_CTRL
,
2463 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET
);
2465 /* Release srst bit */
2466 bnx2x_cl45_write(bp
, port
,
2470 MDIO_PMA_REG_GEN_CTRL
,
2471 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
2473 /* wait for 100ms for code download via SPI port */
2476 /* Clear ser_boot_ctl bit */
2477 bnx2x_cl45_write(bp
, port
,
2481 MDIO_PMA_REG_MISC_CTRL1
, 0x0000);
2483 bnx2x_save_bcm_spirom_ver(bp
, port
,
2489 static void bnx2x_bcm8073_external_rom_boot(struct bnx2x
*bp
, u8 port
,
2493 bnx2x_bcm8073_bcm8727_external_rom_boot(bp
, port
, ext_phy_addr
,
2494 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
2498 static void bnx2x_bcm8727_external_rom_boot(struct bnx2x
*bp
, u8 port
,
2502 bnx2x_bcm8073_bcm8727_external_rom_boot(bp
, port
, ext_phy_addr
,
2503 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
2508 static void bnx2x_bcm8726_external_rom_boot(struct link_params
*params
)
2510 struct bnx2x
*bp
= params
->bp
;
2511 u8 port
= params
->port
;
2512 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2513 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
2515 /* Need to wait 100ms after reset */
2518 /* Set serial boot control for external load */
2519 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2521 MDIO_PMA_REG_MISC_CTRL1
, 0x0001);
2523 /* Micro controller re-boot */
2524 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2526 MDIO_PMA_REG_GEN_CTRL
,
2527 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
2529 /* Set soft reset */
2530 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2532 MDIO_PMA_REG_GEN_CTRL
,
2533 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET
);
2535 /* Set PLL register value to be same like in P13 ver */
2536 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2538 MDIO_PMA_REG_PLL_CTRL
,
2541 /* Clear soft reset.
2542 Will automatically reset micro-controller re-boot */
2543 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2545 MDIO_PMA_REG_GEN_CTRL
,
2546 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
2548 /* wait for 150ms for microcode load */
2551 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
2552 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
2554 MDIO_PMA_REG_MISC_CTRL1
, 0x0000);
2557 bnx2x_save_bcm_spirom_ver(bp
, port
,
2560 params
->shmem_base
);
2563 static void bnx2x_sfp_set_transmitter(struct bnx2x
*bp
, u8 port
,
2564 u32 ext_phy_type
, u8 ext_phy_addr
,
2568 DP(NETIF_MSG_LINK
, "Setting transmitter tx_en=%x for port %x\n",
2570 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
2571 bnx2x_cl45_read(bp
, port
,
2575 MDIO_PMA_REG_PHY_IDENTIFIER
,
2583 bnx2x_cl45_write(bp
, port
,
2587 MDIO_PMA_REG_PHY_IDENTIFIER
,
2591 static u8
bnx2x_8726_read_sfp_module_eeprom(struct link_params
*params
,
2592 u16 addr
, u8 byte_cnt
, u8
*o_buf
)
2594 struct bnx2x
*bp
= params
->bp
;
2597 u8 port
= params
->port
;
2598 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2599 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
2600 if (byte_cnt
> 16) {
2601 DP(NETIF_MSG_LINK
, "Reading from eeprom is"
2602 " is limited to 0xf\n");
2605 /* Set the read command byte count */
2606 bnx2x_cl45_write(bp
, port
,
2610 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT
,
2611 (byte_cnt
| 0xa000));
2613 /* Set the read command address */
2614 bnx2x_cl45_write(bp
, port
,
2618 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR
,
2621 /* Activate read command */
2622 bnx2x_cl45_write(bp
, port
,
2626 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
,
2629 /* Wait up to 500us for command complete status */
2630 for (i
= 0; i
< 100; i
++) {
2631 bnx2x_cl45_read(bp
, port
,
2635 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
2636 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
2637 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
)
2642 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) !=
2643 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
) {
2645 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2646 (val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
));
2650 /* Read the buffer */
2651 for (i
= 0; i
< byte_cnt
; i
++) {
2652 bnx2x_cl45_read(bp
, port
,
2656 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF
+ i
, &val
);
2657 o_buf
[i
] = (u8
)(val
& MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK
);
2660 for (i
= 0; i
< 100; i
++) {
2661 bnx2x_cl45_read(bp
, port
,
2665 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
2666 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
2667 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE
)
2674 static u8
bnx2x_8727_read_sfp_module_eeprom(struct link_params
*params
,
2675 u16 addr
, u8 byte_cnt
, u8
*o_buf
)
2677 struct bnx2x
*bp
= params
->bp
;
2679 u8 port
= params
->port
;
2680 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2681 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
2683 if (byte_cnt
> 16) {
2684 DP(NETIF_MSG_LINK
, "Reading from eeprom is"
2685 " is limited to 0xf\n");
2689 /* Need to read from 1.8000 to clear it */
2690 bnx2x_cl45_read(bp
, port
,
2691 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
2694 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
,
2697 /* Set the read command byte count */
2698 bnx2x_cl45_write(bp
, port
,
2702 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT
,
2703 ((byte_cnt
< 2) ? 2 : byte_cnt
));
2705 /* Set the read command address */
2706 bnx2x_cl45_write(bp
, port
,
2710 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR
,
2712 /* Set the destination address */
2713 bnx2x_cl45_write(bp
, port
,
2718 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF
);
2720 /* Activate read command */
2721 bnx2x_cl45_write(bp
, port
,
2725 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
,
2727 /* Wait appropriate time for two-wire command to finish before
2728 polling the status register */
2731 /* Wait up to 500us for command complete status */
2732 for (i
= 0; i
< 100; i
++) {
2733 bnx2x_cl45_read(bp
, port
,
2737 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
2738 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
2739 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
)
2744 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) !=
2745 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
) {
2747 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2748 (val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
));
2752 /* Read the buffer */
2753 for (i
= 0; i
< byte_cnt
; i
++) {
2754 bnx2x_cl45_read(bp
, port
,
2758 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF
+ i
, &val
);
2759 o_buf
[i
] = (u8
)(val
& MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK
);
2762 for (i
= 0; i
< 100; i
++) {
2763 bnx2x_cl45_read(bp
, port
,
2767 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
2768 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
2769 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE
)
2777 u8
bnx2x_read_sfp_module_eeprom(struct link_params
*params
, u16 addr
,
2778 u8 byte_cnt
, u8
*o_buf
)
2780 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
2782 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
)
2783 return bnx2x_8726_read_sfp_module_eeprom(params
, addr
,
2785 else if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
)
2786 return bnx2x_8727_read_sfp_module_eeprom(params
, addr
,
2791 static u8
bnx2x_get_edc_mode(struct link_params
*params
,
2794 struct bnx2x
*bp
= params
->bp
;
2795 u8 val
, check_limiting_mode
= 0;
2796 *edc_mode
= EDC_MODE_LIMITING
;
2798 /* First check for copper cable */
2799 if (bnx2x_read_sfp_module_eeprom(params
,
2800 SFP_EEPROM_CON_TYPE_ADDR
,
2803 DP(NETIF_MSG_LINK
, "Failed to read from SFP+ module EEPROM\n");
2808 case SFP_EEPROM_CON_TYPE_VAL_COPPER
:
2810 u8 copper_module_type
;
2811 /* Check if its active cable( includes SFP+ module)
2813 if (bnx2x_read_sfp_module_eeprom(params
,
2814 SFP_EEPROM_FC_TX_TECH_ADDR
,
2816 &copper_module_type
) !=
2819 "Failed to read copper-cable-type"
2820 " from SFP+ EEPROM\n");
2824 if (copper_module_type
&
2825 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE
) {
2826 DP(NETIF_MSG_LINK
, "Active Copper cable detected\n");
2827 check_limiting_mode
= 1;
2828 } else if (copper_module_type
&
2829 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE
) {
2830 DP(NETIF_MSG_LINK
, "Passive Copper"
2831 " cable detected\n");
2833 EDC_MODE_PASSIVE_DAC
;
2835 DP(NETIF_MSG_LINK
, "Unknown copper-cable-"
2836 "type 0x%x !!!\n", copper_module_type
);
2841 case SFP_EEPROM_CON_TYPE_VAL_LC
:
2842 DP(NETIF_MSG_LINK
, "Optic module detected\n");
2843 check_limiting_mode
= 1;
2847 DP(NETIF_MSG_LINK
, "Unable to determine module type 0x%x !!!\n",
2852 if (check_limiting_mode
) {
2853 u8 options
[SFP_EEPROM_OPTIONS_SIZE
];
2854 if (bnx2x_read_sfp_module_eeprom(params
,
2855 SFP_EEPROM_OPTIONS_ADDR
,
2856 SFP_EEPROM_OPTIONS_SIZE
,
2858 DP(NETIF_MSG_LINK
, "Failed to read Option"
2859 " field from module EEPROM\n");
2862 if ((options
[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK
))
2863 *edc_mode
= EDC_MODE_LINEAR
;
2865 *edc_mode
= EDC_MODE_LIMITING
;
2867 DP(NETIF_MSG_LINK
, "EDC mode is set to 0x%x\n", *edc_mode
);
2871 /* This function read the relevant field from the module ( SFP+ ),
2872 and verify it is compliant with this board */
2873 static u8
bnx2x_verify_sfp_module(struct link_params
*params
)
2875 struct bnx2x
*bp
= params
->bp
;
2878 char vendor_name
[SFP_EEPROM_VENDOR_NAME_SIZE
+1];
2879 char vendor_pn
[SFP_EEPROM_PART_NO_SIZE
+1];
2881 val
= REG_RD(bp
, params
->shmem_base
+
2882 offsetof(struct shmem_region
, dev_info
.
2883 port_feature_config
[params
->port
].config
));
2884 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
2885 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT
) {
2886 DP(NETIF_MSG_LINK
, "NOT enforcing module verification\n");
2890 /* Ask the FW to validate the module */
2891 if (!(params
->feature_config_flags
&
2892 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY
)) {
2893 DP(NETIF_MSG_LINK
, "FW does not support OPT MDL "
2898 fw_resp
= bnx2x_fw_command(bp
, DRV_MSG_CODE_VRFY_OPT_MDL
);
2899 if (fw_resp
== FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS
) {
2900 DP(NETIF_MSG_LINK
, "Approved module\n");
2904 /* format the warning message */
2905 if (bnx2x_read_sfp_module_eeprom(params
,
2906 SFP_EEPROM_VENDOR_NAME_ADDR
,
2907 SFP_EEPROM_VENDOR_NAME_SIZE
,
2909 vendor_name
[0] = '\0';
2911 vendor_name
[SFP_EEPROM_VENDOR_NAME_SIZE
] = '\0';
2912 if (bnx2x_read_sfp_module_eeprom(params
,
2913 SFP_EEPROM_PART_NO_ADDR
,
2914 SFP_EEPROM_PART_NO_SIZE
,
2916 vendor_pn
[0] = '\0';
2918 vendor_pn
[SFP_EEPROM_PART_NO_SIZE
] = '\0';
2920 printk(KERN_INFO PFX
"Warning: "
2921 "Unqualified SFP+ module "
2922 "detected on %s, Port %d from %s part number %s\n"
2923 , bp
->dev
->name
, params
->port
,
2924 vendor_name
, vendor_pn
);
2928 static u8
bnx2x_bcm8726_set_limiting_mode(struct link_params
*params
,
2931 struct bnx2x
*bp
= params
->bp
;
2932 u8 port
= params
->port
;
2933 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
2934 u16 cur_limiting_mode
;
2936 bnx2x_cl45_read(bp
, port
,
2937 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
,
2940 MDIO_PMA_REG_ROM_VER2
,
2941 &cur_limiting_mode
);
2942 DP(NETIF_MSG_LINK
, "Current Limiting mode is 0x%x\n",
2945 if (edc_mode
== EDC_MODE_LIMITING
) {
2947 "Setting LIMITING MODE\n");
2948 bnx2x_cl45_write(bp
, port
,
2949 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
,
2952 MDIO_PMA_REG_ROM_VER2
,
2954 } else { /* LRM mode ( default )*/
2956 DP(NETIF_MSG_LINK
, "Setting LRM MODE\n");
2958 /* Changing to LRM mode takes quite few seconds.
2959 So do it only if current mode is limiting
2960 ( default is LRM )*/
2961 if (cur_limiting_mode
!= EDC_MODE_LIMITING
)
2964 bnx2x_cl45_write(bp
, port
,
2965 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
,
2968 MDIO_PMA_REG_LRM_MODE
,
2970 bnx2x_cl45_write(bp
, port
,
2971 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
,
2974 MDIO_PMA_REG_ROM_VER2
,
2976 bnx2x_cl45_write(bp
, port
,
2977 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
,
2980 MDIO_PMA_REG_MISC_CTRL0
,
2982 bnx2x_cl45_write(bp
, port
,
2983 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
,
2986 MDIO_PMA_REG_LRM_MODE
,
2992 static u8
bnx2x_bcm8727_set_limiting_mode(struct link_params
*params
,
2995 struct bnx2x
*bp
= params
->bp
;
2996 u8 port
= params
->port
;
2999 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3001 bnx2x_cl45_read(bp
, port
,
3002 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
3005 MDIO_PMA_REG_PHY_IDENTIFIER
,
3008 bnx2x_cl45_write(bp
, port
,
3009 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
3012 MDIO_PMA_REG_PHY_IDENTIFIER
,
3013 (phy_identifier
& ~(1<<9)));
3015 bnx2x_cl45_read(bp
, port
,
3016 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
3019 MDIO_PMA_REG_ROM_VER2
,
3021 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
3022 bnx2x_cl45_write(bp
, port
,
3023 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
3026 MDIO_PMA_REG_ROM_VER2
,
3027 (rom_ver2_val
& 0xff00) | (edc_mode
& 0x00ff));
3029 bnx2x_cl45_write(bp
, port
,
3030 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
3033 MDIO_PMA_REG_PHY_IDENTIFIER
,
3034 (phy_identifier
| (1<<9)));
3040 static u8
bnx2x_wait_for_sfp_module_initialized(struct link_params
*params
)
3043 struct bnx2x
*bp
= params
->bp
;
3045 /* Initialization time after hot-plug may take up to 300ms for some
3046 phys type ( e.g. JDSU ) */
3047 for (timeout
= 0; timeout
< 60; timeout
++) {
3048 if (bnx2x_read_sfp_module_eeprom(params
, 1, 1, &val
)
3050 DP(NETIF_MSG_LINK
, "SFP+ module initialization "
3051 "took %d ms\n", timeout
* 5);
3059 static void bnx2x_8727_power_module(struct bnx2x
*bp
,
3060 struct link_params
*params
,
3061 u8 ext_phy_addr
, u8 is_power_up
) {
3062 /* Make sure GPIOs are not using for LED mode */
3064 u8 port
= params
->port
;
3066 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
3067 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
3069 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
3070 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
3071 * where the 1st bit is the over-current(only input), and 2nd bit is
3072 * for power( only output )
3076 * In case of NOC feature is disabled and power is up, set GPIO control
3077 * as input to enable listening of over-current indication
3080 if (!(params
->feature_config_flags
&
3081 FEATURE_CONFIG_BCM8727_NOC
) && is_power_up
)
3085 * Set GPIO control to OUTPUT, and set the power bit
3086 * to according to the is_power_up
3088 val
= ((!(is_power_up
)) << 1);
3090 bnx2x_cl45_write(bp
, port
,
3091 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
3094 MDIO_PMA_REG_8727_GPIO_CTRL
,
3098 static u8
bnx2x_sfp_module_detection(struct link_params
*params
)
3100 struct bnx2x
*bp
= params
->bp
;
3103 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3104 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3105 u32 val
= REG_RD(bp
, params
->shmem_base
+
3106 offsetof(struct shmem_region
, dev_info
.
3107 port_feature_config
[params
->port
].config
));
3109 DP(NETIF_MSG_LINK
, "SFP+ module plugged in/out detected on port %d\n",
3112 if (bnx2x_get_edc_mode(params
, &edc_mode
) != 0) {
3113 DP(NETIF_MSG_LINK
, "Failed to get valid module type\n");
3115 } else if (bnx2x_verify_sfp_module(params
) !=
3117 /* check SFP+ module compatibility */
3118 DP(NETIF_MSG_LINK
, "Module verification failed!!\n");
3120 /* Turn on fault module-detected led */
3121 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_0
,
3122 MISC_REGISTERS_GPIO_HIGH
,
3124 if ((ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
) &&
3125 ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
3126 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN
)) {
3127 /* Shutdown SFP+ module */
3128 DP(NETIF_MSG_LINK
, "Shutdown SFP+ module!!\n");
3129 bnx2x_8727_power_module(bp
, params
,
3134 /* Turn off fault module-detected led */
3135 DP(NETIF_MSG_LINK
, "Turn off fault module-detected led\n");
3136 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_0
,
3137 MISC_REGISTERS_GPIO_LOW
,
3141 /* power up the SFP module */
3142 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
)
3143 bnx2x_8727_power_module(bp
, params
, ext_phy_addr
, 1);
3145 /* Check and set limiting mode / LRM mode on 8726.
3146 On 8727 it is done automatically */
3147 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
)
3148 bnx2x_bcm8726_set_limiting_mode(params
, edc_mode
);
3150 bnx2x_bcm8727_set_limiting_mode(params
, edc_mode
);
3152 * Enable transmit for this module if the module is approved, or
3153 * if unapproved modules should also enable the Tx laser
3156 (val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) !=
3157 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
)
3158 bnx2x_sfp_set_transmitter(bp
, params
->port
,
3159 ext_phy_type
, ext_phy_addr
, 1);
3161 bnx2x_sfp_set_transmitter(bp
, params
->port
,
3162 ext_phy_type
, ext_phy_addr
, 0);
3167 void bnx2x_handle_module_detect_int(struct link_params
*params
)
3169 struct bnx2x
*bp
= params
->bp
;
3171 u8 port
= params
->port
;
3172 /* Set valid module led off */
3173 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_0
,
3174 MISC_REGISTERS_GPIO_HIGH
,
3177 /* Get current gpio val refelecting module plugged in / out*/
3178 gpio_val
= bnx2x_get_gpio(bp
, MISC_REGISTERS_GPIO_3
, port
);
3180 /* Call the handling function in case module is detected */
3181 if (gpio_val
== 0) {
3183 bnx2x_set_gpio_int(bp
, MISC_REGISTERS_GPIO_3
,
3184 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
,
3187 if (bnx2x_wait_for_sfp_module_initialized(params
) ==
3189 bnx2x_sfp_module_detection(params
);
3191 DP(NETIF_MSG_LINK
, "SFP+ module is not initialized\n");
3193 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3196 XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3197 u32 val
= REG_RD(bp
, params
->shmem_base
+
3198 offsetof(struct shmem_region
, dev_info
.
3199 port_feature_config
[params
->port
].
3202 bnx2x_set_gpio_int(bp
, MISC_REGISTERS_GPIO_3
,
3203 MISC_REGISTERS_GPIO_INT_OUTPUT_SET
,
3205 /* Module was plugged out. */
3206 /* Disable transmit for this module */
3207 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
3208 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
)
3209 bnx2x_sfp_set_transmitter(bp
, params
->port
,
3210 ext_phy_type
, ext_phy_addr
, 0);
3214 static void bnx2x_bcm807x_force_10G(struct link_params
*params
)
3216 struct bnx2x
*bp
= params
->bp
;
3217 u8 port
= params
->port
;
3218 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3219 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3221 /* Force KR or KX */
3222 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3226 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3228 MDIO_PMA_REG_10G_CTRL2
,
3230 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3232 MDIO_PMA_REG_BCM_CTRL
,
3234 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3239 static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params
*params
)
3241 struct bnx2x
*bp
= params
->bp
;
3242 u8 port
= params
->port
;
3244 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3245 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3247 bnx2x_cl45_read(bp
, params
->port
,
3248 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
3251 MDIO_PMA_REG_8073_CHIP_REV
, &val
);
3254 /* Mustn't set low power mode in 8073 A0 */
3258 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3259 bnx2x_cl45_read(bp
, port
, ext_phy_type
, ext_phy_addr
,
3261 MDIO_XS_PLL_SEQUENCER
, &val
);
3263 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3264 MDIO_XS_DEVAD
, MDIO_XS_PLL_SEQUENCER
, val
);
3267 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3268 MDIO_XS_DEVAD
, 0x805E, 0x1077);
3269 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3270 MDIO_XS_DEVAD
, 0x805D, 0x0000);
3271 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3272 MDIO_XS_DEVAD
, 0x805C, 0x030B);
3273 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3274 MDIO_XS_DEVAD
, 0x805B, 0x1240);
3275 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3276 MDIO_XS_DEVAD
, 0x805A, 0x2490);
3279 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3280 MDIO_XS_DEVAD
, 0x80A7, 0x0C74);
3281 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3282 MDIO_XS_DEVAD
, 0x80A6, 0x9041);
3283 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3284 MDIO_XS_DEVAD
, 0x80A5, 0x4640);
3287 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3288 MDIO_XS_DEVAD
, 0x80FE, 0x01C4);
3289 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3290 MDIO_XS_DEVAD
, 0x80FD, 0x9249);
3291 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3292 MDIO_XS_DEVAD
, 0x80FC, 0x2015);
3294 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
3295 bnx2x_cl45_read(bp
, port
, ext_phy_type
, ext_phy_addr
,
3297 MDIO_XS_PLL_SEQUENCER
, &val
);
3299 bnx2x_cl45_write(bp
, port
, ext_phy_type
, ext_phy_addr
,
3300 MDIO_XS_DEVAD
, MDIO_XS_PLL_SEQUENCER
, val
);
3303 static void bnx2x_8073_set_pause_cl37(struct link_params
*params
,
3304 struct link_vars
*vars
)
3307 struct bnx2x
*bp
= params
->bp
;
3309 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3310 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3312 bnx2x_cl45_read(bp
, params
->port
,
3316 MDIO_AN_REG_CL37_FC_LD
, &cl37_val
);
3318 cl37_val
&= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
3319 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3321 if ((vars
->ieee_fc
&
3322 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
) ==
3323 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
) {
3324 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
;
3326 if ((vars
->ieee_fc
&
3327 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) ==
3328 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) {
3329 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
3331 if ((vars
->ieee_fc
&
3332 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) ==
3333 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) {
3334 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
3337 "Ext phy AN advertize cl37 0x%x\n", cl37_val
);
3339 bnx2x_cl45_write(bp
, params
->port
,
3343 MDIO_AN_REG_CL37_FC_LD
, cl37_val
);
3347 static void bnx2x_ext_phy_set_pause(struct link_params
*params
,
3348 struct link_vars
*vars
)
3350 struct bnx2x
*bp
= params
->bp
;
3352 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3353 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3355 /* read modify write pause advertizing */
3356 bnx2x_cl45_read(bp
, params
->port
,
3360 MDIO_AN_REG_ADV_PAUSE
, &val
);
3362 val
&= ~MDIO_AN_REG_ADV_PAUSE_BOTH
;
3364 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3366 if ((vars
->ieee_fc
&
3367 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) ==
3368 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) {
3369 val
|= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC
;
3371 if ((vars
->ieee_fc
&
3372 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) ==
3373 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) {
3375 MDIO_AN_REG_ADV_PAUSE_PAUSE
;
3378 "Ext phy AN advertize 0x%x\n", val
);
3379 bnx2x_cl45_write(bp
, params
->port
,
3383 MDIO_AN_REG_ADV_PAUSE
, val
);
3385 static void bnx2x_set_preemphasis(struct link_params
*params
)
3388 struct bnx2x
*bp
= params
->bp
;
3390 for (bank
= MDIO_REG_BANK_RX0
, i
= 0; bank
<= MDIO_REG_BANK_RX3
;
3391 bank
+= (MDIO_REG_BANK_RX1
-MDIO_REG_BANK_RX0
), i
++) {
3392 CL45_WR_OVER_CL22(bp
, params
->port
,
3395 MDIO_RX0_RX_EQ_BOOST
,
3396 params
->xgxs_config_rx
[i
]);
3399 for (bank
= MDIO_REG_BANK_TX0
, i
= 0; bank
<= MDIO_REG_BANK_TX3
;
3400 bank
+= (MDIO_REG_BANK_TX1
- MDIO_REG_BANK_TX0
), i
++) {
3401 CL45_WR_OVER_CL22(bp
, params
->port
,
3405 params
->xgxs_config_tx
[i
]);
3410 static void bnx2x_8481_set_led4(struct link_params
*params
,
3411 u32 ext_phy_type
, u8 ext_phy_addr
)
3413 struct bnx2x
*bp
= params
->bp
;
3415 /* PHYC_CTL_LED_CTL */
3416 bnx2x_cl45_write(bp
, params
->port
,
3420 MDIO_PMA_REG_8481_LINK_SIGNAL
, 0xa482);
3422 /* Unmask LED4 for 10G link */
3423 bnx2x_cl45_write(bp
, params
->port
,
3427 MDIO_PMA_REG_8481_SIGNAL_MASK
, (1<<6));
3428 /* 'Interrupt Mask' */
3429 bnx2x_cl45_write(bp
, params
->port
,
3435 static void bnx2x_8481_set_legacy_led_mode(struct link_params
*params
,
3436 u32 ext_phy_type
, u8 ext_phy_addr
)
3438 struct bnx2x
*bp
= params
->bp
;
3440 /* LED1 (10G Link): Disable LED1 when 10/100/1000 link */
3441 /* LED2 (1G/100/10 Link): Enable LED2 when 10/100/1000 link) */
3442 bnx2x_cl45_write(bp
, params
->port
,
3446 MDIO_AN_REG_8481_LEGACY_SHADOW
,
3447 (1<<15) | (0xd << 10) | (0xc<<4) | 0xe);
3450 static void bnx2x_8481_set_10G_led_mode(struct link_params
*params
,
3451 u32 ext_phy_type
, u8 ext_phy_addr
)
3453 struct bnx2x
*bp
= params
->bp
;
3456 /* LED1 (10G Link) */
3457 /* Enable continuse based on source 7(10G-link) */
3458 bnx2x_cl45_read(bp
, params
->port
,
3462 MDIO_PMA_REG_8481_LINK_SIGNAL
,
3464 /* Set bit 2 to 0, and bits [1:0] to 10 */
3465 val1
&= ~((1<<0) | (1<<2)); /* Clear bits 0,2*/
3466 val1
|= (1<<1); /* Set bit 1 */
3468 bnx2x_cl45_write(bp
, params
->port
,
3472 MDIO_PMA_REG_8481_LINK_SIGNAL
,
3475 /* Unmask LED1 for 10G link */
3476 bnx2x_cl45_read(bp
, params
->port
,
3480 MDIO_PMA_REG_8481_LED1_MASK
,
3482 /* Set bit 2 to 0, and bits [1:0] to 10 */
3484 bnx2x_cl45_write(bp
, params
->port
,
3488 MDIO_PMA_REG_8481_LED1_MASK
,
3491 /* LED2 (1G/100/10G Link) */
3492 /* Mask LED2 for 10G link */
3493 bnx2x_cl45_write(bp
, params
->port
,
3497 MDIO_PMA_REG_8481_LED2_MASK
,
3500 /* LED3 (10G/1G/100/10G Activity) */
3501 bnx2x_cl45_read(bp
, params
->port
,
3505 MDIO_PMA_REG_8481_LINK_SIGNAL
,
3507 /* Enable blink based on source 4(Activity) */
3508 val1
&= ~((1<<7) | (1<<8)); /* Clear bits 7,8 */
3509 val1
|= (1<<6); /* Set only bit 6 */
3510 bnx2x_cl45_write(bp
, params
->port
,
3514 MDIO_PMA_REG_8481_LINK_SIGNAL
,
3517 bnx2x_cl45_read(bp
, params
->port
,
3521 MDIO_PMA_REG_8481_LED3_MASK
,
3523 val1
|= (1<<4); /* Unmask LED3 for 10G link */
3524 bnx2x_cl45_write(bp
, params
->port
,
3528 MDIO_PMA_REG_8481_LED3_MASK
,
3533 static void bnx2x_init_internal_phy(struct link_params
*params
,
3534 struct link_vars
*vars
,
3537 struct bnx2x
*bp
= params
->bp
;
3538 if (!(vars
->phy_flags
& PHY_SGMII_FLAG
)) {
3539 if ((XGXS_EXT_PHY_TYPE(params
->ext_phy_config
) ==
3540 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) &&
3541 (params
->feature_config_flags
&
3542 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
))
3543 bnx2x_set_preemphasis(params
);
3545 /* forced speed requested? */
3546 if (vars
->line_speed
!= SPEED_AUTO_NEG
) {
3547 DP(NETIF_MSG_LINK
, "not SGMII, no AN\n");
3549 /* disable autoneg */
3550 bnx2x_set_autoneg(params
, vars
, 0);
3552 /* program speed and duplex */
3553 bnx2x_program_serdes(params
, vars
);
3555 } else { /* AN_mode */
3556 DP(NETIF_MSG_LINK
, "not SGMII, AN\n");
3559 bnx2x_set_brcm_cl37_advertisment(params
);
3561 /* program duplex & pause advertisement (for aneg) */
3562 bnx2x_set_ieee_aneg_advertisment(params
,
3565 /* enable autoneg */
3566 bnx2x_set_autoneg(params
, vars
, enable_cl73
);
3568 /* enable and restart AN */
3569 bnx2x_restart_autoneg(params
, enable_cl73
);
3572 } else { /* SGMII mode */
3573 DP(NETIF_MSG_LINK
, "SGMII\n");
3575 bnx2x_initialize_sgmii_process(params
, vars
);
3579 static u8
bnx2x_ext_phy_init(struct link_params
*params
, struct link_vars
*vars
)
3581 struct bnx2x
*bp
= params
->bp
;
3588 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
3589 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
3591 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
3592 /* Make sure that the soft reset is off (expect for the 8072:
3593 * due to the lock, it will be done inside the specific
3596 if ((ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) &&
3597 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) &&
3598 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
) &&
3599 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
) &&
3600 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
)) {
3601 /* Wait for soft reset to get cleared upto 1 sec */
3602 for (cnt
= 0; cnt
< 1000; cnt
++) {
3603 bnx2x_cl45_read(bp
, params
->port
,
3607 MDIO_PMA_REG_CTRL
, &ctrl
);
3608 if (!(ctrl
& (1<<15)))
3612 DP(NETIF_MSG_LINK
, "control reg 0x%x (after %d ms)\n",
3616 switch (ext_phy_type
) {
3617 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
3620 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
:
3621 DP(NETIF_MSG_LINK
, "XGXS 8705\n");
3623 bnx2x_cl45_write(bp
, params
->port
,
3627 MDIO_PMA_REG_MISC_CTRL
,
3629 bnx2x_cl45_write(bp
, params
->port
,
3633 MDIO_PMA_REG_PHY_IDENTIFIER
,
3635 bnx2x_cl45_write(bp
, params
->port
,
3639 MDIO_PMA_REG_CMU_PLL_BYPASS
,
3641 bnx2x_cl45_write(bp
, params
->port
,
3645 MDIO_WIS_REG_LASI_CNTL
, 0x1);
3647 /* BCM8705 doesn't have microcode, hence the 0 */
3648 bnx2x_save_spirom_version(bp
, params
->port
,
3649 params
->shmem_base
, 0);
3652 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
:
3653 /* Wait until fw is loaded */
3654 for (cnt
= 0; cnt
< 100; cnt
++) {
3655 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
3656 ext_phy_addr
, MDIO_PMA_DEVAD
,
3657 MDIO_PMA_REG_ROM_VER1
, &val
);
3662 DP(NETIF_MSG_LINK
, "XGXS 8706 is initialized "
3663 "after %d ms\n", cnt
);
3664 if ((params
->feature_config_flags
&
3665 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
3668 for (i
= 0; i
< 4; i
++) {
3669 reg
= MDIO_XS_8706_REG_BANK_RX0
+
3670 i
*(MDIO_XS_8706_REG_BANK_RX1
-
3671 MDIO_XS_8706_REG_BANK_RX0
);
3672 bnx2x_cl45_read(bp
, params
->port
,
3677 /* Clear first 3 bits of the control */
3679 /* Set control bits according to
3681 val
|= (params
->xgxs_config_rx
[i
] &
3683 DP(NETIF_MSG_LINK
, "Setting RX"
3684 "Equalizer to BCM8706 reg 0x%x"
3685 " <-- val 0x%x\n", reg
, val
);
3686 bnx2x_cl45_write(bp
, params
->port
,
3694 /* First enable LASI */
3695 bnx2x_cl45_write(bp
, params
->port
,
3699 MDIO_PMA_REG_RX_ALARM_CTRL
,
3701 bnx2x_cl45_write(bp
, params
->port
,
3705 MDIO_PMA_REG_LASI_CTRL
, 0x0004);
3707 if (params
->req_line_speed
== SPEED_10000
) {
3708 DP(NETIF_MSG_LINK
, "XGXS 8706 force 10Gbps\n");
3710 bnx2x_cl45_write(bp
, params
->port
,
3714 MDIO_PMA_REG_DIGITAL_CTRL
,
3717 /* Force 1Gbps using autoneg with 1G
3720 /* Allow CL37 through CL73 */
3721 DP(NETIF_MSG_LINK
, "XGXS 8706 AutoNeg\n");
3722 bnx2x_cl45_write(bp
, params
->port
,
3726 MDIO_AN_REG_CL37_CL73
,
3729 /* Enable Full-Duplex advertisment on CL37 */
3730 bnx2x_cl45_write(bp
, params
->port
,
3734 MDIO_AN_REG_CL37_FC_LP
,
3736 /* Enable CL37 AN */
3737 bnx2x_cl45_write(bp
, params
->port
,
3741 MDIO_AN_REG_CL37_AN
,
3744 bnx2x_cl45_write(bp
, params
->port
,
3748 MDIO_AN_REG_ADV
, (1<<5));
3750 /* Enable clause 73 AN */
3751 bnx2x_cl45_write(bp
, params
->port
,
3759 bnx2x_save_bcm_spirom_ver(bp
, params
->port
,
3762 params
->shmem_base
);
3764 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
3765 DP(NETIF_MSG_LINK
, "Initializing BCM8726\n");
3766 bnx2x_bcm8726_external_rom_boot(params
);
3768 /* Need to call module detected on initialization since
3769 the module detection triggered by actual module
3770 insertion might occur before driver is loaded, and when
3771 driver is loaded, it reset all registers, including the
3773 bnx2x_sfp_module_detection(params
);
3775 /* Set Flow control */
3776 bnx2x_ext_phy_set_pause(params
, vars
);
3777 if (params
->req_line_speed
== SPEED_1000
) {
3778 DP(NETIF_MSG_LINK
, "Setting 1G force\n");
3779 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3780 ext_phy_addr
, MDIO_PMA_DEVAD
,
3781 MDIO_PMA_REG_CTRL
, 0x40);
3782 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3783 ext_phy_addr
, MDIO_PMA_DEVAD
,
3784 MDIO_PMA_REG_10G_CTRL2
, 0xD);
3785 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3786 ext_phy_addr
, MDIO_PMA_DEVAD
,
3787 MDIO_PMA_REG_LASI_CTRL
, 0x5);
3788 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3789 ext_phy_addr
, MDIO_PMA_DEVAD
,
3790 MDIO_PMA_REG_RX_ALARM_CTRL
,
3792 } else if ((params
->req_line_speed
==
3794 ((params
->speed_cap_mask
&
3795 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
))) {
3796 DP(NETIF_MSG_LINK
, "Setting 1G clause37 \n");
3797 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3798 ext_phy_addr
, MDIO_AN_DEVAD
,
3799 MDIO_AN_REG_ADV
, 0x20);
3800 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3801 ext_phy_addr
, MDIO_AN_DEVAD
,
3802 MDIO_AN_REG_CL37_CL73
, 0x040c);
3803 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3804 ext_phy_addr
, MDIO_AN_DEVAD
,
3805 MDIO_AN_REG_CL37_FC_LD
, 0x0020);
3806 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3807 ext_phy_addr
, MDIO_AN_DEVAD
,
3808 MDIO_AN_REG_CL37_AN
, 0x1000);
3809 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3810 ext_phy_addr
, MDIO_AN_DEVAD
,
3811 MDIO_AN_REG_CTRL
, 0x1200);
3813 /* Enable RX-ALARM control to receive
3814 interrupt for 1G speed change */
3815 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3816 ext_phy_addr
, MDIO_PMA_DEVAD
,
3817 MDIO_PMA_REG_LASI_CTRL
, 0x4);
3818 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3819 ext_phy_addr
, MDIO_PMA_DEVAD
,
3820 MDIO_PMA_REG_RX_ALARM_CTRL
,
3823 } else { /* Default 10G. Set only LASI control */
3824 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
3825 ext_phy_addr
, MDIO_PMA_DEVAD
,
3826 MDIO_PMA_REG_LASI_CTRL
, 1);
3829 /* Set TX PreEmphasis if needed */
3830 if ((params
->feature_config_flags
&
3831 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
3832 DP(NETIF_MSG_LINK
, "Setting TX_CTRL1 0x%x,"
3834 params
->xgxs_config_tx
[0],
3835 params
->xgxs_config_tx
[1]);
3836 bnx2x_cl45_write(bp
, params
->port
,
3840 MDIO_PMA_REG_8726_TX_CTRL1
,
3841 params
->xgxs_config_tx
[0]);
3843 bnx2x_cl45_write(bp
, params
->port
,
3847 MDIO_PMA_REG_8726_TX_CTRL2
,
3848 params
->xgxs_config_tx
[1]);
3851 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
3852 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
3855 u16 rx_alarm_ctrl_val
;
3858 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
) {
3859 rx_alarm_ctrl_val
= 0x400;
3860 lasi_ctrl_val
= 0x0004;
3862 rx_alarm_ctrl_val
= (1<<2);
3863 lasi_ctrl_val
= 0x0004;
3867 bnx2x_cl45_write(bp
, params
->port
,
3871 MDIO_PMA_REG_RX_ALARM_CTRL
,
3874 bnx2x_cl45_write(bp
, params
->port
,
3878 MDIO_PMA_REG_LASI_CTRL
,
3881 bnx2x_8073_set_pause_cl37(params
, vars
);
3884 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
){
3885 bnx2x_bcm8072_external_rom_boot(params
);
3888 /* In case of 8073 with long xaui lines,
3889 don't set the 8073 xaui low power*/
3890 bnx2x_bcm8073_set_xaui_low_power_mode(params
);
3893 bnx2x_cl45_read(bp
, params
->port
,
3897 MDIO_PMA_REG_M8051_MSGOUT_REG
,
3900 bnx2x_cl45_read(bp
, params
->port
,
3904 MDIO_PMA_REG_RX_ALARM
, &tmp1
);
3906 DP(NETIF_MSG_LINK
, "Before rom RX_ALARM(port1):"
3909 /* If this is forced speed, set to KR or KX
3910 * (all other are not supported)
3912 if (params
->loopback_mode
== LOOPBACK_EXT
) {
3913 bnx2x_bcm807x_force_10G(params
);
3915 "Forced speed 10G on 807X\n");
3918 bnx2x_cl45_write(bp
, params
->port
,
3919 ext_phy_type
, ext_phy_addr
,
3921 MDIO_PMA_REG_BCM_CTRL
,
3924 if (params
->req_line_speed
!= SPEED_AUTO_NEG
) {
3925 if (params
->req_line_speed
== SPEED_10000
) {
3927 } else if (params
->req_line_speed
==
3930 /* Note that 2.5G works only
3931 when used with 1G advertisment */
3937 if (params
->speed_cap_mask
&
3938 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
3941 /* Note that 2.5G works only when
3942 used with 1G advertisment */
3943 if (params
->speed_cap_mask
&
3944 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
|
3945 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
3948 "807x autoneg val = 0x%x\n", val
);
3951 bnx2x_cl45_write(bp
, params
->port
,
3955 MDIO_AN_REG_ADV
, val
);
3958 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
) {
3960 bnx2x_cl45_read(bp
, params
->port
,
3964 MDIO_AN_REG_8073_2_5G
, &tmp1
);
3966 if (((params
->speed_cap_mask
&
3967 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
) &&
3968 (params
->req_line_speed
==
3970 (params
->req_line_speed
==
3973 /* Allow 2.5G for A1 and above */
3974 bnx2x_cl45_read(bp
, params
->port
,
3975 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
3978 MDIO_PMA_REG_8073_CHIP_REV
, &phy_ver
);
3979 DP(NETIF_MSG_LINK
, "Add 2.5G\n");
3985 DP(NETIF_MSG_LINK
, "Disable 2.5G\n");
3989 bnx2x_cl45_write(bp
, params
->port
,
3993 MDIO_AN_REG_8073_2_5G
, tmp1
);
3996 /* Add support for CL37 (passive mode) II */
3998 bnx2x_cl45_read(bp
, params
->port
,
4002 MDIO_AN_REG_CL37_FC_LD
,
4005 bnx2x_cl45_write(bp
, params
->port
,
4009 MDIO_AN_REG_CL37_FC_LD
, (tmp1
|
4010 ((params
->req_duplex
== DUPLEX_FULL
) ?
4013 /* Add support for CL37 (passive mode) III */
4014 bnx2x_cl45_write(bp
, params
->port
,
4018 MDIO_AN_REG_CL37_AN
, 0x1000);
4021 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
) {
4022 /* The SNR will improve about 2db by changing
4023 BW and FEE main tap. Rest commands are executed
4025 /*Change FFE main cursor to 5 in EDC register*/
4026 if (bnx2x_8073_is_snr_needed(params
))
4027 bnx2x_cl45_write(bp
, params
->port
,
4031 MDIO_PMA_REG_EDC_FFE_MAIN
,
4034 /* Enable FEC (Forware Error Correction)
4035 Request in the AN */
4036 bnx2x_cl45_read(bp
, params
->port
,
4040 MDIO_AN_REG_ADV2
, &tmp1
);
4044 bnx2x_cl45_write(bp
, params
->port
,
4048 MDIO_AN_REG_ADV2
, tmp1
);
4052 bnx2x_ext_phy_set_pause(params
, vars
);
4054 /* Restart autoneg */
4056 bnx2x_cl45_write(bp
, params
->port
,
4060 MDIO_AN_REG_CTRL
, 0x1200);
4061 DP(NETIF_MSG_LINK
, "807x Autoneg Restart: "
4062 "Advertise 1G=%x, 10G=%x\n",
4063 ((val
& (1<<5)) > 0),
4064 ((val
& (1<<7)) > 0));
4068 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
4071 u16 rx_alarm_ctrl_val
;
4074 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
4077 rx_alarm_ctrl_val
= (1<<2) | (1<<5) ;
4078 lasi_ctrl_val
= 0x0004;
4080 DP(NETIF_MSG_LINK
, "Initializing BCM8727\n");
4082 bnx2x_cl45_write(bp
, params
->port
,
4086 MDIO_PMA_REG_RX_ALARM_CTRL
,
4089 bnx2x_cl45_write(bp
, params
->port
,
4093 MDIO_PMA_REG_LASI_CTRL
,
4096 /* Initially configure MOD_ABS to interrupt when
4097 module is presence( bit 8) */
4098 bnx2x_cl45_read(bp
, params
->port
,
4102 MDIO_PMA_REG_PHY_IDENTIFIER
, &mod_abs
);
4103 /* Set EDC off by setting OPTXLOS signal input to low
4105 When the EDC is off it locks onto a reference clock and
4106 avoids becoming 'lost'.*/
4107 mod_abs
&= ~((1<<8) | (1<<9));
4108 bnx2x_cl45_write(bp
, params
->port
,
4112 MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
4114 /* Make MOD_ABS give interrupt on change */
4115 bnx2x_cl45_read(bp
, params
->port
,
4119 MDIO_PMA_REG_8727_PCS_OPT_CTRL
,
4122 bnx2x_cl45_write(bp
, params
->port
,
4126 MDIO_PMA_REG_8727_PCS_OPT_CTRL
,
4129 /* Set 8727 GPIOs to input to allow reading from the
4130 8727 GPIO0 status which reflect SFP+ module
4133 bnx2x_cl45_read(bp
, params
->port
,
4134 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4137 MDIO_PMA_REG_8727_PCS_OPT_CTRL
,
4139 val
&= 0xff8f; /* Reset bits 4-6 */
4140 bnx2x_cl45_write(bp
, params
->port
,
4141 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4144 MDIO_PMA_REG_8727_PCS_OPT_CTRL
,
4147 bnx2x_8727_power_module(bp
, params
, ext_phy_addr
, 1);
4148 bnx2x_bcm8073_set_xaui_low_power_mode(params
);
4150 bnx2x_cl45_read(bp
, params
->port
,
4154 MDIO_PMA_REG_M8051_MSGOUT_REG
,
4157 bnx2x_cl45_read(bp
, params
->port
,
4161 MDIO_PMA_REG_RX_ALARM
, &tmp1
);
4163 /* Set option 1G speed */
4164 if (params
->req_line_speed
== SPEED_1000
) {
4166 DP(NETIF_MSG_LINK
, "Setting 1G force\n");
4167 bnx2x_cl45_write(bp
, params
->port
,
4171 MDIO_PMA_REG_CTRL
, 0x40);
4172 bnx2x_cl45_write(bp
, params
->port
,
4176 MDIO_PMA_REG_10G_CTRL2
, 0xD);
4177 bnx2x_cl45_read(bp
, params
->port
,
4181 MDIO_PMA_REG_10G_CTRL2
, &tmp1
);
4182 DP(NETIF_MSG_LINK
, "1.7 = 0x%x \n", tmp1
);
4184 } else if ((params
->req_line_speed
==
4186 ((params
->speed_cap_mask
&
4187 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
))) {
4189 DP(NETIF_MSG_LINK
, "Setting 1G clause37 \n");
4190 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
4191 ext_phy_addr
, MDIO_AN_DEVAD
,
4192 MDIO_PMA_REG_8727_MISC_CTRL
, 0);
4193 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
4194 ext_phy_addr
, MDIO_AN_DEVAD
,
4195 MDIO_AN_REG_CL37_AN
, 0x1300);
4197 /* Since the 8727 has only single reset pin,
4198 need to set the 10G registers although it is
4200 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
4201 ext_phy_addr
, MDIO_AN_DEVAD
,
4202 MDIO_AN_REG_CTRL
, 0x0020);
4203 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
4204 ext_phy_addr
, MDIO_AN_DEVAD
,
4206 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
4207 ext_phy_addr
, MDIO_PMA_DEVAD
,
4208 MDIO_PMA_REG_CTRL
, 0x2040);
4209 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
4210 ext_phy_addr
, MDIO_PMA_DEVAD
,
4211 MDIO_PMA_REG_10G_CTRL2
, 0x0008);
4214 /* Set 2-wire transfer rate to 400Khz since 100Khz
4215 is not operational */
4216 bnx2x_cl45_write(bp
, params
->port
,
4220 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR
,
4223 /* Set TX PreEmphasis if needed */
4224 if ((params
->feature_config_flags
&
4225 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
4226 DP(NETIF_MSG_LINK
, "Setting TX_CTRL1 0x%x,"
4228 params
->xgxs_config_tx
[0],
4229 params
->xgxs_config_tx
[1]);
4230 bnx2x_cl45_write(bp
, params
->port
,
4234 MDIO_PMA_REG_8727_TX_CTRL1
,
4235 params
->xgxs_config_tx
[0]);
4237 bnx2x_cl45_write(bp
, params
->port
,
4241 MDIO_PMA_REG_8727_TX_CTRL2
,
4242 params
->xgxs_config_tx
[1]);
4248 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
4250 u16 fw_ver1
, fw_ver2
;
4252 "Setting the SFX7101 LASI indication\n");
4254 bnx2x_cl45_write(bp
, params
->port
,
4258 MDIO_PMA_REG_LASI_CTRL
, 0x1);
4260 "Setting the SFX7101 LED to blink on traffic\n");
4261 bnx2x_cl45_write(bp
, params
->port
,
4265 MDIO_PMA_REG_7107_LED_CNTL
, (1<<3));
4267 bnx2x_ext_phy_set_pause(params
, vars
);
4268 /* Restart autoneg */
4269 bnx2x_cl45_read(bp
, params
->port
,
4273 MDIO_AN_REG_CTRL
, &val
);
4275 bnx2x_cl45_write(bp
, params
->port
,
4279 MDIO_AN_REG_CTRL
, val
);
4281 /* Save spirom version */
4282 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4283 ext_phy_addr
, MDIO_PMA_DEVAD
,
4284 MDIO_PMA_REG_7101_VER1
, &fw_ver1
);
4286 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4287 ext_phy_addr
, MDIO_PMA_DEVAD
,
4288 MDIO_PMA_REG_7101_VER2
, &fw_ver2
);
4290 bnx2x_save_spirom_version(params
->bp
, params
->port
,
4292 (u32
)(fw_ver1
<<16 | fw_ver2
));
4296 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
:
4297 /* This phy uses the NIG latch mechanism since link
4298 indication arrives through its LED4 and not via
4299 its LASI signal, so we get steady signal
4300 instead of clear on read */
4301 bnx2x_bits_en(bp
, NIG_REG_LATCH_BC_0
+ params
->port
*4,
4302 1 << NIG_LATCH_BC_ENABLE_MI_INT
);
4304 bnx2x_8481_set_led4(params
, ext_phy_type
, ext_phy_addr
);
4305 if (params
->req_line_speed
== SPEED_AUTO_NEG
) {
4307 u16 autoneg_val
, an_1000_val
, an_10_100_val
;
4308 /* set 1000 speed advertisement */
4309 bnx2x_cl45_read(bp
, params
->port
,
4313 MDIO_AN_REG_8481_1000T_CTRL
,
4316 if (params
->speed_cap_mask
&
4317 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
) {
4318 an_1000_val
|= (1<<8);
4319 if (params
->req_duplex
== DUPLEX_FULL
)
4320 an_1000_val
|= (1<<9);
4321 DP(NETIF_MSG_LINK
, "Advertising 1G\n");
4323 an_1000_val
&= ~((1<<8) | (1<<9));
4325 bnx2x_cl45_write(bp
, params
->port
,
4329 MDIO_AN_REG_8481_1000T_CTRL
,
4332 /* set 100 speed advertisement */
4333 bnx2x_cl45_read(bp
, params
->port
,
4337 MDIO_AN_REG_8481_LEGACY_AN_ADV
,
4340 if (params
->speed_cap_mask
&
4341 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
|
4342 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
)) {
4343 an_10_100_val
|= (1<<7);
4344 if (params
->req_duplex
== DUPLEX_FULL
)
4345 an_10_100_val
|= (1<<8);
4347 "Advertising 100M\n");
4349 an_10_100_val
&= ~((1<<7) | (1<<8));
4351 /* set 10 speed advertisement */
4352 if (params
->speed_cap_mask
&
4353 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
|
4354 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
)) {
4355 an_10_100_val
|= (1<<5);
4356 if (params
->req_duplex
== DUPLEX_FULL
)
4357 an_10_100_val
|= (1<<6);
4358 DP(NETIF_MSG_LINK
, "Advertising 10M\n");
4361 an_10_100_val
&= ~((1<<5) | (1<<6));
4363 bnx2x_cl45_write(bp
, params
->port
,
4367 MDIO_AN_REG_8481_LEGACY_AN_ADV
,
4370 bnx2x_cl45_read(bp
, params
->port
,
4374 MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
4377 /* Disable forced speed */
4378 autoneg_val
&= ~(1<<6|1<<13);
4380 /* Enable autoneg and restart autoneg
4381 for legacy speeds */
4382 autoneg_val
|= (1<<9|1<<12);
4384 if (params
->req_duplex
== DUPLEX_FULL
)
4385 autoneg_val
|= (1<<8);
4387 autoneg_val
&= ~(1<<8);
4389 bnx2x_cl45_write(bp
, params
->port
,
4393 MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
4396 if (params
->speed_cap_mask
&
4397 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
) {
4398 DP(NETIF_MSG_LINK
, "Advertising 10G\n");
4399 /* Restart autoneg for 10G*/
4400 bnx2x_cl45_read(bp
, params
->port
,
4404 MDIO_AN_REG_CTRL
, &val
);
4406 bnx2x_cl45_write(bp
, params
->port
,
4410 MDIO_AN_REG_CTRL
, val
);
4414 u16 autoneg_ctrl
, pma_ctrl
;
4415 bnx2x_cl45_read(bp
, params
->port
,
4419 MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
4422 /* Disable autoneg */
4423 autoneg_ctrl
&= ~(1<<12);
4425 /* Set 1000 force */
4426 switch (params
->req_line_speed
) {
4429 "Unable to set 10G force !\n");
4432 bnx2x_cl45_read(bp
, params
->port
,
4438 autoneg_ctrl
&= ~(1<<13);
4439 autoneg_ctrl
|= (1<<6);
4440 pma_ctrl
&= ~(1<<13);
4443 "Setting 1000M force\n");
4444 bnx2x_cl45_write(bp
, params
->port
,
4452 autoneg_ctrl
|= (1<<13);
4453 autoneg_ctrl
&= ~(1<<6);
4455 "Setting 100M force\n");
4458 autoneg_ctrl
&= ~(1<<13);
4459 autoneg_ctrl
&= ~(1<<6);
4461 "Setting 10M force\n");
4466 if (params
->req_duplex
== DUPLEX_FULL
) {
4467 autoneg_ctrl
|= (1<<8);
4469 "Setting full duplex\n");
4471 autoneg_ctrl
&= ~(1<<8);
4473 /* Update autoneg ctrl and pma ctrl */
4474 bnx2x_cl45_write(bp
, params
->port
,
4478 MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
4482 /* Save spirom version */
4483 bnx2x_save_8481_spirom_version(bp
, params
->port
,
4485 params
->shmem_base
);
4487 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
4489 "XGXS PHY Failure detected 0x%x\n",
4490 params
->ext_phy_config
);
4494 DP(NETIF_MSG_LINK
, "BAD XGXS ext_phy_config 0x%x\n",
4495 params
->ext_phy_config
);
4500 } else { /* SerDes */
4502 ext_phy_type
= SERDES_EXT_PHY_TYPE(params
->ext_phy_config
);
4503 switch (ext_phy_type
) {
4504 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
:
4505 DP(NETIF_MSG_LINK
, "SerDes Direct\n");
4508 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482
:
4509 DP(NETIF_MSG_LINK
, "SerDes 5482\n");
4513 DP(NETIF_MSG_LINK
, "BAD SerDes ext_phy_config 0x%x\n",
4514 params
->ext_phy_config
);
4521 static void bnx2x_8727_handle_mod_abs(struct link_params
*params
)
4523 struct bnx2x
*bp
= params
->bp
;
4524 u16 mod_abs
, rx_alarm_status
;
4525 u8 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
4526 u32 val
= REG_RD(bp
, params
->shmem_base
+
4527 offsetof(struct shmem_region
, dev_info
.
4528 port_feature_config
[params
->port
].
4530 bnx2x_cl45_read(bp
, params
->port
,
4531 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4534 MDIO_PMA_REG_PHY_IDENTIFIER
, &mod_abs
);
4535 if (mod_abs
& (1<<8)) {
4537 /* Module is absent */
4538 DP(NETIF_MSG_LINK
, "MOD_ABS indication "
4539 "show module is absent\n");
4541 /* 1. Set mod_abs to detect next module
4543 2. Set EDC off by setting OPTXLOS signal input to low
4545 When the EDC is off it locks onto a reference clock and
4546 avoids becoming 'lost'.*/
4547 mod_abs
&= ~((1<<8)|(1<<9));
4548 bnx2x_cl45_write(bp
, params
->port
,
4549 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4552 MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
4554 /* Clear RX alarm since it stays up as long as
4555 the mod_abs wasn't changed */
4556 bnx2x_cl45_read(bp
, params
->port
,
4557 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4560 MDIO_PMA_REG_RX_ALARM
, &rx_alarm_status
);
4563 /* Module is present */
4564 DP(NETIF_MSG_LINK
, "MOD_ABS indication "
4565 "show module is present\n");
4566 /* First thing, disable transmitter,
4567 and if the module is ok, the
4568 module_detection will enable it*/
4570 /* 1. Set mod_abs to detect next module
4571 absent event ( bit 8)
4572 2. Restore the default polarity of the OPRXLOS signal and
4573 this signal will then correctly indicate the presence or
4574 absence of the Rx signal. (bit 9) */
4575 mod_abs
|= ((1<<8)|(1<<9));
4576 bnx2x_cl45_write(bp
, params
->port
,
4577 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4580 MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
4582 /* Clear RX alarm since it stays up as long as
4583 the mod_abs wasn't changed. This is need to be done
4584 before calling the module detection, otherwise it will clear
4585 the link update alarm */
4586 bnx2x_cl45_read(bp
, params
->port
,
4587 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4590 MDIO_PMA_REG_RX_ALARM
, &rx_alarm_status
);
4593 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
4594 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
)
4595 bnx2x_sfp_set_transmitter(bp
, params
->port
,
4596 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
4599 if (bnx2x_wait_for_sfp_module_initialized(params
)
4601 bnx2x_sfp_module_detection(params
);
4603 DP(NETIF_MSG_LINK
, "SFP+ module is not initialized\n");
4606 DP(NETIF_MSG_LINK
, "8727 RX_ALARM_STATUS 0x%x\n",
4608 /* No need to check link status in case of
4609 module plugged in/out */
4613 static u8
bnx2x_ext_phy_is_link_up(struct link_params
*params
,
4614 struct link_vars
*vars
,
4617 struct bnx2x
*bp
= params
->bp
;
4621 u16 rx_sd
, pcs_status
;
4622 u8 ext_phy_link_up
= 0;
4623 u8 port
= params
->port
;
4624 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
4625 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
4626 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
4627 switch (ext_phy_type
) {
4628 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
4629 DP(NETIF_MSG_LINK
, "XGXS Direct\n");
4630 ext_phy_link_up
= 1;
4633 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
:
4634 DP(NETIF_MSG_LINK
, "XGXS 8705\n");
4635 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4638 MDIO_WIS_REG_LASI_STATUS
, &val1
);
4639 DP(NETIF_MSG_LINK
, "8705 LASI status 0x%x\n", val1
);
4641 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4644 MDIO_WIS_REG_LASI_STATUS
, &val1
);
4645 DP(NETIF_MSG_LINK
, "8705 LASI status 0x%x\n", val1
);
4647 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4650 MDIO_PMA_REG_RX_SD
, &rx_sd
);
4652 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4656 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4661 DP(NETIF_MSG_LINK
, "8705 1.c809 val=0x%x\n", val1
);
4662 ext_phy_link_up
= ((rx_sd
& 0x1) && (val1
& (1<<9))
4663 && ((val1
& (1<<8)) == 0));
4664 if (ext_phy_link_up
)
4665 vars
->line_speed
= SPEED_10000
;
4668 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
:
4669 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
4670 DP(NETIF_MSG_LINK
, "XGXS 8706/8726\n");
4672 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4674 MDIO_PMA_DEVAD
, MDIO_PMA_REG_RX_ALARM
,
4676 /* clear LASI indication*/
4677 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4679 MDIO_PMA_DEVAD
, MDIO_PMA_REG_LASI_STATUS
,
4681 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4683 MDIO_PMA_DEVAD
, MDIO_PMA_REG_LASI_STATUS
,
4685 DP(NETIF_MSG_LINK
, "8706/8726 LASI status 0x%x-->"
4686 "0x%x\n", val1
, val2
);
4688 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4690 MDIO_PMA_DEVAD
, MDIO_PMA_REG_RX_SD
,
4692 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4694 MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
,
4696 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4698 MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
,
4700 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
4702 MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
,
4705 DP(NETIF_MSG_LINK
, "8706/8726 rx_sd 0x%x"
4706 " pcs_status 0x%x 1Gbps link_status 0x%x\n",
4707 rx_sd
, pcs_status
, val2
);
4708 /* link is up if both bit 0 of pmd_rx_sd and
4709 * bit 0 of pcs_status are set, or if the autoneg bit
4712 ext_phy_link_up
= ((rx_sd
& pcs_status
& 0x1) ||
4714 if (ext_phy_link_up
) {
4716 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
) {
4717 /* If transmitter is disabled,
4718 ignore false link up indication */
4719 bnx2x_cl45_read(bp
, params
->port
,
4723 MDIO_PMA_REG_PHY_IDENTIFIER
,
4725 if (val1
& (1<<15)) {
4726 DP(NETIF_MSG_LINK
, "Tx is "
4728 ext_phy_link_up
= 0;
4734 vars
->line_speed
= SPEED_1000
;
4736 vars
->line_speed
= SPEED_10000
;
4740 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
4742 u16 link_status
= 0;
4743 u16 rx_alarm_status
;
4744 /* Check the LASI */
4745 bnx2x_cl45_read(bp
, params
->port
,
4749 MDIO_PMA_REG_RX_ALARM
, &rx_alarm_status
);
4751 DP(NETIF_MSG_LINK
, "8727 RX_ALARM_STATUS 0x%x\n",
4754 bnx2x_cl45_read(bp
, params
->port
,
4758 MDIO_PMA_REG_LASI_STATUS
, &val1
);
4761 "8727 LASI status 0x%x\n",
4765 bnx2x_cl45_read(bp
, params
->port
,
4769 MDIO_PMA_REG_M8051_MSGOUT_REG
,
4773 * If a module is present and there is need to check
4776 if (!(params
->feature_config_flags
&
4777 FEATURE_CONFIG_BCM8727_NOC
) &&
4778 !(rx_alarm_status
& (1<<5))) {
4779 /* Check over-current using 8727 GPIO0 input*/
4780 bnx2x_cl45_read(bp
, params
->port
,
4784 MDIO_PMA_REG_8727_GPIO_CTRL
,
4787 if ((val1
& (1<<8)) == 0) {
4788 DP(NETIF_MSG_LINK
, "8727 Power fault"
4789 " has been detected on port"
4790 " %d\n", params
->port
);
4791 printk(KERN_ERR PFX
"Error: Power"
4792 " fault on %s Port %d has"
4793 " been detected and the"
4794 " power to that SFP+ module"
4795 " has been removed to prevent"
4796 " failure of the card. Please"
4797 " remove the SFP+ module and"
4798 " restart the system to clear"
4800 , bp
->dev
->name
, params
->port
);
4802 * Disable all RX_ALARMs except for
4805 bnx2x_cl45_write(bp
, params
->port
,
4809 MDIO_PMA_REG_RX_ALARM_CTRL
,
4812 bnx2x_cl45_read(bp
, params
->port
,
4816 MDIO_PMA_REG_PHY_IDENTIFIER
,
4818 /* Wait for module_absent_event */
4820 bnx2x_cl45_write(bp
, params
->port
,
4824 MDIO_PMA_REG_PHY_IDENTIFIER
,
4826 /* Clear RX alarm */
4827 bnx2x_cl45_read(bp
, params
->port
,
4831 MDIO_PMA_REG_RX_ALARM
,
4835 } /* Over current check */
4837 /* When module absent bit is set, check module */
4838 if (rx_alarm_status
& (1<<5)) {
4839 bnx2x_8727_handle_mod_abs(params
);
4840 /* Enable all mod_abs and link detection bits */
4841 bnx2x_cl45_write(bp
, params
->port
,
4845 MDIO_PMA_REG_RX_ALARM_CTRL
,
4849 /* If transmitter is disabled,
4850 ignore false link up indication */
4851 bnx2x_cl45_read(bp
, params
->port
,
4855 MDIO_PMA_REG_PHY_IDENTIFIER
,
4857 if (val1
& (1<<15)) {
4858 DP(NETIF_MSG_LINK
, "Tx is disabled\n");
4859 ext_phy_link_up
= 0;
4863 bnx2x_cl45_read(bp
, params
->port
,
4867 MDIO_PMA_REG_8073_SPEED_LINK_STATUS
,
4870 /* Bits 0..2 --> speed detected,
4871 bits 13..15--> link is down */
4872 if ((link_status
& (1<<2)) &&
4873 (!(link_status
& (1<<15)))) {
4874 ext_phy_link_up
= 1;
4875 vars
->line_speed
= SPEED_10000
;
4876 } else if ((link_status
& (1<<0)) &&
4877 (!(link_status
& (1<<13)))) {
4878 ext_phy_link_up
= 1;
4879 vars
->line_speed
= SPEED_1000
;
4881 "port %x: External link"
4882 " up in 1G\n", params
->port
);
4884 ext_phy_link_up
= 0;
4886 "port %x: External link"
4887 " is down\n", params
->port
);
4892 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
4893 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
4895 u16 link_status
= 0;
4896 u16 an1000_status
= 0;
4898 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
) {
4899 bnx2x_cl45_read(bp
, params
->port
,
4903 MDIO_PCS_REG_LASI_STATUS
, &val1
);
4904 bnx2x_cl45_read(bp
, params
->port
,
4908 MDIO_PCS_REG_LASI_STATUS
, &val2
);
4910 "870x LASI status 0x%x->0x%x\n",
4914 /* In 8073, port1 is directed through emac0 and
4915 * port0 is directed through emac1
4917 bnx2x_cl45_read(bp
, params
->port
,
4921 MDIO_PMA_REG_LASI_STATUS
, &val1
);
4924 "8703 LASI status 0x%x\n",
4928 /* clear the interrupt LASI status register */
4929 bnx2x_cl45_read(bp
, params
->port
,
4933 MDIO_PCS_REG_STATUS
, &val2
);
4934 bnx2x_cl45_read(bp
, params
->port
,
4938 MDIO_PCS_REG_STATUS
, &val1
);
4939 DP(NETIF_MSG_LINK
, "807x PCS status 0x%x->0x%x\n",
4942 bnx2x_cl45_read(bp
, params
->port
,
4946 MDIO_PMA_REG_M8051_MSGOUT_REG
,
4949 /* Check the LASI */
4950 bnx2x_cl45_read(bp
, params
->port
,
4954 MDIO_PMA_REG_RX_ALARM
, &val2
);
4956 DP(NETIF_MSG_LINK
, "KR 0x9003 0x%x\n", val2
);
4958 /* Check the link status */
4959 bnx2x_cl45_read(bp
, params
->port
,
4963 MDIO_PCS_REG_STATUS
, &val2
);
4964 DP(NETIF_MSG_LINK
, "KR PCS status 0x%x\n", val2
);
4966 bnx2x_cl45_read(bp
, params
->port
,
4970 MDIO_PMA_REG_STATUS
, &val2
);
4971 bnx2x_cl45_read(bp
, params
->port
,
4975 MDIO_PMA_REG_STATUS
, &val1
);
4976 ext_phy_link_up
= ((val1
& 4) == 4);
4977 DP(NETIF_MSG_LINK
, "PMA_REG_STATUS=0x%x\n", val1
);
4979 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
) {
4981 if (ext_phy_link_up
&&
4982 ((params
->req_line_speed
!=
4984 if (bnx2x_bcm8073_xaui_wa(params
)
4986 ext_phy_link_up
= 0;
4990 bnx2x_cl45_read(bp
, params
->port
,
4994 MDIO_AN_REG_LINK_STATUS
,
4996 bnx2x_cl45_read(bp
, params
->port
,
5000 MDIO_AN_REG_LINK_STATUS
,
5003 /* Check the link status on 1.1.2 */
5004 bnx2x_cl45_read(bp
, params
->port
,
5008 MDIO_PMA_REG_STATUS
, &val2
);
5009 bnx2x_cl45_read(bp
, params
->port
,
5013 MDIO_PMA_REG_STATUS
, &val1
);
5014 DP(NETIF_MSG_LINK
, "KR PMA status 0x%x->0x%x,"
5015 "an_link_status=0x%x\n",
5016 val2
, val1
, an1000_status
);
5018 ext_phy_link_up
= (((val1
& 4) == 4) ||
5019 (an1000_status
& (1<<1)));
5020 if (ext_phy_link_up
&&
5021 bnx2x_8073_is_snr_needed(params
)) {
5022 /* The SNR will improve about 2dbby
5023 changing the BW and FEE main tap.*/
5025 /* The 1st write to change FFE main
5026 tap is set before restart AN */
5027 /* Change PLL Bandwidth in EDC
5029 bnx2x_cl45_write(bp
, port
, ext_phy_type
,
5032 MDIO_PMA_REG_PLL_BANDWIDTH
,
5035 /* Change CDR Bandwidth in EDC
5037 bnx2x_cl45_write(bp
, port
, ext_phy_type
,
5040 MDIO_PMA_REG_CDR_BANDWIDTH
,
5045 bnx2x_cl45_read(bp
, params
->port
,
5049 MDIO_PMA_REG_8073_SPEED_LINK_STATUS
,
5052 /* Bits 0..2 --> speed detected,
5053 bits 13..15--> link is down */
5054 if ((link_status
& (1<<2)) &&
5055 (!(link_status
& (1<<15)))) {
5056 ext_phy_link_up
= 1;
5057 vars
->line_speed
= SPEED_10000
;
5059 "port %x: External link"
5060 " up in 10G\n", params
->port
);
5061 } else if ((link_status
& (1<<1)) &&
5062 (!(link_status
& (1<<14)))) {
5063 ext_phy_link_up
= 1;
5064 vars
->line_speed
= SPEED_2500
;
5066 "port %x: External link"
5067 " up in 2.5G\n", params
->port
);
5068 } else if ((link_status
& (1<<0)) &&
5069 (!(link_status
& (1<<13)))) {
5070 ext_phy_link_up
= 1;
5071 vars
->line_speed
= SPEED_1000
;
5073 "port %x: External link"
5074 " up in 1G\n", params
->port
);
5076 ext_phy_link_up
= 0;
5078 "port %x: External link"
5079 " is down\n", params
->port
);
5082 /* See if 1G link is up for the 8072 */
5083 bnx2x_cl45_read(bp
, params
->port
,
5087 MDIO_AN_REG_LINK_STATUS
,
5089 bnx2x_cl45_read(bp
, params
->port
,
5093 MDIO_AN_REG_LINK_STATUS
,
5095 if (an1000_status
& (1<<1)) {
5096 ext_phy_link_up
= 1;
5097 vars
->line_speed
= SPEED_1000
;
5099 "port %x: External link"
5100 " up in 1G\n", params
->port
);
5101 } else if (ext_phy_link_up
) {
5102 ext_phy_link_up
= 1;
5103 vars
->line_speed
= SPEED_10000
;
5105 "port %x: External link"
5106 " up in 10G\n", params
->port
);
5113 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
5114 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
5117 MDIO_PMA_REG_LASI_STATUS
, &val2
);
5118 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
5121 MDIO_PMA_REG_LASI_STATUS
, &val1
);
5123 "10G-base-T LASI status 0x%x->0x%x\n",
5125 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
5128 MDIO_PMA_REG_STATUS
, &val2
);
5129 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
5132 MDIO_PMA_REG_STATUS
, &val1
);
5134 "10G-base-T PMA status 0x%x->0x%x\n",
5136 ext_phy_link_up
= ((val1
& 4) == 4);
5138 * print the AN outcome of the SFX7101 PHY
5140 if (ext_phy_link_up
) {
5141 bnx2x_cl45_read(bp
, params
->port
,
5145 MDIO_AN_REG_MASTER_STATUS
,
5147 vars
->line_speed
= SPEED_10000
;
5149 "SFX7101 AN status 0x%x->Master=%x\n",
5154 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
:
5155 /* Check 10G-BaseT link status */
5156 /* Check PMD signal ok */
5157 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
5162 bnx2x_cl45_read(bp
, params
->port
, ext_phy_type
,
5165 MDIO_PMA_REG_8481_PMD_SIGNAL
,
5167 DP(NETIF_MSG_LINK
, "PMD_SIGNAL 1.a811 = 0x%x\n", val2
);
5169 /* Check link 10G */
5170 if (val2
& (1<<11)) {
5171 vars
->line_speed
= SPEED_10000
;
5172 ext_phy_link_up
= 1;
5173 bnx2x_8481_set_10G_led_mode(params
,
5176 } else { /* Check Legacy speed link */
5177 u16 legacy_status
, legacy_speed
;
5179 /* Enable expansion register 0x42
5180 (Operation mode status) */
5181 bnx2x_cl45_write(bp
, params
->port
,
5185 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS
,
5188 /* Get legacy speed operation status */
5189 bnx2x_cl45_read(bp
, params
->port
,
5193 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW
,
5196 DP(NETIF_MSG_LINK
, "Legacy speed status"
5197 " = 0x%x\n", legacy_status
);
5198 ext_phy_link_up
= ((legacy_status
& (1<<11))
5200 if (ext_phy_link_up
) {
5201 legacy_speed
= (legacy_status
& (3<<9));
5202 if (legacy_speed
== (0<<9))
5203 vars
->line_speed
= SPEED_10
;
5204 else if (legacy_speed
== (1<<9))
5207 else if (legacy_speed
== (2<<9))
5210 else /* Should not happen */
5211 vars
->line_speed
= 0;
5213 if (legacy_status
& (1<<8))
5214 vars
->duplex
= DUPLEX_FULL
;
5216 vars
->duplex
= DUPLEX_HALF
;
5218 DP(NETIF_MSG_LINK
, "Link is up "
5219 "in %dMbps, is_duplex_full"
5222 (vars
->duplex
== DUPLEX_FULL
));
5223 bnx2x_8481_set_legacy_led_mode(params
,
5231 DP(NETIF_MSG_LINK
, "BAD XGXS ext_phy_config 0x%x\n",
5232 params
->ext_phy_config
);
5233 ext_phy_link_up
= 0;
5236 /* Set SGMII mode for external phy */
5237 if (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) {
5238 if (vars
->line_speed
< SPEED_1000
)
5239 vars
->phy_flags
|= PHY_SGMII_FLAG
;
5241 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
5244 } else { /* SerDes */
5245 ext_phy_type
= SERDES_EXT_PHY_TYPE(params
->ext_phy_config
);
5246 switch (ext_phy_type
) {
5247 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
:
5248 DP(NETIF_MSG_LINK
, "SerDes Direct\n");
5249 ext_phy_link_up
= 1;
5252 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482
:
5253 DP(NETIF_MSG_LINK
, "SerDes 5482\n");
5254 ext_phy_link_up
= 1;
5259 "BAD SerDes ext_phy_config 0x%x\n",
5260 params
->ext_phy_config
);
5261 ext_phy_link_up
= 0;
5266 return ext_phy_link_up
;
5269 static void bnx2x_link_int_enable(struct link_params
*params
)
5271 u8 port
= params
->port
;
5274 struct bnx2x
*bp
= params
->bp
;
5275 /* setting the status to report on link up
5276 for either XGXS or SerDes */
5278 if (params
->switch_cfg
== SWITCH_CFG_10G
) {
5279 mask
= (NIG_MASK_XGXS0_LINK10G
|
5280 NIG_MASK_XGXS0_LINK_STATUS
);
5281 DP(NETIF_MSG_LINK
, "enabled XGXS interrupt\n");
5282 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
5283 if ((ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) &&
5284 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) &&
5286 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
)) {
5287 mask
|= NIG_MASK_MI_INT
;
5288 DP(NETIF_MSG_LINK
, "enabled external phy int\n");
5291 } else { /* SerDes */
5292 mask
= NIG_MASK_SERDES0_LINK_STATUS
;
5293 DP(NETIF_MSG_LINK
, "enabled SerDes interrupt\n");
5294 ext_phy_type
= SERDES_EXT_PHY_TYPE(params
->ext_phy_config
);
5295 if ((ext_phy_type
!=
5296 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
) &&
5298 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN
)) {
5299 mask
|= NIG_MASK_MI_INT
;
5300 DP(NETIF_MSG_LINK
, "enabled external phy int\n");
5304 NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4,
5306 DP(NETIF_MSG_LINK
, "port %x, is_xgxs=%x, int_status 0x%x\n", port
,
5307 (params
->switch_cfg
== SWITCH_CFG_10G
),
5308 REG_RD(bp
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4));
5310 DP(NETIF_MSG_LINK
, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5311 REG_RD(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4),
5312 REG_RD(bp
, NIG_REG_EMAC0_STATUS_MISC_MI_INT
+ port
*0x18),
5313 REG_RD(bp
, NIG_REG_SERDES0_STATUS_LINK_STATUS
+port
*0x3c));
5314 DP(NETIF_MSG_LINK
, " 10G %x, XGXS_LINK %x\n",
5315 REG_RD(bp
, NIG_REG_XGXS0_STATUS_LINK10G
+ port
*0x68),
5316 REG_RD(bp
, NIG_REG_XGXS0_STATUS_LINK_STATUS
+ port
*0x68));
5319 static void bnx2x_8481_rearm_latch_signal(struct bnx2x
*bp
, u8 port
,
5322 u32 latch_status
= 0, is_mi_int_status
;
5323 /* Disable the MI INT ( external phy int )
5324 * by writing 1 to the status register. Link down indication
5325 * is high-active-signal, so in this case we need to write the
5326 * status to clear the XOR
5328 /* Read Latched signals */
5329 latch_status
= REG_RD(bp
,
5330 NIG_REG_LATCH_STATUS_0
+ port
*8);
5331 is_mi_int_status
= REG_RD(bp
,
5332 NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4);
5333 DP(NETIF_MSG_LINK
, "original_signal = 0x%x, nig_status = 0x%x,"
5334 "latch_status = 0x%x\n",
5335 is_mi_int
, is_mi_int_status
, latch_status
);
5336 /* Handle only those with latched-signal=up.*/
5337 if (latch_status
& 1) {
5338 /* For all latched-signal=up,Write original_signal to status */
5341 NIG_REG_STATUS_INTERRUPT_PORT0
5343 NIG_STATUS_EMAC0_MI_INT
);
5346 NIG_REG_STATUS_INTERRUPT_PORT0
5348 NIG_STATUS_EMAC0_MI_INT
);
5349 /* For all latched-signal=up : Re-Arm Latch signals */
5350 REG_WR(bp
, NIG_REG_LATCH_STATUS_0
+ port
*8,
5351 (latch_status
& 0xfffe) | (latch_status
& 1));
5357 static void bnx2x_link_int_ack(struct link_params
*params
,
5358 struct link_vars
*vars
, u8 is_10g
,
5361 struct bnx2x
*bp
= params
->bp
;
5362 u8 port
= params
->port
;
5364 /* first reset all status
5365 * we assume only one line will be change at a time */
5366 bnx2x_bits_dis(bp
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4,
5367 (NIG_STATUS_XGXS0_LINK10G
|
5368 NIG_STATUS_XGXS0_LINK_STATUS
|
5369 NIG_STATUS_SERDES0_LINK_STATUS
));
5370 if (XGXS_EXT_PHY_TYPE(params
->ext_phy_config
)
5371 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
) {
5372 bnx2x_8481_rearm_latch_signal(bp
, port
, is_mi_int
);
5374 if (vars
->phy_link_up
) {
5376 /* Disable the 10G link interrupt
5377 * by writing 1 to the status register
5379 DP(NETIF_MSG_LINK
, "10G XGXS phy link up\n");
5381 NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4,
5382 NIG_STATUS_XGXS0_LINK10G
);
5384 } else if (params
->switch_cfg
== SWITCH_CFG_10G
) {
5385 /* Disable the link interrupt
5386 * by writing 1 to the relevant lane
5387 * in the status register
5389 u32 ser_lane
= ((params
->lane_config
&
5390 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
5391 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
5393 DP(NETIF_MSG_LINK
, "%d speed XGXS phy link up\n",
5396 NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4,
5398 NIG_STATUS_XGXS0_LINK_STATUS_SIZE
));
5400 } else { /* SerDes */
5401 DP(NETIF_MSG_LINK
, "SerDes phy link up\n");
5402 /* Disable the link interrupt
5403 * by writing 1 to the status register
5406 NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4,
5407 NIG_STATUS_SERDES0_LINK_STATUS
);
5410 } else { /* link_down */
5414 static u8
bnx2x_format_ver(u32 num
, u8
*str
, u16 len
)
5417 u32 mask
= 0xf0000000;
5421 /* Need more than 10chars for this format */
5428 digit
= ((num
& mask
) >> shift
);
5430 *str_ptr
= digit
+ '0';
5432 *str_ptr
= digit
- 0xa + 'a';
5444 u8
bnx2x_get_ext_phy_fw_version(struct link_params
*params
, u8 driver_loaded
,
5445 u8
*version
, u16 len
)
5448 u32 ext_phy_type
= 0;
5452 if (version
== NULL
|| params
== NULL
)
5456 spirom_ver
= REG_RD(bp
, params
->shmem_base
+
5457 offsetof(struct shmem_region
,
5458 port_mb
[params
->port
].ext_phy_fw_version
));
5461 /* reset the returned value to zero */
5462 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
5463 switch (ext_phy_type
) {
5464 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
5469 version
[0] = (spirom_ver
& 0xFF);
5470 version
[1] = (spirom_ver
& 0xFF00) >> 8;
5471 version
[2] = (spirom_ver
& 0xFF0000) >> 16;
5472 version
[3] = (spirom_ver
& 0xFF000000) >> 24;
5476 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
5477 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
5478 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
5479 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
:
5480 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
5481 status
= bnx2x_format_ver(spirom_ver
, version
, len
);
5483 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
:
5484 spirom_ver
= ((spirom_ver
& 0xF80) >> 7) << 16 |
5485 (spirom_ver
& 0x7F);
5486 status
= bnx2x_format_ver(spirom_ver
, version
, len
);
5488 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
5489 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
:
5493 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
5494 DP(NETIF_MSG_LINK
, "bnx2x_get_ext_phy_fw_version:"
5495 " type is FAILURE!\n");
5505 static void bnx2x_set_xgxs_loopback(struct link_params
*params
,
5506 struct link_vars
*vars
,
5509 u8 port
= params
->port
;
5510 struct bnx2x
*bp
= params
->bp
;
5515 DP(NETIF_MSG_LINK
, "XGXS 10G loopback enable\n");
5517 /* change the uni_phy_addr in the nig */
5518 md_devad
= REG_RD(bp
, (NIG_REG_XGXS0_CTRL_MD_DEVAD
+
5521 REG_WR(bp
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ port
*0x18, 0x5);
5523 bnx2x_cl45_write(bp
, port
, 0,
5526 (MDIO_REG_BANK_AER_BLOCK
+
5527 (MDIO_AER_BLOCK_AER_REG
& 0xf)),
5530 bnx2x_cl45_write(bp
, port
, 0,
5533 (MDIO_REG_BANK_CL73_IEEEB0
+
5534 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL
& 0xf)),
5537 /* set aer mmd back */
5538 bnx2x_set_aer_mmd(params
, vars
);
5541 REG_WR(bp
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ port
*0x18,
5547 DP(NETIF_MSG_LINK
, "XGXS 1G loopback enable\n");
5549 CL45_RD_OVER_CL22(bp
, port
,
5551 MDIO_REG_BANK_COMBO_IEEE0
,
5552 MDIO_COMBO_IEEE0_MII_CONTROL
,
5555 CL45_WR_OVER_CL22(bp
, port
,
5557 MDIO_REG_BANK_COMBO_IEEE0
,
5558 MDIO_COMBO_IEEE0_MII_CONTROL
,
5560 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK
));
5565 static void bnx2x_ext_phy_loopback(struct link_params
*params
)
5567 struct bnx2x
*bp
= params
->bp
;
5571 if (params
->switch_cfg
== SWITCH_CFG_10G
) {
5572 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
5573 ext_phy_addr
= XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
5574 /* CL37 Autoneg Enabled */
5575 switch (ext_phy_type
) {
5576 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
5577 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
:
5579 "ext_phy_loopback: We should not get here\n");
5581 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
:
5582 DP(NETIF_MSG_LINK
, "ext_phy_loopback: 8705\n");
5584 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
:
5585 DP(NETIF_MSG_LINK
, "ext_phy_loopback: 8706\n");
5587 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
5588 DP(NETIF_MSG_LINK
, "PMA/PMD ext_phy_loopback: 8726\n");
5589 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
5595 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
5596 /* SFX7101_XGXS_TEST1 */
5597 bnx2x_cl45_write(bp
, params
->port
, ext_phy_type
,
5600 MDIO_XS_SFX7101_XGXS_TEST1
,
5603 "ext_phy_loopback: set ext phy loopback\n");
5605 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
5608 } /* switch external PHY type */
5611 ext_phy_type
= SERDES_EXT_PHY_TYPE(params
->ext_phy_config
);
5612 ext_phy_addr
= (params
->ext_phy_config
&
5613 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK
)
5614 >> PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT
;
5620 *------------------------------------------------------------------------
5621 * bnx2x_override_led_value -
5623 * Override the led value of the requsted led
5625 *------------------------------------------------------------------------
5627 u8
bnx2x_override_led_value(struct bnx2x
*bp
, u8 port
,
5628 u32 led_idx
, u32 value
)
5632 /* If port 0 then use EMAC0, else use EMAC1*/
5633 u32 emac_base
= (port
) ? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
5636 "bnx2x_override_led_value() port %x led_idx %d value %d\n",
5637 port
, led_idx
, value
);
5640 case 0: /* 10MB led */
5641 /* Read the current value of the LED register in
5643 reg_val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_LED
);
5644 /* Set the OVERRIDE bit to 1 */
5645 reg_val
|= EMAC_LED_OVERRIDE
;
5646 /* If value is 1, set the 10M_OVERRIDE bit,
5647 otherwise reset it.*/
5648 reg_val
= (value
== 1) ? (reg_val
| EMAC_LED_10MB_OVERRIDE
) :
5649 (reg_val
& ~EMAC_LED_10MB_OVERRIDE
);
5650 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_LED
, reg_val
);
5652 case 1: /*100MB led */
5653 /*Read the current value of the LED register in
5655 reg_val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_LED
);
5656 /* Set the OVERRIDE bit to 1 */
5657 reg_val
|= EMAC_LED_OVERRIDE
;
5658 /* If value is 1, set the 100M_OVERRIDE bit,
5659 otherwise reset it.*/
5660 reg_val
= (value
== 1) ? (reg_val
| EMAC_LED_100MB_OVERRIDE
) :
5661 (reg_val
& ~EMAC_LED_100MB_OVERRIDE
);
5662 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_LED
, reg_val
);
5664 case 2: /* 1000MB led */
5665 /* Read the current value of the LED register in the
5667 reg_val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_LED
);
5668 /* Set the OVERRIDE bit to 1 */
5669 reg_val
|= EMAC_LED_OVERRIDE
;
5670 /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
5672 reg_val
= (value
== 1) ? (reg_val
| EMAC_LED_1000MB_OVERRIDE
) :
5673 (reg_val
& ~EMAC_LED_1000MB_OVERRIDE
);
5674 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_LED
, reg_val
);
5676 case 3: /* 2500MB led */
5677 /* Read the current value of the LED register in the
5679 reg_val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_LED
);
5680 /* Set the OVERRIDE bit to 1 */
5681 reg_val
|= EMAC_LED_OVERRIDE
;
5682 /* If value is 1, set the 2500M_OVERRIDE bit, otherwise
5684 reg_val
= (value
== 1) ? (reg_val
| EMAC_LED_2500MB_OVERRIDE
) :
5685 (reg_val
& ~EMAC_LED_2500MB_OVERRIDE
);
5686 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_LED
, reg_val
);
5688 case 4: /*10G led */
5690 REG_WR(bp
, NIG_REG_LED_10G_P0
,
5693 REG_WR(bp
, NIG_REG_LED_10G_P1
,
5697 case 5: /* TRAFFIC led */
5698 /* Find if the traffic control is via BMAC or EMAC */
5700 reg_val
= REG_RD(bp
, NIG_REG_NIG_EMAC0_EN
);
5702 reg_val
= REG_RD(bp
, NIG_REG_NIG_EMAC1_EN
);
5704 /* Override the traffic led in the EMAC:*/
5706 /* Read the current value of the LED register in
5708 reg_val
= REG_RD(bp
, emac_base
+
5710 /* Set the TRAFFIC_OVERRIDE bit to 1 */
5711 reg_val
|= EMAC_LED_OVERRIDE
;
5712 /* If value is 1, set the TRAFFIC bit, otherwise
5714 reg_val
= (value
== 1) ? (reg_val
| EMAC_LED_TRAFFIC
) :
5715 (reg_val
& ~EMAC_LED_TRAFFIC
);
5716 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_LED
, reg_val
);
5717 } else { /* Override the traffic led in the BMAC: */
5718 REG_WR(bp
, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5720 REG_WR(bp
, NIG_REG_LED_CONTROL_TRAFFIC_P0
+ port
*4,
5726 "bnx2x_override_led_value() unknown led index %d "
5727 "(should be 0-5)\n", led_idx
);
5735 u8
bnx2x_set_led(struct bnx2x
*bp
, u8 port
, u8 mode
, u32 speed
,
5736 u16 hw_led_mode
, u32 chip_id
)
5740 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
5741 DP(NETIF_MSG_LINK
, "bnx2x_set_led: port %x, mode %d\n", port
, mode
);
5742 DP(NETIF_MSG_LINK
, "speed 0x%x, hw_led_mode 0x%x\n",
5743 speed
, hw_led_mode
);
5746 REG_WR(bp
, NIG_REG_LED_10G_P0
+ port
*4, 0);
5747 REG_WR(bp
, NIG_REG_LED_MODE_P0
+ port
*4,
5748 SHARED_HW_CFG_LED_MAC1
);
5750 tmp
= EMAC_RD(bp
, EMAC_REG_EMAC_LED
);
5751 EMAC_WR(bp
, EMAC_REG_EMAC_LED
, (tmp
| EMAC_LED_OVERRIDE
));
5755 REG_WR(bp
, NIG_REG_LED_MODE_P0
+ port
*4, hw_led_mode
);
5756 REG_WR(bp
, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
+
5758 /* Set blinking rate to ~15.9Hz */
5759 REG_WR(bp
, NIG_REG_LED_CONTROL_BLINK_RATE_P0
+ port
*4,
5760 LED_BLINK_RATE_VAL
);
5761 REG_WR(bp
, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0
+
5763 tmp
= EMAC_RD(bp
, EMAC_REG_EMAC_LED
);
5764 EMAC_WR(bp
, EMAC_REG_EMAC_LED
,
5765 (tmp
& (~EMAC_LED_OVERRIDE
)));
5767 if (!CHIP_IS_E1H(bp
) &&
5768 ((speed
== SPEED_2500
) ||
5769 (speed
== SPEED_1000
) ||
5770 (speed
== SPEED_100
) ||
5771 (speed
== SPEED_10
))) {
5772 /* On Everest 1 Ax chip versions for speeds less than
5773 10G LED scheme is different */
5774 REG_WR(bp
, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5776 REG_WR(bp
, NIG_REG_LED_CONTROL_TRAFFIC_P0
+
5778 REG_WR(bp
, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0
+
5785 DP(NETIF_MSG_LINK
, "bnx2x_set_led: Invalid led mode %d\n",
5793 u8
bnx2x_test_link(struct link_params
*params
, struct link_vars
*vars
)
5795 struct bnx2x
*bp
= params
->bp
;
5798 CL45_RD_OVER_CL22(bp
, params
->port
,
5800 MDIO_REG_BANK_GP_STATUS
,
5801 MDIO_GP_STATUS_TOP_AN_STATUS1
,
5803 /* link is up only if both local phy and external phy are up */
5804 if ((gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS
) &&
5805 bnx2x_ext_phy_is_link_up(params
, vars
, 1))
5811 static u8
bnx2x_link_initialize(struct link_params
*params
,
5812 struct link_vars
*vars
)
5814 struct bnx2x
*bp
= params
->bp
;
5815 u8 port
= params
->port
;
5818 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
5819 /* Activate the external PHY */
5820 bnx2x_ext_phy_reset(params
, vars
);
5822 bnx2x_set_aer_mmd(params
, vars
);
5824 if (vars
->phy_flags
& PHY_XGXS_FLAG
)
5825 bnx2x_set_master_ln(params
);
5827 rc
= bnx2x_reset_unicore(params
);
5828 /* reset the SerDes and wait for reset bit return low */
5832 bnx2x_set_aer_mmd(params
, vars
);
5834 /* setting the masterLn_def again after the reset */
5835 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
5836 bnx2x_set_master_ln(params
);
5837 bnx2x_set_swap_lanes(params
);
5840 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
5841 if ((params
->req_line_speed
&&
5842 ((params
->req_line_speed
== SPEED_100
) ||
5843 (params
->req_line_speed
== SPEED_10
))) ||
5844 (!params
->req_line_speed
&&
5845 (params
->speed_cap_mask
>=
5846 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
) &&
5847 (params
->speed_cap_mask
<
5848 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)
5850 vars
->phy_flags
|= PHY_SGMII_FLAG
;
5852 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
5855 /* In case of external phy existance, the line speed would be the
5856 line speed linked up by the external phy. In case it is direct only,
5857 then the line_speed during initialization will be equal to the
5859 vars
->line_speed
= params
->req_line_speed
;
5861 bnx2x_calc_ieee_aneg_adv(params
, &vars
->ieee_fc
);
5863 /* init ext phy and enable link state int */
5864 non_ext_phy
= ((ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) ||
5865 (params
->loopback_mode
== LOOPBACK_XGXS_10
));
5868 (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
) ||
5869 (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
) ||
5870 (params
->loopback_mode
== LOOPBACK_EXT_PHY
)) {
5871 if (params
->req_line_speed
== SPEED_AUTO_NEG
)
5872 bnx2x_set_parallel_detection(params
, vars
->phy_flags
);
5873 bnx2x_init_internal_phy(params
, vars
, non_ext_phy
);
5877 rc
|= bnx2x_ext_phy_init(params
, vars
);
5879 bnx2x_bits_dis(bp
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4,
5880 (NIG_STATUS_XGXS0_LINK10G
|
5881 NIG_STATUS_XGXS0_LINK_STATUS
|
5882 NIG_STATUS_SERDES0_LINK_STATUS
));
5889 u8
bnx2x_phy_init(struct link_params
*params
, struct link_vars
*vars
)
5891 struct bnx2x
*bp
= params
->bp
;
5894 DP(NETIF_MSG_LINK
, "Phy Initialization started \n");
5895 DP(NETIF_MSG_LINK
, "req_speed = %d, req_flowctrl=%d\n",
5896 params
->req_line_speed
, params
->req_flow_ctrl
);
5897 vars
->link_status
= 0;
5898 vars
->phy_link_up
= 0;
5900 vars
->line_speed
= 0;
5901 vars
->duplex
= DUPLEX_FULL
;
5902 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
5903 vars
->mac_type
= MAC_TYPE_NONE
;
5905 if (params
->switch_cfg
== SWITCH_CFG_1G
)
5906 vars
->phy_flags
= PHY_SERDES_FLAG
;
5908 vars
->phy_flags
= PHY_XGXS_FLAG
;
5911 /* disable attentions */
5912 bnx2x_bits_dis(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ params
->port
*4,
5913 (NIG_MASK_XGXS0_LINK_STATUS
|
5914 NIG_MASK_XGXS0_LINK10G
|
5915 NIG_MASK_SERDES0_LINK_STATUS
|
5918 bnx2x_emac_init(params
, vars
);
5920 if (CHIP_REV_IS_FPGA(bp
)) {
5922 vars
->line_speed
= SPEED_10000
;
5923 vars
->duplex
= DUPLEX_FULL
;
5924 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
5925 vars
->link_status
= (LINK_STATUS_LINK_UP
| LINK_10GTFD
);
5926 /* enable on E1.5 FPGA */
5927 if (CHIP_IS_E1H(bp
)) {
5929 (BNX2X_FLOW_CTRL_TX
| BNX2X_FLOW_CTRL_RX
);
5930 vars
->link_status
|=
5931 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED
|
5932 LINK_STATUS_RX_FLOW_CONTROL_ENABLED
);
5935 bnx2x_emac_enable(params
, vars
, 0);
5936 bnx2x_pbf_update(params
, vars
->flow_ctrl
, vars
->line_speed
);
5938 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
5939 + params
->port
*4, 0);
5941 /* update shared memory */
5942 bnx2x_update_mng(params
, vars
->link_status
);
5947 if (CHIP_REV_IS_EMUL(bp
)) {
5950 vars
->line_speed
= SPEED_10000
;
5951 vars
->duplex
= DUPLEX_FULL
;
5952 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
5953 vars
->link_status
= (LINK_STATUS_LINK_UP
| LINK_10GTFD
);
5955 bnx2x_bmac_enable(params
, vars
, 0);
5957 bnx2x_pbf_update(params
, vars
->flow_ctrl
, vars
->line_speed
);
5959 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
5960 + params
->port
*4, 0);
5962 /* update shared memory */
5963 bnx2x_update_mng(params
, vars
->link_status
);
5968 if (params
->loopback_mode
== LOOPBACK_BMAC
) {
5970 vars
->line_speed
= SPEED_10000
;
5971 vars
->duplex
= DUPLEX_FULL
;
5972 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
5973 vars
->mac_type
= MAC_TYPE_BMAC
;
5975 vars
->phy_flags
= PHY_XGXS_FLAG
;
5977 bnx2x_phy_deassert(params
, vars
->phy_flags
);
5978 /* set bmac loopback */
5979 bnx2x_bmac_enable(params
, vars
, 1);
5981 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+
5983 } else if (params
->loopback_mode
== LOOPBACK_EMAC
) {
5985 vars
->line_speed
= SPEED_1000
;
5986 vars
->duplex
= DUPLEX_FULL
;
5987 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
5988 vars
->mac_type
= MAC_TYPE_EMAC
;
5990 vars
->phy_flags
= PHY_XGXS_FLAG
;
5992 bnx2x_phy_deassert(params
, vars
->phy_flags
);
5993 /* set bmac loopback */
5994 bnx2x_emac_enable(params
, vars
, 1);
5995 bnx2x_emac_program(params
, vars
->line_speed
,
5997 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+
5999 } else if ((params
->loopback_mode
== LOOPBACK_XGXS_10
) ||
6000 (params
->loopback_mode
== LOOPBACK_EXT_PHY
)) {
6002 vars
->line_speed
= SPEED_10000
;
6003 vars
->duplex
= DUPLEX_FULL
;
6004 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
6006 vars
->phy_flags
= PHY_XGXS_FLAG
;
6009 NIG_REG_XGXS0_CTRL_PHY_ADDR
+
6011 params
->phy_addr
= (u8
)val
;
6013 bnx2x_phy_deassert(params
, vars
->phy_flags
);
6014 bnx2x_link_initialize(params
, vars
);
6016 vars
->mac_type
= MAC_TYPE_BMAC
;
6018 bnx2x_bmac_enable(params
, vars
, 0);
6020 if (params
->loopback_mode
== LOOPBACK_XGXS_10
) {
6021 /* set 10G XGXS loopback */
6022 bnx2x_set_xgxs_loopback(params
, vars
, 1);
6024 /* set external phy loopback */
6025 bnx2x_ext_phy_loopback(params
);
6027 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+
6030 bnx2x_set_led(bp
, params
->port
, LED_MODE_OPER
,
6031 vars
->line_speed
, params
->hw_led_mode
,
6038 bnx2x_phy_deassert(params
, vars
->phy_flags
);
6039 switch (params
->switch_cfg
) {
6041 vars
->phy_flags
|= PHY_SERDES_FLAG
;
6042 if ((params
->ext_phy_config
&
6043 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK
) ==
6044 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482
) {
6050 NIG_REG_SERDES0_CTRL_PHY_ADDR
+
6053 params
->phy_addr
= (u8
)val
;
6056 case SWITCH_CFG_10G
:
6057 vars
->phy_flags
|= PHY_XGXS_FLAG
;
6059 NIG_REG_XGXS0_CTRL_PHY_ADDR
+
6061 params
->phy_addr
= (u8
)val
;
6065 DP(NETIF_MSG_LINK
, "Invalid switch_cfg\n");
6069 DP(NETIF_MSG_LINK
, "Phy address = 0x%x\n", params
->phy_addr
);
6071 bnx2x_link_initialize(params
, vars
);
6073 bnx2x_link_int_enable(params
);
6078 static void bnx2x_8726_reset_phy(struct bnx2x
*bp
, u8 port
, u8 ext_phy_addr
)
6080 DP(NETIF_MSG_LINK
, "bnx2x_8726_reset_phy port %d\n", port
);
6082 /* Set serial boot control for external load */
6083 bnx2x_cl45_write(bp
, port
,
6084 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
, ext_phy_addr
,
6086 MDIO_PMA_REG_GEN_CTRL
, 0x0001);
6089 u8
bnx2x_link_reset(struct link_params
*params
, struct link_vars
*vars
,
6093 struct bnx2x
*bp
= params
->bp
;
6094 u32 ext_phy_config
= params
->ext_phy_config
;
6095 u16 hw_led_mode
= params
->hw_led_mode
;
6096 u32 chip_id
= params
->chip_id
;
6097 u8 port
= params
->port
;
6098 u32 ext_phy_type
= XGXS_EXT_PHY_TYPE(ext_phy_config
);
6099 u32 val
= REG_RD(bp
, params
->shmem_base
+
6100 offsetof(struct shmem_region
, dev_info
.
6101 port_feature_config
[params
->port
].
6104 /* disable attentions */
6106 vars
->link_status
= 0;
6107 bnx2x_update_mng(params
, vars
->link_status
);
6108 bnx2x_bits_dis(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4,
6109 (NIG_MASK_XGXS0_LINK_STATUS
|
6110 NIG_MASK_XGXS0_LINK10G
|
6111 NIG_MASK_SERDES0_LINK_STATUS
|
6114 /* activate nig drain */
6115 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
*4, 1);
6117 /* disable nig egress interface */
6118 REG_WR(bp
, NIG_REG_BMAC0_OUT_EN
+ port
*4, 0);
6119 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
*4, 0);
6121 /* Stop BigMac rx */
6122 bnx2x_bmac_rx_disable(bp
, port
);
6125 REG_WR(bp
, NIG_REG_NIG_EMAC0_EN
+ port
*4, 0);
6128 /* The PHY reset is controled by GPIO 1
6129 * Hold it as vars low
6131 /* clear link led */
6132 bnx2x_set_led(bp
, port
, LED_MODE_OFF
, 0, hw_led_mode
, chip_id
);
6133 if (reset_ext_phy
) {
6134 switch (ext_phy_type
) {
6135 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
6136 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072
:
6139 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
6142 /* Disable Transmitter */
6144 XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
6145 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
6146 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
)
6147 bnx2x_sfp_set_transmitter(bp
, port
,
6148 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
6152 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
6153 DP(NETIF_MSG_LINK
, "Setting 8073 port %d into "
6156 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
6157 MISC_REGISTERS_GPIO_OUTPUT_LOW
,
6160 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
6163 XGXS_EXT_PHY_ADDR(params
->ext_phy_config
);
6164 /* Set soft reset */
6165 bnx2x_8726_reset_phy(bp
, params
->port
, ext_phy_addr
);
6170 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
6171 MISC_REGISTERS_GPIO_OUTPUT_LOW
,
6173 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
6174 MISC_REGISTERS_GPIO_OUTPUT_LOW
,
6176 DP(NETIF_MSG_LINK
, "reset external PHY\n");
6179 /* reset the SerDes/XGXS */
6180 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_CLEAR
,
6181 (0x1ff << (port
*16)));
6184 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
6185 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
6187 /* disable nig ingress interface */
6188 REG_WR(bp
, NIG_REG_BMAC0_IN_EN
+ port
*4, 0);
6189 REG_WR(bp
, NIG_REG_EMAC0_IN_EN
+ port
*4, 0);
6190 REG_WR(bp
, NIG_REG_BMAC0_OUT_EN
+ port
*4, 0);
6191 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
*4, 0);
6196 static u8
bnx2x_update_link_down(struct link_params
*params
,
6197 struct link_vars
*vars
)
6199 struct bnx2x
*bp
= params
->bp
;
6200 u8 port
= params
->port
;
6201 DP(NETIF_MSG_LINK
, "Port %x: Link is down\n", port
);
6202 bnx2x_set_led(bp
, port
, LED_MODE_OFF
,
6203 0, params
->hw_led_mode
,
6206 /* indicate no mac active */
6207 vars
->mac_type
= MAC_TYPE_NONE
;
6209 /* update shared memory */
6210 vars
->link_status
= 0;
6211 vars
->line_speed
= 0;
6212 bnx2x_update_mng(params
, vars
->link_status
);
6214 /* activate nig drain */
6215 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
*4, 1);
6218 REG_WR(bp
, NIG_REG_NIG_EMAC0_EN
+ port
*4, 0);
6223 bnx2x_bmac_rx_disable(bp
, params
->port
);
6224 REG_WR(bp
, GRCBASE_MISC
+
6225 MISC_REGISTERS_RESET_REG_2_CLEAR
,
6226 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
6230 static u8
bnx2x_update_link_up(struct link_params
*params
,
6231 struct link_vars
*vars
,
6232 u8 link_10g
, u32 gp_status
)
6234 struct bnx2x
*bp
= params
->bp
;
6235 u8 port
= params
->port
;
6237 vars
->link_status
|= LINK_STATUS_LINK_UP
;
6239 bnx2x_bmac_enable(params
, vars
, 0);
6240 bnx2x_set_led(bp
, port
, LED_MODE_OPER
,
6241 SPEED_10000
, params
->hw_led_mode
,
6245 bnx2x_emac_enable(params
, vars
, 0);
6246 rc
= bnx2x_emac_program(params
, vars
->line_speed
,
6250 if (gp_status
& MDIO_AN_CL73_OR_37_COMPLETE
) {
6251 if (!(vars
->phy_flags
&
6253 bnx2x_set_gmii_tx_driver(params
);
6258 rc
|= bnx2x_pbf_update(params
, vars
->flow_ctrl
,
6262 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
*4, 0);
6264 /* update shared memory */
6265 bnx2x_update_mng(params
, vars
->link_status
);
6269 /* This function should called upon link interrupt */
6270 /* In case vars->link_up, driver needs to
6273 3. Update the shared memory
6277 1. Update shared memory
6282 u8
bnx2x_link_update(struct link_params
*params
, struct link_vars
*vars
)
6284 struct bnx2x
*bp
= params
->bp
;
6285 u8 port
= params
->port
;
6288 u8 ext_phy_link_up
, rc
= 0;
6292 DP(NETIF_MSG_LINK
, "port %x, XGXS?%x, int_status 0x%x\n",
6293 port
, (vars
->phy_flags
& PHY_XGXS_FLAG
),
6294 REG_RD(bp
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4));
6296 is_mi_int
= (u8
)(REG_RD(bp
, NIG_REG_EMAC0_STATUS_MISC_MI_INT
+
6298 DP(NETIF_MSG_LINK
, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6299 REG_RD(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4),
6302 NIG_REG_SERDES0_STATUS_LINK_STATUS
+ port
*0x3c));
6304 DP(NETIF_MSG_LINK
, " 10G %x, XGXS_LINK %x\n",
6305 REG_RD(bp
, NIG_REG_XGXS0_STATUS_LINK10G
+ port
*0x68),
6306 REG_RD(bp
, NIG_REG_XGXS0_STATUS_LINK_STATUS
+ port
*0x68));
6309 REG_WR(bp
, NIG_REG_NIG_EMAC0_EN
+ port
*4, 0);
6311 ext_phy_type
= XGXS_EXT_PHY_TYPE(params
->ext_phy_config
);
6313 /* Check external link change only for non-direct */
6314 ext_phy_link_up
= bnx2x_ext_phy_is_link_up(params
, vars
, is_mi_int
);
6316 /* Read gp_status */
6317 CL45_RD_OVER_CL22(bp
, port
, params
->phy_addr
,
6318 MDIO_REG_BANK_GP_STATUS
,
6319 MDIO_GP_STATUS_TOP_AN_STATUS1
,
6322 rc
= bnx2x_link_settings_status(params
, vars
, gp_status
,
6327 /* anything 10 and over uses the bmac */
6328 link_10g
= ((vars
->line_speed
== SPEED_10000
) ||
6329 (vars
->line_speed
== SPEED_12000
) ||
6330 (vars
->line_speed
== SPEED_12500
) ||
6331 (vars
->line_speed
== SPEED_13000
) ||
6332 (vars
->line_speed
== SPEED_15000
) ||
6333 (vars
->line_speed
== SPEED_16000
));
6335 bnx2x_link_int_ack(params
, vars
, link_10g
, is_mi_int
);
6337 /* In case external phy link is up, and internal link is down
6338 ( not initialized yet probably after link initialization, it needs
6340 Note that after link down-up as result of cable plug,
6341 the xgxs link would probably become up again without the need to
6344 if ((ext_phy_type
!= PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
) &&
6345 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
) &&
6346 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
) &&
6347 (ext_phy_link_up
&& !vars
->phy_link_up
))
6348 bnx2x_init_internal_phy(params
, vars
, 0);
6350 /* link is up only if both local phy and external phy are up */
6351 vars
->link_up
= (ext_phy_link_up
&& vars
->phy_link_up
);
6354 rc
= bnx2x_update_link_up(params
, vars
, link_10g
, gp_status
);
6356 rc
= bnx2x_update_link_down(params
, vars
);
6361 static u8
bnx2x_8073_common_init_phy(struct bnx2x
*bp
, u32 shmem_base
)
6363 u8 ext_phy_addr
[PORT_MAX
];
6367 /* PART1 - Reset both phys */
6368 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
6369 /* Extract the ext phy address for the port */
6370 u32 ext_phy_config
= REG_RD(bp
, shmem_base
+
6371 offsetof(struct shmem_region
,
6372 dev_info
.port_hw_config
[port
].external_phy_config
));
6374 /* disable attentions */
6375 bnx2x_bits_dis(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4,
6376 (NIG_MASK_XGXS0_LINK_STATUS
|
6377 NIG_MASK_XGXS0_LINK10G
|
6378 NIG_MASK_SERDES0_LINK_STATUS
|
6381 ext_phy_addr
[port
] = XGXS_EXT_PHY_ADDR(ext_phy_config
);
6383 /* Need to take the phy out of low power mode in order
6384 to write to access its registers */
6385 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
6386 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, port
);
6389 bnx2x_cl45_write(bp
, port
,
6390 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6397 /* Add delay of 150ms after reset */
6400 /* PART2 - Download firmware to both phys */
6401 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
6404 bnx2x_bcm8073_external_rom_boot(bp
, port
,
6405 ext_phy_addr
[port
], shmem_base
);
6407 bnx2x_cl45_read(bp
, port
, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6410 MDIO_PMA_REG_ROM_VER1
, &fw_ver1
);
6411 if (fw_ver1
== 0 || fw_ver1
== 0x4321) {
6413 "bnx2x_8073_common_init_phy port %x:"
6414 "Download failed. fw version = 0x%x\n",
6419 /* Only set bit 10 = 1 (Tx power down) */
6420 bnx2x_cl45_read(bp
, port
,
6421 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6424 MDIO_PMA_REG_TX_POWER_DOWN
, &val
);
6426 /* Phase1 of TX_POWER_DOWN reset */
6427 bnx2x_cl45_write(bp
, port
,
6428 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6431 MDIO_PMA_REG_TX_POWER_DOWN
,
6435 /* Toggle Transmitter: Power down and then up with 600ms
6439 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
6440 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
6441 /* Phase2 of POWER_DOWN_RESET */
6442 /* Release bit 10 (Release Tx power down) */
6443 bnx2x_cl45_read(bp
, port
,
6444 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6447 MDIO_PMA_REG_TX_POWER_DOWN
, &val
);
6449 bnx2x_cl45_write(bp
, port
,
6450 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6453 MDIO_PMA_REG_TX_POWER_DOWN
, (val
& (~(1<<10))));
6456 /* Read modify write the SPI-ROM version select register */
6457 bnx2x_cl45_read(bp
, port
,
6458 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6461 MDIO_PMA_REG_EDC_FFE_MAIN
, &val
);
6462 bnx2x_cl45_write(bp
, port
,
6463 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
6466 MDIO_PMA_REG_EDC_FFE_MAIN
, (val
| (1<<12)));
6468 /* set GPIO2 back to LOW */
6469 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
6470 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
6476 static u8
bnx2x_8727_common_init_phy(struct bnx2x
*bp
, u32 shmem_base
)
6478 u8 ext_phy_addr
[PORT_MAX
];
6479 s8 port
, first_port
, i
;
6480 u32 swap_val
, swap_override
;
6481 DP(NETIF_MSG_LINK
, "Executing BCM8727 common init\n");
6482 swap_val
= REG_RD(bp
, NIG_REG_PORT_SWAP
);
6483 swap_override
= REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
);
6485 bnx2x_ext_phy_hw_reset(bp
, 1 ^ (swap_val
&& swap_override
));
6488 if (swap_val
&& swap_override
)
6489 first_port
= PORT_0
;
6491 first_port
= PORT_1
;
6493 /* PART1 - Reset both phys */
6494 for (i
= 0, port
= first_port
; i
< PORT_MAX
; i
++, port
= !port
) {
6495 /* Extract the ext phy address for the port */
6496 u32 ext_phy_config
= REG_RD(bp
, shmem_base
+
6497 offsetof(struct shmem_region
,
6498 dev_info
.port_hw_config
[port
].external_phy_config
));
6500 /* disable attentions */
6501 bnx2x_bits_dis(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4,
6502 (NIG_MASK_XGXS0_LINK_STATUS
|
6503 NIG_MASK_XGXS0_LINK10G
|
6504 NIG_MASK_SERDES0_LINK_STATUS
|
6507 ext_phy_addr
[port
] = XGXS_EXT_PHY_ADDR(ext_phy_config
);
6510 bnx2x_cl45_write(bp
, port
,
6511 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
6518 /* Add delay of 150ms after reset */
6521 /* PART2 - Download firmware to both phys */
6522 for (i
= 0, port
= first_port
; i
< PORT_MAX
; i
++, port
= !port
) {
6525 bnx2x_bcm8727_external_rom_boot(bp
, port
,
6526 ext_phy_addr
[port
], shmem_base
);
6528 bnx2x_cl45_read(bp
, port
, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
6531 MDIO_PMA_REG_ROM_VER1
, &fw_ver1
);
6532 if (fw_ver1
== 0 || fw_ver1
== 0x4321) {
6534 "bnx2x_8727_common_init_phy port %x:"
6535 "Download failed. fw version = 0x%x\n",
6545 static u8
bnx2x_8726_common_init_phy(struct bnx2x
*bp
, u32 shmem_base
)
6550 /* Use port1 because of the static port-swap */
6551 /* Enable the module detection interrupt */
6552 val
= REG_RD(bp
, MISC_REG_GPIO_EVENT_EN
);
6553 val
|= ((1<<MISC_REGISTERS_GPIO_3
)|
6554 (1<<(MISC_REGISTERS_GPIO_3
+ MISC_REGISTERS_GPIO_PORT_SHIFT
)));
6555 REG_WR(bp
, MISC_REG_GPIO_EVENT_EN
, val
);
6557 bnx2x_ext_phy_hw_reset(bp
, 1);
6559 for (port
= 0; port
< PORT_MAX
; port
++) {
6560 /* Extract the ext phy address for the port */
6561 u32 ext_phy_config
= REG_RD(bp
, shmem_base
+
6562 offsetof(struct shmem_region
,
6563 dev_info
.port_hw_config
[port
].external_phy_config
));
6565 ext_phy_addr
= XGXS_EXT_PHY_ADDR(ext_phy_config
);
6566 DP(NETIF_MSG_LINK
, "8726_common_init : ext_phy_addr = 0x%x\n",
6569 bnx2x_8726_reset_phy(bp
, port
, ext_phy_addr
);
6571 /* Set fault module detected LED on */
6572 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_0
,
6573 MISC_REGISTERS_GPIO_HIGH
,
6580 u8
bnx2x_common_init_phy(struct bnx2x
*bp
, u32 shmem_base
)
6585 DP(NETIF_MSG_LINK
, "Begin common phy init\n");
6587 /* Read the ext_phy_type for arbitrary port(0) */
6588 ext_phy_type
= XGXS_EXT_PHY_TYPE(
6589 REG_RD(bp
, shmem_base
+
6590 offsetof(struct shmem_region
,
6591 dev_info
.port_hw_config
[0].external_phy_config
)));
6593 switch (ext_phy_type
) {
6594 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
6596 rc
= bnx2x_8073_common_init_phy(bp
, shmem_base
);
6600 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
6601 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC
:
6602 rc
= bnx2x_8727_common_init_phy(bp
, shmem_base
);
6605 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
6606 /* GPIO1 affects both ports, so there's need to pull
6607 it for single port alone */
6608 rc
= bnx2x_8726_common_init_phy(bp
, shmem_base
);
6613 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
6621 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x
*bp
, u8 port
, u8 phy_addr
)
6625 bnx2x_cl45_read(bp
, port
,
6626 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
,
6629 MDIO_PMA_REG_7101_RESET
, &val
);
6631 for (cnt
= 0; cnt
< 10; cnt
++) {
6633 /* Writes a self-clearing reset */
6634 bnx2x_cl45_write(bp
, port
,
6635 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
,
6638 MDIO_PMA_REG_7101_RESET
,
6640 /* Wait for clear */
6641 bnx2x_cl45_read(bp
, port
,
6642 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
,
6645 MDIO_PMA_REG_7101_RESET
, &val
);
6647 if ((val
& (1<<15)) == 0)