drivers/net/bnx2x.h

   1 /* bnx2x.h: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2009 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  */
  13
  14 #ifndef BNX2X_H
  15 #define BNX2X_H
  16
  17 /* compilation time flags */
  18
  19 /* define this to make the driver freeze on error to allow getting debug info
  20  * (you will need to reboot afterwards) */
  21 /* #define BNX2X_STOP_ON_ERROR */
  22
  23 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  24 #define BCM_VLAN                        1
  25 #endif
  26
  27
  28 #define BNX2X_MULTI_QUEUE
  29
  30 #define BNX2X_NEW_NAPI
  31
  32
  33
  34 #include <linux/mdio.h>
  35 #include "bnx2x_reg.h"
  36 #include "bnx2x_fw_defs.h"
  37 #include "bnx2x_hsi.h"
  38 #include "bnx2x_link.h"
  39
  40 /* error/debug prints */
  41
  42 #define DRV_MODULE_NAME         "bnx2x"
  43 #define PFX DRV_MODULE_NAME     ": "
  44
  45 /* for messages that are currently off */
  46 #define BNX2X_MSG_OFF                   0
  47 #define BNX2X_MSG_MCP                   0x010000 /* was: NETIF_MSG_HW */
  48 #define BNX2X_MSG_STATS                 0x020000 /* was: NETIF_MSG_TIMER */
  49 #define BNX2X_MSG_NVM                   0x040000 /* was: NETIF_MSG_HW */
  50 #define BNX2X_MSG_DMAE                  0x080000 /* was: NETIF_MSG_HW */
  51 #define BNX2X_MSG_SP                    0x100000 /* was: NETIF_MSG_INTR */
  52 #define BNX2X_MSG_FP                    0x200000 /* was: NETIF_MSG_INTR */
  53
  54 #define DP_LEVEL                        KERN_NOTICE     /* was: KERN_DEBUG */
  55
  56 /* regular debug print */
  57 #define DP(__mask, __fmt, __args...) do { \
  58         if (bp->msglevel & (__mask)) \
  59                 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
  60                         bp->dev ? (bp->dev->name) : "?", ##__args); \
  61         } while (0)
  62
  63 /* errors debug print */
  64 #define BNX2X_DBG_ERR(__fmt, __args...) do { \
  65         if (bp->msglevel & NETIF_MSG_PROBE) \
  66                 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
  67                         bp->dev ? (bp->dev->name) : "?", ##__args); \
  68         } while (0)
  69
  70 /* for errors (never masked) */
  71 #define BNX2X_ERR(__fmt, __args...) do { \
  72         printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
  73                 bp->dev ? (bp->dev->name) : "?", ##__args); \
  74         } while (0)
  75
  76 /* before we have a dev->name use dev_info() */
  77 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
  78         if (bp->msglevel & NETIF_MSG_PROBE) \
  79                 dev_info(&bp->pdev->dev, __fmt, ##__args); \
  80         } while (0)
  81
  82
  83 #ifdef BNX2X_STOP_ON_ERROR
  84 #define bnx2x_panic() do { \
  85                 bp->panic = 1; \
  86                 BNX2X_ERR("driver assert\n"); \
  87                 bnx2x_int_disable(bp); \
  88                 bnx2x_panic_dump(bp); \
  89         } while (0)
  90 #else
  91 #define bnx2x_panic() do { \
  92                 bp->panic = 1; \
  93                 BNX2X_ERR("driver assert\n"); \
  94                 bnx2x_panic_dump(bp); \
  95         } while (0)
  96 #endif
  97
  98
  99 #define U64_LO(x)                       (u32)(((u64)(x)) & 0xffffffff)
 100 #define U64_HI(x)                       (u32)(((u64)(x)) >> 32)
 101 #define HILO_U64(hi, lo)                ((((u64)(hi)) << 32) + (lo))
 102
 103
 104 #define REG_ADDR(bp, offset)            (bp->regview + offset)
 105
 106 #define REG_RD(bp, offset)              readl(REG_ADDR(bp, offset))
 107 #define REG_RD8(bp, offset)             readb(REG_ADDR(bp, offset))
 108
 109 #define REG_WR(bp, offset, val)         writel((u32)val, REG_ADDR(bp, offset))
 110 #define REG_WR8(bp, offset, val)        writeb((u8)val, REG_ADDR(bp, offset))
 111 #define REG_WR16(bp, offset, val)       writew((u16)val, REG_ADDR(bp, offset))
 112
 113 #define REG_RD_IND(bp, offset)          bnx2x_reg_rd_ind(bp, offset)
 114 #define REG_WR_IND(bp, offset, val)     bnx2x_reg_wr_ind(bp, offset, val)
 115
 116 #define REG_RD_DMAE(bp, offset, valp, len32) \
 117         do { \
 118                 bnx2x_read_dmae(bp, offset, len32);\
 119                 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
 120         } while (0)
 121
 122 #define REG_WR_DMAE(bp, offset, valp, len32) \
 123         do { \
 124                 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
 125                 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
 126                                  offset, len32); \
 127         } while (0)
 128
 129 #define SHMEM_ADDR(bp, field)           (bp->common.shmem_base + \
 130                                          offsetof(struct shmem_region, field))
 131 #define SHMEM_RD(bp, field)             REG_RD(bp, SHMEM_ADDR(bp, field))
 132 #define SHMEM_WR(bp, field, val)        REG_WR(bp, SHMEM_ADDR(bp, field), val)
 133
 134 #define SHMEM2_ADDR(bp, field)          (bp->common.shmem2_base + \
 135                                          offsetof(struct shmem2_region, field))
 136 #define SHMEM2_RD(bp, field)            REG_RD(bp, SHMEM2_ADDR(bp, field))
 137 #define SHMEM2_WR(bp, field, val)       REG_WR(bp, SHMEM2_ADDR(bp, field), val)
 138
 139 #define EMAC_RD(bp, reg)                REG_RD(bp, emac_base + reg)
 140 #define EMAC_WR(bp, reg, val)           REG_WR(bp, emac_base + reg, val)
 141
 142
 143 /* fast path */
 144
 145 struct sw_rx_bd {
 146         struct sk_buff  *skb;
 147         DECLARE_PCI_UNMAP_ADDR(mapping)
 148 };
 149
 150 struct sw_tx_bd {
 151         struct sk_buff  *skb;
 152         u16             first_bd;
 153         u8              flags;
 154 /* Set on the first BD descriptor when there is a split BD */
 155 #define BNX2X_TSO_SPLIT_BD              (1<<0)
 156 };
 157
 158 struct sw_rx_page {
 159         struct page     *page;
 160         DECLARE_PCI_UNMAP_ADDR(mapping)
 161 };
 162
 163 union db_prod {
 164         struct doorbell_set_prod data;
 165         u32             raw;
 166 };
 167
 168
 169 /* MC hsi */
 170 #define BCM_PAGE_SHIFT                  12
 171 #define BCM_PAGE_SIZE                   (1 << BCM_PAGE_SHIFT)
 172 #define BCM_PAGE_MASK                   (~(BCM_PAGE_SIZE - 1))
 173 #define BCM_PAGE_ALIGN(addr)    (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
 174
 175 #define PAGES_PER_SGE_SHIFT             0
 176 #define PAGES_PER_SGE                   (1 << PAGES_PER_SGE_SHIFT)
 177 #define SGE_PAGE_SIZE                   PAGE_SIZE
 178 #define SGE_PAGE_SHIFT                  PAGE_SHIFT
 179 #define SGE_PAGE_ALIGN(addr)            PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
 180
 181 /* SGE ring related macros */
 182 #define NUM_RX_SGE_PAGES                2
 183 #define RX_SGE_CNT              (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
 184 #define MAX_RX_SGE_CNT                  (RX_SGE_CNT - 2)
 185 /* RX_SGE_CNT is promised to be a power of 2 */
 186 #define RX_SGE_MASK                     (RX_SGE_CNT - 1)
 187 #define NUM_RX_SGE                      (RX_SGE_CNT * NUM_RX_SGE_PAGES)
 188 #define MAX_RX_SGE                      (NUM_RX_SGE - 1)
 189 #define NEXT_SGE_IDX(x)         ((((x) & RX_SGE_MASK) == \
 190                                   (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
 191 #define RX_SGE(x)                       ((x) & MAX_RX_SGE)
 192
 193 /* SGE producer mask related macros */
 194 /* Number of bits in one sge_mask array element */
 195 #define RX_SGE_MASK_ELEM_SZ             64
 196 #define RX_SGE_MASK_ELEM_SHIFT          6
 197 #define RX_SGE_MASK_ELEM_MASK           ((u64)RX_SGE_MASK_ELEM_SZ - 1)
 198
 199 /* Creates a bitmask of all ones in less significant bits.
 200    idx - index of the most significant bit in the created mask */
 201 #define RX_SGE_ONES_MASK(idx) \
 202                 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
 203 #define RX_SGE_MASK_ELEM_ONE_MASK       ((u64)(~0))
 204
 205 /* Number of u64 elements in SGE mask array */
 206 #define RX_SGE_MASK_LEN                 ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
 207                                          RX_SGE_MASK_ELEM_SZ)
 208 #define RX_SGE_MASK_LEN_MASK            (RX_SGE_MASK_LEN - 1)
 209 #define NEXT_SGE_MASK_ELEM(el)          (((el) + 1) & RX_SGE_MASK_LEN_MASK)
 210
 211
 212 struct bnx2x_eth_q_stats {
 213         u32 total_bytes_received_hi;
 214         u32 total_bytes_received_lo;
 215         u32 total_bytes_transmitted_hi;
 216         u32 total_bytes_transmitted_lo;
 217         u32 total_unicast_packets_received_hi;
 218         u32 total_unicast_packets_received_lo;
 219         u32 total_multicast_packets_received_hi;
 220         u32 total_multicast_packets_received_lo;
 221         u32 total_broadcast_packets_received_hi;
 222         u32 total_broadcast_packets_received_lo;
 223         u32 total_unicast_packets_transmitted_hi;
 224         u32 total_unicast_packets_transmitted_lo;
 225         u32 total_multicast_packets_transmitted_hi;
 226         u32 total_multicast_packets_transmitted_lo;
 227         u32 total_broadcast_packets_transmitted_hi;
 228         u32 total_broadcast_packets_transmitted_lo;
 229         u32 valid_bytes_received_hi;
 230         u32 valid_bytes_received_lo;
 231
 232         u32 error_bytes_received_hi;
 233         u32 error_bytes_received_lo;
 234         u32 etherstatsoverrsizepkts_hi;
 235         u32 etherstatsoverrsizepkts_lo;
 236         u32 no_buff_discard_hi;
 237         u32 no_buff_discard_lo;
 238
 239         u32 driver_xoff;
 240         u32 rx_err_discard_pkt;
 241         u32 rx_skb_alloc_failed;
 242         u32 hw_csum_err;
 243 };
 244
 245 #define BNX2X_NUM_Q_STATS               11
 246 #define Q_STATS_OFFSET32(stat_name) \
 247                         (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
 248
 249 struct bnx2x_fastpath {
 250
 251         struct napi_struct      napi;
 252
 253         u8                      is_rx_queue;
 254
 255         struct host_status_block *status_blk;
 256         dma_addr_t              status_blk_mapping;
 257
 258         struct sw_tx_bd         *tx_buf_ring;
 259
 260         union eth_tx_bd_types   *tx_desc_ring;
 261         dma_addr_t              tx_desc_mapping;
 262
 263         struct sw_rx_bd         *rx_buf_ring;   /* BDs mappings ring */
 264         struct sw_rx_page       *rx_page_ring;  /* SGE pages mappings ring */
 265
 266         struct eth_rx_bd        *rx_desc_ring;
 267         dma_addr_t              rx_desc_mapping;
 268
 269         union eth_rx_cqe        *rx_comp_ring;
 270         dma_addr_t              rx_comp_mapping;
 271
 272         /* SGE ring */
 273         struct eth_rx_sge       *rx_sge_ring;
 274         dma_addr_t              rx_sge_mapping;
 275
 276         u64                     sge_mask[RX_SGE_MASK_LEN];
 277
 278         int                     state;
 279 #define BNX2X_FP_STATE_CLOSED           0
 280 #define BNX2X_FP_STATE_IRQ              0x80000
 281 #define BNX2X_FP_STATE_OPENING          0x90000
 282 #define BNX2X_FP_STATE_OPEN             0xa0000
 283 #define BNX2X_FP_STATE_HALTING          0xb0000
 284 #define BNX2X_FP_STATE_HALTED           0xc0000
 285
 286         u8                      index;  /* number in fp array */
 287         u8                      cl_id;  /* eth client id */
 288         u8                      sb_id;  /* status block number in HW */
 289
 290         union db_prod           tx_db;
 291
 292         u16                     tx_pkt_prod;
 293         u16                     tx_pkt_cons;
 294         u16                     tx_bd_prod;
 295         u16                     tx_bd_cons;
 296         __le16                  *tx_cons_sb;
 297
 298         __le16                  fp_c_idx;
 299         __le16                  fp_u_idx;
 300
 301         u16                     rx_bd_prod;
 302         u16                     rx_bd_cons;
 303         u16                     rx_comp_prod;
 304         u16                     rx_comp_cons;
 305         u16                     rx_sge_prod;
 306         /* The last maximal completed SGE */
 307         u16                     last_max_sge;
 308         __le16                  *rx_cons_sb;
 309         __le16                  *rx_bd_cons_sb;
 310
 311         unsigned long           tx_pkt,
 312                                 rx_pkt,
 313                                 rx_calls;
 314         /* TPA related */
 315         struct sw_rx_bd         tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
 316         u8                      tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
 317 #define BNX2X_TPA_START                 1
 318 #define BNX2X_TPA_STOP                  2
 319         u8                      disable_tpa;
 320 #ifdef BNX2X_STOP_ON_ERROR
 321         u64                     tpa_queue_used;
 322 #endif
 323
 324         struct tstorm_per_client_stats old_tclient;
 325         struct ustorm_per_client_stats old_uclient;
 326         struct xstorm_per_client_stats old_xclient;
 327         struct bnx2x_eth_q_stats eth_q_stats;
 328
 329         /* The size is calculated using the following:
 330              sizeof name field from netdev structure +
 331              4 ('-Xx-' string) +
 332              4 (for the digits and to make it DWORD aligned) */
 333 #define FP_NAME_SIZE            (sizeof(((struct net_device *)0)->name) + 8)
 334         char                    name[FP_NAME_SIZE];
 335         struct bnx2x            *bp; /* parent */
 336 };
 337
 338 #define bnx2x_fp(bp, nr, var)           (bp->fp[nr].var)
 339
 340
 341 /* MC hsi */
 342 #define MAX_FETCH_BD                    13      /* HW max BDs per packet */
 343 #define RX_COPY_THRESH                  92
 344
 345 #define NUM_TX_RINGS                    16
 346 #define TX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
 347 #define MAX_TX_DESC_CNT                 (TX_DESC_CNT - 1)
 348 #define NUM_TX_BD                       (TX_DESC_CNT * NUM_TX_RINGS)
 349 #define MAX_TX_BD                       (NUM_TX_BD - 1)
 350 #define MAX_TX_AVAIL                    (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
 351 #define NEXT_TX_IDX(x)          ((((x) & MAX_TX_DESC_CNT) == \
 352                                   (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
 353 #define TX_BD(x)                        ((x) & MAX_TX_BD)
 354 #define TX_BD_POFF(x)                   ((x) & MAX_TX_DESC_CNT)
 355
 356 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
 357 #define NUM_RX_RINGS                    8
 358 #define RX_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
 359 #define MAX_RX_DESC_CNT                 (RX_DESC_CNT - 2)
 360 #define RX_DESC_MASK                    (RX_DESC_CNT - 1)
 361 #define NUM_RX_BD                       (RX_DESC_CNT * NUM_RX_RINGS)
 362 #define MAX_RX_BD                       (NUM_RX_BD - 1)
 363 #define MAX_RX_AVAIL                    (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
 364 #define NEXT_RX_IDX(x)          ((((x) & RX_DESC_MASK) == \
 365                                   (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
 366 #define RX_BD(x)                        ((x) & MAX_RX_BD)
 367
 368 /* As long as CQE is 4 times bigger than BD entry we have to allocate
 369    4 times more pages for CQ ring in order to keep it balanced with
 370    BD ring */
 371 #define NUM_RCQ_RINGS                   (NUM_RX_RINGS * 4)
 372 #define RCQ_DESC_CNT            (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
 373 #define MAX_RCQ_DESC_CNT                (RCQ_DESC_CNT - 1)
 374 #define NUM_RCQ_BD                      (RCQ_DESC_CNT * NUM_RCQ_RINGS)
 375 #define MAX_RCQ_BD                      (NUM_RCQ_BD - 1)
 376 #define MAX_RCQ_AVAIL                   (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
 377 #define NEXT_RCQ_IDX(x)         ((((x) & MAX_RCQ_DESC_CNT) == \
 378                                   (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
 379 #define RCQ_BD(x)                       ((x) & MAX_RCQ_BD)
 380
 381
 382 /* This is needed for determining of last_max */
 383 #define SUB_S16(a, b)                   (s16)((s16)(a) - (s16)(b))
 384
 385 #define __SGE_MASK_SET_BIT(el, bit) \
 386         do { \
 387                 el = ((el) | ((u64)0x1 << (bit))); \
 388         } while (0)
 389
 390 #define __SGE_MASK_CLEAR_BIT(el, bit) \
 391         do { \
 392                 el = ((el) & (~((u64)0x1 << (bit)))); \
 393         } while (0)
 394
 395 #define SGE_MASK_SET_BIT(fp, idx) \
 396         __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
 397                            ((idx) & RX_SGE_MASK_ELEM_MASK))
 398
 399 #define SGE_MASK_CLEAR_BIT(fp, idx) \
 400         __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
 401                              ((idx) & RX_SGE_MASK_ELEM_MASK))
 402
 403
 404 /* used on a CID received from the HW */
 405 #define SW_CID(x)                       (le32_to_cpu(x) & \
 406                                          (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
 407 #define CQE_CMD(x)                      (le32_to_cpu(x) >> \
 408                                         COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
 409
 410 #define BD_UNMAP_ADDR(bd)               HILO_U64(le32_to_cpu((bd)->addr_hi), \
 411                                                  le32_to_cpu((bd)->addr_lo))
 412 #define BD_UNMAP_LEN(bd)                (le16_to_cpu((bd)->nbytes))
 413
 414
 415 #define DPM_TRIGER_TYPE                 0x40
 416 #define DOORBELL(bp, cid, val) \
 417         do { \
 418                 writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
 419                        DPM_TRIGER_TYPE); \
 420         } while (0)
 421
 422
 423 /* TX CSUM helpers */
 424 #define SKB_CS_OFF(skb)         (offsetof(struct tcphdr, check) - \
 425                                  skb->csum_offset)
 426 #define SKB_CS(skb)             (*(u16 *)(skb_transport_header(skb) + \
 427                                           skb->csum_offset))
 428
 429 #define pbd_tcp_flags(skb)      (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
 430
 431 #define XMIT_PLAIN                      0
 432 #define XMIT_CSUM_V4                    0x1
 433 #define XMIT_CSUM_V6                    0x2
 434 #define XMIT_CSUM_TCP                   0x4
 435 #define XMIT_GSO_V4                     0x8
 436 #define XMIT_GSO_V6                     0x10
 437
 438 #define XMIT_CSUM                       (XMIT_CSUM_V4 | XMIT_CSUM_V6)
 439 #define XMIT_GSO                        (XMIT_GSO_V4 | XMIT_GSO_V6)
 440
 441
 442 /* stuff added to make the code fit 80Col */
 443
 444 #define CQE_TYPE(cqe_fp_flags)  ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
 445
 446 #define TPA_TYPE_START                  ETH_FAST_PATH_RX_CQE_START_FLG
 447 #define TPA_TYPE_END                    ETH_FAST_PATH_RX_CQE_END_FLG
 448 #define TPA_TYPE(cqe_fp_flags)          ((cqe_fp_flags) & \
 449                                          (TPA_TYPE_START | TPA_TYPE_END))
 450
 451 #define ETH_RX_ERROR_FALGS              ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
 452
 453 #define BNX2X_IP_CSUM_ERR(cqe) \
 454                         (!((cqe)->fast_path_cqe.status_flags & \
 455                            ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
 456                          ((cqe)->fast_path_cqe.type_error_flags & \
 457                           ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
 458
 459 #define BNX2X_L4_CSUM_ERR(cqe) \
 460                         (!((cqe)->fast_path_cqe.status_flags & \
 461                            ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
 462                          ((cqe)->fast_path_cqe.type_error_flags & \
 463                           ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
 464
 465 #define BNX2X_RX_CSUM_OK(cqe) \
 466                         (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
 467
 468 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
 469                                 (((le16_to_cpu(flags) & \
 470                                    PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
 471                                   PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
 472                                  == PRS_FLAG_OVERETH_IPV4)
 473 #define BNX2X_RX_SUM_FIX(cqe) \
 474         BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
 475
 476
 477 #define FP_USB_FUNC_OFF                 (2 + 2*HC_USTORM_SB_NUM_INDICES)
 478 #define FP_CSB_FUNC_OFF                 (2 + 2*HC_CSTORM_SB_NUM_INDICES)
 479
 480 #define U_SB_ETH_RX_CQ_INDEX            HC_INDEX_U_ETH_RX_CQ_CONS
 481 #define U_SB_ETH_RX_BD_INDEX            HC_INDEX_U_ETH_RX_BD_CONS
 482 #define C_SB_ETH_TX_CQ_INDEX            HC_INDEX_C_ETH_TX_CQ_CONS
 483
 484 #define BNX2X_RX_SB_INDEX \
 485         (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
 486
 487 #define BNX2X_RX_SB_BD_INDEX \
 488         (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
 489
 490 #define BNX2X_RX_SB_INDEX_NUM \
 491                 (((U_SB_ETH_RX_CQ_INDEX << \
 492                    USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
 493                   USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
 494                  ((U_SB_ETH_RX_BD_INDEX << \
 495                    USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
 496                   USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
 497
 498 #define BNX2X_TX_SB_INDEX \
 499         (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
 500
 501
 502 /* end of fast path */
 503
 504 /* common */
 505
 506 struct bnx2x_common {
 507
 508         u32                     chip_id;
 509 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
 510 #define CHIP_ID(bp)                     (bp->common.chip_id & 0xfffffff0)
 511
 512 #define CHIP_NUM(bp)                    (bp->common.chip_id >> 16)
 513 #define CHIP_NUM_57710                  0x164e
 514 #define CHIP_NUM_57711                  0x164f
 515 #define CHIP_NUM_57711E                 0x1650
 516 #define CHIP_IS_E1(bp)                  (CHIP_NUM(bp) == CHIP_NUM_57710)
 517 #define CHIP_IS_57711(bp)               (CHIP_NUM(bp) == CHIP_NUM_57711)
 518 #define CHIP_IS_57711E(bp)              (CHIP_NUM(bp) == CHIP_NUM_57711E)
 519 #define CHIP_IS_E1H(bp)                 (CHIP_IS_57711(bp) || \
 520                                          CHIP_IS_57711E(bp))
 521 #define IS_E1H_OFFSET                   CHIP_IS_E1H(bp)
 522
 523 #define CHIP_REV(bp)                    (bp->common.chip_id & 0x0000f000)
 524 #define CHIP_REV_Ax                     0x00000000
 525 /* assume maximum 5 revisions */
 526 #define CHIP_REV_IS_SLOW(bp)            (CHIP_REV(bp) > 0x00005000)
 527 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
 528 #define CHIP_REV_IS_EMUL(bp)            ((CHIP_REV_IS_SLOW(bp)) && \
 529                                          !(CHIP_REV(bp) & 0x00001000))
 530 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
 531 #define CHIP_REV_IS_FPGA(bp)            ((CHIP_REV_IS_SLOW(bp)) && \
 532                                          (CHIP_REV(bp) & 0x00001000))
 533
 534 #define CHIP_TIME(bp)                   ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
 535                                         ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
 536
 537 #define CHIP_METAL(bp)                  (bp->common.chip_id & 0x00000ff0)
 538 #define CHIP_BOND_ID(bp)                (bp->common.chip_id & 0x0000000f)
 539
 540         int                     flash_size;
 541 #define NVRAM_1MB_SIZE                  0x20000 /* 1M bit in bytes */
 542 #define NVRAM_TIMEOUT_COUNT             30000
 543 #define NVRAM_PAGE_SIZE                 256
 544
 545         u32                     shmem_base;
 546         u32                     shmem2_base;
 547
 548         u32                     hw_config;
 549
 550         u32                     bc_ver;
 551 };
 552
 553
 554 /* end of common */
 555
 556 /* port */
 557
 558 struct nig_stats {
 559         u32 brb_discard;
 560         u32 brb_packet;
 561         u32 brb_truncate;
 562         u32 flow_ctrl_discard;
 563         u32 flow_ctrl_octets;
 564         u32 flow_ctrl_packet;
 565         u32 mng_discard;
 566         u32 mng_octet_inp;
 567         u32 mng_octet_out;
 568         u32 mng_packet_inp;
 569         u32 mng_packet_out;
 570         u32 pbf_octets;
 571         u32 pbf_packet;
 572         u32 safc_inp;
 573         u32 egress_mac_pkt0_lo;
 574         u32 egress_mac_pkt0_hi;
 575         u32 egress_mac_pkt1_lo;
 576         u32 egress_mac_pkt1_hi;
 577 };
 578
 579 struct bnx2x_port {
 580         u32                     pmf;
 581
 582         u32                     link_config;
 583
 584         u32                     supported;
 585 /* link settings - missing defines */
 586 #define SUPPORTED_2500baseX_Full        (1 << 15)
 587
 588         u32                     advertising;
 589 /* link settings - missing defines */
 590 #define ADVERTISED_2500baseX_Full       (1 << 15)
 591
 592         u32                     phy_addr;
 593
 594         /* used to synchronize phy accesses */
 595         struct mutex            phy_mutex;
 596         int                     need_hw_lock;
 597
 598         u32                     port_stx;
 599
 600         struct nig_stats        old_nig_stats;
 601 };
 602
 603 /* end of port */
 604
 605
 606 enum bnx2x_stats_event {
 607         STATS_EVENT_PMF = 0,
 608         STATS_EVENT_LINK_UP,
 609         STATS_EVENT_UPDATE,
 610         STATS_EVENT_STOP,
 611         STATS_EVENT_MAX
 612 };
 613
 614 enum bnx2x_stats_state {
 615         STATS_STATE_DISABLED = 0,
 616         STATS_STATE_ENABLED,
 617         STATS_STATE_MAX
 618 };
 619
 620 struct bnx2x_eth_stats {
 621         u32 total_bytes_received_hi;
 622         u32 total_bytes_received_lo;
 623         u32 total_bytes_transmitted_hi;
 624         u32 total_bytes_transmitted_lo;
 625         u32 total_unicast_packets_received_hi;
 626         u32 total_unicast_packets_received_lo;
 627         u32 total_multicast_packets_received_hi;
 628         u32 total_multicast_packets_received_lo;
 629         u32 total_broadcast_packets_received_hi;
 630         u32 total_broadcast_packets_received_lo;
 631         u32 total_unicast_packets_transmitted_hi;
 632         u32 total_unicast_packets_transmitted_lo;
 633         u32 total_multicast_packets_transmitted_hi;
 634         u32 total_multicast_packets_transmitted_lo;
 635         u32 total_broadcast_packets_transmitted_hi;
 636         u32 total_broadcast_packets_transmitted_lo;
 637         u32 valid_bytes_received_hi;
 638         u32 valid_bytes_received_lo;
 639
 640         u32 error_bytes_received_hi;
 641         u32 error_bytes_received_lo;
 642         u32 etherstatsoverrsizepkts_hi;
 643         u32 etherstatsoverrsizepkts_lo;
 644         u32 no_buff_discard_hi;
 645         u32 no_buff_discard_lo;
 646
 647         u32 rx_stat_ifhcinbadoctets_hi;
 648         u32 rx_stat_ifhcinbadoctets_lo;
 649         u32 tx_stat_ifhcoutbadoctets_hi;
 650         u32 tx_stat_ifhcoutbadoctets_lo;
 651         u32 rx_stat_dot3statsfcserrors_hi;
 652         u32 rx_stat_dot3statsfcserrors_lo;
 653         u32 rx_stat_dot3statsalignmenterrors_hi;
 654         u32 rx_stat_dot3statsalignmenterrors_lo;
 655         u32 rx_stat_dot3statscarriersenseerrors_hi;
 656         u32 rx_stat_dot3statscarriersenseerrors_lo;
 657         u32 rx_stat_falsecarriererrors_hi;
 658         u32 rx_stat_falsecarriererrors_lo;
 659         u32 rx_stat_etherstatsundersizepkts_hi;
 660         u32 rx_stat_etherstatsundersizepkts_lo;
 661         u32 rx_stat_dot3statsframestoolong_hi;
 662         u32 rx_stat_dot3statsframestoolong_lo;
 663         u32 rx_stat_etherstatsfragments_hi;
 664         u32 rx_stat_etherstatsfragments_lo;
 665         u32 rx_stat_etherstatsjabbers_hi;
 666         u32 rx_stat_etherstatsjabbers_lo;
 667         u32 rx_stat_maccontrolframesreceived_hi;
 668         u32 rx_stat_maccontrolframesreceived_lo;
 669         u32 rx_stat_bmac_xpf_hi;
 670         u32 rx_stat_bmac_xpf_lo;
 671         u32 rx_stat_bmac_xcf_hi;
 672         u32 rx_stat_bmac_xcf_lo;
 673         u32 rx_stat_xoffstateentered_hi;
 674         u32 rx_stat_xoffstateentered_lo;
 675         u32 rx_stat_xonpauseframesreceived_hi;
 676         u32 rx_stat_xonpauseframesreceived_lo;
 677         u32 rx_stat_xoffpauseframesreceived_hi;
 678         u32 rx_stat_xoffpauseframesreceived_lo;
 679         u32 tx_stat_outxonsent_hi;
 680         u32 tx_stat_outxonsent_lo;
 681         u32 tx_stat_outxoffsent_hi;
 682         u32 tx_stat_outxoffsent_lo;
 683         u32 tx_stat_flowcontroldone_hi;
 684         u32 tx_stat_flowcontroldone_lo;
 685         u32 tx_stat_etherstatscollisions_hi;
 686         u32 tx_stat_etherstatscollisions_lo;
 687         u32 tx_stat_dot3statssinglecollisionframes_hi;
 688         u32 tx_stat_dot3statssinglecollisionframes_lo;
 689         u32 tx_stat_dot3statsmultiplecollisionframes_hi;
 690         u32 tx_stat_dot3statsmultiplecollisionframes_lo;
 691         u32 tx_stat_dot3statsdeferredtransmissions_hi;
 692         u32 tx_stat_dot3statsdeferredtransmissions_lo;
 693         u32 tx_stat_dot3statsexcessivecollisions_hi;
 694         u32 tx_stat_dot3statsexcessivecollisions_lo;
 695         u32 tx_stat_dot3statslatecollisions_hi;
 696         u32 tx_stat_dot3statslatecollisions_lo;
 697         u32 tx_stat_etherstatspkts64octets_hi;
 698         u32 tx_stat_etherstatspkts64octets_lo;
 699         u32 tx_stat_etherstatspkts65octetsto127octets_hi;
 700         u32 tx_stat_etherstatspkts65octetsto127octets_lo;
 701         u32 tx_stat_etherstatspkts128octetsto255octets_hi;
 702         u32 tx_stat_etherstatspkts128octetsto255octets_lo;
 703         u32 tx_stat_etherstatspkts256octetsto511octets_hi;
 704         u32 tx_stat_etherstatspkts256octetsto511octets_lo;
 705         u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
 706         u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
 707         u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
 708         u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
 709         u32 tx_stat_etherstatspktsover1522octets_hi;
 710         u32 tx_stat_etherstatspktsover1522octets_lo;
 711         u32 tx_stat_bmac_2047_hi;
 712         u32 tx_stat_bmac_2047_lo;
 713         u32 tx_stat_bmac_4095_hi;
 714         u32 tx_stat_bmac_4095_lo;
 715         u32 tx_stat_bmac_9216_hi;
 716         u32 tx_stat_bmac_9216_lo;
 717         u32 tx_stat_bmac_16383_hi;
 718         u32 tx_stat_bmac_16383_lo;
 719         u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
 720         u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
 721         u32 tx_stat_bmac_ufl_hi;
 722         u32 tx_stat_bmac_ufl_lo;
 723
 724         u32 pause_frames_received_hi;
 725         u32 pause_frames_received_lo;
 726         u32 pause_frames_sent_hi;
 727         u32 pause_frames_sent_lo;
 728
 729         u32 etherstatspkts1024octetsto1522octets_hi;
 730         u32 etherstatspkts1024octetsto1522octets_lo;
 731         u32 etherstatspktsover1522octets_hi;
 732         u32 etherstatspktsover1522octets_lo;
 733
 734         u32 brb_drop_hi;
 735         u32 brb_drop_lo;
 736         u32 brb_truncate_hi;
 737         u32 brb_truncate_lo;
 738
 739         u32 mac_filter_discard;
 740         u32 xxoverflow_discard;
 741         u32 brb_truncate_discard;
 742         u32 mac_discard;
 743
 744         u32 driver_xoff;
 745         u32 rx_err_discard_pkt;
 746         u32 rx_skb_alloc_failed;
 747         u32 hw_csum_err;
 748
 749         u32 nig_timer_max;
 750 };
 751
 752 #define BNX2X_NUM_STATS                 41
 753 #define STATS_OFFSET32(stat_name) \
 754                         (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
 755
 756
 757 #define MAX_CONTEXT                     16
 758
 759 union cdu_context {
 760         struct eth_context eth;
 761         char pad[1024];
 762 };
 763
 764 #define MAX_DMAE_C                      8
 765
 766 /* DMA memory not used in fastpath */
 767 struct bnx2x_slowpath {
 768         union cdu_context               context[MAX_CONTEXT];
 769         struct eth_stats_query          fw_stats;
 770         struct mac_configuration_cmd    mac_config;
 771         struct mac_configuration_cmd    mcast_config;
 772
 773         /* used by dmae command executer */
 774         struct dmae_command             dmae[MAX_DMAE_C];
 775
 776         u32                             stats_comp;
 777         union mac_stats                 mac_stats;
 778         struct nig_stats                nig_stats;
 779         struct host_port_stats          port_stats;
 780         struct host_func_stats          func_stats;
 781         struct host_func_stats          func_stats_base;
 782
 783         u32                             wb_comp;
 784         u32                             wb_data[4];
 785 };
 786
 787 #define bnx2x_sp(bp, var)               (&bp->slowpath->var)
 788 #define bnx2x_sp_mapping(bp, var) \
 789                 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
 790
 791
 792 /* attn group wiring */
 793 #define MAX_DYNAMIC_ATTN_GRPS           8
 794
 795 struct attn_route {
 796         u32     sig[4];
 797 };
 798
 799 struct bnx2x {
 800         /* Fields used in the tx and intr/napi performance paths
 801          * are grouped together in the beginning of the structure
 802          */
 803         struct bnx2x_fastpath   fp[MAX_CONTEXT];
 804         void __iomem            *regview;
 805         void __iomem            *doorbells;
 806 #define BNX2X_DB_SIZE           (16*BCM_PAGE_SIZE)
 807
 808         struct net_device       *dev;
 809         struct pci_dev          *pdev;
 810
 811         atomic_t                intr_sem;
 812         struct msix_entry       msix_table[MAX_CONTEXT+1];
 813 #define INT_MODE_INTx                   1
 814 #define INT_MODE_MSI                    2
 815 #define INT_MODE_MSIX                   3
 816
 817         int                     tx_ring_size;
 818
 819 #ifdef BCM_VLAN
 820         struct vlan_group       *vlgrp;
 821 #endif
 822
 823         u32                     rx_csum;
 824         u32                     rx_buf_size;
 825 #define ETH_OVREHEAD                    (ETH_HLEN + 8)  /* 8 for CRC + VLAN */
 826 #define ETH_MIN_PACKET_SIZE             60
 827 #define ETH_MAX_PACKET_SIZE             1500
 828 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
 829
 830         /* Max supported alignment is 256 (8 shift) */
 831 #define BNX2X_RX_ALIGN_SHIFT            ((L1_CACHE_SHIFT < 8) ? \
 832                                          L1_CACHE_SHIFT : 8)
 833 #define BNX2X_RX_ALIGN                  (1 << BNX2X_RX_ALIGN_SHIFT)
 834
 835         struct host_def_status_block *def_status_blk;
 836 #define DEF_SB_ID                       16
 837         __le16                  def_c_idx;
 838         __le16                  def_u_idx;
 839         __le16                  def_x_idx;
 840         __le16                  def_t_idx;
 841         __le16                  def_att_idx;
 842         u32                     attn_state;
 843         struct attn_route       attn_group[MAX_DYNAMIC_ATTN_GRPS];
 844
 845         /* slow path ring */
 846         struct eth_spe          *spq;
 847         dma_addr_t              spq_mapping;
 848         u16                     spq_prod_idx;
 849         struct eth_spe          *spq_prod_bd;
 850         struct eth_spe          *spq_last_bd;
 851         __le16                  *dsb_sp_prod;
 852         u16                     spq_left; /* serialize spq */
 853         /* used to synchronize spq accesses */
 854         spinlock_t              spq_lock;
 855
 856         /* Flags for marking that there is a STAT_QUERY or
 857            SET_MAC ramrod pending */
 858         u8                      stats_pending;
 859         u8                      set_mac_pending;
 860
 861         /* End of fields used in the performance code paths */
 862
 863         int                     panic;
 864         int                     msglevel;
 865
 866         u32                     flags;
 867 #define PCIX_FLAG                       1
 868 #define PCI_32BIT_FLAG                  2
 869 #define ONE_PORT_FLAG                   4
 870 #define NO_WOL_FLAG                     8
 871 #define USING_DAC_FLAG                  0x10
 872 #define USING_MSIX_FLAG                 0x20
 873 #define USING_MSI_FLAG                  0x40
 874 #define TPA_ENABLE_FLAG                 0x80
 875 #define NO_MCP_FLAG                     0x100
 876 #define BP_NOMCP(bp)                    (bp->flags & NO_MCP_FLAG)
 877 #define HW_VLAN_TX_FLAG                 0x400
 878 #define HW_VLAN_RX_FLAG                 0x800
 879
 880         int                     func;
 881 #define BP_PORT(bp)                     (bp->func % PORT_MAX)
 882 #define BP_FUNC(bp)                     (bp->func)
 883 #define BP_E1HVN(bp)                    (bp->func >> 1)
 884 #define BP_L_ID(bp)                     (BP_E1HVN(bp) << 2)
 885
 886         int                     pm_cap;
 887         int                     pcie_cap;
 888         int                     mrrs;
 889
 890         struct delayed_work     sp_task;
 891         struct work_struct      reset_task;
 892
 893         struct timer_list       timer;
 894         int                     current_interval;
 895
 896         u16                     fw_seq;
 897         u16                     fw_drv_pulse_wr_seq;
 898         u32                     func_stx;
 899
 900         struct link_params      link_params;
 901         struct link_vars        link_vars;
 902         struct mdio_if_info     mdio;
 903
 904         struct bnx2x_common     common;
 905         struct bnx2x_port       port;
 906
 907         struct cmng_struct_per_port cmng;
 908         u32                     vn_weight_sum;
 909
 910         u32                     mf_config;
 911         u16                     e1hov;
 912         u8                      e1hmf;
 913 #define IS_E1HMF(bp)                    (bp->e1hmf != 0)
 914
 915         u8                      wol;
 916
 917         int                     rx_ring_size;
 918
 919         u16                     tx_quick_cons_trip_int;
 920         u16                     tx_quick_cons_trip;
 921         u16                     tx_ticks_int;
 922         u16                     tx_ticks;
 923
 924         u16                     rx_quick_cons_trip_int;
 925         u16                     rx_quick_cons_trip;
 926         u16                     rx_ticks_int;
 927         u16                     rx_ticks;
 928
 929         u32                     lin_cnt;
 930
 931         int                     state;
 932 #define BNX2X_STATE_CLOSED              0
 933 #define BNX2X_STATE_OPENING_WAIT4_LOAD  0x1000
 934 #define BNX2X_STATE_OPENING_WAIT4_PORT  0x2000
 935 #define BNX2X_STATE_OPEN                0x3000
 936 #define BNX2X_STATE_CLOSING_WAIT4_HALT  0x4000
 937 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
 938 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
 939 #define BNX2X_STATE_DISABLED            0xd000
 940 #define BNX2X_STATE_DIAG                0xe000
 941 #define BNX2X_STATE_ERROR               0xf000
 942
 943         int                     multi_mode;
 944         int                     num_rx_queues;
 945         int                     num_tx_queues;
 946
 947         u32                     rx_mode;
 948 #define BNX2X_RX_MODE_NONE              0
 949 #define BNX2X_RX_MODE_NORMAL            1
 950 #define BNX2X_RX_MODE_ALLMULTI          2
 951 #define BNX2X_RX_MODE_PROMISC           3
 952 #define BNX2X_MAX_MULTICAST             64
 953 #define BNX2X_MAX_EMUL_MULTI            16
 954
 955         dma_addr_t              def_status_blk_mapping;
 956
 957         struct bnx2x_slowpath   *slowpath;
 958         dma_addr_t              slowpath_mapping;
 959
 960 #ifdef BCM_ISCSI
 961         void                    *t1;
 962         dma_addr_t              t1_mapping;
 963         void                    *t2;
 964         dma_addr_t              t2_mapping;
 965         void                    *timers;
 966         dma_addr_t              timers_mapping;
 967         void                    *qm;
 968         dma_addr_t              qm_mapping;
 969 #endif
 970
 971         int                     dropless_fc;
 972
 973         int                     dmae_ready;
 974         /* used to synchronize dmae accesses */
 975         struct mutex            dmae_mutex;
 976         struct dmae_command     init_dmae;
 977
 978         /* used to synchronize stats collecting */
 979         int                     stats_state;
 980         /* used by dmae command loader */
 981         struct dmae_command     stats_dmae;
 982         int                     executer_idx;
 983
 984         u16                     stats_counter;
 985         struct bnx2x_eth_stats  eth_stats;
 986
 987         struct z_stream_s       *strm;
 988         void                    *gunzip_buf;
 989         dma_addr_t              gunzip_mapping;
 990         int                     gunzip_outlen;
 991 #define FW_BUF_SIZE                     0x8000
 992
 993         struct raw_op          *init_ops;
 994         /* Init blocks offsets inside init_ops */
 995         u16                    *init_ops_offsets;
 996         /* Data blob - has 32 bit granularity */
 997         u32                    *init_data;
 998         /* Zipped PRAM blobs - raw data */
 999         const u8               *tsem_int_table_data;
1000         const u8               *tsem_pram_data;
1001         const u8               *usem_int_table_data;
1002         const u8               *usem_pram_data;
1003         const u8               *xsem_int_table_data;
1004         const u8               *xsem_pram_data;
1005         const u8               *csem_int_table_data;
1006         const u8               *csem_pram_data;
1007         const struct firmware  *firmware;
1008 };
1009
1010
1011 #define BNX2X_MAX_QUEUES(bp)    (IS_E1HMF(bp) ? (MAX_CONTEXT/(2 * E1HVN_MAX)) \
1012                                               : (MAX_CONTEXT/2))
1013 #define BNX2X_NUM_QUEUES(bp)    (bp->num_rx_queues + bp->num_tx_queues)
1014 #define is_multi(bp)            (BNX2X_NUM_QUEUES(bp) > 2)
1015
1016 #define for_each_rx_queue(bp, var) \
1017                         for (var = 0; var < bp->num_rx_queues; var++)
1018 #define for_each_tx_queue(bp, var) \
1019                         for (var = bp->num_rx_queues; \
1020                              var < BNX2X_NUM_QUEUES(bp); var++)
1021 #define for_each_queue(bp, var) \
1022                         for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
1023 #define for_each_nondefault_queue(bp, var) \
1024                         for (var = 1; var < bp->num_rx_queues; var++)
1025
1026
1027 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1028 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1029                       u32 len32);
1030 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1031 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1032 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1033 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
1034
1035 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1036                            int wait)
1037 {
1038         u32 val;
1039
1040         do {
1041                 val = REG_RD(bp, reg);
1042                 if (val == expected)
1043                         break;
1044                 ms -= wait;
1045                 msleep(wait);
1046
1047         } while (ms > 0);
1048
1049         return val;
1050 }
1051
1052
1053 /* load/unload mode */
1054 #define LOAD_NORMAL                     0
1055 #define LOAD_OPEN                       1
1056 #define LOAD_DIAG                       2
1057 #define UNLOAD_NORMAL                   0
1058 #define UNLOAD_CLOSE                    1
1059
1060
1061 /* DMAE command defines */
1062 #define DMAE_CMD_SRC_PCI                0
1063 #define DMAE_CMD_SRC_GRC                DMAE_COMMAND_SRC
1064
1065 #define DMAE_CMD_DST_PCI                (1 << DMAE_COMMAND_DST_SHIFT)
1066 #define DMAE_CMD_DST_GRC                (2 << DMAE_COMMAND_DST_SHIFT)
1067
1068 #define DMAE_CMD_C_DST_PCI              0
1069 #define DMAE_CMD_C_DST_GRC              (1 << DMAE_COMMAND_C_DST_SHIFT)
1070
1071 #define DMAE_CMD_C_ENABLE               DMAE_COMMAND_C_TYPE_ENABLE
1072
1073 #define DMAE_CMD_ENDIANITY_NO_SWAP      (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1074 #define DMAE_CMD_ENDIANITY_B_SWAP       (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1075 #define DMAE_CMD_ENDIANITY_DW_SWAP      (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1076 #define DMAE_CMD_ENDIANITY_B_DW_SWAP    (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1077
1078 #define DMAE_CMD_PORT_0                 0
1079 #define DMAE_CMD_PORT_1                 DMAE_COMMAND_PORT
1080
1081 #define DMAE_CMD_SRC_RESET              DMAE_COMMAND_SRC_RESET
1082 #define DMAE_CMD_DST_RESET              DMAE_COMMAND_DST_RESET
1083 #define DMAE_CMD_E1HVN_SHIFT            DMAE_COMMAND_E1HVN_SHIFT
1084
1085 #define DMAE_LEN32_RD_MAX               0x80
1086 #define DMAE_LEN32_WR_MAX               0x400
1087
1088 #define DMAE_COMP_VAL                   0xe0d0d0ae
1089
1090 #define MAX_DMAE_C_PER_PORT             8
1091 #define INIT_DMAE_C(bp)                 (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1092                                          BP_E1HVN(bp))
1093 #define PMF_DMAE_C(bp)                  (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1094                                          E1HVN_MAX)
1095
1096
1097 /* PCIE link and speed */
1098 #define PCICFG_LINK_WIDTH               0x1f00000
1099 #define PCICFG_LINK_WIDTH_SHIFT         20
1100 #define PCICFG_LINK_SPEED               0xf0000
1101 #define PCICFG_LINK_SPEED_SHIFT         16
1102
1103
1104 #define BNX2X_NUM_TESTS                 7
1105
1106 #define BNX2X_PHY_LOOPBACK              0
1107 #define BNX2X_MAC_LOOPBACK              1
1108 #define BNX2X_PHY_LOOPBACK_FAILED       1
1109 #define BNX2X_MAC_LOOPBACK_FAILED       2
1110 #define BNX2X_LOOPBACK_FAILED           (BNX2X_MAC_LOOPBACK_FAILED | \
1111                                          BNX2X_PHY_LOOPBACK_FAILED)
1112
1113
1114 #define STROM_ASSERT_ARRAY_SIZE         50
1115
1116
1117 /* must be used on a CID before placing it on a HW ring */
1118 #define HW_CID(bp, x)           ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
1119
1120 #define SP_DESC_CNT             (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1121 #define MAX_SP_DESC_CNT                 (SP_DESC_CNT - 1)
1122
1123
1124 #define BNX2X_BTR                       3
1125 #define MAX_SPQ_PENDING                 8
1126
1127
1128 /* CMNG constants
1129    derived from lab experiments, and not from system spec calculations !!! */
1130 #define DEF_MIN_RATE                    100
1131 /* resolution of the rate shaping timer - 100 usec */
1132 #define RS_PERIODIC_TIMEOUT_USEC        100
1133 /* resolution of fairness algorithm in usecs -
1134    coefficient for calculating the actual t fair */
1135 #define T_FAIR_COEF                     10000000
1136 /* number of bytes in single QM arbitration cycle -
1137    coefficient for calculating the fairness timer */
1138 #define QM_ARB_BYTES                    40000
1139 #define FAIR_MEM                        2
1140
1141
1142 #define ATTN_NIG_FOR_FUNC               (1L << 8)
1143 #define ATTN_SW_TIMER_4_FUNC            (1L << 9)
1144 #define GPIO_2_FUNC                     (1L << 10)
1145 #define GPIO_3_FUNC                     (1L << 11)
1146 #define GPIO_4_FUNC                     (1L << 12)
1147 #define ATTN_GENERAL_ATTN_1             (1L << 13)
1148 #define ATTN_GENERAL_ATTN_2             (1L << 14)
1149 #define ATTN_GENERAL_ATTN_3             (1L << 15)
1150 #define ATTN_GENERAL_ATTN_4             (1L << 13)
1151 #define ATTN_GENERAL_ATTN_5             (1L << 14)
1152 #define ATTN_GENERAL_ATTN_6             (1L << 15)
1153
1154 #define ATTN_HARD_WIRED_MASK            0xff00
1155 #define ATTENTION_ID                    4
1156
1157
1158 /* stuff added to make the code fit 80Col */
1159
1160 #define BNX2X_PMF_LINK_ASSERT \
1161         GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1162
1163 #define BNX2X_MC_ASSERT_BITS \
1164         (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1165          GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1166          GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1167          GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1168
1169 #define BNX2X_MCP_ASSERT \
1170         GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1171
1172 #define BNX2X_GRC_TIMEOUT       GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1173 #define BNX2X_GRC_RSV           (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1174                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1175                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1176                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1177                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1178                                  GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1179
1180 #define HW_INTERRUT_ASSERT_SET_0 \
1181                                 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1182                                  AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1183                                  AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1184                                  AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1185 #define HW_PRTY_ASSERT_SET_0    (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1186                                  AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1187                                  AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1188                                  AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1189                                  AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1190 #define HW_INTERRUT_ASSERT_SET_1 \
1191                                 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1192                                  AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1193                                  AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1194                                  AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1195                                  AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1196                                  AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1197                                  AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1198                                  AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1199                                  AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1200                                  AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1201                                  AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1202 #define HW_PRTY_ASSERT_SET_1    (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1203                                  AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1204                                  AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1205                                  AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1206                                 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1207                             AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1208                                  AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1209                                  AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1210                                  AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1211                                  AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1212                                  AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1213 #define HW_INTERRUT_ASSERT_SET_2 \
1214                                 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1215                                  AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1216                                  AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1217                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1218                                  AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1219 #define HW_PRTY_ASSERT_SET_2    (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1220                                  AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1221                         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1222                                  AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1223                                  AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1224                                  AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1225                                  AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1226
1227
1228 #define MULTI_FLAGS(bp) \
1229                 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1230                  TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1231                  TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1232                  TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1233                  (bp->multi_mode << \
1234                   TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1235
1236 #define MULTI_MASK                      0x7f
1237
1238
1239 #define DEF_USB_FUNC_OFF                (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1240 #define DEF_CSB_FUNC_OFF                (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1241 #define DEF_XSB_FUNC_OFF                (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1242 #define DEF_TSB_FUNC_OFF                (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1243
1244 #define C_DEF_SB_SP_INDEX               HC_INDEX_DEF_C_ETH_SLOW_PATH
1245
1246 #define BNX2X_SP_DSB_INDEX \
1247 (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1248
1249
1250 #define CAM_IS_INVALID(x) \
1251 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1252
1253 #define CAM_INVALIDATE(x) \
1254         (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1255
1256
1257 /* Number of u32 elements in MC hash array */
1258 #define MC_HASH_SIZE                    8
1259 #define MC_HASH_OFFSET(bp, i)           (BAR_TSTRORM_INTMEM + \
1260         TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1261
1262
1263 #ifndef PXP2_REG_PXP2_INT_STS
1264 #define PXP2_REG_PXP2_INT_STS           PXP2_REG_PXP2_INT_STS_0
1265 #endif
1266
1267 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1268
1269 #endif /* bnx2x.h */