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bnx2x: Using the new FW
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2x.h
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2009 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16
17 /* compilation time flags */
18
19 /* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21 /* #define BNX2X_STOP_ON_ERROR */
22
23 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
24 #define BCM_VLAN 1
25 #endif
26
27
28 #define BNX2X_MULTI_QUEUE
29
30 #define BNX2X_NEW_NAPI
31
32
33 #include "bnx2x_reg.h"
34 #include "bnx2x_fw_defs.h"
35 #include "bnx2x_hsi.h"
36 #include "bnx2x_link.h"
37
38 /* error/debug prints */
39
40 #define DRV_MODULE_NAME "bnx2x"
41 #define PFX DRV_MODULE_NAME ": "
42
43 /* for messages that are currently off */
44 #define BNX2X_MSG_OFF 0
45 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
46 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
47 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
48 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
49 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
50 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
51
52 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
53
54 /* regular debug print */
55 #define DP(__mask, __fmt, __args...) do { \
56 if (bp->msglevel & (__mask)) \
57 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
58 bp->dev ? (bp->dev->name) : "?", ##__args); \
59 } while (0)
60
61 /* errors debug print */
62 #define BNX2X_DBG_ERR(__fmt, __args...) do { \
63 if (bp->msglevel & NETIF_MSG_PROBE) \
64 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
65 bp->dev ? (bp->dev->name) : "?", ##__args); \
66 } while (0)
67
68 /* for errors (never masked) */
69 #define BNX2X_ERR(__fmt, __args...) do { \
70 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
71 bp->dev ? (bp->dev->name) : "?", ##__args); \
72 } while (0)
73
74 /* before we have a dev->name use dev_info() */
75 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
76 if (bp->msglevel & NETIF_MSG_PROBE) \
77 dev_info(&bp->pdev->dev, __fmt, ##__args); \
78 } while (0)
79
80
81 #ifdef BNX2X_STOP_ON_ERROR
82 #define bnx2x_panic() do { \
83 bp->panic = 1; \
84 BNX2X_ERR("driver assert\n"); \
85 bnx2x_int_disable(bp); \
86 bnx2x_panic_dump(bp); \
87 } while (0)
88 #else
89 #define bnx2x_panic() do { \
90 BNX2X_ERR("driver assert\n"); \
91 bnx2x_panic_dump(bp); \
92 } while (0)
93 #endif
94
95
96 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
97 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
98 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
99
100
101 #define REG_ADDR(bp, offset) (bp->regview + offset)
102
103 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
104 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
105
106 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
107 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
108 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
109
110 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
111 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
112
113 #define REG_RD_DMAE(bp, offset, valp, len32) \
114 do { \
115 bnx2x_read_dmae(bp, offset, len32);\
116 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
117 } while (0)
118
119 #define REG_WR_DMAE(bp, offset, valp, len32) \
120 do { \
121 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
122 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
123 offset, len32); \
124 } while (0)
125
126 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
127 offsetof(struct shmem_region, field))
128 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
129 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
130
131 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
132 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
133
134
135 /* fast path */
136
137 struct sw_rx_bd {
138 struct sk_buff *skb;
139 DECLARE_PCI_UNMAP_ADDR(mapping)
140 };
141
142 struct sw_tx_bd {
143 struct sk_buff *skb;
144 u16 first_bd;
145 u8 flags;
146 /* Set on the first BD descriptor when there is a split BD */
147 #define BNX2X_TSO_SPLIT_BD (1<<0)
148 };
149
150 struct sw_rx_page {
151 struct page *page;
152 DECLARE_PCI_UNMAP_ADDR(mapping)
153 };
154
155 union db_prod {
156 struct doorbell_set_prod data;
157 u32 raw;
158 };
159
160
161 /* MC hsi */
162 #define BCM_PAGE_SHIFT 12
163 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
164 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
165 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
166
167 #define PAGES_PER_SGE_SHIFT 0
168 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
169 #define SGE_PAGE_SIZE PAGE_SIZE
170 #define SGE_PAGE_SHIFT PAGE_SHIFT
171 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
172
173 /* SGE ring related macros */
174 #define NUM_RX_SGE_PAGES 2
175 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
176 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
177 /* RX_SGE_CNT is promised to be a power of 2 */
178 #define RX_SGE_MASK (RX_SGE_CNT - 1)
179 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
180 #define MAX_RX_SGE (NUM_RX_SGE - 1)
181 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
182 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
183 #define RX_SGE(x) ((x) & MAX_RX_SGE)
184
185 /* SGE producer mask related macros */
186 /* Number of bits in one sge_mask array element */
187 #define RX_SGE_MASK_ELEM_SZ 64
188 #define RX_SGE_MASK_ELEM_SHIFT 6
189 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
190
191 /* Creates a bitmask of all ones in less significant bits.
192 idx - index of the most significant bit in the created mask */
193 #define RX_SGE_ONES_MASK(idx) \
194 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
195 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
196
197 /* Number of u64 elements in SGE mask array */
198 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
199 RX_SGE_MASK_ELEM_SZ)
200 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
201 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
202
203
204 struct bnx2x_eth_q_stats {
205 u32 total_bytes_received_hi;
206 u32 total_bytes_received_lo;
207 u32 total_bytes_transmitted_hi;
208 u32 total_bytes_transmitted_lo;
209 u32 total_unicast_packets_received_hi;
210 u32 total_unicast_packets_received_lo;
211 u32 total_multicast_packets_received_hi;
212 u32 total_multicast_packets_received_lo;
213 u32 total_broadcast_packets_received_hi;
214 u32 total_broadcast_packets_received_lo;
215 u32 total_unicast_packets_transmitted_hi;
216 u32 total_unicast_packets_transmitted_lo;
217 u32 total_multicast_packets_transmitted_hi;
218 u32 total_multicast_packets_transmitted_lo;
219 u32 total_broadcast_packets_transmitted_hi;
220 u32 total_broadcast_packets_transmitted_lo;
221 u32 valid_bytes_received_hi;
222 u32 valid_bytes_received_lo;
223
224 u32 error_bytes_received_hi;
225 u32 error_bytes_received_lo;
226 u32 etherstatsoverrsizepkts_hi;
227 u32 etherstatsoverrsizepkts_lo;
228 u32 no_buff_discard_hi;
229 u32 no_buff_discard_lo;
230
231 u32 driver_xoff;
232 u32 rx_err_discard_pkt;
233 u32 rx_skb_alloc_failed;
234 u32 hw_csum_err;
235 };
236
237 #define BNX2X_NUM_Q_STATS 11
238 #define Q_STATS_OFFSET32(stat_name) \
239 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
240
241 struct bnx2x_fastpath {
242
243 struct napi_struct napi;
244
245 u8 is_rx_queue;
246
247 struct host_status_block *status_blk;
248 dma_addr_t status_blk_mapping;
249
250 struct sw_tx_bd *tx_buf_ring;
251
252 union eth_tx_bd_types *tx_desc_ring;
253 dma_addr_t tx_desc_mapping;
254
255 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
256 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
257
258 struct eth_rx_bd *rx_desc_ring;
259 dma_addr_t rx_desc_mapping;
260
261 union eth_rx_cqe *rx_comp_ring;
262 dma_addr_t rx_comp_mapping;
263
264 /* SGE ring */
265 struct eth_rx_sge *rx_sge_ring;
266 dma_addr_t rx_sge_mapping;
267
268 u64 sge_mask[RX_SGE_MASK_LEN];
269
270 int state;
271 #define BNX2X_FP_STATE_CLOSED 0
272 #define BNX2X_FP_STATE_IRQ 0x80000
273 #define BNX2X_FP_STATE_OPENING 0x90000
274 #define BNX2X_FP_STATE_OPEN 0xa0000
275 #define BNX2X_FP_STATE_HALTING 0xb0000
276 #define BNX2X_FP_STATE_HALTED 0xc0000
277
278 u8 index; /* number in fp array */
279 u8 cl_id; /* eth client id */
280 u8 sb_id; /* status block number in HW */
281
282 union db_prod tx_db;
283
284 u16 tx_pkt_prod;
285 u16 tx_pkt_cons;
286 u16 tx_bd_prod;
287 u16 tx_bd_cons;
288 __le16 *tx_cons_sb;
289
290 __le16 fp_c_idx;
291 __le16 fp_u_idx;
292
293 u16 rx_bd_prod;
294 u16 rx_bd_cons;
295 u16 rx_comp_prod;
296 u16 rx_comp_cons;
297 u16 rx_sge_prod;
298 /* The last maximal completed SGE */
299 u16 last_max_sge;
300 __le16 *rx_cons_sb;
301 __le16 *rx_bd_cons_sb;
302
303 unsigned long tx_pkt,
304 rx_pkt,
305 rx_calls;
306 /* TPA related */
307 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
308 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
309 #define BNX2X_TPA_START 1
310 #define BNX2X_TPA_STOP 2
311 u8 disable_tpa;
312 #ifdef BNX2X_STOP_ON_ERROR
313 u64 tpa_queue_used;
314 #endif
315
316 struct tstorm_per_client_stats old_tclient;
317 struct ustorm_per_client_stats old_uclient;
318 struct xstorm_per_client_stats old_xclient;
319 struct bnx2x_eth_q_stats eth_q_stats;
320
321 /* The size is calculated using the following:
322 sizeof name field from netdev structure +
323 4 ('-Xx-' string) +
324 4 (for the digits and to make it DWORD aligned) */
325 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
326 char name[FP_NAME_SIZE];
327 struct bnx2x *bp; /* parent */
328 };
329
330 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
331
332
333 /* MC hsi */
334 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
335 #define RX_COPY_THRESH 92
336
337 #define NUM_TX_RINGS 16
338 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
339 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
340 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
341 #define MAX_TX_BD (NUM_TX_BD - 1)
342 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
343 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
344 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
345 #define TX_BD(x) ((x) & MAX_TX_BD)
346 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
347
348 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
349 #define NUM_RX_RINGS 8
350 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
351 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
352 #define RX_DESC_MASK (RX_DESC_CNT - 1)
353 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
354 #define MAX_RX_BD (NUM_RX_BD - 1)
355 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
356 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
357 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
358 #define RX_BD(x) ((x) & MAX_RX_BD)
359
360 /* As long as CQE is 4 times bigger than BD entry we have to allocate
361 4 times more pages for CQ ring in order to keep it balanced with
362 BD ring */
363 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
364 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
365 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
366 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
367 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
368 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
369 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
370 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
371 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
372
373
374 /* This is needed for determining of last_max */
375 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
376
377 #define __SGE_MASK_SET_BIT(el, bit) \
378 do { \
379 el = ((el) | ((u64)0x1 << (bit))); \
380 } while (0)
381
382 #define __SGE_MASK_CLEAR_BIT(el, bit) \
383 do { \
384 el = ((el) & (~((u64)0x1 << (bit)))); \
385 } while (0)
386
387 #define SGE_MASK_SET_BIT(fp, idx) \
388 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
389 ((idx) & RX_SGE_MASK_ELEM_MASK))
390
391 #define SGE_MASK_CLEAR_BIT(fp, idx) \
392 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
393 ((idx) & RX_SGE_MASK_ELEM_MASK))
394
395
396 /* used on a CID received from the HW */
397 #define SW_CID(x) (le32_to_cpu(x) & \
398 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
399 #define CQE_CMD(x) (le32_to_cpu(x) >> \
400 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
401
402 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
403 le32_to_cpu((bd)->addr_lo))
404 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
405
406
407 #define DPM_TRIGER_TYPE 0x40
408 #define DOORBELL(bp, cid, val) \
409 do { \
410 writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
411 DPM_TRIGER_TYPE); \
412 } while (0)
413
414
415 /* TX CSUM helpers */
416 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
417 skb->csum_offset)
418 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
419 skb->csum_offset))
420
421 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
422
423 #define XMIT_PLAIN 0
424 #define XMIT_CSUM_V4 0x1
425 #define XMIT_CSUM_V6 0x2
426 #define XMIT_CSUM_TCP 0x4
427 #define XMIT_GSO_V4 0x8
428 #define XMIT_GSO_V6 0x10
429
430 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
431 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
432
433
434 /* stuff added to make the code fit 80Col */
435
436 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
437
438 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
439 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
440 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
441 (TPA_TYPE_START | TPA_TYPE_END))
442
443 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
444
445 #define BNX2X_IP_CSUM_ERR(cqe) \
446 (!((cqe)->fast_path_cqe.status_flags & \
447 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
448 ((cqe)->fast_path_cqe.type_error_flags & \
449 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
450
451 #define BNX2X_L4_CSUM_ERR(cqe) \
452 (!((cqe)->fast_path_cqe.status_flags & \
453 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
454 ((cqe)->fast_path_cqe.type_error_flags & \
455 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
456
457 #define BNX2X_RX_CSUM_OK(cqe) \
458 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
459
460 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
461 (((le16_to_cpu(flags) & \
462 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
463 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
464 == PRS_FLAG_OVERETH_IPV4)
465 #define BNX2X_RX_SUM_FIX(cqe) \
466 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
467
468
469 #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
470 #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
471
472 #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
473 #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
474 #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
475
476 #define BNX2X_RX_SB_INDEX \
477 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
478
479 #define BNX2X_RX_SB_BD_INDEX \
480 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
481
482 #define BNX2X_RX_SB_INDEX_NUM \
483 (((U_SB_ETH_RX_CQ_INDEX << \
484 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
485 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
486 ((U_SB_ETH_RX_BD_INDEX << \
487 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
488 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
489
490 #define BNX2X_TX_SB_INDEX \
491 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
492
493
494 /* end of fast path */
495
496 /* common */
497
498 struct bnx2x_common {
499
500 u32 chip_id;
501 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
502 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
503
504 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
505 #define CHIP_NUM_57710 0x164e
506 #define CHIP_NUM_57711 0x164f
507 #define CHIP_NUM_57711E 0x1650
508 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
509 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
510 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
511 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
512 CHIP_IS_57711E(bp))
513 #define IS_E1H_OFFSET CHIP_IS_E1H(bp)
514
515 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
516 #define CHIP_REV_Ax 0x00000000
517 /* assume maximum 5 revisions */
518 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
519 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
520 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
521 !(CHIP_REV(bp) & 0x00001000))
522 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
523 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
524 (CHIP_REV(bp) & 0x00001000))
525
526 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
527 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
528
529 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
530 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
531
532 int flash_size;
533 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
534 #define NVRAM_TIMEOUT_COUNT 30000
535 #define NVRAM_PAGE_SIZE 256
536
537 u32 shmem_base;
538
539 u32 hw_config;
540
541 u32 bc_ver;
542 };
543
544
545 /* end of common */
546
547 /* port */
548
549 struct nig_stats {
550 u32 brb_discard;
551 u32 brb_packet;
552 u32 brb_truncate;
553 u32 flow_ctrl_discard;
554 u32 flow_ctrl_octets;
555 u32 flow_ctrl_packet;
556 u32 mng_discard;
557 u32 mng_octet_inp;
558 u32 mng_octet_out;
559 u32 mng_packet_inp;
560 u32 mng_packet_out;
561 u32 pbf_octets;
562 u32 pbf_packet;
563 u32 safc_inp;
564 u32 egress_mac_pkt0_lo;
565 u32 egress_mac_pkt0_hi;
566 u32 egress_mac_pkt1_lo;
567 u32 egress_mac_pkt1_hi;
568 };
569
570 struct bnx2x_port {
571 u32 pmf;
572
573 u32 link_config;
574
575 u32 supported;
576 /* link settings - missing defines */
577 #define SUPPORTED_2500baseX_Full (1 << 15)
578
579 u32 advertising;
580 /* link settings - missing defines */
581 #define ADVERTISED_2500baseX_Full (1 << 15)
582
583 u32 phy_addr;
584
585 /* used to synchronize phy accesses */
586 struct mutex phy_mutex;
587 int need_hw_lock;
588
589 u32 port_stx;
590
591 struct nig_stats old_nig_stats;
592 };
593
594 /* end of port */
595
596
597 enum bnx2x_stats_event {
598 STATS_EVENT_PMF = 0,
599 STATS_EVENT_LINK_UP,
600 STATS_EVENT_UPDATE,
601 STATS_EVENT_STOP,
602 STATS_EVENT_MAX
603 };
604
605 enum bnx2x_stats_state {
606 STATS_STATE_DISABLED = 0,
607 STATS_STATE_ENABLED,
608 STATS_STATE_MAX
609 };
610
611 struct bnx2x_eth_stats {
612 u32 total_bytes_received_hi;
613 u32 total_bytes_received_lo;
614 u32 total_bytes_transmitted_hi;
615 u32 total_bytes_transmitted_lo;
616 u32 total_unicast_packets_received_hi;
617 u32 total_unicast_packets_received_lo;
618 u32 total_multicast_packets_received_hi;
619 u32 total_multicast_packets_received_lo;
620 u32 total_broadcast_packets_received_hi;
621 u32 total_broadcast_packets_received_lo;
622 u32 total_unicast_packets_transmitted_hi;
623 u32 total_unicast_packets_transmitted_lo;
624 u32 total_multicast_packets_transmitted_hi;
625 u32 total_multicast_packets_transmitted_lo;
626 u32 total_broadcast_packets_transmitted_hi;
627 u32 total_broadcast_packets_transmitted_lo;
628 u32 valid_bytes_received_hi;
629 u32 valid_bytes_received_lo;
630
631 u32 error_bytes_received_hi;
632 u32 error_bytes_received_lo;
633 u32 etherstatsoverrsizepkts_hi;
634 u32 etherstatsoverrsizepkts_lo;
635 u32 no_buff_discard_hi;
636 u32 no_buff_discard_lo;
637
638 u32 rx_stat_ifhcinbadoctets_hi;
639 u32 rx_stat_ifhcinbadoctets_lo;
640 u32 tx_stat_ifhcoutbadoctets_hi;
641 u32 tx_stat_ifhcoutbadoctets_lo;
642 u32 rx_stat_dot3statsfcserrors_hi;
643 u32 rx_stat_dot3statsfcserrors_lo;
644 u32 rx_stat_dot3statsalignmenterrors_hi;
645 u32 rx_stat_dot3statsalignmenterrors_lo;
646 u32 rx_stat_dot3statscarriersenseerrors_hi;
647 u32 rx_stat_dot3statscarriersenseerrors_lo;
648 u32 rx_stat_falsecarriererrors_hi;
649 u32 rx_stat_falsecarriererrors_lo;
650 u32 rx_stat_etherstatsundersizepkts_hi;
651 u32 rx_stat_etherstatsundersizepkts_lo;
652 u32 rx_stat_dot3statsframestoolong_hi;
653 u32 rx_stat_dot3statsframestoolong_lo;
654 u32 rx_stat_etherstatsfragments_hi;
655 u32 rx_stat_etherstatsfragments_lo;
656 u32 rx_stat_etherstatsjabbers_hi;
657 u32 rx_stat_etherstatsjabbers_lo;
658 u32 rx_stat_maccontrolframesreceived_hi;
659 u32 rx_stat_maccontrolframesreceived_lo;
660 u32 rx_stat_bmac_xpf_hi;
661 u32 rx_stat_bmac_xpf_lo;
662 u32 rx_stat_bmac_xcf_hi;
663 u32 rx_stat_bmac_xcf_lo;
664 u32 rx_stat_xoffstateentered_hi;
665 u32 rx_stat_xoffstateentered_lo;
666 u32 rx_stat_xonpauseframesreceived_hi;
667 u32 rx_stat_xonpauseframesreceived_lo;
668 u32 rx_stat_xoffpauseframesreceived_hi;
669 u32 rx_stat_xoffpauseframesreceived_lo;
670 u32 tx_stat_outxonsent_hi;
671 u32 tx_stat_outxonsent_lo;
672 u32 tx_stat_outxoffsent_hi;
673 u32 tx_stat_outxoffsent_lo;
674 u32 tx_stat_flowcontroldone_hi;
675 u32 tx_stat_flowcontroldone_lo;
676 u32 tx_stat_etherstatscollisions_hi;
677 u32 tx_stat_etherstatscollisions_lo;
678 u32 tx_stat_dot3statssinglecollisionframes_hi;
679 u32 tx_stat_dot3statssinglecollisionframes_lo;
680 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
681 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
682 u32 tx_stat_dot3statsdeferredtransmissions_hi;
683 u32 tx_stat_dot3statsdeferredtransmissions_lo;
684 u32 tx_stat_dot3statsexcessivecollisions_hi;
685 u32 tx_stat_dot3statsexcessivecollisions_lo;
686 u32 tx_stat_dot3statslatecollisions_hi;
687 u32 tx_stat_dot3statslatecollisions_lo;
688 u32 tx_stat_etherstatspkts64octets_hi;
689 u32 tx_stat_etherstatspkts64octets_lo;
690 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
691 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
692 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
693 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
694 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
695 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
696 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
697 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
698 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
699 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
700 u32 tx_stat_etherstatspktsover1522octets_hi;
701 u32 tx_stat_etherstatspktsover1522octets_lo;
702 u32 tx_stat_bmac_2047_hi;
703 u32 tx_stat_bmac_2047_lo;
704 u32 tx_stat_bmac_4095_hi;
705 u32 tx_stat_bmac_4095_lo;
706 u32 tx_stat_bmac_9216_hi;
707 u32 tx_stat_bmac_9216_lo;
708 u32 tx_stat_bmac_16383_hi;
709 u32 tx_stat_bmac_16383_lo;
710 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
711 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
712 u32 tx_stat_bmac_ufl_hi;
713 u32 tx_stat_bmac_ufl_lo;
714
715 u32 pause_frames_received_hi;
716 u32 pause_frames_received_lo;
717 u32 pause_frames_sent_hi;
718 u32 pause_frames_sent_lo;
719
720 u32 etherstatspkts1024octetsto1522octets_hi;
721 u32 etherstatspkts1024octetsto1522octets_lo;
722 u32 etherstatspktsover1522octets_hi;
723 u32 etherstatspktsover1522octets_lo;
724
725 u32 brb_drop_hi;
726 u32 brb_drop_lo;
727 u32 brb_truncate_hi;
728 u32 brb_truncate_lo;
729
730 u32 mac_filter_discard;
731 u32 xxoverflow_discard;
732 u32 brb_truncate_discard;
733 u32 mac_discard;
734
735 u32 driver_xoff;
736 u32 rx_err_discard_pkt;
737 u32 rx_skb_alloc_failed;
738 u32 hw_csum_err;
739
740 u32 nig_timer_max;
741 };
742
743 #define BNX2X_NUM_STATS 41
744 #define STATS_OFFSET32(stat_name) \
745 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
746
747
748 #define MAX_CONTEXT 16
749
750 union cdu_context {
751 struct eth_context eth;
752 char pad[1024];
753 };
754
755 #define MAX_DMAE_C 8
756
757 /* DMA memory not used in fastpath */
758 struct bnx2x_slowpath {
759 union cdu_context context[MAX_CONTEXT];
760 struct eth_stats_query fw_stats;
761 struct mac_configuration_cmd mac_config;
762 struct mac_configuration_cmd mcast_config;
763
764 /* used by dmae command executer */
765 struct dmae_command dmae[MAX_DMAE_C];
766
767 u32 stats_comp;
768 union mac_stats mac_stats;
769 struct nig_stats nig_stats;
770 struct host_port_stats port_stats;
771 struct host_func_stats func_stats;
772
773 u32 wb_comp;
774 u32 wb_data[4];
775 };
776
777 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
778 #define bnx2x_sp_mapping(bp, var) \
779 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
780
781
782 /* attn group wiring */
783 #define MAX_DYNAMIC_ATTN_GRPS 8
784
785 struct attn_route {
786 u32 sig[4];
787 };
788
789 struct bnx2x {
790 /* Fields used in the tx and intr/napi performance paths
791 * are grouped together in the beginning of the structure
792 */
793 struct bnx2x_fastpath fp[MAX_CONTEXT];
794 void __iomem *regview;
795 void __iomem *doorbells;
796 #define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE)
797
798 struct net_device *dev;
799 struct pci_dev *pdev;
800
801 atomic_t intr_sem;
802 struct msix_entry msix_table[MAX_CONTEXT+1];
803 #define INT_MODE_INTx 1
804 #define INT_MODE_MSI 2
805 #define INT_MODE_MSIX 3
806
807 int tx_ring_size;
808
809 #ifdef BCM_VLAN
810 struct vlan_group *vlgrp;
811 #endif
812
813 u32 rx_csum;
814 u32 rx_buf_size;
815 #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
816 #define ETH_MIN_PACKET_SIZE 60
817 #define ETH_MAX_PACKET_SIZE 1500
818 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
819
820 /* Max supported alignment is 256 (8 shift) */
821 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
822 L1_CACHE_SHIFT : 8)
823 #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
824
825 struct host_def_status_block *def_status_blk;
826 #define DEF_SB_ID 16
827 __le16 def_c_idx;
828 __le16 def_u_idx;
829 __le16 def_x_idx;
830 __le16 def_t_idx;
831 __le16 def_att_idx;
832 u32 attn_state;
833 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
834
835 /* slow path ring */
836 struct eth_spe *spq;
837 dma_addr_t spq_mapping;
838 u16 spq_prod_idx;
839 struct eth_spe *spq_prod_bd;
840 struct eth_spe *spq_last_bd;
841 __le16 *dsb_sp_prod;
842 u16 spq_left; /* serialize spq */
843 /* used to synchronize spq accesses */
844 spinlock_t spq_lock;
845
846 /* Flags for marking that there is a STAT_QUERY or
847 SET_MAC ramrod pending */
848 u8 stats_pending;
849 u8 set_mac_pending;
850
851 /* End of fields used in the performance code paths */
852
853 int panic;
854 int msglevel;
855
856 u32 flags;
857 #define PCIX_FLAG 1
858 #define PCI_32BIT_FLAG 2
859 #define ONE_PORT_FLAG 4
860 #define NO_WOL_FLAG 8
861 #define USING_DAC_FLAG 0x10
862 #define USING_MSIX_FLAG 0x20
863 #define USING_MSI_FLAG 0x40
864 #define TPA_ENABLE_FLAG 0x80
865 #define NO_MCP_FLAG 0x100
866 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
867 #define HW_VLAN_TX_FLAG 0x400
868 #define HW_VLAN_RX_FLAG 0x800
869
870 int func;
871 #define BP_PORT(bp) (bp->func % PORT_MAX)
872 #define BP_FUNC(bp) (bp->func)
873 #define BP_E1HVN(bp) (bp->func >> 1)
874 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
875
876 int pm_cap;
877 int pcie_cap;
878 int mrrs;
879
880 struct delayed_work sp_task;
881 struct work_struct reset_task;
882
883 struct timer_list timer;
884 int current_interval;
885
886 u16 fw_seq;
887 u16 fw_drv_pulse_wr_seq;
888 u32 func_stx;
889
890 struct link_params link_params;
891 struct link_vars link_vars;
892
893 struct bnx2x_common common;
894 struct bnx2x_port port;
895
896 struct cmng_struct_per_port cmng;
897 u32 vn_weight_sum;
898
899 u32 mf_config;
900 u16 e1hov;
901 u8 e1hmf;
902 #define IS_E1HMF(bp) (bp->e1hmf != 0)
903
904 u8 wol;
905
906 int rx_ring_size;
907
908 u16 tx_quick_cons_trip_int;
909 u16 tx_quick_cons_trip;
910 u16 tx_ticks_int;
911 u16 tx_ticks;
912
913 u16 rx_quick_cons_trip_int;
914 u16 rx_quick_cons_trip;
915 u16 rx_ticks_int;
916 u16 rx_ticks;
917
918 u32 lin_cnt;
919
920 int state;
921 #define BNX2X_STATE_CLOSED 0
922 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
923 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
924 #define BNX2X_STATE_OPEN 0x3000
925 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
926 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
927 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
928 #define BNX2X_STATE_DISABLED 0xd000
929 #define BNX2X_STATE_DIAG 0xe000
930 #define BNX2X_STATE_ERROR 0xf000
931
932 int multi_mode;
933 int num_rx_queues;
934 int num_tx_queues;
935
936 u32 rx_mode;
937 #define BNX2X_RX_MODE_NONE 0
938 #define BNX2X_RX_MODE_NORMAL 1
939 #define BNX2X_RX_MODE_ALLMULTI 2
940 #define BNX2X_RX_MODE_PROMISC 3
941 #define BNX2X_MAX_MULTICAST 64
942 #define BNX2X_MAX_EMUL_MULTI 16
943
944 dma_addr_t def_status_blk_mapping;
945
946 struct bnx2x_slowpath *slowpath;
947 dma_addr_t slowpath_mapping;
948
949 #ifdef BCM_ISCSI
950 void *t1;
951 dma_addr_t t1_mapping;
952 void *t2;
953 dma_addr_t t2_mapping;
954 void *timers;
955 dma_addr_t timers_mapping;
956 void *qm;
957 dma_addr_t qm_mapping;
958 #endif
959
960 int dmae_ready;
961 /* used to synchronize dmae accesses */
962 struct mutex dmae_mutex;
963 struct dmae_command init_dmae;
964
965 /* used to synchronize stats collecting */
966 int stats_state;
967 /* used by dmae command loader */
968 struct dmae_command stats_dmae;
969 int executer_idx;
970
971 u16 stats_counter;
972 struct bnx2x_eth_stats eth_stats;
973
974 struct z_stream_s *strm;
975 void *gunzip_buf;
976 dma_addr_t gunzip_mapping;
977 int gunzip_outlen;
978 #define FW_BUF_SIZE 0x8000
979
980 struct raw_op *init_ops;
981 /* Init blocks offsets inside init_ops */
982 u16 *init_ops_offsets;
983 /* Data blob - has 32 bit granularity */
984 u32 *init_data;
985 /* Zipped PRAM blobs - raw data */
986 const u8 *tsem_int_table_data;
987 const u8 *tsem_pram_data;
988 const u8 *usem_int_table_data;
989 const u8 *usem_pram_data;
990 const u8 *xsem_int_table_data;
991 const u8 *xsem_pram_data;
992 const u8 *csem_int_table_data;
993 const u8 *csem_pram_data;
994 const struct firmware *firmware;
995 };
996
997
998 #define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT/(2 * E1HVN_MAX)) \
999 : (MAX_CONTEXT/2))
1000 #define BNX2X_NUM_QUEUES(bp) (bp->num_rx_queues + bp->num_tx_queues)
1001 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 2)
1002
1003 #define for_each_rx_queue(bp, var) \
1004 for (var = 0; var < bp->num_rx_queues; var++)
1005 #define for_each_tx_queue(bp, var) \
1006 for (var = bp->num_rx_queues; \
1007 var < BNX2X_NUM_QUEUES(bp); var++)
1008 #define for_each_queue(bp, var) \
1009 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
1010 #define for_each_nondefault_queue(bp, var) \
1011 for (var = 1; var < bp->num_rx_queues; var++)
1012
1013
1014 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1015 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1016 u32 len32);
1017 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1018 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1019 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1020 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
1021
1022 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1023 int wait)
1024 {
1025 u32 val;
1026
1027 do {
1028 val = REG_RD(bp, reg);
1029 if (val == expected)
1030 break;
1031 ms -= wait;
1032 msleep(wait);
1033
1034 } while (ms > 0);
1035
1036 return val;
1037 }
1038
1039
1040 /* load/unload mode */
1041 #define LOAD_NORMAL 0
1042 #define LOAD_OPEN 1
1043 #define LOAD_DIAG 2
1044 #define UNLOAD_NORMAL 0
1045 #define UNLOAD_CLOSE 1
1046
1047
1048 /* DMAE command defines */
1049 #define DMAE_CMD_SRC_PCI 0
1050 #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
1051
1052 #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
1053 #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
1054
1055 #define DMAE_CMD_C_DST_PCI 0
1056 #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
1057
1058 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1059
1060 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1061 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1062 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1063 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1064
1065 #define DMAE_CMD_PORT_0 0
1066 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1067
1068 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1069 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1070 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1071
1072 #define DMAE_LEN32_RD_MAX 0x80
1073 #define DMAE_LEN32_WR_MAX 0x400
1074
1075 #define DMAE_COMP_VAL 0xe0d0d0ae
1076
1077 #define MAX_DMAE_C_PER_PORT 8
1078 #define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1079 BP_E1HVN(bp))
1080 #define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1081 E1HVN_MAX)
1082
1083
1084 /* PCIE link and speed */
1085 #define PCICFG_LINK_WIDTH 0x1f00000
1086 #define PCICFG_LINK_WIDTH_SHIFT 20
1087 #define PCICFG_LINK_SPEED 0xf0000
1088 #define PCICFG_LINK_SPEED_SHIFT 16
1089
1090
1091 #define BNX2X_NUM_TESTS 7
1092
1093 #define BNX2X_PHY_LOOPBACK 0
1094 #define BNX2X_MAC_LOOPBACK 1
1095 #define BNX2X_PHY_LOOPBACK_FAILED 1
1096 #define BNX2X_MAC_LOOPBACK_FAILED 2
1097 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1098 BNX2X_PHY_LOOPBACK_FAILED)
1099
1100
1101 #define STROM_ASSERT_ARRAY_SIZE 50
1102
1103
1104 /* must be used on a CID before placing it on a HW ring */
1105 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
1106
1107 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1108 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1109
1110
1111 #define BNX2X_BTR 3
1112 #define MAX_SPQ_PENDING 8
1113
1114
1115 /* CMNG constants
1116 derived from lab experiments, and not from system spec calculations !!! */
1117 #define DEF_MIN_RATE 100
1118 /* resolution of the rate shaping timer - 100 usec */
1119 #define RS_PERIODIC_TIMEOUT_USEC 100
1120 /* resolution of fairness algorithm in usecs -
1121 coefficient for calculating the actual t fair */
1122 #define T_FAIR_COEF 10000000
1123 /* number of bytes in single QM arbitration cycle -
1124 coefficient for calculating the fairness timer */
1125 #define QM_ARB_BYTES 40000
1126 #define FAIR_MEM 2
1127
1128
1129 #define ATTN_NIG_FOR_FUNC (1L << 8)
1130 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1131 #define GPIO_2_FUNC (1L << 10)
1132 #define GPIO_3_FUNC (1L << 11)
1133 #define GPIO_4_FUNC (1L << 12)
1134 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1135 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1136 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1137 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1138 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1139 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1140
1141 #define ATTN_HARD_WIRED_MASK 0xff00
1142 #define ATTENTION_ID 4
1143
1144
1145 /* stuff added to make the code fit 80Col */
1146
1147 #define BNX2X_PMF_LINK_ASSERT \
1148 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1149
1150 #define BNX2X_MC_ASSERT_BITS \
1151 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1152 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1153 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1154 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1155
1156 #define BNX2X_MCP_ASSERT \
1157 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1158
1159 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1160 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1161 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1162 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1163 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1164 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1165 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1166
1167 #define HW_INTERRUT_ASSERT_SET_0 \
1168 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1169 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1170 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1171 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1172 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1173 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1174 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1175 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1176 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1177 #define HW_INTERRUT_ASSERT_SET_1 \
1178 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1179 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1180 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1181 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1182 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1183 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1184 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1185 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1186 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1187 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1188 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1189 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1190 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1191 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1192 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1193 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1194 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1195 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1196 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1197 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1198 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1199 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1200 #define HW_INTERRUT_ASSERT_SET_2 \
1201 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1202 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1203 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1204 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1205 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1206 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1207 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1208 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1209 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1210 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1211 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1212 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1213
1214
1215 #define MULTI_FLAGS(bp) \
1216 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1217 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1218 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1219 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1220 (bp->multi_mode << \
1221 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1222
1223 #define MULTI_MASK 0x7f
1224
1225
1226 #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1227 #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1228 #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1229 #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1230
1231 #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1232
1233 #define BNX2X_SP_DSB_INDEX \
1234 (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1235
1236
1237 #define CAM_IS_INVALID(x) \
1238 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1239
1240 #define CAM_INVALIDATE(x) \
1241 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1242
1243
1244 /* Number of u32 elements in MC hash array */
1245 #define MC_HASH_SIZE 8
1246 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1247 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1248
1249
1250 #ifndef PXP2_REG_PXP2_INT_STS
1251 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1252 #endif
1253
1254 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1255
1256 #endif /* bnx2x.h */
kernel source for telekom puls (alcatel/mediatek)