1 /* bnx2x.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2009 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
17 /* compilation time flags */
19 /* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21 /* #define BNX2X_STOP_ON_ERROR */
23 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
28 #define BNX2X_MULTI_QUEUE
30 #define BNX2X_NEW_NAPI
33 #include "bnx2x_reg.h"
34 #include "bnx2x_fw_defs.h"
35 #include "bnx2x_hsi.h"
36 #include "bnx2x_link.h"
38 /* error/debug prints */
40 #define DRV_MODULE_NAME "bnx2x"
41 #define PFX DRV_MODULE_NAME ": "
43 /* for messages that are currently off */
44 #define BNX2X_MSG_OFF 0
45 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
46 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
47 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
48 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
49 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
50 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
52 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
54 /* regular debug print */
55 #define DP(__mask, __fmt, __args...) do { \
56 if (bp->msglevel & (__mask)) \
57 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
58 bp->dev ? (bp->dev->name) : "?", ##__args); \
61 /* errors debug print */
62 #define BNX2X_DBG_ERR(__fmt, __args...) do { \
63 if (bp->msglevel & NETIF_MSG_PROBE) \
64 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
65 bp->dev ? (bp->dev->name) : "?", ##__args); \
68 /* for errors (never masked) */
69 #define BNX2X_ERR(__fmt, __args...) do { \
70 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
71 bp->dev ? (bp->dev->name) : "?", ##__args); \
74 /* before we have a dev->name use dev_info() */
75 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
76 if (bp->msglevel & NETIF_MSG_PROBE) \
77 dev_info(&bp->pdev->dev, __fmt, ##__args); \
81 #ifdef BNX2X_STOP_ON_ERROR
82 #define bnx2x_panic() do { \
84 BNX2X_ERR("driver assert\n"); \
85 bnx2x_int_disable(bp); \
86 bnx2x_panic_dump(bp); \
89 #define bnx2x_panic() do { \
90 BNX2X_ERR("driver assert\n"); \
91 bnx2x_panic_dump(bp); \
96 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
97 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
98 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
101 #define REG_ADDR(bp, offset) (bp->regview + offset)
103 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
104 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
106 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
107 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
108 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
110 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
111 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
113 #define REG_RD_DMAE(bp, offset, valp, len32) \
115 bnx2x_read_dmae(bp, offset, len32);\
116 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
119 #define REG_WR_DMAE(bp, offset, valp, len32) \
121 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
122 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
126 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
127 offsetof(struct shmem_region, field))
128 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
129 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
131 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
132 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
139 DECLARE_PCI_UNMAP_ADDR(mapping
)
149 DECLARE_PCI_UNMAP_ADDR(mapping
)
154 #define BCM_PAGE_SHIFT 12
155 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
156 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
157 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
159 #define PAGES_PER_SGE_SHIFT 0
160 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
161 #define SGE_PAGE_SIZE PAGE_SIZE
162 #define SGE_PAGE_SHIFT PAGE_SHIFT
163 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
165 /* SGE ring related macros */
166 #define NUM_RX_SGE_PAGES 2
167 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
168 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
169 /* RX_SGE_CNT is promised to be a power of 2 */
170 #define RX_SGE_MASK (RX_SGE_CNT - 1)
171 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
172 #define MAX_RX_SGE (NUM_RX_SGE - 1)
173 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
174 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
175 #define RX_SGE(x) ((x) & MAX_RX_SGE)
177 /* SGE producer mask related macros */
178 /* Number of bits in one sge_mask array element */
179 #define RX_SGE_MASK_ELEM_SZ 64
180 #define RX_SGE_MASK_ELEM_SHIFT 6
181 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
183 /* Creates a bitmask of all ones in less significant bits.
184 idx - index of the most significant bit in the created mask */
185 #define RX_SGE_ONES_MASK(idx) \
186 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
187 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
189 /* Number of u64 elements in SGE mask array */
190 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
192 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
193 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
196 struct bnx2x_eth_q_stats
{
197 u32 total_bytes_received_hi
;
198 u32 total_bytes_received_lo
;
199 u32 total_bytes_transmitted_hi
;
200 u32 total_bytes_transmitted_lo
;
201 u32 total_unicast_packets_received_hi
;
202 u32 total_unicast_packets_received_lo
;
203 u32 total_multicast_packets_received_hi
;
204 u32 total_multicast_packets_received_lo
;
205 u32 total_broadcast_packets_received_hi
;
206 u32 total_broadcast_packets_received_lo
;
207 u32 total_unicast_packets_transmitted_hi
;
208 u32 total_unicast_packets_transmitted_lo
;
209 u32 total_multicast_packets_transmitted_hi
;
210 u32 total_multicast_packets_transmitted_lo
;
211 u32 total_broadcast_packets_transmitted_hi
;
212 u32 total_broadcast_packets_transmitted_lo
;
213 u32 valid_bytes_received_hi
;
214 u32 valid_bytes_received_lo
;
216 u32 error_bytes_received_hi
;
217 u32 error_bytes_received_lo
;
218 u32 etherstatsoverrsizepkts_hi
;
219 u32 etherstatsoverrsizepkts_lo
;
220 u32 no_buff_discard_hi
;
221 u32 no_buff_discard_lo
;
224 u32 rx_err_discard_pkt
;
225 u32 rx_skb_alloc_failed
;
229 #define BNX2X_NUM_Q_STATS 11
230 #define Q_STATS_OFFSET32(stat_name) \
231 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
233 struct bnx2x_fastpath
{
235 struct napi_struct napi
;
237 struct host_status_block
*status_blk
;
238 dma_addr_t status_blk_mapping
;
240 struct eth_tx_db_data
*hw_tx_prods
;
241 dma_addr_t tx_prods_mapping
;
243 struct sw_tx_bd
*tx_buf_ring
;
245 struct eth_tx_bd
*tx_desc_ring
;
246 dma_addr_t tx_desc_mapping
;
248 struct sw_rx_bd
*rx_buf_ring
; /* BDs mappings ring */
249 struct sw_rx_page
*rx_page_ring
; /* SGE pages mappings ring */
251 struct eth_rx_bd
*rx_desc_ring
;
252 dma_addr_t rx_desc_mapping
;
254 union eth_rx_cqe
*rx_comp_ring
;
255 dma_addr_t rx_comp_mapping
;
258 struct eth_rx_sge
*rx_sge_ring
;
259 dma_addr_t rx_sge_mapping
;
261 u64 sge_mask
[RX_SGE_MASK_LEN
];
264 #define BNX2X_FP_STATE_CLOSED 0
265 #define BNX2X_FP_STATE_IRQ 0x80000
266 #define BNX2X_FP_STATE_OPENING 0x90000
267 #define BNX2X_FP_STATE_OPEN 0xa0000
268 #define BNX2X_FP_STATE_HALTING 0xb0000
269 #define BNX2X_FP_STATE_HALTED 0xc0000
271 u8 index
; /* number in fp array */
272 u8 cl_id
; /* eth client id */
273 u8 sb_id
; /* status block number in HW */
289 /* The last maximal completed SGE */
292 __le16
*rx_bd_cons_sb
;
294 unsigned long tx_pkt
,
298 struct sw_rx_bd tpa_pool
[ETH_MAX_AGGREGATION_QUEUES_E1H
];
299 u8 tpa_state
[ETH_MAX_AGGREGATION_QUEUES_E1H
];
300 #define BNX2X_TPA_START 1
301 #define BNX2X_TPA_STOP 2
303 #ifdef BNX2X_STOP_ON_ERROR
307 struct tstorm_per_client_stats old_tclient
;
308 struct ustorm_per_client_stats old_uclient
;
309 struct xstorm_per_client_stats old_xclient
;
310 struct bnx2x_eth_q_stats eth_q_stats
;
313 struct bnx2x
*bp
; /* parent */
316 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
318 #define BNX2X_HAS_WORK(fp) (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))
322 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
323 #define RX_COPY_THRESH 92
325 #define NUM_TX_RINGS 16
326 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
327 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
328 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
329 #define MAX_TX_BD (NUM_TX_BD - 1)
330 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
331 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
332 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
333 #define TX_BD(x) ((x) & MAX_TX_BD)
334 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
336 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
337 #define NUM_RX_RINGS 8
338 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
339 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
340 #define RX_DESC_MASK (RX_DESC_CNT - 1)
341 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
342 #define MAX_RX_BD (NUM_RX_BD - 1)
343 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
344 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
345 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
346 #define RX_BD(x) ((x) & MAX_RX_BD)
348 /* As long as CQE is 4 times bigger than BD entry we have to allocate
349 4 times more pages for CQ ring in order to keep it balanced with
351 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
352 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
353 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
354 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
355 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
356 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
357 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
358 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
359 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
362 /* This is needed for determining of last_max */
363 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
365 #define __SGE_MASK_SET_BIT(el, bit) \
367 el = ((el) | ((u64)0x1 << (bit))); \
370 #define __SGE_MASK_CLEAR_BIT(el, bit) \
372 el = ((el) & (~((u64)0x1 << (bit)))); \
375 #define SGE_MASK_SET_BIT(fp, idx) \
376 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
377 ((idx) & RX_SGE_MASK_ELEM_MASK))
379 #define SGE_MASK_CLEAR_BIT(fp, idx) \
380 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
381 ((idx) & RX_SGE_MASK_ELEM_MASK))
384 /* used on a CID received from the HW */
385 #define SW_CID(x) (le32_to_cpu(x) & \
386 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
387 #define CQE_CMD(x) (le32_to_cpu(x) >> \
388 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
390 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
391 le32_to_cpu((bd)->addr_lo))
392 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
395 #define DPM_TRIGER_TYPE 0x40
396 #define DOORBELL(bp, cid, val) \
398 writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \
403 /* TX CSUM helpers */
404 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
406 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
409 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
412 #define XMIT_CSUM_V4 0x1
413 #define XMIT_CSUM_V6 0x2
414 #define XMIT_CSUM_TCP 0x4
415 #define XMIT_GSO_V4 0x8
416 #define XMIT_GSO_V6 0x10
418 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
419 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
422 /* stuff added to make the code fit 80Col */
424 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
426 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
427 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
428 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
429 (TPA_TYPE_START | TPA_TYPE_END))
431 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
433 #define BNX2X_IP_CSUM_ERR(cqe) \
434 (!((cqe)->fast_path_cqe.status_flags & \
435 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
436 ((cqe)->fast_path_cqe.type_error_flags & \
437 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
439 #define BNX2X_L4_CSUM_ERR(cqe) \
440 (!((cqe)->fast_path_cqe.status_flags & \
441 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
442 ((cqe)->fast_path_cqe.type_error_flags & \
443 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
445 #define BNX2X_RX_CSUM_OK(cqe) \
446 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
448 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
449 (((le16_to_cpu(flags) & \
450 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
451 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
452 == PRS_FLAG_OVERETH_IPV4)
453 #define BNX2X_RX_SUM_FIX(cqe) \
454 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
457 #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
458 #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
460 #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
461 #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
462 #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
464 #define BNX2X_RX_SB_INDEX \
465 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
467 #define BNX2X_RX_SB_BD_INDEX \
468 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
470 #define BNX2X_RX_SB_INDEX_NUM \
471 (((U_SB_ETH_RX_CQ_INDEX << \
472 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
473 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
474 ((U_SB_ETH_RX_BD_INDEX << \
475 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
476 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
478 #define BNX2X_TX_SB_INDEX \
479 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
482 /* end of fast path */
486 struct bnx2x_common
{
489 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
490 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
492 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
493 #define CHIP_NUM_57710 0x164e
494 #define CHIP_NUM_57711 0x164f
495 #define CHIP_NUM_57711E 0x1650
496 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
497 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
498 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
499 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
501 #define IS_E1H_OFFSET CHIP_IS_E1H(bp)
503 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
504 #define CHIP_REV_Ax 0x00000000
505 /* assume maximum 5 revisions */
506 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
507 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
508 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
509 !(CHIP_REV(bp) & 0x00001000))
510 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
511 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
512 (CHIP_REV(bp) & 0x00001000))
514 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
515 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
517 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
518 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
521 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
522 #define NVRAM_TIMEOUT_COUNT 30000
523 #define NVRAM_PAGE_SIZE 256
541 u32 flow_ctrl_discard
;
542 u32 flow_ctrl_octets
;
543 u32 flow_ctrl_packet
;
552 u32 egress_mac_pkt0_lo
;
553 u32 egress_mac_pkt0_hi
;
554 u32 egress_mac_pkt1_lo
;
555 u32 egress_mac_pkt1_hi
;
564 /* link settings - missing defines */
565 #define SUPPORTED_2500baseX_Full (1 << 15)
568 /* link settings - missing defines */
569 #define ADVERTISED_2500baseX_Full (1 << 15)
573 /* used to synchronize phy accesses */
574 struct mutex phy_mutex
;
579 struct nig_stats old_nig_stats
;
585 enum bnx2x_stats_event
{
593 enum bnx2x_stats_state
{
594 STATS_STATE_DISABLED
= 0,
599 struct bnx2x_eth_stats
{
600 u32 total_bytes_received_hi
;
601 u32 total_bytes_received_lo
;
602 u32 total_bytes_transmitted_hi
;
603 u32 total_bytes_transmitted_lo
;
604 u32 total_unicast_packets_received_hi
;
605 u32 total_unicast_packets_received_lo
;
606 u32 total_multicast_packets_received_hi
;
607 u32 total_multicast_packets_received_lo
;
608 u32 total_broadcast_packets_received_hi
;
609 u32 total_broadcast_packets_received_lo
;
610 u32 total_unicast_packets_transmitted_hi
;
611 u32 total_unicast_packets_transmitted_lo
;
612 u32 total_multicast_packets_transmitted_hi
;
613 u32 total_multicast_packets_transmitted_lo
;
614 u32 total_broadcast_packets_transmitted_hi
;
615 u32 total_broadcast_packets_transmitted_lo
;
616 u32 valid_bytes_received_hi
;
617 u32 valid_bytes_received_lo
;
619 u32 error_bytes_received_hi
;
620 u32 error_bytes_received_lo
;
621 u32 etherstatsoverrsizepkts_hi
;
622 u32 etherstatsoverrsizepkts_lo
;
623 u32 no_buff_discard_hi
;
624 u32 no_buff_discard_lo
;
626 u32 rx_stat_ifhcinbadoctets_hi
;
627 u32 rx_stat_ifhcinbadoctets_lo
;
628 u32 tx_stat_ifhcoutbadoctets_hi
;
629 u32 tx_stat_ifhcoutbadoctets_lo
;
630 u32 rx_stat_dot3statsfcserrors_hi
;
631 u32 rx_stat_dot3statsfcserrors_lo
;
632 u32 rx_stat_dot3statsalignmenterrors_hi
;
633 u32 rx_stat_dot3statsalignmenterrors_lo
;
634 u32 rx_stat_dot3statscarriersenseerrors_hi
;
635 u32 rx_stat_dot3statscarriersenseerrors_lo
;
636 u32 rx_stat_falsecarriererrors_hi
;
637 u32 rx_stat_falsecarriererrors_lo
;
638 u32 rx_stat_etherstatsundersizepkts_hi
;
639 u32 rx_stat_etherstatsundersizepkts_lo
;
640 u32 rx_stat_dot3statsframestoolong_hi
;
641 u32 rx_stat_dot3statsframestoolong_lo
;
642 u32 rx_stat_etherstatsfragments_hi
;
643 u32 rx_stat_etherstatsfragments_lo
;
644 u32 rx_stat_etherstatsjabbers_hi
;
645 u32 rx_stat_etherstatsjabbers_lo
;
646 u32 rx_stat_maccontrolframesreceived_hi
;
647 u32 rx_stat_maccontrolframesreceived_lo
;
648 u32 rx_stat_bmac_xpf_hi
;
649 u32 rx_stat_bmac_xpf_lo
;
650 u32 rx_stat_bmac_xcf_hi
;
651 u32 rx_stat_bmac_xcf_lo
;
652 u32 rx_stat_xoffstateentered_hi
;
653 u32 rx_stat_xoffstateentered_lo
;
654 u32 rx_stat_xonpauseframesreceived_hi
;
655 u32 rx_stat_xonpauseframesreceived_lo
;
656 u32 rx_stat_xoffpauseframesreceived_hi
;
657 u32 rx_stat_xoffpauseframesreceived_lo
;
658 u32 tx_stat_outxonsent_hi
;
659 u32 tx_stat_outxonsent_lo
;
660 u32 tx_stat_outxoffsent_hi
;
661 u32 tx_stat_outxoffsent_lo
;
662 u32 tx_stat_flowcontroldone_hi
;
663 u32 tx_stat_flowcontroldone_lo
;
664 u32 tx_stat_etherstatscollisions_hi
;
665 u32 tx_stat_etherstatscollisions_lo
;
666 u32 tx_stat_dot3statssinglecollisionframes_hi
;
667 u32 tx_stat_dot3statssinglecollisionframes_lo
;
668 u32 tx_stat_dot3statsmultiplecollisionframes_hi
;
669 u32 tx_stat_dot3statsmultiplecollisionframes_lo
;
670 u32 tx_stat_dot3statsdeferredtransmissions_hi
;
671 u32 tx_stat_dot3statsdeferredtransmissions_lo
;
672 u32 tx_stat_dot3statsexcessivecollisions_hi
;
673 u32 tx_stat_dot3statsexcessivecollisions_lo
;
674 u32 tx_stat_dot3statslatecollisions_hi
;
675 u32 tx_stat_dot3statslatecollisions_lo
;
676 u32 tx_stat_etherstatspkts64octets_hi
;
677 u32 tx_stat_etherstatspkts64octets_lo
;
678 u32 tx_stat_etherstatspkts65octetsto127octets_hi
;
679 u32 tx_stat_etherstatspkts65octetsto127octets_lo
;
680 u32 tx_stat_etherstatspkts128octetsto255octets_hi
;
681 u32 tx_stat_etherstatspkts128octetsto255octets_lo
;
682 u32 tx_stat_etherstatspkts256octetsto511octets_hi
;
683 u32 tx_stat_etherstatspkts256octetsto511octets_lo
;
684 u32 tx_stat_etherstatspkts512octetsto1023octets_hi
;
685 u32 tx_stat_etherstatspkts512octetsto1023octets_lo
;
686 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi
;
687 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo
;
688 u32 tx_stat_etherstatspktsover1522octets_hi
;
689 u32 tx_stat_etherstatspktsover1522octets_lo
;
690 u32 tx_stat_bmac_2047_hi
;
691 u32 tx_stat_bmac_2047_lo
;
692 u32 tx_stat_bmac_4095_hi
;
693 u32 tx_stat_bmac_4095_lo
;
694 u32 tx_stat_bmac_9216_hi
;
695 u32 tx_stat_bmac_9216_lo
;
696 u32 tx_stat_bmac_16383_hi
;
697 u32 tx_stat_bmac_16383_lo
;
698 u32 tx_stat_dot3statsinternalmactransmiterrors_hi
;
699 u32 tx_stat_dot3statsinternalmactransmiterrors_lo
;
700 u32 tx_stat_bmac_ufl_hi
;
701 u32 tx_stat_bmac_ufl_lo
;
703 u32 pause_frames_received_hi
;
704 u32 pause_frames_received_lo
;
705 u32 pause_frames_sent_hi
;
706 u32 pause_frames_sent_lo
;
708 u32 etherstatspkts1024octetsto1522octets_hi
;
709 u32 etherstatspkts1024octetsto1522octets_lo
;
710 u32 etherstatspktsover1522octets_hi
;
711 u32 etherstatspktsover1522octets_lo
;
718 u32 mac_filter_discard
;
719 u32 xxoverflow_discard
;
720 u32 brb_truncate_discard
;
724 u32 rx_err_discard_pkt
;
725 u32 rx_skb_alloc_failed
;
731 #define BNX2X_NUM_STATS 41
732 #define STATS_OFFSET32(stat_name) \
733 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
736 #define MAX_CONTEXT 16
739 struct eth_context eth
;
745 /* DMA memory not used in fastpath */
746 struct bnx2x_slowpath
{
747 union cdu_context context
[MAX_CONTEXT
];
748 struct eth_stats_query fw_stats
;
749 struct mac_configuration_cmd mac_config
;
750 struct mac_configuration_cmd mcast_config
;
752 /* used by dmae command executer */
753 struct dmae_command dmae
[MAX_DMAE_C
];
756 union mac_stats mac_stats
;
757 struct nig_stats nig_stats
;
758 struct host_port_stats port_stats
;
759 struct host_func_stats func_stats
;
765 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
766 #define bnx2x_sp_mapping(bp, var) \
767 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
770 /* attn group wiring */
771 #define MAX_DYNAMIC_ATTN_GRPS 8
778 /* Fields used in the tx and intr/napi performance paths
779 * are grouped together in the beginning of the structure
781 struct bnx2x_fastpath fp
[MAX_CONTEXT
];
782 void __iomem
*regview
;
783 void __iomem
*doorbells
;
784 #define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE)
786 struct net_device
*dev
;
787 struct pci_dev
*pdev
;
790 struct msix_entry msix_table
[MAX_CONTEXT
+1];
791 #define INT_MODE_INTx 1
792 #define INT_MODE_MSI 2
793 #define INT_MODE_MSIX 3
798 struct vlan_group
*vlgrp
;
803 #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
804 #define ETH_MIN_PACKET_SIZE 60
805 #define ETH_MAX_PACKET_SIZE 1500
806 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
808 /* Max supported alignment is 256 (8 shift) */
809 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
811 #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
813 struct host_def_status_block
*def_status_blk
;
821 struct attn_route attn_group
[MAX_DYNAMIC_ATTN_GRPS
];
825 dma_addr_t spq_mapping
;
827 struct eth_spe
*spq_prod_bd
;
828 struct eth_spe
*spq_last_bd
;
830 u16 spq_left
; /* serialize spq */
831 /* used to synchronize spq accesses */
834 /* Flags for marking that there is a STAT_QUERY or
835 SET_MAC ramrod pending */
839 /* End of fields used in the performance code paths */
846 #define PCI_32BIT_FLAG 2
847 #define ONE_PORT_FLAG 4
848 #define NO_WOL_FLAG 8
849 #define USING_DAC_FLAG 0x10
850 #define USING_MSIX_FLAG 0x20
851 #define USING_MSI_FLAG 0x40
852 #define TPA_ENABLE_FLAG 0x80
853 #define NO_MCP_FLAG 0x100
854 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
855 #define HW_VLAN_TX_FLAG 0x400
856 #define HW_VLAN_RX_FLAG 0x800
859 #define BP_PORT(bp) (bp->func % PORT_MAX)
860 #define BP_FUNC(bp) (bp->func)
861 #define BP_E1HVN(bp) (bp->func >> 1)
862 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
868 struct delayed_work sp_task
;
869 struct work_struct reset_task
;
871 struct timer_list timer
;
872 int current_interval
;
875 u16 fw_drv_pulse_wr_seq
;
878 struct link_params link_params
;
879 struct link_vars link_vars
;
881 struct bnx2x_common common
;
882 struct bnx2x_port port
;
884 struct cmng_struct_per_port cmng
;
890 #define IS_E1HMF(bp) (bp->e1hmf != 0)
896 u16 tx_quick_cons_trip_int
;
897 u16 tx_quick_cons_trip
;
901 u16 rx_quick_cons_trip_int
;
902 u16 rx_quick_cons_trip
;
905 /* Maximal coalescing timeout in us */
906 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
911 #define BNX2X_STATE_CLOSED 0
912 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
913 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
914 #define BNX2X_STATE_OPEN 0x3000
915 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
916 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
917 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
918 #define BNX2X_STATE_DISABLED 0xd000
919 #define BNX2X_STATE_DIAG 0xe000
920 #define BNX2X_STATE_ERROR 0xf000
927 #define BNX2X_RX_MODE_NONE 0
928 #define BNX2X_RX_MODE_NORMAL 1
929 #define BNX2X_RX_MODE_ALLMULTI 2
930 #define BNX2X_RX_MODE_PROMISC 3
931 #define BNX2X_MAX_MULTICAST 64
932 #define BNX2X_MAX_EMUL_MULTI 16
934 dma_addr_t def_status_blk_mapping
;
936 struct bnx2x_slowpath
*slowpath
;
937 dma_addr_t slowpath_mapping
;
941 dma_addr_t t1_mapping
;
943 dma_addr_t t2_mapping
;
945 dma_addr_t timers_mapping
;
947 dma_addr_t qm_mapping
;
951 /* used to synchronize dmae accesses */
952 struct mutex dmae_mutex
;
953 struct dmae_command init_dmae
;
955 /* used to synchronize stats collecting */
957 /* used by dmae command loader */
958 struct dmae_command stats_dmae
;
962 struct bnx2x_eth_stats eth_stats
;
964 struct z_stream_s
*strm
;
966 dma_addr_t gunzip_mapping
;
968 #define FW_BUF_SIZE 0x8000
970 struct raw_op
*init_ops
;
971 /* Init blocks offsets inside init_ops */
972 u16
*init_ops_offsets
;
973 /* Data blob - has 32 bit granularity */
975 /* Zipped PRAM blobs - raw data */
976 const u8
*tsem_int_table_data
;
977 const u8
*tsem_pram_data
;
978 const u8
*usem_int_table_data
;
979 const u8
*usem_pram_data
;
980 const u8
*xsem_int_table_data
;
981 const u8
*xsem_pram_data
;
982 const u8
*csem_int_table_data
;
983 const u8
*csem_pram_data
;
984 const struct firmware
*firmware
;
988 #define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT / E1HVN_MAX) : \
990 #define BNX2X_NUM_QUEUES(bp) max(bp->num_rx_queues, bp->num_tx_queues)
991 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
993 #define for_each_rx_queue(bp, var) \
994 for (var = 0; var < bp->num_rx_queues; var++)
995 #define for_each_tx_queue(bp, var) \
996 for (var = 0; var < bp->num_tx_queues; var++)
997 #define for_each_queue(bp, var) \
998 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
999 #define for_each_nondefault_queue(bp, var) \
1000 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
1003 void bnx2x_read_dmae(struct bnx2x
*bp
, u32 src_addr
, u32 len32
);
1004 void bnx2x_write_dmae(struct bnx2x
*bp
, dma_addr_t dma_addr
, u32 dst_addr
,
1006 int bnx2x_get_gpio(struct bnx2x
*bp
, int gpio_num
, u8 port
);
1007 int bnx2x_set_gpio(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
);
1008 int bnx2x_set_gpio_int(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
);
1009 u32
bnx2x_fw_command(struct bnx2x
*bp
, u32 command
);
1011 static inline u32
reg_poll(struct bnx2x
*bp
, u32 reg
, u32 expected
, int ms
,
1017 val
= REG_RD(bp
, reg
);
1018 if (val
== expected
)
1029 /* load/unload mode */
1030 #define LOAD_NORMAL 0
1033 #define UNLOAD_NORMAL 0
1034 #define UNLOAD_CLOSE 1
1037 /* DMAE command defines */
1038 #define DMAE_CMD_SRC_PCI 0
1039 #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
1041 #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
1042 #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
1044 #define DMAE_CMD_C_DST_PCI 0
1045 #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
1047 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1049 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1050 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1051 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1052 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1054 #define DMAE_CMD_PORT_0 0
1055 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1057 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1058 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1059 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1061 #define DMAE_LEN32_RD_MAX 0x80
1062 #define DMAE_LEN32_WR_MAX 0x400
1064 #define DMAE_COMP_VAL 0xe0d0d0ae
1066 #define MAX_DMAE_C_PER_PORT 8
1067 #define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1069 #define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1073 /* PCIE link and speed */
1074 #define PCICFG_LINK_WIDTH 0x1f00000
1075 #define PCICFG_LINK_WIDTH_SHIFT 20
1076 #define PCICFG_LINK_SPEED 0xf0000
1077 #define PCICFG_LINK_SPEED_SHIFT 16
1080 #define BNX2X_NUM_TESTS 7
1082 #define BNX2X_PHY_LOOPBACK 0
1083 #define BNX2X_MAC_LOOPBACK 1
1084 #define BNX2X_PHY_LOOPBACK_FAILED 1
1085 #define BNX2X_MAC_LOOPBACK_FAILED 2
1086 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1087 BNX2X_PHY_LOOPBACK_FAILED)
1090 #define STROM_ASSERT_ARRAY_SIZE 50
1093 /* must be used on a CID before placing it on a HW ring */
1094 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
1096 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1097 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1101 #define MAX_SPQ_PENDING 8
1105 derived from lab experiments, and not from system spec calculations !!! */
1106 #define DEF_MIN_RATE 100
1107 /* resolution of the rate shaping timer - 100 usec */
1108 #define RS_PERIODIC_TIMEOUT_USEC 100
1109 /* resolution of fairness algorithm in usecs -
1110 coefficient for calculating the actual t fair */
1111 #define T_FAIR_COEF 10000000
1112 /* number of bytes in single QM arbitration cycle -
1113 coefficient for calculating the fairness timer */
1114 #define QM_ARB_BYTES 40000
1118 #define ATTN_NIG_FOR_FUNC (1L << 8)
1119 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1120 #define GPIO_2_FUNC (1L << 10)
1121 #define GPIO_3_FUNC (1L << 11)
1122 #define GPIO_4_FUNC (1L << 12)
1123 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1124 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1125 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1126 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1127 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1128 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1130 #define ATTN_HARD_WIRED_MASK 0xff00
1131 #define ATTENTION_ID 4
1134 /* stuff added to make the code fit 80Col */
1136 #define BNX2X_PMF_LINK_ASSERT \
1137 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1139 #define BNX2X_MC_ASSERT_BITS \
1140 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1141 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1142 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1143 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1145 #define BNX2X_MCP_ASSERT \
1146 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1148 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1149 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1150 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1151 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1152 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1153 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1154 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1156 #define HW_INTERRUT_ASSERT_SET_0 \
1157 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1158 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1159 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1160 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1161 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1162 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1163 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1164 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1165 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1166 #define HW_INTERRUT_ASSERT_SET_1 \
1167 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1168 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1169 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1170 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1171 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1172 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1173 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1174 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1175 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1176 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1177 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1178 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1179 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1180 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1181 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1182 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1183 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1184 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1185 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1186 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1187 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1188 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1189 #define HW_INTERRUT_ASSERT_SET_2 \
1190 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1191 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1192 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1193 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1194 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1195 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1196 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1197 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1198 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1199 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1200 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1201 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1204 #define MULTI_FLAGS(bp) \
1205 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1206 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1207 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1208 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1209 (bp->multi_mode << \
1210 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1212 #define MULTI_MASK 0x7f
1215 #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1216 #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1217 #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1218 #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1220 #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1222 #define BNX2X_SP_DSB_INDEX \
1223 (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1226 #define CAM_IS_INVALID(x) \
1227 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1229 #define CAM_INVALIDATE(x) \
1230 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1233 /* Number of u32 elements in MC hash array */
1234 #define MC_HASH_SIZE 8
1235 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1236 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1239 #ifndef PXP2_REG_PXP2_INT_STS
1240 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1243 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1245 #endif /* bnx2x.h */