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bnx2x: Supporting Device Control Channel
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2x.h
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2009 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16
17 /* compilation time flags */
18
19 /* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21 /* #define BNX2X_STOP_ON_ERROR */
22
23 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
24 #define BCM_VLAN 1
25 #endif
26
27
28 #define BNX2X_MULTI_QUEUE
29
30 #define BNX2X_NEW_NAPI
31
32
33 #include "bnx2x_reg.h"
34 #include "bnx2x_fw_defs.h"
35 #include "bnx2x_hsi.h"
36 #include "bnx2x_link.h"
37
38 /* error/debug prints */
39
40 #define DRV_MODULE_NAME "bnx2x"
41 #define PFX DRV_MODULE_NAME ": "
42
43 /* for messages that are currently off */
44 #define BNX2X_MSG_OFF 0
45 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
46 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
47 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
48 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
49 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
50 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
51
52 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
53
54 /* regular debug print */
55 #define DP(__mask, __fmt, __args...) do { \
56 if (bp->msglevel & (__mask)) \
57 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
58 bp->dev ? (bp->dev->name) : "?", ##__args); \
59 } while (0)
60
61 /* errors debug print */
62 #define BNX2X_DBG_ERR(__fmt, __args...) do { \
63 if (bp->msglevel & NETIF_MSG_PROBE) \
64 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
65 bp->dev ? (bp->dev->name) : "?", ##__args); \
66 } while (0)
67
68 /* for errors (never masked) */
69 #define BNX2X_ERR(__fmt, __args...) do { \
70 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
71 bp->dev ? (bp->dev->name) : "?", ##__args); \
72 } while (0)
73
74 /* before we have a dev->name use dev_info() */
75 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
76 if (bp->msglevel & NETIF_MSG_PROBE) \
77 dev_info(&bp->pdev->dev, __fmt, ##__args); \
78 } while (0)
79
80
81 #ifdef BNX2X_STOP_ON_ERROR
82 #define bnx2x_panic() do { \
83 bp->panic = 1; \
84 BNX2X_ERR("driver assert\n"); \
85 bnx2x_int_disable(bp); \
86 bnx2x_panic_dump(bp); \
87 } while (0)
88 #else
89 #define bnx2x_panic() do { \
90 BNX2X_ERR("driver assert\n"); \
91 bnx2x_panic_dump(bp); \
92 } while (0)
93 #endif
94
95
96 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
97 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
98 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
99
100
101 #define REG_ADDR(bp, offset) (bp->regview + offset)
102
103 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
104 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
105
106 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
107 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
108 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
109
110 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
111 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
112
113 #define REG_RD_DMAE(bp, offset, valp, len32) \
114 do { \
115 bnx2x_read_dmae(bp, offset, len32);\
116 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
117 } while (0)
118
119 #define REG_WR_DMAE(bp, offset, valp, len32) \
120 do { \
121 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
122 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
123 offset, len32); \
124 } while (0)
125
126 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
127 offsetof(struct shmem_region, field))
128 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
129 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
130
131 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
132 offsetof(struct shmem2_region, field))
133 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
134 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
135
136 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
137 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
138
139
140 /* fast path */
141
142 struct sw_rx_bd {
143 struct sk_buff *skb;
144 DECLARE_PCI_UNMAP_ADDR(mapping)
145 };
146
147 struct sw_tx_bd {
148 struct sk_buff *skb;
149 u16 first_bd;
150 u8 flags;
151 /* Set on the first BD descriptor when there is a split BD */
152 #define BNX2X_TSO_SPLIT_BD (1<<0)
153 };
154
155 struct sw_rx_page {
156 struct page *page;
157 DECLARE_PCI_UNMAP_ADDR(mapping)
158 };
159
160 union db_prod {
161 struct doorbell_set_prod data;
162 u32 raw;
163 };
164
165
166 /* MC hsi */
167 #define BCM_PAGE_SHIFT 12
168 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
169 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
170 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
171
172 #define PAGES_PER_SGE_SHIFT 0
173 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
174 #define SGE_PAGE_SIZE PAGE_SIZE
175 #define SGE_PAGE_SHIFT PAGE_SHIFT
176 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
177
178 /* SGE ring related macros */
179 #define NUM_RX_SGE_PAGES 2
180 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
181 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
182 /* RX_SGE_CNT is promised to be a power of 2 */
183 #define RX_SGE_MASK (RX_SGE_CNT - 1)
184 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
185 #define MAX_RX_SGE (NUM_RX_SGE - 1)
186 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
187 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
188 #define RX_SGE(x) ((x) & MAX_RX_SGE)
189
190 /* SGE producer mask related macros */
191 /* Number of bits in one sge_mask array element */
192 #define RX_SGE_MASK_ELEM_SZ 64
193 #define RX_SGE_MASK_ELEM_SHIFT 6
194 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
195
196 /* Creates a bitmask of all ones in less significant bits.
197 idx - index of the most significant bit in the created mask */
198 #define RX_SGE_ONES_MASK(idx) \
199 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
200 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
201
202 /* Number of u64 elements in SGE mask array */
203 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
204 RX_SGE_MASK_ELEM_SZ)
205 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
206 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
207
208
209 struct bnx2x_eth_q_stats {
210 u32 total_bytes_received_hi;
211 u32 total_bytes_received_lo;
212 u32 total_bytes_transmitted_hi;
213 u32 total_bytes_transmitted_lo;
214 u32 total_unicast_packets_received_hi;
215 u32 total_unicast_packets_received_lo;
216 u32 total_multicast_packets_received_hi;
217 u32 total_multicast_packets_received_lo;
218 u32 total_broadcast_packets_received_hi;
219 u32 total_broadcast_packets_received_lo;
220 u32 total_unicast_packets_transmitted_hi;
221 u32 total_unicast_packets_transmitted_lo;
222 u32 total_multicast_packets_transmitted_hi;
223 u32 total_multicast_packets_transmitted_lo;
224 u32 total_broadcast_packets_transmitted_hi;
225 u32 total_broadcast_packets_transmitted_lo;
226 u32 valid_bytes_received_hi;
227 u32 valid_bytes_received_lo;
228
229 u32 error_bytes_received_hi;
230 u32 error_bytes_received_lo;
231 u32 etherstatsoverrsizepkts_hi;
232 u32 etherstatsoverrsizepkts_lo;
233 u32 no_buff_discard_hi;
234 u32 no_buff_discard_lo;
235
236 u32 driver_xoff;
237 u32 rx_err_discard_pkt;
238 u32 rx_skb_alloc_failed;
239 u32 hw_csum_err;
240 };
241
242 #define BNX2X_NUM_Q_STATS 11
243 #define Q_STATS_OFFSET32(stat_name) \
244 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
245
246 struct bnx2x_fastpath {
247
248 struct napi_struct napi;
249
250 u8 is_rx_queue;
251
252 struct host_status_block *status_blk;
253 dma_addr_t status_blk_mapping;
254
255 struct sw_tx_bd *tx_buf_ring;
256
257 union eth_tx_bd_types *tx_desc_ring;
258 dma_addr_t tx_desc_mapping;
259
260 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
261 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
262
263 struct eth_rx_bd *rx_desc_ring;
264 dma_addr_t rx_desc_mapping;
265
266 union eth_rx_cqe *rx_comp_ring;
267 dma_addr_t rx_comp_mapping;
268
269 /* SGE ring */
270 struct eth_rx_sge *rx_sge_ring;
271 dma_addr_t rx_sge_mapping;
272
273 u64 sge_mask[RX_SGE_MASK_LEN];
274
275 int state;
276 #define BNX2X_FP_STATE_CLOSED 0
277 #define BNX2X_FP_STATE_IRQ 0x80000
278 #define BNX2X_FP_STATE_OPENING 0x90000
279 #define BNX2X_FP_STATE_OPEN 0xa0000
280 #define BNX2X_FP_STATE_HALTING 0xb0000
281 #define BNX2X_FP_STATE_HALTED 0xc0000
282
283 u8 index; /* number in fp array */
284 u8 cl_id; /* eth client id */
285 u8 sb_id; /* status block number in HW */
286
287 union db_prod tx_db;
288
289 u16 tx_pkt_prod;
290 u16 tx_pkt_cons;
291 u16 tx_bd_prod;
292 u16 tx_bd_cons;
293 __le16 *tx_cons_sb;
294
295 __le16 fp_c_idx;
296 __le16 fp_u_idx;
297
298 u16 rx_bd_prod;
299 u16 rx_bd_cons;
300 u16 rx_comp_prod;
301 u16 rx_comp_cons;
302 u16 rx_sge_prod;
303 /* The last maximal completed SGE */
304 u16 last_max_sge;
305 __le16 *rx_cons_sb;
306 __le16 *rx_bd_cons_sb;
307
308 unsigned long tx_pkt,
309 rx_pkt,
310 rx_calls;
311 /* TPA related */
312 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
313 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
314 #define BNX2X_TPA_START 1
315 #define BNX2X_TPA_STOP 2
316 u8 disable_tpa;
317 #ifdef BNX2X_STOP_ON_ERROR
318 u64 tpa_queue_used;
319 #endif
320
321 struct tstorm_per_client_stats old_tclient;
322 struct ustorm_per_client_stats old_uclient;
323 struct xstorm_per_client_stats old_xclient;
324 struct bnx2x_eth_q_stats eth_q_stats;
325
326 /* The size is calculated using the following:
327 sizeof name field from netdev structure +
328 4 ('-Xx-' string) +
329 4 (for the digits and to make it DWORD aligned) */
330 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
331 char name[FP_NAME_SIZE];
332 struct bnx2x *bp; /* parent */
333 };
334
335 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
336
337
338 /* MC hsi */
339 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
340 #define RX_COPY_THRESH 92
341
342 #define NUM_TX_RINGS 16
343 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
344 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
345 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
346 #define MAX_TX_BD (NUM_TX_BD - 1)
347 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
348 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
349 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
350 #define TX_BD(x) ((x) & MAX_TX_BD)
351 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
352
353 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
354 #define NUM_RX_RINGS 8
355 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
356 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
357 #define RX_DESC_MASK (RX_DESC_CNT - 1)
358 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
359 #define MAX_RX_BD (NUM_RX_BD - 1)
360 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
361 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
362 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
363 #define RX_BD(x) ((x) & MAX_RX_BD)
364
365 /* As long as CQE is 4 times bigger than BD entry we have to allocate
366 4 times more pages for CQ ring in order to keep it balanced with
367 BD ring */
368 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
369 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
370 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
371 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
372 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
373 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
374 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
375 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
376 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
377
378
379 /* This is needed for determining of last_max */
380 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
381
382 #define __SGE_MASK_SET_BIT(el, bit) \
383 do { \
384 el = ((el) | ((u64)0x1 << (bit))); \
385 } while (0)
386
387 #define __SGE_MASK_CLEAR_BIT(el, bit) \
388 do { \
389 el = ((el) & (~((u64)0x1 << (bit)))); \
390 } while (0)
391
392 #define SGE_MASK_SET_BIT(fp, idx) \
393 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
394 ((idx) & RX_SGE_MASK_ELEM_MASK))
395
396 #define SGE_MASK_CLEAR_BIT(fp, idx) \
397 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
398 ((idx) & RX_SGE_MASK_ELEM_MASK))
399
400
401 /* used on a CID received from the HW */
402 #define SW_CID(x) (le32_to_cpu(x) & \
403 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
404 #define CQE_CMD(x) (le32_to_cpu(x) >> \
405 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
406
407 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
408 le32_to_cpu((bd)->addr_lo))
409 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
410
411
412 #define DPM_TRIGER_TYPE 0x40
413 #define DOORBELL(bp, cid, val) \
414 do { \
415 writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
416 DPM_TRIGER_TYPE); \
417 } while (0)
418
419
420 /* TX CSUM helpers */
421 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
422 skb->csum_offset)
423 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
424 skb->csum_offset))
425
426 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
427
428 #define XMIT_PLAIN 0
429 #define XMIT_CSUM_V4 0x1
430 #define XMIT_CSUM_V6 0x2
431 #define XMIT_CSUM_TCP 0x4
432 #define XMIT_GSO_V4 0x8
433 #define XMIT_GSO_V6 0x10
434
435 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
436 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
437
438
439 /* stuff added to make the code fit 80Col */
440
441 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
442
443 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
444 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
445 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
446 (TPA_TYPE_START | TPA_TYPE_END))
447
448 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
449
450 #define BNX2X_IP_CSUM_ERR(cqe) \
451 (!((cqe)->fast_path_cqe.status_flags & \
452 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
453 ((cqe)->fast_path_cqe.type_error_flags & \
454 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
455
456 #define BNX2X_L4_CSUM_ERR(cqe) \
457 (!((cqe)->fast_path_cqe.status_flags & \
458 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
459 ((cqe)->fast_path_cqe.type_error_flags & \
460 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
461
462 #define BNX2X_RX_CSUM_OK(cqe) \
463 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
464
465 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
466 (((le16_to_cpu(flags) & \
467 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
468 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
469 == PRS_FLAG_OVERETH_IPV4)
470 #define BNX2X_RX_SUM_FIX(cqe) \
471 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
472
473
474 #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
475 #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
476
477 #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
478 #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
479 #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
480
481 #define BNX2X_RX_SB_INDEX \
482 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
483
484 #define BNX2X_RX_SB_BD_INDEX \
485 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
486
487 #define BNX2X_RX_SB_INDEX_NUM \
488 (((U_SB_ETH_RX_CQ_INDEX << \
489 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
490 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
491 ((U_SB_ETH_RX_BD_INDEX << \
492 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
493 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
494
495 #define BNX2X_TX_SB_INDEX \
496 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
497
498
499 /* end of fast path */
500
501 /* common */
502
503 struct bnx2x_common {
504
505 u32 chip_id;
506 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
507 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
508
509 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
510 #define CHIP_NUM_57710 0x164e
511 #define CHIP_NUM_57711 0x164f
512 #define CHIP_NUM_57711E 0x1650
513 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
514 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
515 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
516 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
517 CHIP_IS_57711E(bp))
518 #define IS_E1H_OFFSET CHIP_IS_E1H(bp)
519
520 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
521 #define CHIP_REV_Ax 0x00000000
522 /* assume maximum 5 revisions */
523 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
524 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
525 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
526 !(CHIP_REV(bp) & 0x00001000))
527 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
528 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
529 (CHIP_REV(bp) & 0x00001000))
530
531 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
532 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
533
534 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
535 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
536
537 int flash_size;
538 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
539 #define NVRAM_TIMEOUT_COUNT 30000
540 #define NVRAM_PAGE_SIZE 256
541
542 u32 shmem_base;
543 u32 shmem2_base;
544
545 u32 hw_config;
546
547 u32 bc_ver;
548 };
549
550
551 /* end of common */
552
553 /* port */
554
555 struct nig_stats {
556 u32 brb_discard;
557 u32 brb_packet;
558 u32 brb_truncate;
559 u32 flow_ctrl_discard;
560 u32 flow_ctrl_octets;
561 u32 flow_ctrl_packet;
562 u32 mng_discard;
563 u32 mng_octet_inp;
564 u32 mng_octet_out;
565 u32 mng_packet_inp;
566 u32 mng_packet_out;
567 u32 pbf_octets;
568 u32 pbf_packet;
569 u32 safc_inp;
570 u32 egress_mac_pkt0_lo;
571 u32 egress_mac_pkt0_hi;
572 u32 egress_mac_pkt1_lo;
573 u32 egress_mac_pkt1_hi;
574 };
575
576 struct bnx2x_port {
577 u32 pmf;
578
579 u32 link_config;
580
581 u32 supported;
582 /* link settings - missing defines */
583 #define SUPPORTED_2500baseX_Full (1 << 15)
584
585 u32 advertising;
586 /* link settings - missing defines */
587 #define ADVERTISED_2500baseX_Full (1 << 15)
588
589 u32 phy_addr;
590
591 /* used to synchronize phy accesses */
592 struct mutex phy_mutex;
593 int need_hw_lock;
594
595 u32 port_stx;
596
597 struct nig_stats old_nig_stats;
598 };
599
600 /* end of port */
601
602
603 enum bnx2x_stats_event {
604 STATS_EVENT_PMF = 0,
605 STATS_EVENT_LINK_UP,
606 STATS_EVENT_UPDATE,
607 STATS_EVENT_STOP,
608 STATS_EVENT_MAX
609 };
610
611 enum bnx2x_stats_state {
612 STATS_STATE_DISABLED = 0,
613 STATS_STATE_ENABLED,
614 STATS_STATE_MAX
615 };
616
617 struct bnx2x_eth_stats {
618 u32 total_bytes_received_hi;
619 u32 total_bytes_received_lo;
620 u32 total_bytes_transmitted_hi;
621 u32 total_bytes_transmitted_lo;
622 u32 total_unicast_packets_received_hi;
623 u32 total_unicast_packets_received_lo;
624 u32 total_multicast_packets_received_hi;
625 u32 total_multicast_packets_received_lo;
626 u32 total_broadcast_packets_received_hi;
627 u32 total_broadcast_packets_received_lo;
628 u32 total_unicast_packets_transmitted_hi;
629 u32 total_unicast_packets_transmitted_lo;
630 u32 total_multicast_packets_transmitted_hi;
631 u32 total_multicast_packets_transmitted_lo;
632 u32 total_broadcast_packets_transmitted_hi;
633 u32 total_broadcast_packets_transmitted_lo;
634 u32 valid_bytes_received_hi;
635 u32 valid_bytes_received_lo;
636
637 u32 error_bytes_received_hi;
638 u32 error_bytes_received_lo;
639 u32 etherstatsoverrsizepkts_hi;
640 u32 etherstatsoverrsizepkts_lo;
641 u32 no_buff_discard_hi;
642 u32 no_buff_discard_lo;
643
644 u32 rx_stat_ifhcinbadoctets_hi;
645 u32 rx_stat_ifhcinbadoctets_lo;
646 u32 tx_stat_ifhcoutbadoctets_hi;
647 u32 tx_stat_ifhcoutbadoctets_lo;
648 u32 rx_stat_dot3statsfcserrors_hi;
649 u32 rx_stat_dot3statsfcserrors_lo;
650 u32 rx_stat_dot3statsalignmenterrors_hi;
651 u32 rx_stat_dot3statsalignmenterrors_lo;
652 u32 rx_stat_dot3statscarriersenseerrors_hi;
653 u32 rx_stat_dot3statscarriersenseerrors_lo;
654 u32 rx_stat_falsecarriererrors_hi;
655 u32 rx_stat_falsecarriererrors_lo;
656 u32 rx_stat_etherstatsundersizepkts_hi;
657 u32 rx_stat_etherstatsundersizepkts_lo;
658 u32 rx_stat_dot3statsframestoolong_hi;
659 u32 rx_stat_dot3statsframestoolong_lo;
660 u32 rx_stat_etherstatsfragments_hi;
661 u32 rx_stat_etherstatsfragments_lo;
662 u32 rx_stat_etherstatsjabbers_hi;
663 u32 rx_stat_etherstatsjabbers_lo;
664 u32 rx_stat_maccontrolframesreceived_hi;
665 u32 rx_stat_maccontrolframesreceived_lo;
666 u32 rx_stat_bmac_xpf_hi;
667 u32 rx_stat_bmac_xpf_lo;
668 u32 rx_stat_bmac_xcf_hi;
669 u32 rx_stat_bmac_xcf_lo;
670 u32 rx_stat_xoffstateentered_hi;
671 u32 rx_stat_xoffstateentered_lo;
672 u32 rx_stat_xonpauseframesreceived_hi;
673 u32 rx_stat_xonpauseframesreceived_lo;
674 u32 rx_stat_xoffpauseframesreceived_hi;
675 u32 rx_stat_xoffpauseframesreceived_lo;
676 u32 tx_stat_outxonsent_hi;
677 u32 tx_stat_outxonsent_lo;
678 u32 tx_stat_outxoffsent_hi;
679 u32 tx_stat_outxoffsent_lo;
680 u32 tx_stat_flowcontroldone_hi;
681 u32 tx_stat_flowcontroldone_lo;
682 u32 tx_stat_etherstatscollisions_hi;
683 u32 tx_stat_etherstatscollisions_lo;
684 u32 tx_stat_dot3statssinglecollisionframes_hi;
685 u32 tx_stat_dot3statssinglecollisionframes_lo;
686 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
687 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
688 u32 tx_stat_dot3statsdeferredtransmissions_hi;
689 u32 tx_stat_dot3statsdeferredtransmissions_lo;
690 u32 tx_stat_dot3statsexcessivecollisions_hi;
691 u32 tx_stat_dot3statsexcessivecollisions_lo;
692 u32 tx_stat_dot3statslatecollisions_hi;
693 u32 tx_stat_dot3statslatecollisions_lo;
694 u32 tx_stat_etherstatspkts64octets_hi;
695 u32 tx_stat_etherstatspkts64octets_lo;
696 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
697 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
698 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
699 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
700 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
701 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
702 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
703 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
704 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
705 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
706 u32 tx_stat_etherstatspktsover1522octets_hi;
707 u32 tx_stat_etherstatspktsover1522octets_lo;
708 u32 tx_stat_bmac_2047_hi;
709 u32 tx_stat_bmac_2047_lo;
710 u32 tx_stat_bmac_4095_hi;
711 u32 tx_stat_bmac_4095_lo;
712 u32 tx_stat_bmac_9216_hi;
713 u32 tx_stat_bmac_9216_lo;
714 u32 tx_stat_bmac_16383_hi;
715 u32 tx_stat_bmac_16383_lo;
716 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
717 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
718 u32 tx_stat_bmac_ufl_hi;
719 u32 tx_stat_bmac_ufl_lo;
720
721 u32 pause_frames_received_hi;
722 u32 pause_frames_received_lo;
723 u32 pause_frames_sent_hi;
724 u32 pause_frames_sent_lo;
725
726 u32 etherstatspkts1024octetsto1522octets_hi;
727 u32 etherstatspkts1024octetsto1522octets_lo;
728 u32 etherstatspktsover1522octets_hi;
729 u32 etherstatspktsover1522octets_lo;
730
731 u32 brb_drop_hi;
732 u32 brb_drop_lo;
733 u32 brb_truncate_hi;
734 u32 brb_truncate_lo;
735
736 u32 mac_filter_discard;
737 u32 xxoverflow_discard;
738 u32 brb_truncate_discard;
739 u32 mac_discard;
740
741 u32 driver_xoff;
742 u32 rx_err_discard_pkt;
743 u32 rx_skb_alloc_failed;
744 u32 hw_csum_err;
745
746 u32 nig_timer_max;
747 };
748
749 #define BNX2X_NUM_STATS 41
750 #define STATS_OFFSET32(stat_name) \
751 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
752
753
754 #define MAX_CONTEXT 16
755
756 union cdu_context {
757 struct eth_context eth;
758 char pad[1024];
759 };
760
761 #define MAX_DMAE_C 8
762
763 /* DMA memory not used in fastpath */
764 struct bnx2x_slowpath {
765 union cdu_context context[MAX_CONTEXT];
766 struct eth_stats_query fw_stats;
767 struct mac_configuration_cmd mac_config;
768 struct mac_configuration_cmd mcast_config;
769
770 /* used by dmae command executer */
771 struct dmae_command dmae[MAX_DMAE_C];
772
773 u32 stats_comp;
774 union mac_stats mac_stats;
775 struct nig_stats nig_stats;
776 struct host_port_stats port_stats;
777 struct host_func_stats func_stats;
778
779 u32 wb_comp;
780 u32 wb_data[4];
781 };
782
783 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
784 #define bnx2x_sp_mapping(bp, var) \
785 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
786
787
788 /* attn group wiring */
789 #define MAX_DYNAMIC_ATTN_GRPS 8
790
791 struct attn_route {
792 u32 sig[4];
793 };
794
795 struct bnx2x {
796 /* Fields used in the tx and intr/napi performance paths
797 * are grouped together in the beginning of the structure
798 */
799 struct bnx2x_fastpath fp[MAX_CONTEXT];
800 void __iomem *regview;
801 void __iomem *doorbells;
802 #define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE)
803
804 struct net_device *dev;
805 struct pci_dev *pdev;
806
807 atomic_t intr_sem;
808 struct msix_entry msix_table[MAX_CONTEXT+1];
809 #define INT_MODE_INTx 1
810 #define INT_MODE_MSI 2
811 #define INT_MODE_MSIX 3
812
813 int tx_ring_size;
814
815 #ifdef BCM_VLAN
816 struct vlan_group *vlgrp;
817 #endif
818
819 u32 rx_csum;
820 u32 rx_buf_size;
821 #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
822 #define ETH_MIN_PACKET_SIZE 60
823 #define ETH_MAX_PACKET_SIZE 1500
824 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
825
826 /* Max supported alignment is 256 (8 shift) */
827 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
828 L1_CACHE_SHIFT : 8)
829 #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
830
831 struct host_def_status_block *def_status_blk;
832 #define DEF_SB_ID 16
833 __le16 def_c_idx;
834 __le16 def_u_idx;
835 __le16 def_x_idx;
836 __le16 def_t_idx;
837 __le16 def_att_idx;
838 u32 attn_state;
839 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
840
841 /* slow path ring */
842 struct eth_spe *spq;
843 dma_addr_t spq_mapping;
844 u16 spq_prod_idx;
845 struct eth_spe *spq_prod_bd;
846 struct eth_spe *spq_last_bd;
847 __le16 *dsb_sp_prod;
848 u16 spq_left; /* serialize spq */
849 /* used to synchronize spq accesses */
850 spinlock_t spq_lock;
851
852 /* Flags for marking that there is a STAT_QUERY or
853 SET_MAC ramrod pending */
854 u8 stats_pending;
855 u8 set_mac_pending;
856
857 /* End of fields used in the performance code paths */
858
859 int panic;
860 int msglevel;
861
862 u32 flags;
863 #define PCIX_FLAG 1
864 #define PCI_32BIT_FLAG 2
865 #define ONE_PORT_FLAG 4
866 #define NO_WOL_FLAG 8
867 #define USING_DAC_FLAG 0x10
868 #define USING_MSIX_FLAG 0x20
869 #define USING_MSI_FLAG 0x40
870 #define TPA_ENABLE_FLAG 0x80
871 #define NO_MCP_FLAG 0x100
872 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
873 #define HW_VLAN_TX_FLAG 0x400
874 #define HW_VLAN_RX_FLAG 0x800
875
876 int func;
877 #define BP_PORT(bp) (bp->func % PORT_MAX)
878 #define BP_FUNC(bp) (bp->func)
879 #define BP_E1HVN(bp) (bp->func >> 1)
880 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
881
882 int pm_cap;
883 int pcie_cap;
884 int mrrs;
885
886 struct delayed_work sp_task;
887 struct work_struct reset_task;
888
889 struct timer_list timer;
890 int current_interval;
891
892 u16 fw_seq;
893 u16 fw_drv_pulse_wr_seq;
894 u32 func_stx;
895
896 struct link_params link_params;
897 struct link_vars link_vars;
898
899 struct bnx2x_common common;
900 struct bnx2x_port port;
901
902 struct cmng_struct_per_port cmng;
903 u32 vn_weight_sum;
904
905 u32 mf_config;
906 u16 e1hov;
907 u8 e1hmf;
908 #define IS_E1HMF(bp) (bp->e1hmf != 0)
909
910 u8 wol;
911
912 int rx_ring_size;
913
914 u16 tx_quick_cons_trip_int;
915 u16 tx_quick_cons_trip;
916 u16 tx_ticks_int;
917 u16 tx_ticks;
918
919 u16 rx_quick_cons_trip_int;
920 u16 rx_quick_cons_trip;
921 u16 rx_ticks_int;
922 u16 rx_ticks;
923
924 u32 lin_cnt;
925
926 int state;
927 #define BNX2X_STATE_CLOSED 0
928 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
929 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
930 #define BNX2X_STATE_OPEN 0x3000
931 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
932 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
933 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
934 #define BNX2X_STATE_DISABLED 0xd000
935 #define BNX2X_STATE_DIAG 0xe000
936 #define BNX2X_STATE_ERROR 0xf000
937
938 int multi_mode;
939 int num_rx_queues;
940 int num_tx_queues;
941
942 u32 rx_mode;
943 #define BNX2X_RX_MODE_NONE 0
944 #define BNX2X_RX_MODE_NORMAL 1
945 #define BNX2X_RX_MODE_ALLMULTI 2
946 #define BNX2X_RX_MODE_PROMISC 3
947 #define BNX2X_MAX_MULTICAST 64
948 #define BNX2X_MAX_EMUL_MULTI 16
949
950 dma_addr_t def_status_blk_mapping;
951
952 struct bnx2x_slowpath *slowpath;
953 dma_addr_t slowpath_mapping;
954
955 #ifdef BCM_ISCSI
956 void *t1;
957 dma_addr_t t1_mapping;
958 void *t2;
959 dma_addr_t t2_mapping;
960 void *timers;
961 dma_addr_t timers_mapping;
962 void *qm;
963 dma_addr_t qm_mapping;
964 #endif
965
966 int dmae_ready;
967 /* used to synchronize dmae accesses */
968 struct mutex dmae_mutex;
969 struct dmae_command init_dmae;
970
971 /* used to synchronize stats collecting */
972 int stats_state;
973 /* used by dmae command loader */
974 struct dmae_command stats_dmae;
975 int executer_idx;
976
977 u16 stats_counter;
978 struct bnx2x_eth_stats eth_stats;
979
980 struct z_stream_s *strm;
981 void *gunzip_buf;
982 dma_addr_t gunzip_mapping;
983 int gunzip_outlen;
984 #define FW_BUF_SIZE 0x8000
985
986 struct raw_op *init_ops;
987 /* Init blocks offsets inside init_ops */
988 u16 *init_ops_offsets;
989 /* Data blob - has 32 bit granularity */
990 u32 *init_data;
991 /* Zipped PRAM blobs - raw data */
992 const u8 *tsem_int_table_data;
993 const u8 *tsem_pram_data;
994 const u8 *usem_int_table_data;
995 const u8 *usem_pram_data;
996 const u8 *xsem_int_table_data;
997 const u8 *xsem_pram_data;
998 const u8 *csem_int_table_data;
999 const u8 *csem_pram_data;
1000 const struct firmware *firmware;
1001 };
1002
1003
1004 #define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT/(2 * E1HVN_MAX)) \
1005 : (MAX_CONTEXT/2))
1006 #define BNX2X_NUM_QUEUES(bp) (bp->num_rx_queues + bp->num_tx_queues)
1007 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 2)
1008
1009 #define for_each_rx_queue(bp, var) \
1010 for (var = 0; var < bp->num_rx_queues; var++)
1011 #define for_each_tx_queue(bp, var) \
1012 for (var = bp->num_rx_queues; \
1013 var < BNX2X_NUM_QUEUES(bp); var++)
1014 #define for_each_queue(bp, var) \
1015 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
1016 #define for_each_nondefault_queue(bp, var) \
1017 for (var = 1; var < bp->num_rx_queues; var++)
1018
1019
1020 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1021 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1022 u32 len32);
1023 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1024 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1025 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1026 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
1027
1028 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1029 int wait)
1030 {
1031 u32 val;
1032
1033 do {
1034 val = REG_RD(bp, reg);
1035 if (val == expected)
1036 break;
1037 ms -= wait;
1038 msleep(wait);
1039
1040 } while (ms > 0);
1041
1042 return val;
1043 }
1044
1045
1046 /* load/unload mode */
1047 #define LOAD_NORMAL 0
1048 #define LOAD_OPEN 1
1049 #define LOAD_DIAG 2
1050 #define UNLOAD_NORMAL 0
1051 #define UNLOAD_CLOSE 1
1052
1053
1054 /* DMAE command defines */
1055 #define DMAE_CMD_SRC_PCI 0
1056 #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
1057
1058 #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
1059 #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
1060
1061 #define DMAE_CMD_C_DST_PCI 0
1062 #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
1063
1064 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1065
1066 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1067 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1068 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1069 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1070
1071 #define DMAE_CMD_PORT_0 0
1072 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1073
1074 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1075 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1076 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1077
1078 #define DMAE_LEN32_RD_MAX 0x80
1079 #define DMAE_LEN32_WR_MAX 0x400
1080
1081 #define DMAE_COMP_VAL 0xe0d0d0ae
1082
1083 #define MAX_DMAE_C_PER_PORT 8
1084 #define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1085 BP_E1HVN(bp))
1086 #define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1087 E1HVN_MAX)
1088
1089
1090 /* PCIE link and speed */
1091 #define PCICFG_LINK_WIDTH 0x1f00000
1092 #define PCICFG_LINK_WIDTH_SHIFT 20
1093 #define PCICFG_LINK_SPEED 0xf0000
1094 #define PCICFG_LINK_SPEED_SHIFT 16
1095
1096
1097 #define BNX2X_NUM_TESTS 7
1098
1099 #define BNX2X_PHY_LOOPBACK 0
1100 #define BNX2X_MAC_LOOPBACK 1
1101 #define BNX2X_PHY_LOOPBACK_FAILED 1
1102 #define BNX2X_MAC_LOOPBACK_FAILED 2
1103 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1104 BNX2X_PHY_LOOPBACK_FAILED)
1105
1106
1107 #define STROM_ASSERT_ARRAY_SIZE 50
1108
1109
1110 /* must be used on a CID before placing it on a HW ring */
1111 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
1112
1113 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1114 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1115
1116
1117 #define BNX2X_BTR 3
1118 #define MAX_SPQ_PENDING 8
1119
1120
1121 /* CMNG constants
1122 derived from lab experiments, and not from system spec calculations !!! */
1123 #define DEF_MIN_RATE 100
1124 /* resolution of the rate shaping timer - 100 usec */
1125 #define RS_PERIODIC_TIMEOUT_USEC 100
1126 /* resolution of fairness algorithm in usecs -
1127 coefficient for calculating the actual t fair */
1128 #define T_FAIR_COEF 10000000
1129 /* number of bytes in single QM arbitration cycle -
1130 coefficient for calculating the fairness timer */
1131 #define QM_ARB_BYTES 40000
1132 #define FAIR_MEM 2
1133
1134
1135 #define ATTN_NIG_FOR_FUNC (1L << 8)
1136 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1137 #define GPIO_2_FUNC (1L << 10)
1138 #define GPIO_3_FUNC (1L << 11)
1139 #define GPIO_4_FUNC (1L << 12)
1140 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1141 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1142 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1143 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1144 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1145 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1146
1147 #define ATTN_HARD_WIRED_MASK 0xff00
1148 #define ATTENTION_ID 4
1149
1150
1151 /* stuff added to make the code fit 80Col */
1152
1153 #define BNX2X_PMF_LINK_ASSERT \
1154 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1155
1156 #define BNX2X_MC_ASSERT_BITS \
1157 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1158 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1159 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1160 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1161
1162 #define BNX2X_MCP_ASSERT \
1163 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1164
1165 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1166 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1167 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1168 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1169 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1170 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1171 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1172
1173 #define HW_INTERRUT_ASSERT_SET_0 \
1174 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1175 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1176 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1177 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1178 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1179 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1180 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1181 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1182 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1183 #define HW_INTERRUT_ASSERT_SET_1 \
1184 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1185 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1186 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1187 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1188 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1189 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1190 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1191 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1192 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1193 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1194 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1195 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1196 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1197 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1198 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1199 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1200 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1201 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1202 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1203 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1204 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1205 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1206 #define HW_INTERRUT_ASSERT_SET_2 \
1207 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1208 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1209 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1210 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1211 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1212 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1213 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1214 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1215 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1216 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1217 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1218 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1219
1220
1221 #define MULTI_FLAGS(bp) \
1222 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1223 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1224 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1225 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1226 (bp->multi_mode << \
1227 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1228
1229 #define MULTI_MASK 0x7f
1230
1231
1232 #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1233 #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1234 #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1235 #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1236
1237 #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1238
1239 #define BNX2X_SP_DSB_INDEX \
1240 (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1241
1242
1243 #define CAM_IS_INVALID(x) \
1244 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1245
1246 #define CAM_INVALIDATE(x) \
1247 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1248
1249
1250 /* Number of u32 elements in MC hash array */
1251 #define MC_HASH_SIZE 8
1252 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1253 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1254
1255
1256 #ifndef PXP2_REG_PXP2_INT_STS
1257 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1258 #endif
1259
1260 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1261
1262 #endif /* bnx2x.h */
kernel source for telekom puls (alcatel/mediatek)