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bnx2x: MDC/MDIO CL45 IOCTLs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2x.h
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2009 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16
17 /* compilation time flags */
18
19 /* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21 /* #define BNX2X_STOP_ON_ERROR */
22
23 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
24 #define BCM_VLAN 1
25 #endif
26
27
28 #define BNX2X_MULTI_QUEUE
29
30 #define BNX2X_NEW_NAPI
31
32
33
34 #include <linux/mdio.h>
35 #include "bnx2x_reg.h"
36 #include "bnx2x_fw_defs.h"
37 #include "bnx2x_hsi.h"
38 #include "bnx2x_link.h"
39
40 /* error/debug prints */
41
42 #define DRV_MODULE_NAME "bnx2x"
43 #define PFX DRV_MODULE_NAME ": "
44
45 /* for messages that are currently off */
46 #define BNX2X_MSG_OFF 0
47 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
48 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
49 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
50 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
51 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
52 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
53
54 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
55
56 /* regular debug print */
57 #define DP(__mask, __fmt, __args...) do { \
58 if (bp->msglevel & (__mask)) \
59 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
60 bp->dev ? (bp->dev->name) : "?", ##__args); \
61 } while (0)
62
63 /* errors debug print */
64 #define BNX2X_DBG_ERR(__fmt, __args...) do { \
65 if (bp->msglevel & NETIF_MSG_PROBE) \
66 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
67 bp->dev ? (bp->dev->name) : "?", ##__args); \
68 } while (0)
69
70 /* for errors (never masked) */
71 #define BNX2X_ERR(__fmt, __args...) do { \
72 printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
73 bp->dev ? (bp->dev->name) : "?", ##__args); \
74 } while (0)
75
76 /* before we have a dev->name use dev_info() */
77 #define BNX2X_DEV_INFO(__fmt, __args...) do { \
78 if (bp->msglevel & NETIF_MSG_PROBE) \
79 dev_info(&bp->pdev->dev, __fmt, ##__args); \
80 } while (0)
81
82
83 #ifdef BNX2X_STOP_ON_ERROR
84 #define bnx2x_panic() do { \
85 bp->panic = 1; \
86 BNX2X_ERR("driver assert\n"); \
87 bnx2x_int_disable(bp); \
88 bnx2x_panic_dump(bp); \
89 } while (0)
90 #else
91 #define bnx2x_panic() do { \
92 BNX2X_ERR("driver assert\n"); \
93 bnx2x_panic_dump(bp); \
94 } while (0)
95 #endif
96
97
98 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
99 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
100 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
101
102
103 #define REG_ADDR(bp, offset) (bp->regview + offset)
104
105 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
106 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
107
108 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
109 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
110 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
111
112 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
113 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
114
115 #define REG_RD_DMAE(bp, offset, valp, len32) \
116 do { \
117 bnx2x_read_dmae(bp, offset, len32);\
118 memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
119 } while (0)
120
121 #define REG_WR_DMAE(bp, offset, valp, len32) \
122 do { \
123 memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
124 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
125 offset, len32); \
126 } while (0)
127
128 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
129 offsetof(struct shmem_region, field))
130 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
131 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
132
133 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
134 offsetof(struct shmem2_region, field))
135 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
136 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
137
138 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
139 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
140
141
142 /* fast path */
143
144 struct sw_rx_bd {
145 struct sk_buff *skb;
146 DECLARE_PCI_UNMAP_ADDR(mapping)
147 };
148
149 struct sw_tx_bd {
150 struct sk_buff *skb;
151 u16 first_bd;
152 u8 flags;
153 /* Set on the first BD descriptor when there is a split BD */
154 #define BNX2X_TSO_SPLIT_BD (1<<0)
155 };
156
157 struct sw_rx_page {
158 struct page *page;
159 DECLARE_PCI_UNMAP_ADDR(mapping)
160 };
161
162 union db_prod {
163 struct doorbell_set_prod data;
164 u32 raw;
165 };
166
167
168 /* MC hsi */
169 #define BCM_PAGE_SHIFT 12
170 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
171 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
172 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
173
174 #define PAGES_PER_SGE_SHIFT 0
175 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
176 #define SGE_PAGE_SIZE PAGE_SIZE
177 #define SGE_PAGE_SHIFT PAGE_SHIFT
178 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
179
180 /* SGE ring related macros */
181 #define NUM_RX_SGE_PAGES 2
182 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
183 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
184 /* RX_SGE_CNT is promised to be a power of 2 */
185 #define RX_SGE_MASK (RX_SGE_CNT - 1)
186 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
187 #define MAX_RX_SGE (NUM_RX_SGE - 1)
188 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
189 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
190 #define RX_SGE(x) ((x) & MAX_RX_SGE)
191
192 /* SGE producer mask related macros */
193 /* Number of bits in one sge_mask array element */
194 #define RX_SGE_MASK_ELEM_SZ 64
195 #define RX_SGE_MASK_ELEM_SHIFT 6
196 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
197
198 /* Creates a bitmask of all ones in less significant bits.
199 idx - index of the most significant bit in the created mask */
200 #define RX_SGE_ONES_MASK(idx) \
201 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
202 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
203
204 /* Number of u64 elements in SGE mask array */
205 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
206 RX_SGE_MASK_ELEM_SZ)
207 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
208 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
209
210
211 struct bnx2x_eth_q_stats {
212 u32 total_bytes_received_hi;
213 u32 total_bytes_received_lo;
214 u32 total_bytes_transmitted_hi;
215 u32 total_bytes_transmitted_lo;
216 u32 total_unicast_packets_received_hi;
217 u32 total_unicast_packets_received_lo;
218 u32 total_multicast_packets_received_hi;
219 u32 total_multicast_packets_received_lo;
220 u32 total_broadcast_packets_received_hi;
221 u32 total_broadcast_packets_received_lo;
222 u32 total_unicast_packets_transmitted_hi;
223 u32 total_unicast_packets_transmitted_lo;
224 u32 total_multicast_packets_transmitted_hi;
225 u32 total_multicast_packets_transmitted_lo;
226 u32 total_broadcast_packets_transmitted_hi;
227 u32 total_broadcast_packets_transmitted_lo;
228 u32 valid_bytes_received_hi;
229 u32 valid_bytes_received_lo;
230
231 u32 error_bytes_received_hi;
232 u32 error_bytes_received_lo;
233 u32 etherstatsoverrsizepkts_hi;
234 u32 etherstatsoverrsizepkts_lo;
235 u32 no_buff_discard_hi;
236 u32 no_buff_discard_lo;
237
238 u32 driver_xoff;
239 u32 rx_err_discard_pkt;
240 u32 rx_skb_alloc_failed;
241 u32 hw_csum_err;
242 };
243
244 #define BNX2X_NUM_Q_STATS 11
245 #define Q_STATS_OFFSET32(stat_name) \
246 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
247
248 struct bnx2x_fastpath {
249
250 struct napi_struct napi;
251
252 u8 is_rx_queue;
253
254 struct host_status_block *status_blk;
255 dma_addr_t status_blk_mapping;
256
257 struct sw_tx_bd *tx_buf_ring;
258
259 union eth_tx_bd_types *tx_desc_ring;
260 dma_addr_t tx_desc_mapping;
261
262 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
263 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
264
265 struct eth_rx_bd *rx_desc_ring;
266 dma_addr_t rx_desc_mapping;
267
268 union eth_rx_cqe *rx_comp_ring;
269 dma_addr_t rx_comp_mapping;
270
271 /* SGE ring */
272 struct eth_rx_sge *rx_sge_ring;
273 dma_addr_t rx_sge_mapping;
274
275 u64 sge_mask[RX_SGE_MASK_LEN];
276
277 int state;
278 #define BNX2X_FP_STATE_CLOSED 0
279 #define BNX2X_FP_STATE_IRQ 0x80000
280 #define BNX2X_FP_STATE_OPENING 0x90000
281 #define BNX2X_FP_STATE_OPEN 0xa0000
282 #define BNX2X_FP_STATE_HALTING 0xb0000
283 #define BNX2X_FP_STATE_HALTED 0xc0000
284
285 u8 index; /* number in fp array */
286 u8 cl_id; /* eth client id */
287 u8 sb_id; /* status block number in HW */
288
289 union db_prod tx_db;
290
291 u16 tx_pkt_prod;
292 u16 tx_pkt_cons;
293 u16 tx_bd_prod;
294 u16 tx_bd_cons;
295 __le16 *tx_cons_sb;
296
297 __le16 fp_c_idx;
298 __le16 fp_u_idx;
299
300 u16 rx_bd_prod;
301 u16 rx_bd_cons;
302 u16 rx_comp_prod;
303 u16 rx_comp_cons;
304 u16 rx_sge_prod;
305 /* The last maximal completed SGE */
306 u16 last_max_sge;
307 __le16 *rx_cons_sb;
308 __le16 *rx_bd_cons_sb;
309
310 unsigned long tx_pkt,
311 rx_pkt,
312 rx_calls;
313 /* TPA related */
314 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
315 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
316 #define BNX2X_TPA_START 1
317 #define BNX2X_TPA_STOP 2
318 u8 disable_tpa;
319 #ifdef BNX2X_STOP_ON_ERROR
320 u64 tpa_queue_used;
321 #endif
322
323 struct tstorm_per_client_stats old_tclient;
324 struct ustorm_per_client_stats old_uclient;
325 struct xstorm_per_client_stats old_xclient;
326 struct bnx2x_eth_q_stats eth_q_stats;
327
328 /* The size is calculated using the following:
329 sizeof name field from netdev structure +
330 4 ('-Xx-' string) +
331 4 (for the digits and to make it DWORD aligned) */
332 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
333 char name[FP_NAME_SIZE];
334 struct bnx2x *bp; /* parent */
335 };
336
337 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
338
339
340 /* MC hsi */
341 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
342 #define RX_COPY_THRESH 92
343
344 #define NUM_TX_RINGS 16
345 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
346 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
347 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
348 #define MAX_TX_BD (NUM_TX_BD - 1)
349 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
350 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
351 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
352 #define TX_BD(x) ((x) & MAX_TX_BD)
353 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
354
355 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
356 #define NUM_RX_RINGS 8
357 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
358 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
359 #define RX_DESC_MASK (RX_DESC_CNT - 1)
360 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
361 #define MAX_RX_BD (NUM_RX_BD - 1)
362 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
363 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
364 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
365 #define RX_BD(x) ((x) & MAX_RX_BD)
366
367 /* As long as CQE is 4 times bigger than BD entry we have to allocate
368 4 times more pages for CQ ring in order to keep it balanced with
369 BD ring */
370 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
371 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
372 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
373 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
374 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
375 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
376 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
377 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
378 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
379
380
381 /* This is needed for determining of last_max */
382 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
383
384 #define __SGE_MASK_SET_BIT(el, bit) \
385 do { \
386 el = ((el) | ((u64)0x1 << (bit))); \
387 } while (0)
388
389 #define __SGE_MASK_CLEAR_BIT(el, bit) \
390 do { \
391 el = ((el) & (~((u64)0x1 << (bit)))); \
392 } while (0)
393
394 #define SGE_MASK_SET_BIT(fp, idx) \
395 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
396 ((idx) & RX_SGE_MASK_ELEM_MASK))
397
398 #define SGE_MASK_CLEAR_BIT(fp, idx) \
399 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
400 ((idx) & RX_SGE_MASK_ELEM_MASK))
401
402
403 /* used on a CID received from the HW */
404 #define SW_CID(x) (le32_to_cpu(x) & \
405 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
406 #define CQE_CMD(x) (le32_to_cpu(x) >> \
407 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
408
409 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
410 le32_to_cpu((bd)->addr_lo))
411 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
412
413
414 #define DPM_TRIGER_TYPE 0x40
415 #define DOORBELL(bp, cid, val) \
416 do { \
417 writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
418 DPM_TRIGER_TYPE); \
419 } while (0)
420
421
422 /* TX CSUM helpers */
423 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
424 skb->csum_offset)
425 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
426 skb->csum_offset))
427
428 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
429
430 #define XMIT_PLAIN 0
431 #define XMIT_CSUM_V4 0x1
432 #define XMIT_CSUM_V6 0x2
433 #define XMIT_CSUM_TCP 0x4
434 #define XMIT_GSO_V4 0x8
435 #define XMIT_GSO_V6 0x10
436
437 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
438 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
439
440
441 /* stuff added to make the code fit 80Col */
442
443 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
444
445 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
446 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
447 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
448 (TPA_TYPE_START | TPA_TYPE_END))
449
450 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
451
452 #define BNX2X_IP_CSUM_ERR(cqe) \
453 (!((cqe)->fast_path_cqe.status_flags & \
454 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
455 ((cqe)->fast_path_cqe.type_error_flags & \
456 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
457
458 #define BNX2X_L4_CSUM_ERR(cqe) \
459 (!((cqe)->fast_path_cqe.status_flags & \
460 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
461 ((cqe)->fast_path_cqe.type_error_flags & \
462 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
463
464 #define BNX2X_RX_CSUM_OK(cqe) \
465 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
466
467 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
468 (((le16_to_cpu(flags) & \
469 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
470 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
471 == PRS_FLAG_OVERETH_IPV4)
472 #define BNX2X_RX_SUM_FIX(cqe) \
473 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
474
475
476 #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
477 #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
478
479 #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
480 #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
481 #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
482
483 #define BNX2X_RX_SB_INDEX \
484 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
485
486 #define BNX2X_RX_SB_BD_INDEX \
487 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
488
489 #define BNX2X_RX_SB_INDEX_NUM \
490 (((U_SB_ETH_RX_CQ_INDEX << \
491 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
492 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
493 ((U_SB_ETH_RX_BD_INDEX << \
494 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
495 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
496
497 #define BNX2X_TX_SB_INDEX \
498 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
499
500
501 /* end of fast path */
502
503 /* common */
504
505 struct bnx2x_common {
506
507 u32 chip_id;
508 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
509 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
510
511 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
512 #define CHIP_NUM_57710 0x164e
513 #define CHIP_NUM_57711 0x164f
514 #define CHIP_NUM_57711E 0x1650
515 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
516 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
517 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
518 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
519 CHIP_IS_57711E(bp))
520 #define IS_E1H_OFFSET CHIP_IS_E1H(bp)
521
522 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
523 #define CHIP_REV_Ax 0x00000000
524 /* assume maximum 5 revisions */
525 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
526 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
527 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
528 !(CHIP_REV(bp) & 0x00001000))
529 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
530 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
531 (CHIP_REV(bp) & 0x00001000))
532
533 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
534 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
535
536 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
537 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
538
539 int flash_size;
540 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
541 #define NVRAM_TIMEOUT_COUNT 30000
542 #define NVRAM_PAGE_SIZE 256
543
544 u32 shmem_base;
545 u32 shmem2_base;
546
547 u32 hw_config;
548
549 u32 bc_ver;
550 };
551
552
553 /* end of common */
554
555 /* port */
556
557 struct nig_stats {
558 u32 brb_discard;
559 u32 brb_packet;
560 u32 brb_truncate;
561 u32 flow_ctrl_discard;
562 u32 flow_ctrl_octets;
563 u32 flow_ctrl_packet;
564 u32 mng_discard;
565 u32 mng_octet_inp;
566 u32 mng_octet_out;
567 u32 mng_packet_inp;
568 u32 mng_packet_out;
569 u32 pbf_octets;
570 u32 pbf_packet;
571 u32 safc_inp;
572 u32 egress_mac_pkt0_lo;
573 u32 egress_mac_pkt0_hi;
574 u32 egress_mac_pkt1_lo;
575 u32 egress_mac_pkt1_hi;
576 };
577
578 struct bnx2x_port {
579 u32 pmf;
580
581 u32 link_config;
582
583 u32 supported;
584 /* link settings - missing defines */
585 #define SUPPORTED_2500baseX_Full (1 << 15)
586
587 u32 advertising;
588 /* link settings - missing defines */
589 #define ADVERTISED_2500baseX_Full (1 << 15)
590
591 u32 phy_addr;
592
593 /* used to synchronize phy accesses */
594 struct mutex phy_mutex;
595 int need_hw_lock;
596
597 u32 port_stx;
598
599 struct nig_stats old_nig_stats;
600 };
601
602 /* end of port */
603
604
605 enum bnx2x_stats_event {
606 STATS_EVENT_PMF = 0,
607 STATS_EVENT_LINK_UP,
608 STATS_EVENT_UPDATE,
609 STATS_EVENT_STOP,
610 STATS_EVENT_MAX
611 };
612
613 enum bnx2x_stats_state {
614 STATS_STATE_DISABLED = 0,
615 STATS_STATE_ENABLED,
616 STATS_STATE_MAX
617 };
618
619 struct bnx2x_eth_stats {
620 u32 total_bytes_received_hi;
621 u32 total_bytes_received_lo;
622 u32 total_bytes_transmitted_hi;
623 u32 total_bytes_transmitted_lo;
624 u32 total_unicast_packets_received_hi;
625 u32 total_unicast_packets_received_lo;
626 u32 total_multicast_packets_received_hi;
627 u32 total_multicast_packets_received_lo;
628 u32 total_broadcast_packets_received_hi;
629 u32 total_broadcast_packets_received_lo;
630 u32 total_unicast_packets_transmitted_hi;
631 u32 total_unicast_packets_transmitted_lo;
632 u32 total_multicast_packets_transmitted_hi;
633 u32 total_multicast_packets_transmitted_lo;
634 u32 total_broadcast_packets_transmitted_hi;
635 u32 total_broadcast_packets_transmitted_lo;
636 u32 valid_bytes_received_hi;
637 u32 valid_bytes_received_lo;
638
639 u32 error_bytes_received_hi;
640 u32 error_bytes_received_lo;
641 u32 etherstatsoverrsizepkts_hi;
642 u32 etherstatsoverrsizepkts_lo;
643 u32 no_buff_discard_hi;
644 u32 no_buff_discard_lo;
645
646 u32 rx_stat_ifhcinbadoctets_hi;
647 u32 rx_stat_ifhcinbadoctets_lo;
648 u32 tx_stat_ifhcoutbadoctets_hi;
649 u32 tx_stat_ifhcoutbadoctets_lo;
650 u32 rx_stat_dot3statsfcserrors_hi;
651 u32 rx_stat_dot3statsfcserrors_lo;
652 u32 rx_stat_dot3statsalignmenterrors_hi;
653 u32 rx_stat_dot3statsalignmenterrors_lo;
654 u32 rx_stat_dot3statscarriersenseerrors_hi;
655 u32 rx_stat_dot3statscarriersenseerrors_lo;
656 u32 rx_stat_falsecarriererrors_hi;
657 u32 rx_stat_falsecarriererrors_lo;
658 u32 rx_stat_etherstatsundersizepkts_hi;
659 u32 rx_stat_etherstatsundersizepkts_lo;
660 u32 rx_stat_dot3statsframestoolong_hi;
661 u32 rx_stat_dot3statsframestoolong_lo;
662 u32 rx_stat_etherstatsfragments_hi;
663 u32 rx_stat_etherstatsfragments_lo;
664 u32 rx_stat_etherstatsjabbers_hi;
665 u32 rx_stat_etherstatsjabbers_lo;
666 u32 rx_stat_maccontrolframesreceived_hi;
667 u32 rx_stat_maccontrolframesreceived_lo;
668 u32 rx_stat_bmac_xpf_hi;
669 u32 rx_stat_bmac_xpf_lo;
670 u32 rx_stat_bmac_xcf_hi;
671 u32 rx_stat_bmac_xcf_lo;
672 u32 rx_stat_xoffstateentered_hi;
673 u32 rx_stat_xoffstateentered_lo;
674 u32 rx_stat_xonpauseframesreceived_hi;
675 u32 rx_stat_xonpauseframesreceived_lo;
676 u32 rx_stat_xoffpauseframesreceived_hi;
677 u32 rx_stat_xoffpauseframesreceived_lo;
678 u32 tx_stat_outxonsent_hi;
679 u32 tx_stat_outxonsent_lo;
680 u32 tx_stat_outxoffsent_hi;
681 u32 tx_stat_outxoffsent_lo;
682 u32 tx_stat_flowcontroldone_hi;
683 u32 tx_stat_flowcontroldone_lo;
684 u32 tx_stat_etherstatscollisions_hi;
685 u32 tx_stat_etherstatscollisions_lo;
686 u32 tx_stat_dot3statssinglecollisionframes_hi;
687 u32 tx_stat_dot3statssinglecollisionframes_lo;
688 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
689 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
690 u32 tx_stat_dot3statsdeferredtransmissions_hi;
691 u32 tx_stat_dot3statsdeferredtransmissions_lo;
692 u32 tx_stat_dot3statsexcessivecollisions_hi;
693 u32 tx_stat_dot3statsexcessivecollisions_lo;
694 u32 tx_stat_dot3statslatecollisions_hi;
695 u32 tx_stat_dot3statslatecollisions_lo;
696 u32 tx_stat_etherstatspkts64octets_hi;
697 u32 tx_stat_etherstatspkts64octets_lo;
698 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
699 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
700 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
701 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
702 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
703 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
704 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
705 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
706 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
707 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
708 u32 tx_stat_etherstatspktsover1522octets_hi;
709 u32 tx_stat_etherstatspktsover1522octets_lo;
710 u32 tx_stat_bmac_2047_hi;
711 u32 tx_stat_bmac_2047_lo;
712 u32 tx_stat_bmac_4095_hi;
713 u32 tx_stat_bmac_4095_lo;
714 u32 tx_stat_bmac_9216_hi;
715 u32 tx_stat_bmac_9216_lo;
716 u32 tx_stat_bmac_16383_hi;
717 u32 tx_stat_bmac_16383_lo;
718 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
719 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
720 u32 tx_stat_bmac_ufl_hi;
721 u32 tx_stat_bmac_ufl_lo;
722
723 u32 pause_frames_received_hi;
724 u32 pause_frames_received_lo;
725 u32 pause_frames_sent_hi;
726 u32 pause_frames_sent_lo;
727
728 u32 etherstatspkts1024octetsto1522octets_hi;
729 u32 etherstatspkts1024octetsto1522octets_lo;
730 u32 etherstatspktsover1522octets_hi;
731 u32 etherstatspktsover1522octets_lo;
732
733 u32 brb_drop_hi;
734 u32 brb_drop_lo;
735 u32 brb_truncate_hi;
736 u32 brb_truncate_lo;
737
738 u32 mac_filter_discard;
739 u32 xxoverflow_discard;
740 u32 brb_truncate_discard;
741 u32 mac_discard;
742
743 u32 driver_xoff;
744 u32 rx_err_discard_pkt;
745 u32 rx_skb_alloc_failed;
746 u32 hw_csum_err;
747
748 u32 nig_timer_max;
749 };
750
751 #define BNX2X_NUM_STATS 41
752 #define STATS_OFFSET32(stat_name) \
753 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
754
755
756 #define MAX_CONTEXT 16
757
758 union cdu_context {
759 struct eth_context eth;
760 char pad[1024];
761 };
762
763 #define MAX_DMAE_C 8
764
765 /* DMA memory not used in fastpath */
766 struct bnx2x_slowpath {
767 union cdu_context context[MAX_CONTEXT];
768 struct eth_stats_query fw_stats;
769 struct mac_configuration_cmd mac_config;
770 struct mac_configuration_cmd mcast_config;
771
772 /* used by dmae command executer */
773 struct dmae_command dmae[MAX_DMAE_C];
774
775 u32 stats_comp;
776 union mac_stats mac_stats;
777 struct nig_stats nig_stats;
778 struct host_port_stats port_stats;
779 struct host_func_stats func_stats;
780
781 u32 wb_comp;
782 u32 wb_data[4];
783 };
784
785 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
786 #define bnx2x_sp_mapping(bp, var) \
787 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
788
789
790 /* attn group wiring */
791 #define MAX_DYNAMIC_ATTN_GRPS 8
792
793 struct attn_route {
794 u32 sig[4];
795 };
796
797 struct bnx2x {
798 /* Fields used in the tx and intr/napi performance paths
799 * are grouped together in the beginning of the structure
800 */
801 struct bnx2x_fastpath fp[MAX_CONTEXT];
802 void __iomem *regview;
803 void __iomem *doorbells;
804 #define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE)
805
806 struct net_device *dev;
807 struct pci_dev *pdev;
808
809 atomic_t intr_sem;
810 struct msix_entry msix_table[MAX_CONTEXT+1];
811 #define INT_MODE_INTx 1
812 #define INT_MODE_MSI 2
813 #define INT_MODE_MSIX 3
814
815 int tx_ring_size;
816
817 #ifdef BCM_VLAN
818 struct vlan_group *vlgrp;
819 #endif
820
821 u32 rx_csum;
822 u32 rx_buf_size;
823 #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
824 #define ETH_MIN_PACKET_SIZE 60
825 #define ETH_MAX_PACKET_SIZE 1500
826 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
827
828 /* Max supported alignment is 256 (8 shift) */
829 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
830 L1_CACHE_SHIFT : 8)
831 #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
832
833 struct host_def_status_block *def_status_blk;
834 #define DEF_SB_ID 16
835 __le16 def_c_idx;
836 __le16 def_u_idx;
837 __le16 def_x_idx;
838 __le16 def_t_idx;
839 __le16 def_att_idx;
840 u32 attn_state;
841 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
842
843 /* slow path ring */
844 struct eth_spe *spq;
845 dma_addr_t spq_mapping;
846 u16 spq_prod_idx;
847 struct eth_spe *spq_prod_bd;
848 struct eth_spe *spq_last_bd;
849 __le16 *dsb_sp_prod;
850 u16 spq_left; /* serialize spq */
851 /* used to synchronize spq accesses */
852 spinlock_t spq_lock;
853
854 /* Flags for marking that there is a STAT_QUERY or
855 SET_MAC ramrod pending */
856 u8 stats_pending;
857 u8 set_mac_pending;
858
859 /* End of fields used in the performance code paths */
860
861 int panic;
862 int msglevel;
863
864 u32 flags;
865 #define PCIX_FLAG 1
866 #define PCI_32BIT_FLAG 2
867 #define ONE_PORT_FLAG 4
868 #define NO_WOL_FLAG 8
869 #define USING_DAC_FLAG 0x10
870 #define USING_MSIX_FLAG 0x20
871 #define USING_MSI_FLAG 0x40
872 #define TPA_ENABLE_FLAG 0x80
873 #define NO_MCP_FLAG 0x100
874 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
875 #define HW_VLAN_TX_FLAG 0x400
876 #define HW_VLAN_RX_FLAG 0x800
877
878 int func;
879 #define BP_PORT(bp) (bp->func % PORT_MAX)
880 #define BP_FUNC(bp) (bp->func)
881 #define BP_E1HVN(bp) (bp->func >> 1)
882 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
883
884 int pm_cap;
885 int pcie_cap;
886 int mrrs;
887
888 struct delayed_work sp_task;
889 struct work_struct reset_task;
890
891 struct timer_list timer;
892 int current_interval;
893
894 u16 fw_seq;
895 u16 fw_drv_pulse_wr_seq;
896 u32 func_stx;
897
898 struct link_params link_params;
899 struct link_vars link_vars;
900 struct mdio_if_info mdio;
901
902 struct bnx2x_common common;
903 struct bnx2x_port port;
904
905 struct cmng_struct_per_port cmng;
906 u32 vn_weight_sum;
907
908 u32 mf_config;
909 u16 e1hov;
910 u8 e1hmf;
911 #define IS_E1HMF(bp) (bp->e1hmf != 0)
912
913 u8 wol;
914
915 int rx_ring_size;
916
917 u16 tx_quick_cons_trip_int;
918 u16 tx_quick_cons_trip;
919 u16 tx_ticks_int;
920 u16 tx_ticks;
921
922 u16 rx_quick_cons_trip_int;
923 u16 rx_quick_cons_trip;
924 u16 rx_ticks_int;
925 u16 rx_ticks;
926
927 u32 lin_cnt;
928
929 int state;
930 #define BNX2X_STATE_CLOSED 0
931 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
932 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
933 #define BNX2X_STATE_OPEN 0x3000
934 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
935 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
936 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
937 #define BNX2X_STATE_DISABLED 0xd000
938 #define BNX2X_STATE_DIAG 0xe000
939 #define BNX2X_STATE_ERROR 0xf000
940
941 int multi_mode;
942 int num_rx_queues;
943 int num_tx_queues;
944
945 u32 rx_mode;
946 #define BNX2X_RX_MODE_NONE 0
947 #define BNX2X_RX_MODE_NORMAL 1
948 #define BNX2X_RX_MODE_ALLMULTI 2
949 #define BNX2X_RX_MODE_PROMISC 3
950 #define BNX2X_MAX_MULTICAST 64
951 #define BNX2X_MAX_EMUL_MULTI 16
952
953 dma_addr_t def_status_blk_mapping;
954
955 struct bnx2x_slowpath *slowpath;
956 dma_addr_t slowpath_mapping;
957
958 #ifdef BCM_ISCSI
959 void *t1;
960 dma_addr_t t1_mapping;
961 void *t2;
962 dma_addr_t t2_mapping;
963 void *timers;
964 dma_addr_t timers_mapping;
965 void *qm;
966 dma_addr_t qm_mapping;
967 #endif
968
969 int dmae_ready;
970 /* used to synchronize dmae accesses */
971 struct mutex dmae_mutex;
972 struct dmae_command init_dmae;
973
974 /* used to synchronize stats collecting */
975 int stats_state;
976 /* used by dmae command loader */
977 struct dmae_command stats_dmae;
978 int executer_idx;
979
980 u16 stats_counter;
981 struct bnx2x_eth_stats eth_stats;
982
983 struct z_stream_s *strm;
984 void *gunzip_buf;
985 dma_addr_t gunzip_mapping;
986 int gunzip_outlen;
987 #define FW_BUF_SIZE 0x8000
988
989 struct raw_op *init_ops;
990 /* Init blocks offsets inside init_ops */
991 u16 *init_ops_offsets;
992 /* Data blob - has 32 bit granularity */
993 u32 *init_data;
994 /* Zipped PRAM blobs - raw data */
995 const u8 *tsem_int_table_data;
996 const u8 *tsem_pram_data;
997 const u8 *usem_int_table_data;
998 const u8 *usem_pram_data;
999 const u8 *xsem_int_table_data;
1000 const u8 *xsem_pram_data;
1001 const u8 *csem_int_table_data;
1002 const u8 *csem_pram_data;
1003 const struct firmware *firmware;
1004 };
1005
1006
1007 #define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT/(2 * E1HVN_MAX)) \
1008 : (MAX_CONTEXT/2))
1009 #define BNX2X_NUM_QUEUES(bp) (bp->num_rx_queues + bp->num_tx_queues)
1010 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 2)
1011
1012 #define for_each_rx_queue(bp, var) \
1013 for (var = 0; var < bp->num_rx_queues; var++)
1014 #define for_each_tx_queue(bp, var) \
1015 for (var = bp->num_rx_queues; \
1016 var < BNX2X_NUM_QUEUES(bp); var++)
1017 #define for_each_queue(bp, var) \
1018 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
1019 #define for_each_nondefault_queue(bp, var) \
1020 for (var = 1; var < bp->num_rx_queues; var++)
1021
1022
1023 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1024 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1025 u32 len32);
1026 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1027 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1028 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1029 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
1030
1031 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1032 int wait)
1033 {
1034 u32 val;
1035
1036 do {
1037 val = REG_RD(bp, reg);
1038 if (val == expected)
1039 break;
1040 ms -= wait;
1041 msleep(wait);
1042
1043 } while (ms > 0);
1044
1045 return val;
1046 }
1047
1048
1049 /* load/unload mode */
1050 #define LOAD_NORMAL 0
1051 #define LOAD_OPEN 1
1052 #define LOAD_DIAG 2
1053 #define UNLOAD_NORMAL 0
1054 #define UNLOAD_CLOSE 1
1055
1056
1057 /* DMAE command defines */
1058 #define DMAE_CMD_SRC_PCI 0
1059 #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
1060
1061 #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
1062 #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
1063
1064 #define DMAE_CMD_C_DST_PCI 0
1065 #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
1066
1067 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1068
1069 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1070 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1071 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1072 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1073
1074 #define DMAE_CMD_PORT_0 0
1075 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1076
1077 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1078 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1079 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1080
1081 #define DMAE_LEN32_RD_MAX 0x80
1082 #define DMAE_LEN32_WR_MAX 0x400
1083
1084 #define DMAE_COMP_VAL 0xe0d0d0ae
1085
1086 #define MAX_DMAE_C_PER_PORT 8
1087 #define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1088 BP_E1HVN(bp))
1089 #define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \
1090 E1HVN_MAX)
1091
1092
1093 /* PCIE link and speed */
1094 #define PCICFG_LINK_WIDTH 0x1f00000
1095 #define PCICFG_LINK_WIDTH_SHIFT 20
1096 #define PCICFG_LINK_SPEED 0xf0000
1097 #define PCICFG_LINK_SPEED_SHIFT 16
1098
1099
1100 #define BNX2X_NUM_TESTS 7
1101
1102 #define BNX2X_PHY_LOOPBACK 0
1103 #define BNX2X_MAC_LOOPBACK 1
1104 #define BNX2X_PHY_LOOPBACK_FAILED 1
1105 #define BNX2X_MAC_LOOPBACK_FAILED 2
1106 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1107 BNX2X_PHY_LOOPBACK_FAILED)
1108
1109
1110 #define STROM_ASSERT_ARRAY_SIZE 50
1111
1112
1113 /* must be used on a CID before placing it on a HW ring */
1114 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x)
1115
1116 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1117 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1118
1119
1120 #define BNX2X_BTR 3
1121 #define MAX_SPQ_PENDING 8
1122
1123
1124 /* CMNG constants
1125 derived from lab experiments, and not from system spec calculations !!! */
1126 #define DEF_MIN_RATE 100
1127 /* resolution of the rate shaping timer - 100 usec */
1128 #define RS_PERIODIC_TIMEOUT_USEC 100
1129 /* resolution of fairness algorithm in usecs -
1130 coefficient for calculating the actual t fair */
1131 #define T_FAIR_COEF 10000000
1132 /* number of bytes in single QM arbitration cycle -
1133 coefficient for calculating the fairness timer */
1134 #define QM_ARB_BYTES 40000
1135 #define FAIR_MEM 2
1136
1137
1138 #define ATTN_NIG_FOR_FUNC (1L << 8)
1139 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1140 #define GPIO_2_FUNC (1L << 10)
1141 #define GPIO_3_FUNC (1L << 11)
1142 #define GPIO_4_FUNC (1L << 12)
1143 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1144 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1145 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1146 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1147 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1148 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1149
1150 #define ATTN_HARD_WIRED_MASK 0xff00
1151 #define ATTENTION_ID 4
1152
1153
1154 /* stuff added to make the code fit 80Col */
1155
1156 #define BNX2X_PMF_LINK_ASSERT \
1157 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1158
1159 #define BNX2X_MC_ASSERT_BITS \
1160 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1161 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1162 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1163 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1164
1165 #define BNX2X_MCP_ASSERT \
1166 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1167
1168 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1169 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1170 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1171 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1172 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1173 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1174 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1175
1176 #define HW_INTERRUT_ASSERT_SET_0 \
1177 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1178 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1179 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1180 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1181 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1182 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1183 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1184 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1185 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1186 #define HW_INTERRUT_ASSERT_SET_1 \
1187 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1188 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1189 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1190 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1191 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1192 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1193 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1194 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1195 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1196 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1197 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1198 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1199 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1200 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1201 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1202 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1203 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1204 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1205 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1206 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1207 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1208 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1209 #define HW_INTERRUT_ASSERT_SET_2 \
1210 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1211 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1212 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1213 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1214 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1215 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1216 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1217 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1218 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1219 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1220 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1221 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1222
1223
1224 #define MULTI_FLAGS(bp) \
1225 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1226 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1227 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1228 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1229 (bp->multi_mode << \
1230 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1231
1232 #define MULTI_MASK 0x7f
1233
1234
1235 #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1236 #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1237 #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1238 #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
1239
1240 #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1241
1242 #define BNX2X_SP_DSB_INDEX \
1243 (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
1244
1245
1246 #define CAM_IS_INVALID(x) \
1247 (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1248
1249 #define CAM_INVALIDATE(x) \
1250 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1251
1252
1253 /* Number of u32 elements in MC hash array */
1254 #define MC_HASH_SIZE 8
1255 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1256 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1257
1258
1259 #ifndef PXP2_REG_PXP2_INT_STS
1260 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1261 #endif
1262
1263 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1264
1265 #endif /* bnx2x.h */
kernel source for telekom puls (alcatel/mediatek)