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bnx2x: Add TX fault check for fiber PHYs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2x / bnx2x_link.c
1 /* Copyright 2008-2011 Broadcom Corporation
2 *
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
7 *
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
11 * consent.
12 *
13 * Written by Yaniv Rosner
14 *
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
26
27 #include "bnx2x.h"
28
29 /********************************************************/
30 #define ETH_HLEN 14
31 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
32 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
33 #define ETH_MIN_PACKET_SIZE 60
34 #define ETH_MAX_PACKET_SIZE 1500
35 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
36 #define MDIO_ACCESS_TIMEOUT 1000
37 #define BMAC_CONTROL_RX_ENABLE 2
38
39 /***********************************************************/
40 /* Shortcut definitions */
41 /***********************************************************/
42
43 #define NIG_LATCH_BC_ENABLE_MI_INT 0
44
45 #define NIG_STATUS_EMAC0_MI_INT \
46 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
47 #define NIG_STATUS_XGXS0_LINK10G \
48 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
49 #define NIG_STATUS_XGXS0_LINK_STATUS \
50 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
51 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
52 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
53 #define NIG_STATUS_SERDES0_LINK_STATUS \
54 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
55 #define NIG_MASK_MI_INT \
56 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
57 #define NIG_MASK_XGXS0_LINK10G \
58 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
59 #define NIG_MASK_XGXS0_LINK_STATUS \
60 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
61 #define NIG_MASK_SERDES0_LINK_STATUS \
62 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
63
64 #define MDIO_AN_CL73_OR_37_COMPLETE \
65 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
66 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
67
68 #define XGXS_RESET_BITS \
69 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
71 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
72 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
73 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
74
75 #define SERDES_RESET_BITS \
76 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
77 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
78 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
79 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
80
81 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
82 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
83 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
84 #define AUTONEG_PARALLEL \
85 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
86 #define AUTONEG_SGMII_FIBER_AUTODET \
87 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
88 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
89
90 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
91 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
92 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
93 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
94 #define GP_STATUS_SPEED_MASK \
95 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
96 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
97 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
98 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
99 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
100 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
101 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
102 #define GP_STATUS_10G_HIG \
103 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
104 #define GP_STATUS_10G_CX4 \
105 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
106 #define GP_STATUS_12G_HIG \
107 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
108 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
109 #define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
110 #define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
111 #define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
112 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
113 #define GP_STATUS_10G_KX4 \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
115
116 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
117 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
118 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
119 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
120 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
121 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
122 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
123 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
124 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
125 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
126 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
127 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
128 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
129 #define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
130 #define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
131 #define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
132 #define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
133 #define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
134 #define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
135 #define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
136 #define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
137 #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
138 #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
139
140 #define PHY_XGXS_FLAG 0x1
141 #define PHY_SGMII_FLAG 0x2
142 #define PHY_SERDES_FLAG 0x4
143
144 /* */
145 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
146 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
147 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
148
149
150 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
151 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
152 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
153 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
154
155 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
156 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
157 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
158
159 #define SFP_EEPROM_OPTIONS_ADDR 0x40
160 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
161 #define SFP_EEPROM_OPTIONS_SIZE 2
162
163 #define EDC_MODE_LINEAR 0x0022
164 #define EDC_MODE_LIMITING 0x0044
165 #define EDC_MODE_PASSIVE_DAC 0x0055
166
167
168 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
169 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
170 /**********************************************************/
171 /* INTERFACE */
172 /**********************************************************/
173
174 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
175 bnx2x_cl45_write(_bp, _phy, \
176 (_phy)->def_md_devad, \
177 (_bank + (_addr & 0xf)), \
178 _val)
179
180 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
181 bnx2x_cl45_read(_bp, _phy, \
182 (_phy)->def_md_devad, \
183 (_bank + (_addr & 0xf)), \
184 _val)
185
186 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
187 {
188 u32 val = REG_RD(bp, reg);
189
190 val |= bits;
191 REG_WR(bp, reg, val);
192 return val;
193 }
194
195 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
196 {
197 u32 val = REG_RD(bp, reg);
198
199 val &= ~bits;
200 REG_WR(bp, reg, val);
201 return val;
202 }
203
204 /******************************************************************/
205 /* ETS section */
206 /******************************************************************/
207 void bnx2x_ets_disabled(struct link_params *params)
208 {
209 /* ETS disabled configuration*/
210 struct bnx2x *bp = params->bp;
211
212 DP(NETIF_MSG_LINK, "ETS disabled configuration\n");
213
214 /*
215 * mapping between entry priority to client number (0,1,2 -debug and
216 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
217 * 3bits client num.
218 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
219 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
220 */
221
222 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
223 /*
224 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
225 * as strict. Bits 0,1,2 - debug and management entries, 3 -
226 * COS0 entry, 4 - COS1 entry.
227 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
228 * bit4 bit3 bit2 bit1 bit0
229 * MCP and debug are strict
230 */
231
232 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
233 /* defines which entries (clients) are subjected to WFQ arbitration */
234 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
235 /*
236 * For strict priority entries defines the number of consecutive
237 * slots for the highest priority.
238 */
239 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
240 /*
241 * mapping between the CREDIT_WEIGHT registers and actual client
242 * numbers
243 */
244 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
245 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
246 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
247
248 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
249 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
250 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
251 /* ETS mode disable */
252 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
253 /*
254 * If ETS mode is enabled (there is no strict priority) defines a WFQ
255 * weight for COS0/COS1.
256 */
257 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
258 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
259 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
260 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
261 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
262 /* Defines the number of consecutive slots for the strict priority */
263 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
264 }
265
266 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
267 {
268 /* ETS disabled configuration */
269 struct bnx2x *bp = params->bp;
270 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
271 /*
272 * defines which entries (clients) are subjected to WFQ arbitration
273 * COS0 0x8
274 * COS1 0x10
275 */
276 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
277 /*
278 * mapping between the ARB_CREDIT_WEIGHT registers and actual
279 * client numbers (WEIGHT_0 does not actually have to represent
280 * client 0)
281 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
282 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
283 */
284 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
285
286 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
287 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
288 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
289 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
290
291 /* ETS mode enabled*/
292 REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
293
294 /* Defines the number of consecutive slots for the strict priority */
295 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
296 /*
297 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
298 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
299 * entry, 4 - COS1 entry.
300 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
301 * bit4 bit3 bit2 bit1 bit0
302 * MCP and debug are strict
303 */
304 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
305
306 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
307 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
308 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
309 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
310 ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
311 }
312
313 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
314 const u32 cos1_bw)
315 {
316 /* ETS disabled configuration*/
317 struct bnx2x *bp = params->bp;
318 const u32 total_bw = cos0_bw + cos1_bw;
319 u32 cos0_credit_weight = 0;
320 u32 cos1_credit_weight = 0;
321
322 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
323
324 if ((0 == total_bw) ||
325 (0 == cos0_bw) ||
326 (0 == cos1_bw)) {
327 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
328 return;
329 }
330
331 cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
332 total_bw;
333 cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
334 total_bw;
335
336 bnx2x_ets_bw_limit_common(params);
337
338 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
339 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
340
341 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
342 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
343 }
344
345 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
346 {
347 /* ETS disabled configuration*/
348 struct bnx2x *bp = params->bp;
349 u32 val = 0;
350
351 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
352 /*
353 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
354 * as strict. Bits 0,1,2 - debug and management entries,
355 * 3 - COS0 entry, 4 - COS1 entry.
356 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
357 * bit4 bit3 bit2 bit1 bit0
358 * MCP and debug are strict
359 */
360 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
361 /*
362 * For strict priority entries defines the number of consecutive slots
363 * for the highest priority.
364 */
365 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
366 /* ETS mode disable */
367 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
368 /* Defines the number of consecutive slots for the strict priority */
369 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
370
371 /* Defines the number of consecutive slots for the strict priority */
372 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
373
374 /*
375 * mapping between entry priority to client number (0,1,2 -debug and
376 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
377 * 3bits client num.
378 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
379 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
380 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
381 */
382 val = (0 == strict_cos) ? 0x2318 : 0x22E0;
383 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
384
385 return 0;
386 }
387 /******************************************************************/
388 /* PFC section */
389 /******************************************************************/
390
391 static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
392 u32 pfc_frames_sent[2],
393 u32 pfc_frames_received[2])
394 {
395 /* Read pfc statistic */
396 struct bnx2x *bp = params->bp;
397 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
398 NIG_REG_INGRESS_BMAC0_MEM;
399
400 DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
401
402 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
403 pfc_frames_sent, 2);
404
405 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
406 pfc_frames_received, 2);
407
408 }
409 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
410 u32 pfc_frames_sent[2],
411 u32 pfc_frames_received[2])
412 {
413 /* Read pfc statistic */
414 struct bnx2x *bp = params->bp;
415 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
416 u32 val_xon = 0;
417 u32 val_xoff = 0;
418
419 DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
420
421 /* PFC received frames */
422 val_xoff = REG_RD(bp, emac_base +
423 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
424 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
425 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
426 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
427
428 pfc_frames_received[0] = val_xon + val_xoff;
429
430 /* PFC received sent */
431 val_xoff = REG_RD(bp, emac_base +
432 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
433 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
434 val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
435 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
436
437 pfc_frames_sent[0] = val_xon + val_xoff;
438 }
439
440 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
441 u32 pfc_frames_sent[2],
442 u32 pfc_frames_received[2])
443 {
444 /* Read pfc statistic */
445 struct bnx2x *bp = params->bp;
446 u32 val = 0;
447 DP(NETIF_MSG_LINK, "pfc statistic\n");
448
449 if (!vars->link_up)
450 return;
451
452 val = REG_RD(bp, MISC_REG_RESET_REG_2);
453 if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
454 == 0) {
455 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
456 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
457 pfc_frames_received);
458 } else {
459 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
460 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
461 pfc_frames_received);
462 }
463 }
464 /******************************************************************/
465 /* MAC/PBF section */
466 /******************************************************************/
467 static void bnx2x_emac_init(struct link_params *params,
468 struct link_vars *vars)
469 {
470 /* reset and unreset the emac core */
471 struct bnx2x *bp = params->bp;
472 u8 port = params->port;
473 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
474 u32 val;
475 u16 timeout;
476
477 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
478 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
479 udelay(5);
480 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
481 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
482
483 /* init emac - use read-modify-write */
484 /* self clear reset */
485 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
486 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
487
488 timeout = 200;
489 do {
490 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
491 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
492 if (!timeout) {
493 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
494 return;
495 }
496 timeout--;
497 } while (val & EMAC_MODE_RESET);
498
499 /* Set mac address */
500 val = ((params->mac_addr[0] << 8) |
501 params->mac_addr[1]);
502 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
503
504 val = ((params->mac_addr[2] << 24) |
505 (params->mac_addr[3] << 16) |
506 (params->mac_addr[4] << 8) |
507 params->mac_addr[5]);
508 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
509 }
510
511 static int bnx2x_emac_enable(struct link_params *params,
512 struct link_vars *vars, u8 lb)
513 {
514 struct bnx2x *bp = params->bp;
515 u8 port = params->port;
516 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
517 u32 val;
518
519 DP(NETIF_MSG_LINK, "enabling EMAC\n");
520
521 /* enable emac and not bmac */
522 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
523
524 /* ASIC */
525 if (vars->phy_flags & PHY_XGXS_FLAG) {
526 u32 ser_lane = ((params->lane_config &
527 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
528 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
529
530 DP(NETIF_MSG_LINK, "XGXS\n");
531 /* select the master lanes (out of 0-3) */
532 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
533 /* select XGXS */
534 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
535
536 } else { /* SerDes */
537 DP(NETIF_MSG_LINK, "SerDes\n");
538 /* select SerDes */
539 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
540 }
541
542 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
543 EMAC_RX_MODE_RESET);
544 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
545 EMAC_TX_MODE_RESET);
546
547 if (CHIP_REV_IS_SLOW(bp)) {
548 /* config GMII mode */
549 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
550 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
551 } else { /* ASIC */
552 /* pause enable/disable */
553 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
554 EMAC_RX_MODE_FLOW_EN);
555
556 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
557 (EMAC_TX_MODE_EXT_PAUSE_EN |
558 EMAC_TX_MODE_FLOW_EN));
559 if (!(params->feature_config_flags &
560 FEATURE_CONFIG_PFC_ENABLED)) {
561 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
562 bnx2x_bits_en(bp, emac_base +
563 EMAC_REG_EMAC_RX_MODE,
564 EMAC_RX_MODE_FLOW_EN);
565
566 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
567 bnx2x_bits_en(bp, emac_base +
568 EMAC_REG_EMAC_TX_MODE,
569 (EMAC_TX_MODE_EXT_PAUSE_EN |
570 EMAC_TX_MODE_FLOW_EN));
571 } else
572 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
573 EMAC_TX_MODE_FLOW_EN);
574 }
575
576 /* KEEP_VLAN_TAG, promiscuous */
577 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
578 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
579
580 /*
581 * Setting this bit causes MAC control frames (except for pause
582 * frames) to be passed on for processing. This setting has no
583 * affect on the operation of the pause frames. This bit effects
584 * all packets regardless of RX Parser packet sorting logic.
585 * Turn the PFC off to make sure we are in Xon state before
586 * enabling it.
587 */
588 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
589 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
590 DP(NETIF_MSG_LINK, "PFC is enabled\n");
591 /* Enable PFC again */
592 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
593 EMAC_REG_RX_PFC_MODE_RX_EN |
594 EMAC_REG_RX_PFC_MODE_TX_EN |
595 EMAC_REG_RX_PFC_MODE_PRIORITIES);
596
597 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
598 ((0x0101 <<
599 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
600 (0x00ff <<
601 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
602 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
603 }
604 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
605
606 /* Set Loopback */
607 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
608 if (lb)
609 val |= 0x810;
610 else
611 val &= ~0x810;
612 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
613
614 /* enable emac */
615 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
616
617 /* enable emac for jumbo packets */
618 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
619 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
620 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
621
622 /* strip CRC */
623 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
624
625 /* disable the NIG in/out to the bmac */
626 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
627 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
628 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
629
630 /* enable the NIG in/out to the emac */
631 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
632 val = 0;
633 if ((params->feature_config_flags &
634 FEATURE_CONFIG_PFC_ENABLED) ||
635 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
636 val = 1;
637
638 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
639 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
640
641 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
642
643 vars->mac_type = MAC_TYPE_EMAC;
644 return 0;
645 }
646
647 static void bnx2x_update_pfc_bmac1(struct link_params *params,
648 struct link_vars *vars)
649 {
650 u32 wb_data[2];
651 struct bnx2x *bp = params->bp;
652 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
653 NIG_REG_INGRESS_BMAC0_MEM;
654
655 u32 val = 0x14;
656 if ((!(params->feature_config_flags &
657 FEATURE_CONFIG_PFC_ENABLED)) &&
658 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
659 /* Enable BigMAC to react on received Pause packets */
660 val |= (1<<5);
661 wb_data[0] = val;
662 wb_data[1] = 0;
663 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
664
665 /* tx control */
666 val = 0xc0;
667 if (!(params->feature_config_flags &
668 FEATURE_CONFIG_PFC_ENABLED) &&
669 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
670 val |= 0x800000;
671 wb_data[0] = val;
672 wb_data[1] = 0;
673 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
674 }
675
676 static void bnx2x_update_pfc_bmac2(struct link_params *params,
677 struct link_vars *vars,
678 u8 is_lb)
679 {
680 /*
681 * Set rx control: Strip CRC and enable BigMAC to relay
682 * control packets to the system as well
683 */
684 u32 wb_data[2];
685 struct bnx2x *bp = params->bp;
686 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
687 NIG_REG_INGRESS_BMAC0_MEM;
688 u32 val = 0x14;
689
690 if ((!(params->feature_config_flags &
691 FEATURE_CONFIG_PFC_ENABLED)) &&
692 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
693 /* Enable BigMAC to react on received Pause packets */
694 val |= (1<<5);
695 wb_data[0] = val;
696 wb_data[1] = 0;
697 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
698 udelay(30);
699
700 /* Tx control */
701 val = 0xc0;
702 if (!(params->feature_config_flags &
703 FEATURE_CONFIG_PFC_ENABLED) &&
704 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
705 val |= 0x800000;
706 wb_data[0] = val;
707 wb_data[1] = 0;
708 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
709
710 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
711 DP(NETIF_MSG_LINK, "PFC is enabled\n");
712 /* Enable PFC RX & TX & STATS and set 8 COS */
713 wb_data[0] = 0x0;
714 wb_data[0] |= (1<<0); /* RX */
715 wb_data[0] |= (1<<1); /* TX */
716 wb_data[0] |= (1<<2); /* Force initial Xon */
717 wb_data[0] |= (1<<3); /* 8 cos */
718 wb_data[0] |= (1<<5); /* STATS */
719 wb_data[1] = 0;
720 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
721 wb_data, 2);
722 /* Clear the force Xon */
723 wb_data[0] &= ~(1<<2);
724 } else {
725 DP(NETIF_MSG_LINK, "PFC is disabled\n");
726 /* disable PFC RX & TX & STATS and set 8 COS */
727 wb_data[0] = 0x8;
728 wb_data[1] = 0;
729 }
730
731 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
732
733 /*
734 * Set Time (based unit is 512 bit time) between automatic
735 * re-sending of PP packets amd enable automatic re-send of
736 * Per-Priroity Packet as long as pp_gen is asserted and
737 * pp_disable is low.
738 */
739 val = 0x8000;
740 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
741 val |= (1<<16); /* enable automatic re-send */
742
743 wb_data[0] = val;
744 wb_data[1] = 0;
745 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
746 wb_data, 2);
747
748 /* mac control */
749 val = 0x3; /* Enable RX and TX */
750 if (is_lb) {
751 val |= 0x4; /* Local loopback */
752 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
753 }
754 /* When PFC enabled, Pass pause frames towards the NIG. */
755 if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
756 val |= ((1<<6)|(1<<5));
757
758 wb_data[0] = val;
759 wb_data[1] = 0;
760 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
761 }
762
763 static void bnx2x_update_pfc_brb(struct link_params *params,
764 struct link_vars *vars,
765 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
766 {
767 struct bnx2x *bp = params->bp;
768 int set_pfc = params->feature_config_flags &
769 FEATURE_CONFIG_PFC_ENABLED;
770
771 /* default - pause configuration */
772 u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
773 u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
774 u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
775 u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
776
777 if (set_pfc && pfc_params)
778 /* First COS */
779 if (!pfc_params->cos0_pauseable) {
780 pause_xoff_th =
781 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
782 pause_xon_th =
783 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
784 full_xoff_th =
785 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
786 full_xon_th =
787 PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
788 }
789 /*
790 * The number of free blocks below which the pause signal to class 0
791 * of MAC #n is asserted. n=0,1
792 */
793 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th);
794 /*
795 * The number of free blocks above which the pause signal to class 0
796 * of MAC #n is de-asserted. n=0,1
797 */
798 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th);
799 /*
800 * The number of free blocks below which the full signal to class 0
801 * of MAC #n is asserted. n=0,1
802 */
803 REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th);
804 /*
805 * The number of free blocks above which the full signal to class 0
806 * of MAC #n is de-asserted. n=0,1
807 */
808 REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th);
809
810 if (set_pfc && pfc_params) {
811 /* Second COS */
812 if (pfc_params->cos1_pauseable) {
813 pause_xoff_th =
814 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
815 pause_xon_th =
816 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
817 full_xoff_th =
818 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
819 full_xon_th =
820 PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
821 } else {
822 pause_xoff_th =
823 PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
824 pause_xon_th =
825 PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
826 full_xoff_th =
827 PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
828 full_xon_th =
829 PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
830 }
831 /*
832 * The number of free blocks below which the pause signal to
833 * class 1 of MAC #n is asserted. n=0,1
834 */
835 REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th);
836 /*
837 * The number of free blocks above which the pause signal to
838 * class 1 of MAC #n is de-asserted. n=0,1
839 */
840 REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th);
841 /*
842 * The number of free blocks below which the full signal to
843 * class 1 of MAC #n is asserted. n=0,1
844 */
845 REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th);
846 /*
847 * The number of free blocks above which the full signal to
848 * class 1 of MAC #n is de-asserted. n=0,1
849 */
850 REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th);
851 }
852 }
853
854 static void bnx2x_update_pfc_nig(struct link_params *params,
855 struct link_vars *vars,
856 struct bnx2x_nig_brb_pfc_port_params *nig_params)
857 {
858 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
859 u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
860 u32 pkt_priority_to_cos = 0;
861 u32 val;
862 struct bnx2x *bp = params->bp;
863 int port = params->port;
864 int set_pfc = params->feature_config_flags &
865 FEATURE_CONFIG_PFC_ENABLED;
866 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
867
868 /*
869 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
870 * MAC control frames (that are not pause packets)
871 * will be forwarded to the XCM.
872 */
873 xcm_mask = REG_RD(bp,
874 port ? NIG_REG_LLH1_XCM_MASK :
875 NIG_REG_LLH0_XCM_MASK);
876 /*
877 * nig params will override non PFC params, since it's possible to
878 * do transition from PFC to SAFC
879 */
880 if (set_pfc) {
881 pause_enable = 0;
882 llfc_out_en = 0;
883 llfc_enable = 0;
884 ppp_enable = 1;
885 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
886 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
887 xcm0_out_en = 0;
888 p0_hwpfc_enable = 1;
889 } else {
890 if (nig_params) {
891 llfc_out_en = nig_params->llfc_out_en;
892 llfc_enable = nig_params->llfc_enable;
893 pause_enable = nig_params->pause_enable;
894 } else /*defaul non PFC mode - PAUSE */
895 pause_enable = 1;
896
897 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
898 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
899 xcm0_out_en = 1;
900 }
901
902 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
903 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
904 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
905 NIG_REG_LLFC_ENABLE_0, llfc_enable);
906 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
907 NIG_REG_PAUSE_ENABLE_0, pause_enable);
908
909 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
910 NIG_REG_PPP_ENABLE_0, ppp_enable);
911
912 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
913 NIG_REG_LLH0_XCM_MASK, xcm_mask);
914
915 REG_WR(bp, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
916
917 /* output enable for RX_XCM # IF */
918 REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
919
920 /* HW PFC TX enable */
921 REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
922
923 /* 0x2 = BMAC, 0x1= EMAC */
924 switch (vars->mac_type) {
925 case MAC_TYPE_EMAC:
926 val = 1;
927 break;
928 case MAC_TYPE_BMAC:
929 val = 0;
930 break;
931 default:
932 val = 0;
933 break;
934 }
935 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val);
936
937 if (nig_params) {
938 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
939
940 REG_WR(bp, port ? NIG_REG_P1_RX_COS0_PRIORITY_MASK :
941 NIG_REG_P0_RX_COS0_PRIORITY_MASK,
942 nig_params->rx_cos0_priority_mask);
943
944 REG_WR(bp, port ? NIG_REG_P1_RX_COS1_PRIORITY_MASK :
945 NIG_REG_P0_RX_COS1_PRIORITY_MASK,
946 nig_params->rx_cos1_priority_mask);
947
948 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
949 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
950 nig_params->llfc_high_priority_classes);
951
952 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
953 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
954 nig_params->llfc_low_priority_classes);
955 }
956 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
957 NIG_REG_P0_PKT_PRIORITY_TO_COS,
958 pkt_priority_to_cos);
959 }
960
961
962 void bnx2x_update_pfc(struct link_params *params,
963 struct link_vars *vars,
964 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
965 {
966 /*
967 * The PFC and pause are orthogonal to one another, meaning when
968 * PFC is enabled, the pause are disabled, and when PFC is
969 * disabled, pause are set according to the pause result.
970 */
971 u32 val;
972 struct bnx2x *bp = params->bp;
973
974 /* update NIG params */
975 bnx2x_update_pfc_nig(params, vars, pfc_params);
976
977 /* update BRB params */
978 bnx2x_update_pfc_brb(params, vars, pfc_params);
979
980 if (!vars->link_up)
981 return;
982
983 val = REG_RD(bp, MISC_REG_RESET_REG_2);
984 if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
985 == 0) {
986 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
987 bnx2x_emac_enable(params, vars, 0);
988 return;
989 }
990
991 DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
992 if (CHIP_IS_E2(bp))
993 bnx2x_update_pfc_bmac2(params, vars, 0);
994 else
995 bnx2x_update_pfc_bmac1(params, vars);
996
997 val = 0;
998 if ((params->feature_config_flags &
999 FEATURE_CONFIG_PFC_ENABLED) ||
1000 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1001 val = 1;
1002 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
1003 }
1004
1005 static int bnx2x_bmac1_enable(struct link_params *params,
1006 struct link_vars *vars,
1007 u8 is_lb)
1008 {
1009 struct bnx2x *bp = params->bp;
1010 u8 port = params->port;
1011 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1012 NIG_REG_INGRESS_BMAC0_MEM;
1013 u32 wb_data[2];
1014 u32 val;
1015
1016 DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
1017
1018 /* XGXS control */
1019 wb_data[0] = 0x3c;
1020 wb_data[1] = 0;
1021 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1022 wb_data, 2);
1023
1024 /* tx MAC SA */
1025 wb_data[0] = ((params->mac_addr[2] << 24) |
1026 (params->mac_addr[3] << 16) |
1027 (params->mac_addr[4] << 8) |
1028 params->mac_addr[5]);
1029 wb_data[1] = ((params->mac_addr[0] << 8) |
1030 params->mac_addr[1]);
1031 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
1032
1033 /* mac control */
1034 val = 0x3;
1035 if (is_lb) {
1036 val |= 0x4;
1037 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1038 }
1039 wb_data[0] = val;
1040 wb_data[1] = 0;
1041 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
1042
1043 /* set rx mtu */
1044 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1045 wb_data[1] = 0;
1046 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
1047
1048 bnx2x_update_pfc_bmac1(params, vars);
1049
1050 /* set tx mtu */
1051 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1052 wb_data[1] = 0;
1053 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
1054
1055 /* set cnt max size */
1056 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1057 wb_data[1] = 0;
1058 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1059
1060 /* configure safc */
1061 wb_data[0] = 0x1000200;
1062 wb_data[1] = 0;
1063 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
1064 wb_data, 2);
1065
1066 return 0;
1067 }
1068
1069 static int bnx2x_bmac2_enable(struct link_params *params,
1070 struct link_vars *vars,
1071 u8 is_lb)
1072 {
1073 struct bnx2x *bp = params->bp;
1074 u8 port = params->port;
1075 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1076 NIG_REG_INGRESS_BMAC0_MEM;
1077 u32 wb_data[2];
1078
1079 DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
1080
1081 wb_data[0] = 0;
1082 wb_data[1] = 0;
1083 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1084 udelay(30);
1085
1086 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
1087 wb_data[0] = 0x3c;
1088 wb_data[1] = 0;
1089 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
1090 wb_data, 2);
1091
1092 udelay(30);
1093
1094 /* tx MAC SA */
1095 wb_data[0] = ((params->mac_addr[2] << 24) |
1096 (params->mac_addr[3] << 16) |
1097 (params->mac_addr[4] << 8) |
1098 params->mac_addr[5]);
1099 wb_data[1] = ((params->mac_addr[0] << 8) |
1100 params->mac_addr[1]);
1101 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
1102 wb_data, 2);
1103
1104 udelay(30);
1105
1106 /* Configure SAFC */
1107 wb_data[0] = 0x1000200;
1108 wb_data[1] = 0;
1109 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
1110 wb_data, 2);
1111 udelay(30);
1112
1113 /* set rx mtu */
1114 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1115 wb_data[1] = 0;
1116 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
1117 udelay(30);
1118
1119 /* set tx mtu */
1120 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1121 wb_data[1] = 0;
1122 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
1123 udelay(30);
1124 /* set cnt max size */
1125 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
1126 wb_data[1] = 0;
1127 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
1128 udelay(30);
1129 bnx2x_update_pfc_bmac2(params, vars, is_lb);
1130
1131 return 0;
1132 }
1133
1134 static int bnx2x_bmac_enable(struct link_params *params,
1135 struct link_vars *vars,
1136 u8 is_lb)
1137 {
1138 int rc = 0;
1139 u8 port = params->port;
1140 struct bnx2x *bp = params->bp;
1141 u32 val;
1142 /* reset and unreset the BigMac */
1143 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1144 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1145 msleep(1);
1146
1147 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1148 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1149
1150 /* enable access for bmac registers */
1151 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
1152
1153 /* Enable BMAC according to BMAC type*/
1154 if (CHIP_IS_E2(bp))
1155 rc = bnx2x_bmac2_enable(params, vars, is_lb);
1156 else
1157 rc = bnx2x_bmac1_enable(params, vars, is_lb);
1158 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
1159 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
1160 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
1161 val = 0;
1162 if ((params->feature_config_flags &
1163 FEATURE_CONFIG_PFC_ENABLED) ||
1164 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1165 val = 1;
1166 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
1167 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
1168 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
1169 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
1170 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
1171 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
1172
1173 vars->mac_type = MAC_TYPE_BMAC;
1174 return rc;
1175 }
1176
1177
1178 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
1179 {
1180 struct bnx2x *bp = params->bp;
1181
1182 REG_WR(bp, params->shmem_base +
1183 offsetof(struct shmem_region,
1184 port_mb[params->port].link_status), link_status);
1185 }
1186
1187 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1188 {
1189 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1190 NIG_REG_INGRESS_BMAC0_MEM;
1191 u32 wb_data[2];
1192 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
1193
1194 /* Only if the bmac is out of reset */
1195 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1196 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
1197 nig_bmac_enable) {
1198
1199 if (CHIP_IS_E2(bp)) {
1200 /* Clear Rx Enable bit in BMAC_CONTROL register */
1201 REG_RD_DMAE(bp, bmac_addr +
1202 BIGMAC2_REGISTER_BMAC_CONTROL,
1203 wb_data, 2);
1204 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1205 REG_WR_DMAE(bp, bmac_addr +
1206 BIGMAC2_REGISTER_BMAC_CONTROL,
1207 wb_data, 2);
1208 } else {
1209 /* Clear Rx Enable bit in BMAC_CONTROL register */
1210 REG_RD_DMAE(bp, bmac_addr +
1211 BIGMAC_REGISTER_BMAC_CONTROL,
1212 wb_data, 2);
1213 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1214 REG_WR_DMAE(bp, bmac_addr +
1215 BIGMAC_REGISTER_BMAC_CONTROL,
1216 wb_data, 2);
1217 }
1218 msleep(1);
1219 }
1220 }
1221
1222 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
1223 u32 line_speed)
1224 {
1225 struct bnx2x *bp = params->bp;
1226 u8 port = params->port;
1227 u32 init_crd, crd;
1228 u32 count = 1000;
1229
1230 /* disable port */
1231 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
1232
1233 /* wait for init credit */
1234 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
1235 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1236 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
1237
1238 while ((init_crd != crd) && count) {
1239 msleep(5);
1240
1241 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1242 count--;
1243 }
1244 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1245 if (init_crd != crd) {
1246 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
1247 init_crd, crd);
1248 return -EINVAL;
1249 }
1250
1251 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
1252 line_speed == SPEED_10 ||
1253 line_speed == SPEED_100 ||
1254 line_speed == SPEED_1000 ||
1255 line_speed == SPEED_2500) {
1256 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
1257 /* update threshold */
1258 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
1259 /* update init credit */
1260 init_crd = 778; /* (800-18-4) */
1261
1262 } else {
1263 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
1264 ETH_OVREHEAD)/16;
1265 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
1266 /* update threshold */
1267 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
1268 /* update init credit */
1269 switch (line_speed) {
1270 case SPEED_10000:
1271 init_crd = thresh + 553 - 22;
1272 break;
1273
1274 case SPEED_12000:
1275 init_crd = thresh + 664 - 22;
1276 break;
1277
1278 case SPEED_13000:
1279 init_crd = thresh + 742 - 22;
1280 break;
1281
1282 case SPEED_16000:
1283 init_crd = thresh + 778 - 22;
1284 break;
1285 default:
1286 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1287 line_speed);
1288 return -EINVAL;
1289 }
1290 }
1291 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
1292 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
1293 line_speed, init_crd);
1294
1295 /* probe the credit changes */
1296 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
1297 msleep(5);
1298 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
1299
1300 /* enable port */
1301 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
1302 return 0;
1303 }
1304
1305 /**
1306 * bnx2x_get_emac_base - retrive emac base address
1307 *
1308 * @bp: driver handle
1309 * @mdc_mdio_access: access type
1310 * @port: port id
1311 *
1312 * This function selects the MDC/MDIO access (through emac0 or
1313 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
1314 * phy has a default access mode, which could also be overridden
1315 * by nvram configuration. This parameter, whether this is the
1316 * default phy configuration, or the nvram overrun
1317 * configuration, is passed here as mdc_mdio_access and selects
1318 * the emac_base for the CL45 read/writes operations
1319 */
1320 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
1321 u32 mdc_mdio_access, u8 port)
1322 {
1323 u32 emac_base = 0;
1324 switch (mdc_mdio_access) {
1325 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
1326 break;
1327 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
1328 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1329 emac_base = GRCBASE_EMAC1;
1330 else
1331 emac_base = GRCBASE_EMAC0;
1332 break;
1333 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
1334 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1335 emac_base = GRCBASE_EMAC0;
1336 else
1337 emac_base = GRCBASE_EMAC1;
1338 break;
1339 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
1340 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1341 break;
1342 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
1343 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
1344 break;
1345 default:
1346 break;
1347 }
1348 return emac_base;
1349
1350 }
1351
1352 /******************************************************************/
1353 /* CL45 access functions */
1354 /******************************************************************/
1355 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
1356 u8 devad, u16 reg, u16 val)
1357 {
1358 u32 tmp, saved_mode;
1359 u8 i;
1360 int rc = 0;
1361 /*
1362 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1363 * (a value of 49==0x31) and make sure that the AUTO poll is off
1364 */
1365
1366 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1367 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
1368 EMAC_MDIO_MODE_CLOCK_CNT);
1369 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1370 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1371 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1372 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1373 udelay(40);
1374
1375 /* address */
1376
1377 tmp = ((phy->addr << 21) | (devad << 16) | reg |
1378 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1379 EMAC_MDIO_COMM_START_BUSY);
1380 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1381
1382 for (i = 0; i < 50; i++) {
1383 udelay(10);
1384
1385 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1386 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1387 udelay(5);
1388 break;
1389 }
1390 }
1391 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1392 DP(NETIF_MSG_LINK, "write phy register failed\n");
1393 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
1394 rc = -EFAULT;
1395 } else {
1396 /* data */
1397 tmp = ((phy->addr << 21) | (devad << 16) | val |
1398 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1399 EMAC_MDIO_COMM_START_BUSY);
1400 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1401
1402 for (i = 0; i < 50; i++) {
1403 udelay(10);
1404
1405 tmp = REG_RD(bp, phy->mdio_ctrl +
1406 EMAC_REG_EMAC_MDIO_COMM);
1407 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1408 udelay(5);
1409 break;
1410 }
1411 }
1412 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1413 DP(NETIF_MSG_LINK, "write phy register failed\n");
1414 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
1415 rc = -EFAULT;
1416 }
1417 }
1418
1419 /* Restore the saved mode */
1420 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1421
1422 return rc;
1423 }
1424
1425 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
1426 u8 devad, u16 reg, u16 *ret_val)
1427 {
1428 u32 val, saved_mode;
1429 u16 i;
1430 int rc = 0;
1431 /*
1432 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1433 * (a value of 49==0x31) and make sure that the AUTO poll is off
1434 */
1435
1436 saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1437 val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
1438 EMAC_MDIO_MODE_CLOCK_CNT));
1439 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
1440 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1441 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1442 REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1443 udelay(40);
1444
1445 /* address */
1446 val = ((phy->addr << 21) | (devad << 16) | reg |
1447 EMAC_MDIO_COMM_COMMAND_ADDRESS |
1448 EMAC_MDIO_COMM_START_BUSY);
1449 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1450
1451 for (i = 0; i < 50; i++) {
1452 udelay(10);
1453
1454 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1455 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1456 udelay(5);
1457 break;
1458 }
1459 }
1460 if (val & EMAC_MDIO_COMM_START_BUSY) {
1461 DP(NETIF_MSG_LINK, "read phy register failed\n");
1462 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
1463 *ret_val = 0;
1464 rc = -EFAULT;
1465
1466 } else {
1467 /* data */
1468 val = ((phy->addr << 21) | (devad << 16) |
1469 EMAC_MDIO_COMM_COMMAND_READ_45 |
1470 EMAC_MDIO_COMM_START_BUSY);
1471 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1472
1473 for (i = 0; i < 50; i++) {
1474 udelay(10);
1475
1476 val = REG_RD(bp, phy->mdio_ctrl +
1477 EMAC_REG_EMAC_MDIO_COMM);
1478 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1479 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
1480 break;
1481 }
1482 }
1483 if (val & EMAC_MDIO_COMM_START_BUSY) {
1484 DP(NETIF_MSG_LINK, "read phy register failed\n");
1485 netdev_err(bp->dev, "MDC/MDIO access timeout\n");
1486 *ret_val = 0;
1487 rc = -EFAULT;
1488 }
1489 }
1490
1491 /* Restore the saved mode */
1492 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1493
1494 return rc;
1495 }
1496
1497 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
1498 u8 devad, u16 reg, u16 *ret_val)
1499 {
1500 u8 phy_index;
1501 /*
1502 * Probe for the phy according to the given phy_addr, and execute
1503 * the read request on it
1504 */
1505 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1506 if (params->phy[phy_index].addr == phy_addr) {
1507 return bnx2x_cl45_read(params->bp,
1508 &params->phy[phy_index], devad,
1509 reg, ret_val);
1510 }
1511 }
1512 return -EINVAL;
1513 }
1514
1515 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
1516 u8 devad, u16 reg, u16 val)
1517 {
1518 u8 phy_index;
1519 /*
1520 * Probe for the phy according to the given phy_addr, and execute
1521 * the write request on it
1522 */
1523 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1524 if (params->phy[phy_index].addr == phy_addr) {
1525 return bnx2x_cl45_write(params->bp,
1526 &params->phy[phy_index], devad,
1527 reg, val);
1528 }
1529 }
1530 return -EINVAL;
1531 }
1532
1533 static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
1534 struct bnx2x_phy *phy)
1535 {
1536 u32 ser_lane;
1537 u16 offset, aer_val;
1538 struct bnx2x *bp = params->bp;
1539 ser_lane = ((params->lane_config &
1540 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1541 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1542
1543 offset = phy->addr + ser_lane;
1544 if (CHIP_IS_E2(bp))
1545 aer_val = 0x3800 + offset - 1;
1546 else
1547 aer_val = 0x3800 + offset;
1548 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
1549 MDIO_AER_BLOCK_AER_REG, aer_val);
1550 }
1551 static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
1552 struct bnx2x_phy *phy)
1553 {
1554 CL22_WR_OVER_CL45(bp, phy,
1555 MDIO_REG_BANK_AER_BLOCK,
1556 MDIO_AER_BLOCK_AER_REG, 0x3800);
1557 }
1558
1559 /******************************************************************/
1560 /* Internal phy section */
1561 /******************************************************************/
1562
1563 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
1564 {
1565 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1566
1567 /* Set Clause 22 */
1568 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
1569 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
1570 udelay(500);
1571 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
1572 udelay(500);
1573 /* Set Clause 45 */
1574 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
1575 }
1576
1577 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
1578 {
1579 u32 val;
1580
1581 DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
1582
1583 val = SERDES_RESET_BITS << (port*16);
1584
1585 /* reset and unreset the SerDes/XGXS */
1586 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1587 udelay(500);
1588 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1589
1590 bnx2x_set_serdes_access(bp, port);
1591
1592 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
1593 DEFAULT_PHY_DEV_ADDR);
1594 }
1595
1596 static void bnx2x_xgxs_deassert(struct link_params *params)
1597 {
1598 struct bnx2x *bp = params->bp;
1599 u8 port;
1600 u32 val;
1601 DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
1602 port = params->port;
1603
1604 val = XGXS_RESET_BITS << (port*16);
1605
1606 /* reset and unreset the SerDes/XGXS */
1607 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1608 udelay(500);
1609 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1610
1611 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
1612 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
1613 params->phy[INT_PHY].def_md_devad);
1614 }
1615
1616
1617 void bnx2x_link_status_update(struct link_params *params,
1618 struct link_vars *vars)
1619 {
1620 struct bnx2x *bp = params->bp;
1621 u8 link_10g;
1622 u8 port = params->port;
1623 u32 sync_offset, media_types;
1624 vars->link_status = REG_RD(bp, params->shmem_base +
1625 offsetof(struct shmem_region,
1626 port_mb[port].link_status));
1627
1628 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
1629
1630 if (vars->link_up) {
1631 DP(NETIF_MSG_LINK, "phy link up\n");
1632
1633 vars->phy_link_up = 1;
1634 vars->duplex = DUPLEX_FULL;
1635 switch (vars->link_status &
1636 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
1637 case LINK_10THD:
1638 vars->duplex = DUPLEX_HALF;
1639 /* fall thru */
1640 case LINK_10TFD:
1641 vars->line_speed = SPEED_10;
1642 break;
1643
1644 case LINK_100TXHD:
1645 vars->duplex = DUPLEX_HALF;
1646 /* fall thru */
1647 case LINK_100T4:
1648 case LINK_100TXFD:
1649 vars->line_speed = SPEED_100;
1650 break;
1651
1652 case LINK_1000THD:
1653 vars->duplex = DUPLEX_HALF;
1654 /* fall thru */
1655 case LINK_1000TFD:
1656 vars->line_speed = SPEED_1000;
1657 break;
1658
1659 case LINK_2500THD:
1660 vars->duplex = DUPLEX_HALF;
1661 /* fall thru */
1662 case LINK_2500TFD:
1663 vars->line_speed = SPEED_2500;
1664 break;
1665
1666 case LINK_10GTFD:
1667 vars->line_speed = SPEED_10000;
1668 break;
1669
1670 case LINK_12GTFD:
1671 vars->line_speed = SPEED_12000;
1672 break;
1673
1674 case LINK_12_5GTFD:
1675 vars->line_speed = SPEED_12500;
1676 break;
1677
1678 case LINK_13GTFD:
1679 vars->line_speed = SPEED_13000;
1680 break;
1681
1682 case LINK_15GTFD:
1683 vars->line_speed = SPEED_15000;
1684 break;
1685
1686 case LINK_16GTFD:
1687 vars->line_speed = SPEED_16000;
1688 break;
1689
1690 default:
1691 break;
1692 }
1693 vars->flow_ctrl = 0;
1694 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
1695 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
1696
1697 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
1698 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
1699
1700 if (!vars->flow_ctrl)
1701 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1702
1703 if (vars->line_speed &&
1704 ((vars->line_speed == SPEED_10) ||
1705 (vars->line_speed == SPEED_100))) {
1706 vars->phy_flags |= PHY_SGMII_FLAG;
1707 } else {
1708 vars->phy_flags &= ~PHY_SGMII_FLAG;
1709 }
1710
1711 /* anything 10 and over uses the bmac */
1712 link_10g = ((vars->line_speed == SPEED_10000) ||
1713 (vars->line_speed == SPEED_12000) ||
1714 (vars->line_speed == SPEED_12500) ||
1715 (vars->line_speed == SPEED_13000) ||
1716 (vars->line_speed == SPEED_15000) ||
1717 (vars->line_speed == SPEED_16000));
1718 if (link_10g)
1719 vars->mac_type = MAC_TYPE_BMAC;
1720 else
1721 vars->mac_type = MAC_TYPE_EMAC;
1722
1723 } else { /* link down */
1724 DP(NETIF_MSG_LINK, "phy link down\n");
1725
1726 vars->phy_link_up = 0;
1727
1728 vars->line_speed = 0;
1729 vars->duplex = DUPLEX_FULL;
1730 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1731
1732 /* indicate no mac active */
1733 vars->mac_type = MAC_TYPE_NONE;
1734 }
1735
1736 /* Sync media type */
1737 sync_offset = params->shmem_base +
1738 offsetof(struct shmem_region,
1739 dev_info.port_hw_config[port].media_type);
1740 media_types = REG_RD(bp, sync_offset);
1741
1742 params->phy[INT_PHY].media_type =
1743 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
1744 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
1745 params->phy[EXT_PHY1].media_type =
1746 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
1747 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
1748 params->phy[EXT_PHY2].media_type =
1749 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
1750 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
1751 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
1752
1753 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
1754 vars->link_status, vars->phy_link_up);
1755 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
1756 vars->line_speed, vars->duplex, vars->flow_ctrl);
1757 }
1758
1759
1760 static void bnx2x_set_master_ln(struct link_params *params,
1761 struct bnx2x_phy *phy)
1762 {
1763 struct bnx2x *bp = params->bp;
1764 u16 new_master_ln, ser_lane;
1765 ser_lane = ((params->lane_config &
1766 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1767 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1768
1769 /* set the master_ln for AN */
1770 CL22_RD_OVER_CL45(bp, phy,
1771 MDIO_REG_BANK_XGXS_BLOCK2,
1772 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1773 &new_master_ln);
1774
1775 CL22_WR_OVER_CL45(bp, phy,
1776 MDIO_REG_BANK_XGXS_BLOCK2 ,
1777 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1778 (new_master_ln | ser_lane));
1779 }
1780
1781 static int bnx2x_reset_unicore(struct link_params *params,
1782 struct bnx2x_phy *phy,
1783 u8 set_serdes)
1784 {
1785 struct bnx2x *bp = params->bp;
1786 u16 mii_control;
1787 u16 i;
1788 CL22_RD_OVER_CL45(bp, phy,
1789 MDIO_REG_BANK_COMBO_IEEE0,
1790 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1791
1792 /* reset the unicore */
1793 CL22_WR_OVER_CL45(bp, phy,
1794 MDIO_REG_BANK_COMBO_IEEE0,
1795 MDIO_COMBO_IEEE0_MII_CONTROL,
1796 (mii_control |
1797 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1798 if (set_serdes)
1799 bnx2x_set_serdes_access(bp, params->port);
1800
1801 /* wait for the reset to self clear */
1802 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1803 udelay(5);
1804
1805 /* the reset erased the previous bank value */
1806 CL22_RD_OVER_CL45(bp, phy,
1807 MDIO_REG_BANK_COMBO_IEEE0,
1808 MDIO_COMBO_IEEE0_MII_CONTROL,
1809 &mii_control);
1810
1811 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1812 udelay(5);
1813 return 0;
1814 }
1815 }
1816
1817 netdev_err(bp->dev, "Warning: PHY was not initialized,"
1818 " Port %d\n",
1819 params->port);
1820 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1821 return -EINVAL;
1822
1823 }
1824
1825 static void bnx2x_set_swap_lanes(struct link_params *params,
1826 struct bnx2x_phy *phy)
1827 {
1828 struct bnx2x *bp = params->bp;
1829 /*
1830 * Each two bits represents a lane number:
1831 * No swap is 0123 => 0x1b no need to enable the swap
1832 */
1833 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1834
1835 ser_lane = ((params->lane_config &
1836 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1837 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1838 rx_lane_swap = ((params->lane_config &
1839 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1840 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1841 tx_lane_swap = ((params->lane_config &
1842 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1843 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1844
1845 if (rx_lane_swap != 0x1b) {
1846 CL22_WR_OVER_CL45(bp, phy,
1847 MDIO_REG_BANK_XGXS_BLOCK2,
1848 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1849 (rx_lane_swap |
1850 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1851 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1852 } else {
1853 CL22_WR_OVER_CL45(bp, phy,
1854 MDIO_REG_BANK_XGXS_BLOCK2,
1855 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1856 }
1857
1858 if (tx_lane_swap != 0x1b) {
1859 CL22_WR_OVER_CL45(bp, phy,
1860 MDIO_REG_BANK_XGXS_BLOCK2,
1861 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1862 (tx_lane_swap |
1863 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1864 } else {
1865 CL22_WR_OVER_CL45(bp, phy,
1866 MDIO_REG_BANK_XGXS_BLOCK2,
1867 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1868 }
1869 }
1870
1871 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1872 struct link_params *params)
1873 {
1874 struct bnx2x *bp = params->bp;
1875 u16 control2;
1876 CL22_RD_OVER_CL45(bp, phy,
1877 MDIO_REG_BANK_SERDES_DIGITAL,
1878 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1879 &control2);
1880 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1881 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1882 else
1883 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1884 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1885 phy->speed_cap_mask, control2);
1886 CL22_WR_OVER_CL45(bp, phy,
1887 MDIO_REG_BANK_SERDES_DIGITAL,
1888 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1889 control2);
1890
1891 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
1892 (phy->speed_cap_mask &
1893 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
1894 DP(NETIF_MSG_LINK, "XGXS\n");
1895
1896 CL22_WR_OVER_CL45(bp, phy,
1897 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1898 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1899 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1900
1901 CL22_RD_OVER_CL45(bp, phy,
1902 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1903 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1904 &control2);
1905
1906
1907 control2 |=
1908 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1909
1910 CL22_WR_OVER_CL45(bp, phy,
1911 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1912 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1913 control2);
1914
1915 /* Disable parallel detection of HiG */
1916 CL22_WR_OVER_CL45(bp, phy,
1917 MDIO_REG_BANK_XGXS_BLOCK2,
1918 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1919 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1920 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1921 }
1922 }
1923
1924 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1925 struct link_params *params,
1926 struct link_vars *vars,
1927 u8 enable_cl73)
1928 {
1929 struct bnx2x *bp = params->bp;
1930 u16 reg_val;
1931
1932 /* CL37 Autoneg */
1933 CL22_RD_OVER_CL45(bp, phy,
1934 MDIO_REG_BANK_COMBO_IEEE0,
1935 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1936
1937 /* CL37 Autoneg Enabled */
1938 if (vars->line_speed == SPEED_AUTO_NEG)
1939 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1940 else /* CL37 Autoneg Disabled */
1941 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1942 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1943
1944 CL22_WR_OVER_CL45(bp, phy,
1945 MDIO_REG_BANK_COMBO_IEEE0,
1946 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1947
1948 /* Enable/Disable Autodetection */
1949
1950 CL22_RD_OVER_CL45(bp, phy,
1951 MDIO_REG_BANK_SERDES_DIGITAL,
1952 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
1953 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1954 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1955 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
1956 if (vars->line_speed == SPEED_AUTO_NEG)
1957 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1958 else
1959 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1960
1961 CL22_WR_OVER_CL45(bp, phy,
1962 MDIO_REG_BANK_SERDES_DIGITAL,
1963 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1964
1965 /* Enable TetonII and BAM autoneg */
1966 CL22_RD_OVER_CL45(bp, phy,
1967 MDIO_REG_BANK_BAM_NEXT_PAGE,
1968 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1969 &reg_val);
1970 if (vars->line_speed == SPEED_AUTO_NEG) {
1971 /* Enable BAM aneg Mode and TetonII aneg Mode */
1972 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1973 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1974 } else {
1975 /* TetonII and BAM Autoneg Disabled */
1976 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1977 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1978 }
1979 CL22_WR_OVER_CL45(bp, phy,
1980 MDIO_REG_BANK_BAM_NEXT_PAGE,
1981 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1982 reg_val);
1983
1984 if (enable_cl73) {
1985 /* Enable Cl73 FSM status bits */
1986 CL22_WR_OVER_CL45(bp, phy,
1987 MDIO_REG_BANK_CL73_USERB0,
1988 MDIO_CL73_USERB0_CL73_UCTRL,
1989 0xe);
1990
1991 /* Enable BAM Station Manager*/
1992 CL22_WR_OVER_CL45(bp, phy,
1993 MDIO_REG_BANK_CL73_USERB0,
1994 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1995 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1996 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1997 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1998
1999 /* Advertise CL73 link speeds */
2000 CL22_RD_OVER_CL45(bp, phy,
2001 MDIO_REG_BANK_CL73_IEEEB1,
2002 MDIO_CL73_IEEEB1_AN_ADV2,
2003 &reg_val);
2004 if (phy->speed_cap_mask &
2005 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2006 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
2007 if (phy->speed_cap_mask &
2008 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2009 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
2010
2011 CL22_WR_OVER_CL45(bp, phy,
2012 MDIO_REG_BANK_CL73_IEEEB1,
2013 MDIO_CL73_IEEEB1_AN_ADV2,
2014 reg_val);
2015
2016 /* CL73 Autoneg Enabled */
2017 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2018
2019 } else /* CL73 Autoneg Disabled */
2020 reg_val = 0;
2021
2022 CL22_WR_OVER_CL45(bp, phy,
2023 MDIO_REG_BANK_CL73_IEEEB0,
2024 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2025 }
2026
2027 /* program SerDes, forced speed */
2028 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2029 struct link_params *params,
2030 struct link_vars *vars)
2031 {
2032 struct bnx2x *bp = params->bp;
2033 u16 reg_val;
2034
2035 /* program duplex, disable autoneg and sgmii*/
2036 CL22_RD_OVER_CL45(bp, phy,
2037 MDIO_REG_BANK_COMBO_IEEE0,
2038 MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2039 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2040 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2041 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
2042 if (phy->req_duplex == DUPLEX_FULL)
2043 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2044 CL22_WR_OVER_CL45(bp, phy,
2045 MDIO_REG_BANK_COMBO_IEEE0,
2046 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2047
2048 /*
2049 * program speed
2050 * - needed only if the speed is greater than 1G (2.5G or 10G)
2051 */
2052 CL22_RD_OVER_CL45(bp, phy,
2053 MDIO_REG_BANK_SERDES_DIGITAL,
2054 MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2055 /* clearing the speed value before setting the right speed */
2056 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
2057
2058 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
2059 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2060
2061 if (!((vars->line_speed == SPEED_1000) ||
2062 (vars->line_speed == SPEED_100) ||
2063 (vars->line_speed == SPEED_10))) {
2064
2065 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2066 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2067 if (vars->line_speed == SPEED_10000)
2068 reg_val |=
2069 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
2070 if (vars->line_speed == SPEED_13000)
2071 reg_val |=
2072 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
2073 }
2074
2075 CL22_WR_OVER_CL45(bp, phy,
2076 MDIO_REG_BANK_SERDES_DIGITAL,
2077 MDIO_SERDES_DIGITAL_MISC1, reg_val);
2078
2079 }
2080
2081 static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
2082 struct link_params *params)
2083 {
2084 struct bnx2x *bp = params->bp;
2085 u16 val = 0;
2086
2087 /* configure the 48 bits for BAM AN */
2088
2089 /* set extended capabilities */
2090 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
2091 val |= MDIO_OVER_1G_UP1_2_5G;
2092 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2093 val |= MDIO_OVER_1G_UP1_10G;
2094 CL22_WR_OVER_CL45(bp, phy,
2095 MDIO_REG_BANK_OVER_1G,
2096 MDIO_OVER_1G_UP1, val);
2097
2098 CL22_WR_OVER_CL45(bp, phy,
2099 MDIO_REG_BANK_OVER_1G,
2100 MDIO_OVER_1G_UP3, 0x400);
2101 }
2102
2103 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
2104 struct link_params *params, u16 *ieee_fc)
2105 {
2106 struct bnx2x *bp = params->bp;
2107 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
2108 /*
2109 * Resolve pause mode and advertisement.
2110 * Please refer to Table 28B-3 of the 802.3ab-1999 spec
2111 */
2112
2113 switch (phy->req_flow_ctrl) {
2114 case BNX2X_FLOW_CTRL_AUTO:
2115 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
2116 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2117 else
2118 *ieee_fc |=
2119 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2120 break;
2121 case BNX2X_FLOW_CTRL_TX:
2122 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2123 break;
2124
2125 case BNX2X_FLOW_CTRL_RX:
2126 case BNX2X_FLOW_CTRL_BOTH:
2127 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2128 break;
2129
2130 case BNX2X_FLOW_CTRL_NONE:
2131 default:
2132 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
2133 break;
2134 }
2135 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
2136 }
2137
2138 static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
2139 struct link_params *params,
2140 u16 ieee_fc)
2141 {
2142 struct bnx2x *bp = params->bp;
2143 u16 val;
2144 /* for AN, we are always publishing full duplex */
2145
2146 CL22_WR_OVER_CL45(bp, phy,
2147 MDIO_REG_BANK_COMBO_IEEE0,
2148 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
2149 CL22_RD_OVER_CL45(bp, phy,
2150 MDIO_REG_BANK_CL73_IEEEB1,
2151 MDIO_CL73_IEEEB1_AN_ADV1, &val);
2152 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
2153 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
2154 CL22_WR_OVER_CL45(bp, phy,
2155 MDIO_REG_BANK_CL73_IEEEB1,
2156 MDIO_CL73_IEEEB1_AN_ADV1, val);
2157 }
2158
2159 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
2160 struct link_params *params,
2161 u8 enable_cl73)
2162 {
2163 struct bnx2x *bp = params->bp;
2164 u16 mii_control;
2165
2166 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
2167 /* Enable and restart BAM/CL37 aneg */
2168
2169 if (enable_cl73) {
2170 CL22_RD_OVER_CL45(bp, phy,
2171 MDIO_REG_BANK_CL73_IEEEB0,
2172 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2173 &mii_control);
2174
2175 CL22_WR_OVER_CL45(bp, phy,
2176 MDIO_REG_BANK_CL73_IEEEB0,
2177 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2178 (mii_control |
2179 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2180 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
2181 } else {
2182
2183 CL22_RD_OVER_CL45(bp, phy,
2184 MDIO_REG_BANK_COMBO_IEEE0,
2185 MDIO_COMBO_IEEE0_MII_CONTROL,
2186 &mii_control);
2187 DP(NETIF_MSG_LINK,
2188 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
2189 mii_control);
2190 CL22_WR_OVER_CL45(bp, phy,
2191 MDIO_REG_BANK_COMBO_IEEE0,
2192 MDIO_COMBO_IEEE0_MII_CONTROL,
2193 (mii_control |
2194 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2195 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
2196 }
2197 }
2198
2199 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2200 struct link_params *params,
2201 struct link_vars *vars)
2202 {
2203 struct bnx2x *bp = params->bp;
2204 u16 control1;
2205
2206 /* in SGMII mode, the unicore is always slave */
2207
2208 CL22_RD_OVER_CL45(bp, phy,
2209 MDIO_REG_BANK_SERDES_DIGITAL,
2210 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2211 &control1);
2212 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2213 /* set sgmii mode (and not fiber) */
2214 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2215 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2216 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
2217 CL22_WR_OVER_CL45(bp, phy,
2218 MDIO_REG_BANK_SERDES_DIGITAL,
2219 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2220 control1);
2221
2222 /* if forced speed */
2223 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
2224 /* set speed, disable autoneg */
2225 u16 mii_control;
2226
2227 CL22_RD_OVER_CL45(bp, phy,
2228 MDIO_REG_BANK_COMBO_IEEE0,
2229 MDIO_COMBO_IEEE0_MII_CONTROL,
2230 &mii_control);
2231 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2232 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
2233 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
2234
2235 switch (vars->line_speed) {
2236 case SPEED_100:
2237 mii_control |=
2238 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
2239 break;
2240 case SPEED_1000:
2241 mii_control |=
2242 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
2243 break;
2244 case SPEED_10:
2245 /* there is nothing to set for 10M */
2246 break;
2247 default:
2248 /* invalid speed for SGMII */
2249 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2250 vars->line_speed);
2251 break;
2252 }
2253
2254 /* setting the full duplex */
2255 if (phy->req_duplex == DUPLEX_FULL)
2256 mii_control |=
2257 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2258 CL22_WR_OVER_CL45(bp, phy,
2259 MDIO_REG_BANK_COMBO_IEEE0,
2260 MDIO_COMBO_IEEE0_MII_CONTROL,
2261 mii_control);
2262
2263 } else { /* AN mode */
2264 /* enable and restart AN */
2265 bnx2x_restart_autoneg(phy, params, 0);
2266 }
2267 }
2268
2269
2270 /*
2271 * link management
2272 */
2273
2274 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
2275 { /* LD LP */
2276 switch (pause_result) { /* ASYM P ASYM P */
2277 case 0xb: /* 1 0 1 1 */
2278 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
2279 break;
2280
2281 case 0xe: /* 1 1 1 0 */
2282 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
2283 break;
2284
2285 case 0x5: /* 0 1 0 1 */
2286 case 0x7: /* 0 1 1 1 */
2287 case 0xd: /* 1 1 0 1 */
2288 case 0xf: /* 1 1 1 1 */
2289 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
2290 break;
2291
2292 default:
2293 break;
2294 }
2295 if (pause_result & (1<<0))
2296 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
2297 if (pause_result & (1<<1))
2298 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
2299 }
2300
2301 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
2302 struct link_params *params)
2303 {
2304 struct bnx2x *bp = params->bp;
2305 u16 pd_10g, status2_1000x;
2306 if (phy->req_line_speed != SPEED_AUTO_NEG)
2307 return 0;
2308 CL22_RD_OVER_CL45(bp, phy,
2309 MDIO_REG_BANK_SERDES_DIGITAL,
2310 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2311 &status2_1000x);
2312 CL22_RD_OVER_CL45(bp, phy,
2313 MDIO_REG_BANK_SERDES_DIGITAL,
2314 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2315 &status2_1000x);
2316 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
2317 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
2318 params->port);
2319 return 1;
2320 }
2321
2322 CL22_RD_OVER_CL45(bp, phy,
2323 MDIO_REG_BANK_10G_PARALLEL_DETECT,
2324 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
2325 &pd_10g);
2326
2327 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
2328 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
2329 params->port);
2330 return 1;
2331 }
2332 return 0;
2333 }
2334
2335 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
2336 struct link_params *params,
2337 struct link_vars *vars,
2338 u32 gp_status)
2339 {
2340 struct bnx2x *bp = params->bp;
2341 u16 ld_pause; /* local driver */
2342 u16 lp_pause; /* link partner */
2343 u16 pause_result;
2344
2345 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2346
2347 /* resolve from gp_status in case of AN complete and not sgmii */
2348 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
2349 vars->flow_ctrl = phy->req_flow_ctrl;
2350 else if (phy->req_line_speed != SPEED_AUTO_NEG)
2351 vars->flow_ctrl = params->req_fc_auto_adv;
2352 else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
2353 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
2354 if (bnx2x_direct_parallel_detect_used(phy, params)) {
2355 vars->flow_ctrl = params->req_fc_auto_adv;
2356 return;
2357 }
2358 if ((gp_status &
2359 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2360 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
2361 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2362 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
2363
2364 CL22_RD_OVER_CL45(bp, phy,
2365 MDIO_REG_BANK_CL73_IEEEB1,
2366 MDIO_CL73_IEEEB1_AN_ADV1,
2367 &ld_pause);
2368 CL22_RD_OVER_CL45(bp, phy,
2369 MDIO_REG_BANK_CL73_IEEEB1,
2370 MDIO_CL73_IEEEB1_AN_LP_ADV1,
2371 &lp_pause);
2372 pause_result = (ld_pause &
2373 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
2374 >> 8;
2375 pause_result |= (lp_pause &
2376 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
2377 >> 10;
2378 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
2379 pause_result);
2380 } else {
2381 CL22_RD_OVER_CL45(bp, phy,
2382 MDIO_REG_BANK_COMBO_IEEE0,
2383 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
2384 &ld_pause);
2385 CL22_RD_OVER_CL45(bp, phy,
2386 MDIO_REG_BANK_COMBO_IEEE0,
2387 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
2388 &lp_pause);
2389 pause_result = (ld_pause &
2390 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
2391 pause_result |= (lp_pause &
2392 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
2393 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
2394 pause_result);
2395 }
2396 bnx2x_pause_resolve(vars, pause_result);
2397 }
2398 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
2399 }
2400
2401 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2402 struct link_params *params)
2403 {
2404 struct bnx2x *bp = params->bp;
2405 u16 rx_status, ustat_val, cl37_fsm_recieved;
2406 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
2407 /* Step 1: Make sure signal is detected */
2408 CL22_RD_OVER_CL45(bp, phy,
2409 MDIO_REG_BANK_RX0,
2410 MDIO_RX0_RX_STATUS,
2411 &rx_status);
2412 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
2413 (MDIO_RX0_RX_STATUS_SIGDET)) {
2414 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
2415 "rx_status(0x80b0) = 0x%x\n", rx_status);
2416 CL22_WR_OVER_CL45(bp, phy,
2417 MDIO_REG_BANK_CL73_IEEEB0,
2418 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2419 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
2420 return;
2421 }
2422 /* Step 2: Check CL73 state machine */
2423 CL22_RD_OVER_CL45(bp, phy,
2424 MDIO_REG_BANK_CL73_USERB0,
2425 MDIO_CL73_USERB0_CL73_USTAT1,
2426 &ustat_val);
2427 if ((ustat_val &
2428 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2429 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
2430 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2431 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
2432 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
2433 "ustat_val(0x8371) = 0x%x\n", ustat_val);
2434 return;
2435 }
2436 /*
2437 * Step 3: Check CL37 Message Pages received to indicate LP
2438 * supports only CL37
2439 */
2440 CL22_RD_OVER_CL45(bp, phy,
2441 MDIO_REG_BANK_REMOTE_PHY,
2442 MDIO_REMOTE_PHY_MISC_RX_STATUS,
2443 &cl37_fsm_recieved);
2444 if ((cl37_fsm_recieved &
2445 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2446 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
2447 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2448 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
2449 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
2450 "misc_rx_status(0x8330) = 0x%x\n",
2451 cl37_fsm_recieved);
2452 return;
2453 }
2454 /*
2455 * The combined cl37/cl73 fsm state information indicating that
2456 * we are connected to a device which does not support cl73, but
2457 * does support cl37 BAM. In this case we disable cl73 and
2458 * restart cl37 auto-neg
2459 */
2460
2461 /* Disable CL73 */
2462 CL22_WR_OVER_CL45(bp, phy,
2463 MDIO_REG_BANK_CL73_IEEEB0,
2464 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2465 0);
2466 /* Restart CL37 autoneg */
2467 bnx2x_restart_autoneg(phy, params, 0);
2468 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
2469 }
2470
2471 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
2472 struct link_params *params,
2473 struct link_vars *vars,
2474 u32 gp_status)
2475 {
2476 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
2477 vars->link_status |=
2478 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
2479
2480 if (bnx2x_direct_parallel_detect_used(phy, params))
2481 vars->link_status |=
2482 LINK_STATUS_PARALLEL_DETECTION_USED;
2483 }
2484
2485 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
2486 struct link_params *params,
2487 struct link_vars *vars)
2488 {
2489 struct bnx2x *bp = params->bp;
2490 u16 new_line_speed, gp_status;
2491 int rc = 0;
2492
2493 /* Read gp_status */
2494 CL22_RD_OVER_CL45(bp, phy,
2495 MDIO_REG_BANK_GP_STATUS,
2496 MDIO_GP_STATUS_TOP_AN_STATUS1,
2497 &gp_status);
2498
2499 if (phy->req_line_speed == SPEED_AUTO_NEG)
2500 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
2501 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
2502 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
2503 gp_status);
2504
2505 vars->phy_link_up = 1;
2506 vars->link_status |= LINK_STATUS_LINK_UP;
2507
2508 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
2509 vars->duplex = DUPLEX_FULL;
2510 else
2511 vars->duplex = DUPLEX_HALF;
2512
2513 if (SINGLE_MEDIA_DIRECT(params)) {
2514 bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
2515 if (phy->req_line_speed == SPEED_AUTO_NEG)
2516 bnx2x_xgxs_an_resolve(phy, params, vars,
2517 gp_status);
2518 }
2519
2520 switch (gp_status & GP_STATUS_SPEED_MASK) {
2521 case GP_STATUS_10M:
2522 new_line_speed = SPEED_10;
2523 if (vars->duplex == DUPLEX_FULL)
2524 vars->link_status |= LINK_10TFD;
2525 else
2526 vars->link_status |= LINK_10THD;
2527 break;
2528
2529 case GP_STATUS_100M:
2530 new_line_speed = SPEED_100;
2531 if (vars->duplex == DUPLEX_FULL)
2532 vars->link_status |= LINK_100TXFD;
2533 else
2534 vars->link_status |= LINK_100TXHD;
2535 break;
2536
2537 case GP_STATUS_1G:
2538 case GP_STATUS_1G_KX:
2539 new_line_speed = SPEED_1000;
2540 if (vars->duplex == DUPLEX_FULL)
2541 vars->link_status |= LINK_1000TFD;
2542 else
2543 vars->link_status |= LINK_1000THD;
2544 break;
2545
2546 case GP_STATUS_2_5G:
2547 new_line_speed = SPEED_2500;
2548 if (vars->duplex == DUPLEX_FULL)
2549 vars->link_status |= LINK_2500TFD;
2550 else
2551 vars->link_status |= LINK_2500THD;
2552 break;
2553
2554 case GP_STATUS_5G:
2555 case GP_STATUS_6G:
2556 DP(NETIF_MSG_LINK,
2557 "link speed unsupported gp_status 0x%x\n",
2558 gp_status);
2559 return -EINVAL;
2560
2561 case GP_STATUS_10G_KX4:
2562 case GP_STATUS_10G_HIG:
2563 case GP_STATUS_10G_CX4:
2564 new_line_speed = SPEED_10000;
2565 vars->link_status |= LINK_10GTFD;
2566 break;
2567
2568 case GP_STATUS_12G_HIG:
2569 new_line_speed = SPEED_12000;
2570 vars->link_status |= LINK_12GTFD;
2571 break;
2572
2573 case GP_STATUS_12_5G:
2574 new_line_speed = SPEED_12500;
2575 vars->link_status |= LINK_12_5GTFD;
2576 break;
2577
2578 case GP_STATUS_13G:
2579 new_line_speed = SPEED_13000;
2580 vars->link_status |= LINK_13GTFD;
2581 break;
2582
2583 case GP_STATUS_15G:
2584 new_line_speed = SPEED_15000;
2585 vars->link_status |= LINK_15GTFD;
2586 break;
2587
2588 case GP_STATUS_16G:
2589 new_line_speed = SPEED_16000;
2590 vars->link_status |= LINK_16GTFD;
2591 break;
2592
2593 default:
2594 DP(NETIF_MSG_LINK,
2595 "link speed unsupported gp_status 0x%x\n",
2596 gp_status);
2597 return -EINVAL;
2598 }
2599
2600 vars->line_speed = new_line_speed;
2601
2602 } else { /* link_down */
2603 DP(NETIF_MSG_LINK, "phy link down\n");
2604
2605 vars->phy_link_up = 0;
2606
2607 vars->duplex = DUPLEX_FULL;
2608 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2609 vars->mac_type = MAC_TYPE_NONE;
2610
2611 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
2612 SINGLE_MEDIA_DIRECT(params)) {
2613 /* Check signal is detected */
2614 bnx2x_check_fallback_to_cl37(phy, params);
2615 }
2616 }
2617
2618 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x\n",
2619 gp_status, vars->phy_link_up, vars->line_speed);
2620 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
2621 vars->duplex, vars->flow_ctrl, vars->link_status);
2622 return rc;
2623 }
2624
2625 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
2626 {
2627 struct bnx2x *bp = params->bp;
2628 struct bnx2x_phy *phy = &params->phy[INT_PHY];
2629 u16 lp_up2;
2630 u16 tx_driver;
2631 u16 bank;
2632
2633 /* read precomp */
2634 CL22_RD_OVER_CL45(bp, phy,
2635 MDIO_REG_BANK_OVER_1G,
2636 MDIO_OVER_1G_LP_UP2, &lp_up2);
2637
2638 /* bits [10:7] at lp_up2, positioned at [15:12] */
2639 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2640 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2641 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2642
2643 if (lp_up2 == 0)
2644 return;
2645
2646 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2647 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
2648 CL22_RD_OVER_CL45(bp, phy,
2649 bank,
2650 MDIO_TX0_TX_DRIVER, &tx_driver);
2651
2652 /* replace tx_driver bits [15:12] */
2653 if (lp_up2 !=
2654 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2655 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2656 tx_driver |= lp_up2;
2657 CL22_WR_OVER_CL45(bp, phy,
2658 bank,
2659 MDIO_TX0_TX_DRIVER, tx_driver);
2660 }
2661 }
2662 }
2663
2664 static int bnx2x_emac_program(struct link_params *params,
2665 struct link_vars *vars)
2666 {
2667 struct bnx2x *bp = params->bp;
2668 u8 port = params->port;
2669 u16 mode = 0;
2670
2671 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2672 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
2673 EMAC_REG_EMAC_MODE,
2674 (EMAC_MODE_25G_MODE |
2675 EMAC_MODE_PORT_MII_10M |
2676 EMAC_MODE_HALF_DUPLEX));
2677 switch (vars->line_speed) {
2678 case SPEED_10:
2679 mode |= EMAC_MODE_PORT_MII_10M;
2680 break;
2681
2682 case SPEED_100:
2683 mode |= EMAC_MODE_PORT_MII;
2684 break;
2685
2686 case SPEED_1000:
2687 mode |= EMAC_MODE_PORT_GMII;
2688 break;
2689
2690 case SPEED_2500:
2691 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2692 break;
2693
2694 default:
2695 /* 10G not valid for EMAC */
2696 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2697 vars->line_speed);
2698 return -EINVAL;
2699 }
2700
2701 if (vars->duplex == DUPLEX_HALF)
2702 mode |= EMAC_MODE_HALF_DUPLEX;
2703 bnx2x_bits_en(bp,
2704 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2705 mode);
2706
2707 bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
2708 return 0;
2709 }
2710
2711 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
2712 struct link_params *params)
2713 {
2714
2715 u16 bank, i = 0;
2716 struct bnx2x *bp = params->bp;
2717
2718 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
2719 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
2720 CL22_WR_OVER_CL45(bp, phy,
2721 bank,
2722 MDIO_RX0_RX_EQ_BOOST,
2723 phy->rx_preemphasis[i]);
2724 }
2725
2726 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
2727 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
2728 CL22_WR_OVER_CL45(bp, phy,
2729 bank,
2730 MDIO_TX0_TX_DRIVER,
2731 phy->tx_preemphasis[i]);
2732 }
2733 }
2734
2735 static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2736 struct link_params *params,
2737 struct link_vars *vars)
2738 {
2739 struct bnx2x *bp = params->bp;
2740 u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
2741 (params->loopback_mode == LOOPBACK_XGXS));
2742 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2743 if (SINGLE_MEDIA_DIRECT(params) &&
2744 (params->feature_config_flags &
2745 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2746 bnx2x_set_preemphasis(phy, params);
2747
2748 /* forced speed requested? */
2749 if (vars->line_speed != SPEED_AUTO_NEG ||
2750 (SINGLE_MEDIA_DIRECT(params) &&
2751 params->loopback_mode == LOOPBACK_EXT)) {
2752 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2753
2754 /* disable autoneg */
2755 bnx2x_set_autoneg(phy, params, vars, 0);
2756
2757 /* program speed and duplex */
2758 bnx2x_program_serdes(phy, params, vars);
2759
2760 } else { /* AN_mode */
2761 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2762
2763 /* AN enabled */
2764 bnx2x_set_brcm_cl37_advertisment(phy, params);
2765
2766 /* program duplex & pause advertisement (for aneg) */
2767 bnx2x_set_ieee_aneg_advertisment(phy, params,
2768 vars->ieee_fc);
2769
2770 /* enable autoneg */
2771 bnx2x_set_autoneg(phy, params, vars, enable_cl73);
2772
2773 /* enable and restart AN */
2774 bnx2x_restart_autoneg(phy, params, enable_cl73);
2775 }
2776
2777 } else { /* SGMII mode */
2778 DP(NETIF_MSG_LINK, "SGMII\n");
2779
2780 bnx2x_initialize_sgmii_process(phy, params, vars);
2781 }
2782 }
2783
2784 static int bnx2x_init_serdes(struct bnx2x_phy *phy,
2785 struct link_params *params,
2786 struct link_vars *vars)
2787 {
2788 int rc;
2789 vars->phy_flags |= PHY_SGMII_FLAG;
2790 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2791 bnx2x_set_aer_mmd_serdes(params->bp, phy);
2792 rc = bnx2x_reset_unicore(params, phy, 1);
2793 /* reset the SerDes and wait for reset bit return low */
2794 if (rc != 0)
2795 return rc;
2796 bnx2x_set_aer_mmd_serdes(params->bp, phy);
2797
2798 return rc;
2799 }
2800
2801 static int bnx2x_init_xgxs(struct bnx2x_phy *phy,
2802 struct link_params *params,
2803 struct link_vars *vars)
2804 {
2805 int rc;
2806 vars->phy_flags = PHY_XGXS_FLAG;
2807 if ((phy->req_line_speed &&
2808 ((phy->req_line_speed == SPEED_100) ||
2809 (phy->req_line_speed == SPEED_10))) ||
2810 (!phy->req_line_speed &&
2811 (phy->speed_cap_mask >=
2812 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2813 (phy->speed_cap_mask <
2814 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2815 ))
2816 vars->phy_flags |= PHY_SGMII_FLAG;
2817 else
2818 vars->phy_flags &= ~PHY_SGMII_FLAG;
2819
2820 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2821 bnx2x_set_aer_mmd_xgxs(params, phy);
2822 bnx2x_set_master_ln(params, phy);
2823
2824 rc = bnx2x_reset_unicore(params, phy, 0);
2825 /* reset the SerDes and wait for reset bit return low */
2826 if (rc != 0)
2827 return rc;
2828
2829 bnx2x_set_aer_mmd_xgxs(params, phy);
2830
2831 /* setting the masterLn_def again after the reset */
2832 bnx2x_set_master_ln(params, phy);
2833 bnx2x_set_swap_lanes(params, phy);
2834
2835 return rc;
2836 }
2837
2838 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
2839 struct bnx2x_phy *phy,
2840 struct link_params *params)
2841 {
2842 u16 cnt, ctrl;
2843 /* Wait for soft reset to get cleared up to 1 sec */
2844 for (cnt = 0; cnt < 1000; cnt++) {
2845 bnx2x_cl45_read(bp, phy,
2846 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
2847 if (!(ctrl & (1<<15)))
2848 break;
2849 msleep(1);
2850 }
2851
2852 if (cnt == 1000)
2853 netdev_err(bp->dev, "Warning: PHY was not initialized,"
2854 " Port %d\n",
2855 params->port);
2856 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
2857 return cnt;
2858 }
2859
2860 static void bnx2x_link_int_enable(struct link_params *params)
2861 {
2862 u8 port = params->port;
2863 u32 mask;
2864 struct bnx2x *bp = params->bp;
2865
2866 /* Setting the status to report on link up for either XGXS or SerDes */
2867 if (params->switch_cfg == SWITCH_CFG_10G) {
2868 mask = (NIG_MASK_XGXS0_LINK10G |
2869 NIG_MASK_XGXS0_LINK_STATUS);
2870 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
2871 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2872 params->phy[INT_PHY].type !=
2873 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
2874 mask |= NIG_MASK_MI_INT;
2875 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2876 }
2877
2878 } else { /* SerDes */
2879 mask = NIG_MASK_SERDES0_LINK_STATUS;
2880 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
2881 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2882 params->phy[INT_PHY].type !=
2883 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
2884 mask |= NIG_MASK_MI_INT;
2885 DP(NETIF_MSG_LINK, "enabled external phy int\n");
2886 }
2887 }
2888 bnx2x_bits_en(bp,
2889 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2890 mask);
2891
2892 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
2893 (params->switch_cfg == SWITCH_CFG_10G),
2894 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
2895 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
2896 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
2897 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2898 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
2899 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
2900 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2901 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
2902 }
2903
2904 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
2905 u8 exp_mi_int)
2906 {
2907 u32 latch_status = 0;
2908
2909 /*
2910 * Disable the MI INT ( external phy int ) by writing 1 to the
2911 * status register. Link down indication is high-active-signal,
2912 * so in this case we need to write the status to clear the XOR
2913 */
2914 /* Read Latched signals */
2915 latch_status = REG_RD(bp,
2916 NIG_REG_LATCH_STATUS_0 + port*8);
2917 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
2918 /* Handle only those with latched-signal=up.*/
2919 if (exp_mi_int)
2920 bnx2x_bits_en(bp,
2921 NIG_REG_STATUS_INTERRUPT_PORT0
2922 + port*4,
2923 NIG_STATUS_EMAC0_MI_INT);
2924 else
2925 bnx2x_bits_dis(bp,
2926 NIG_REG_STATUS_INTERRUPT_PORT0
2927 + port*4,
2928 NIG_STATUS_EMAC0_MI_INT);
2929
2930 if (latch_status & 1) {
2931
2932 /* For all latched-signal=up : Re-Arm Latch signals */
2933 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
2934 (latch_status & 0xfffe) | (latch_status & 1));
2935 }
2936 /* For all latched-signal=up,Write original_signal to status */
2937 }
2938
2939 static void bnx2x_link_int_ack(struct link_params *params,
2940 struct link_vars *vars, u8 is_10g)
2941 {
2942 struct bnx2x *bp = params->bp;
2943 u8 port = params->port;
2944
2945 /*
2946 * First reset all status we assume only one line will be
2947 * change at a time
2948 */
2949 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2950 (NIG_STATUS_XGXS0_LINK10G |
2951 NIG_STATUS_XGXS0_LINK_STATUS |
2952 NIG_STATUS_SERDES0_LINK_STATUS));
2953 if (vars->phy_link_up) {
2954 if (is_10g) {
2955 /*
2956 * Disable the 10G link interrupt by writing 1 to the
2957 * status register
2958 */
2959 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
2960 bnx2x_bits_en(bp,
2961 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2962 NIG_STATUS_XGXS0_LINK10G);
2963
2964 } else if (params->switch_cfg == SWITCH_CFG_10G) {
2965 /*
2966 * Disable the link interrupt by writing 1 to the
2967 * relevant lane in the status register
2968 */
2969 u32 ser_lane = ((params->lane_config &
2970 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2971 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2972
2973 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
2974 vars->line_speed);
2975 bnx2x_bits_en(bp,
2976 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2977 ((1 << ser_lane) <<
2978 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
2979
2980 } else { /* SerDes */
2981 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
2982 /*
2983 * Disable the link interrupt by writing 1 to the status
2984 * register
2985 */
2986 bnx2x_bits_en(bp,
2987 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2988 NIG_STATUS_SERDES0_LINK_STATUS);
2989 }
2990
2991 }
2992 }
2993
2994 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
2995 {
2996 u8 *str_ptr = str;
2997 u32 mask = 0xf0000000;
2998 u8 shift = 8*4;
2999 u8 digit;
3000 u8 remove_leading_zeros = 1;
3001 if (*len < 10) {
3002 /* Need more than 10chars for this format */
3003 *str_ptr = '\0';
3004 (*len)--;
3005 return -EINVAL;
3006 }
3007 while (shift > 0) {
3008
3009 shift -= 4;
3010 digit = ((num & mask) >> shift);
3011 if (digit == 0 && remove_leading_zeros) {
3012 mask = mask >> 4;
3013 continue;
3014 } else if (digit < 0xa)
3015 *str_ptr = digit + '0';
3016 else
3017 *str_ptr = digit - 0xa + 'a';
3018 remove_leading_zeros = 0;
3019 str_ptr++;
3020 (*len)--;
3021 mask = mask >> 4;
3022 if (shift == 4*4) {
3023 *str_ptr = '.';
3024 str_ptr++;
3025 (*len)--;
3026 remove_leading_zeros = 1;
3027 }
3028 }
3029 return 0;
3030 }
3031
3032
3033 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
3034 {
3035 str[0] = '\0';
3036 (*len)--;
3037 return 0;
3038 }
3039
3040 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3041 u8 *version, u16 len)
3042 {
3043 struct bnx2x *bp;
3044 u32 spirom_ver = 0;
3045 int status = 0;
3046 u8 *ver_p = version;
3047 u16 remain_len = len;
3048 if (version == NULL || params == NULL)
3049 return -EINVAL;
3050 bp = params->bp;
3051
3052 /* Extract first external phy*/
3053 version[0] = '\0';
3054 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
3055
3056 if (params->phy[EXT_PHY1].format_fw_ver) {
3057 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
3058 ver_p,
3059 &remain_len);
3060 ver_p += (len - remain_len);
3061 }
3062 if ((params->num_phys == MAX_PHYS) &&
3063 (params->phy[EXT_PHY2].ver_addr != 0)) {
3064 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
3065 if (params->phy[EXT_PHY2].format_fw_ver) {
3066 *ver_p = '/';
3067 ver_p++;
3068 remain_len--;
3069 status |= params->phy[EXT_PHY2].format_fw_ver(
3070 spirom_ver,
3071 ver_p,
3072 &remain_len);
3073 ver_p = version + (len - remain_len);
3074 }
3075 }
3076 *ver_p = '\0';
3077 return status;
3078 }
3079
3080 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
3081 struct link_params *params)
3082 {
3083 u8 port = params->port;
3084 struct bnx2x *bp = params->bp;
3085
3086 if (phy->req_line_speed != SPEED_1000) {
3087 u32 md_devad;
3088
3089 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3090
3091 /* change the uni_phy_addr in the nig */
3092 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
3093 port*0x18));
3094
3095 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3096
3097 bnx2x_cl45_write(bp, phy,
3098 5,
3099 (MDIO_REG_BANK_AER_BLOCK +
3100 (MDIO_AER_BLOCK_AER_REG & 0xf)),
3101 0x2800);
3102
3103 bnx2x_cl45_write(bp, phy,
3104 5,
3105 (MDIO_REG_BANK_CL73_IEEEB0 +
3106 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3107 0x6041);
3108 msleep(200);
3109 /* set aer mmd back */
3110 bnx2x_set_aer_mmd_xgxs(params, phy);
3111
3112 /* and md_devad */
3113 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, md_devad);
3114 } else {
3115 u16 mii_ctrl;
3116 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3117 bnx2x_cl45_read(bp, phy, 5,
3118 (MDIO_REG_BANK_COMBO_IEEE0 +
3119 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3120 &mii_ctrl);
3121 bnx2x_cl45_write(bp, phy, 5,
3122 (MDIO_REG_BANK_COMBO_IEEE0 +
3123 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3124 mii_ctrl |
3125 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
3126 }
3127 }
3128
3129 int bnx2x_set_led(struct link_params *params,
3130 struct link_vars *vars, u8 mode, u32 speed)
3131 {
3132 u8 port = params->port;
3133 u16 hw_led_mode = params->hw_led_mode;
3134 int rc = 0;
3135 u8 phy_idx;
3136 u32 tmp;
3137 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3138 struct bnx2x *bp = params->bp;
3139 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3140 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3141 speed, hw_led_mode);
3142 /* In case */
3143 for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
3144 if (params->phy[phy_idx].set_link_led) {
3145 params->phy[phy_idx].set_link_led(
3146 &params->phy[phy_idx], params, mode);
3147 }
3148 }
3149
3150 switch (mode) {
3151 case LED_MODE_FRONT_PANEL_OFF:
3152 case LED_MODE_OFF:
3153 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3154 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3155 SHARED_HW_CFG_LED_MAC1);
3156
3157 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3158 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
3159 break;
3160
3161 case LED_MODE_OPER:
3162 /*
3163 * For all other phys, OPER mode is same as ON, so in case
3164 * link is down, do nothing
3165 */
3166 if (!vars->link_up)
3167 break;
3168 case LED_MODE_ON:
3169 if (((params->phy[EXT_PHY1].type ==
3170 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
3171 (params->phy[EXT_PHY1].type ==
3172 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
3173 CHIP_IS_E2(bp) && params->num_phys == 2) {
3174 /*
3175 * This is a work-around for E2+8727 Configurations
3176 */
3177 if (mode == LED_MODE_ON ||
3178 speed == SPEED_10000){
3179 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3180 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3181
3182 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3183 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3184 (tmp | EMAC_LED_OVERRIDE));
3185 return rc;
3186 }
3187 } else if (SINGLE_MEDIA_DIRECT(params)) {
3188 /*
3189 * This is a work-around for HW issue found when link
3190 * is up in CL73
3191 */
3192 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3193 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3194 } else {
3195 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
3196 }
3197
3198 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
3199 /* Set blinking rate to ~15.9Hz */
3200 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
3201 LED_BLINK_RATE_VAL);
3202 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3203 port*4, 1);
3204 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3205 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
3206
3207 if (CHIP_IS_E1(bp) &&
3208 ((speed == SPEED_2500) ||
3209 (speed == SPEED_1000) ||
3210 (speed == SPEED_100) ||
3211 (speed == SPEED_10))) {
3212 /*
3213 * On Everest 1 Ax chip versions for speeds less than
3214 * 10G LED scheme is different
3215 */
3216 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3217 + port*4, 1);
3218 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
3219 port*4, 0);
3220 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
3221 port*4, 1);
3222 }
3223 break;
3224
3225 default:
3226 rc = -EINVAL;
3227 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3228 mode);
3229 break;
3230 }
3231 return rc;
3232
3233 }
3234
3235 /*
3236 * This function comes to reflect the actual link state read DIRECTLY from the
3237 * HW
3238 */
3239 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
3240 u8 is_serdes)
3241 {
3242 struct bnx2x *bp = params->bp;
3243 u16 gp_status = 0, phy_index = 0;
3244 u8 ext_phy_link_up = 0, serdes_phy_type;
3245 struct link_vars temp_vars;
3246
3247 CL22_RD_OVER_CL45(bp, &params->phy[INT_PHY],
3248 MDIO_REG_BANK_GP_STATUS,
3249 MDIO_GP_STATUS_TOP_AN_STATUS1,
3250 &gp_status);
3251 /* link is up only if both local phy and external phy are up */
3252 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
3253 return -ESRCH;
3254
3255 switch (params->num_phys) {
3256 case 1:
3257 /* No external PHY */
3258 return 0;
3259 case 2:
3260 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
3261 &params->phy[EXT_PHY1],
3262 params, &temp_vars);
3263 break;
3264 case 3: /* Dual Media */
3265 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3266 phy_index++) {
3267 serdes_phy_type = ((params->phy[phy_index].media_type ==
3268 ETH_PHY_SFP_FIBER) ||
3269 (params->phy[phy_index].media_type ==
3270 ETH_PHY_XFP_FIBER) ||
3271 (params->phy[phy_index].media_type ==
3272 ETH_PHY_DA_TWINAX));
3273
3274 if (is_serdes != serdes_phy_type)
3275 continue;
3276 if (params->phy[phy_index].read_status) {
3277 ext_phy_link_up |=
3278 params->phy[phy_index].read_status(
3279 &params->phy[phy_index],
3280 params, &temp_vars);
3281 }
3282 }
3283 break;
3284 }
3285 if (ext_phy_link_up)
3286 return 0;
3287 return -ESRCH;
3288 }
3289
3290 static int bnx2x_link_initialize(struct link_params *params,
3291 struct link_vars *vars)
3292 {
3293 int rc = 0;
3294 u8 phy_index, non_ext_phy;
3295 struct bnx2x *bp = params->bp;
3296 /*
3297 * In case of external phy existence, the line speed would be the
3298 * line speed linked up by the external phy. In case it is direct
3299 * only, then the line_speed during initialization will be
3300 * equal to the req_line_speed
3301 */
3302 vars->line_speed = params->phy[INT_PHY].req_line_speed;
3303
3304 /*
3305 * Initialize the internal phy in case this is a direct board
3306 * (no external phys), or this board has external phy which requires
3307 * to first.
3308 */
3309
3310 if (params->phy[INT_PHY].config_init)
3311 params->phy[INT_PHY].config_init(
3312 &params->phy[INT_PHY],
3313 params, vars);
3314
3315 /* init ext phy and enable link state int */
3316 non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
3317 (params->loopback_mode == LOOPBACK_XGXS));
3318
3319 if (non_ext_phy ||
3320 (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
3321 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
3322 struct bnx2x_phy *phy = &params->phy[INT_PHY];
3323 if (vars->line_speed == SPEED_AUTO_NEG)
3324 bnx2x_set_parallel_detection(phy, params);
3325 bnx2x_init_internal_phy(phy, params, vars);
3326 }
3327
3328 /* Init external phy*/
3329 if (!non_ext_phy)
3330 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3331 phy_index++) {
3332 /*
3333 * No need to initialize second phy in case of first
3334 * phy only selection. In case of second phy, we do
3335 * need to initialize the first phy, since they are
3336 * connected.
3337 */
3338 if (phy_index == EXT_PHY2 &&
3339 (bnx2x_phy_selection(params) ==
3340 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
3341 DP(NETIF_MSG_LINK, "Ignoring second phy\n");
3342 continue;
3343 }
3344 params->phy[phy_index].config_init(
3345 &params->phy[phy_index],
3346 params, vars);
3347 }
3348
3349 /* Reset the interrupt indication after phy was initialized */
3350 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
3351 params->port*4,
3352 (NIG_STATUS_XGXS0_LINK10G |
3353 NIG_STATUS_XGXS0_LINK_STATUS |
3354 NIG_STATUS_SERDES0_LINK_STATUS |
3355 NIG_MASK_MI_INT));
3356 return rc;
3357 }
3358
3359 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
3360 struct link_params *params)
3361 {
3362 /* reset the SerDes/XGXS */
3363 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
3364 (0x1ff << (params->port*16)));
3365 }
3366
3367 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
3368 struct link_params *params)
3369 {
3370 struct bnx2x *bp = params->bp;
3371 u8 gpio_port;
3372 /* HW reset */
3373 if (CHIP_IS_E2(bp))
3374 gpio_port = BP_PATH(bp);
3375 else
3376 gpio_port = params->port;
3377 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3378 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3379 gpio_port);
3380 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3381 MISC_REGISTERS_GPIO_OUTPUT_LOW,
3382 gpio_port);
3383 DP(NETIF_MSG_LINK, "reset external PHY\n");
3384 }
3385
3386 static int bnx2x_update_link_down(struct link_params *params,
3387 struct link_vars *vars)
3388 {
3389 struct bnx2x *bp = params->bp;
3390 u8 port = params->port;
3391
3392 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
3393 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
3394
3395 /* indicate no mac active */
3396 vars->mac_type = MAC_TYPE_NONE;
3397
3398 /* update shared memory */
3399 vars->link_status = 0;
3400 vars->line_speed = 0;
3401 bnx2x_update_mng(params, vars->link_status);
3402
3403 /* activate nig drain */
3404 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3405
3406 /* disable emac */
3407 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3408
3409 msleep(10);
3410
3411 /* reset BigMac */
3412 bnx2x_bmac_rx_disable(bp, params->port);
3413 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3414 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3415 return 0;
3416 }
3417
3418 static int bnx2x_update_link_up(struct link_params *params,
3419 struct link_vars *vars,
3420 u8 link_10g)
3421 {
3422 struct bnx2x *bp = params->bp;
3423 u8 port = params->port;
3424 int rc = 0;
3425
3426 vars->link_status |= LINK_STATUS_LINK_UP;
3427
3428 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
3429 vars->link_status |=
3430 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
3431
3432 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
3433 vars->link_status |=
3434 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
3435
3436 if (link_10g) {
3437 bnx2x_bmac_enable(params, vars, 0);
3438 bnx2x_set_led(params, vars,
3439 LED_MODE_OPER, SPEED_10000);
3440 } else {
3441 rc = bnx2x_emac_program(params, vars);
3442
3443 bnx2x_emac_enable(params, vars, 0);
3444
3445 /* AN complete? */
3446 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
3447 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
3448 SINGLE_MEDIA_DIRECT(params))
3449 bnx2x_set_gmii_tx_driver(params);
3450 }
3451
3452 /* PBF - link up */
3453 if (!(CHIP_IS_E2(bp)))
3454 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
3455 vars->line_speed);
3456
3457 /* disable drain */
3458 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
3459
3460 /* update shared memory */
3461 bnx2x_update_mng(params, vars->link_status);
3462 msleep(20);
3463 return rc;
3464 }
3465 /*
3466 * The bnx2x_link_update function should be called upon link
3467 * interrupt.
3468 * Link is considered up as follows:
3469 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
3470 * to be up
3471 * - SINGLE_MEDIA - The link between the 577xx and the external
3472 * phy (XGXS) need to up as well as the external link of the
3473 * phy (PHY_EXT1)
3474 * - DUAL_MEDIA - The link between the 577xx and the first
3475 * external phy needs to be up, and at least one of the 2
3476 * external phy link must be up.
3477 */
3478 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
3479 {
3480 struct bnx2x *bp = params->bp;
3481 struct link_vars phy_vars[MAX_PHYS];
3482 u8 port = params->port;
3483 u8 link_10g, phy_index;
3484 u8 ext_phy_link_up = 0, cur_link_up;
3485 int rc = 0;
3486 u8 is_mi_int = 0;
3487 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
3488 u8 active_external_phy = INT_PHY;
3489 vars->link_status = 0;
3490 for (phy_index = INT_PHY; phy_index < params->num_phys;
3491 phy_index++) {
3492 phy_vars[phy_index].flow_ctrl = 0;
3493 phy_vars[phy_index].link_status = 0;
3494 phy_vars[phy_index].line_speed = 0;
3495 phy_vars[phy_index].duplex = DUPLEX_FULL;
3496 phy_vars[phy_index].phy_link_up = 0;
3497 phy_vars[phy_index].link_up = 0;
3498 phy_vars[phy_index].fault_detected = 0;
3499 }
3500
3501 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
3502 port, (vars->phy_flags & PHY_XGXS_FLAG),
3503 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
3504
3505 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
3506 port*0x18) > 0);
3507 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
3508 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3509 is_mi_int,
3510 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
3511
3512 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3513 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3514 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3515
3516 /* disable emac */
3517 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3518
3519 /*
3520 * Step 1:
3521 * Check external link change only for external phys, and apply
3522 * priority selection between them in case the link on both phys
3523 * is up. Note that the instead of the common vars, a temporary
3524 * vars argument is used since each phy may have different link/
3525 * speed/duplex result
3526 */
3527 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3528 phy_index++) {
3529 struct bnx2x_phy *phy = &params->phy[phy_index];
3530 if (!phy->read_status)
3531 continue;
3532 /* Read link status and params of this ext phy */
3533 cur_link_up = phy->read_status(phy, params,
3534 &phy_vars[phy_index]);
3535 if (cur_link_up) {
3536 DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
3537 phy_index);
3538 } else {
3539 DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
3540 phy_index);
3541 continue;
3542 }
3543
3544 if (!ext_phy_link_up) {
3545 ext_phy_link_up = 1;
3546 active_external_phy = phy_index;
3547 } else {
3548 switch (bnx2x_phy_selection(params)) {
3549 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
3550 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
3551 /*
3552 * In this option, the first PHY makes sure to pass the
3553 * traffic through itself only.
3554 * Its not clear how to reset the link on the second phy
3555 */
3556 active_external_phy = EXT_PHY1;
3557 break;
3558 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
3559 /*
3560 * In this option, the first PHY makes sure to pass the
3561 * traffic through the second PHY.
3562 */
3563 active_external_phy = EXT_PHY2;
3564 break;
3565 default:
3566 /*
3567 * Link indication on both PHYs with the following cases
3568 * is invalid:
3569 * - FIRST_PHY means that second phy wasn't initialized,
3570 * hence its link is expected to be down
3571 * - SECOND_PHY means that first phy should not be able
3572 * to link up by itself (using configuration)
3573 * - DEFAULT should be overriden during initialiazation
3574 */
3575 DP(NETIF_MSG_LINK, "Invalid link indication"
3576 "mpc=0x%x. DISABLING LINK !!!\n",
3577 params->multi_phy_config);
3578 ext_phy_link_up = 0;
3579 break;
3580 }
3581 }
3582 }
3583 prev_line_speed = vars->line_speed;
3584 /*
3585 * Step 2:
3586 * Read the status of the internal phy. In case of
3587 * DIRECT_SINGLE_MEDIA board, this link is the external link,
3588 * otherwise this is the link between the 577xx and the first
3589 * external phy
3590 */
3591 if (params->phy[INT_PHY].read_status)
3592 params->phy[INT_PHY].read_status(
3593 &params->phy[INT_PHY],
3594 params, vars);
3595 /*
3596 * The INT_PHY flow control reside in the vars. This include the
3597 * case where the speed or flow control are not set to AUTO.
3598 * Otherwise, the active external phy flow control result is set
3599 * to the vars. The ext_phy_line_speed is needed to check if the
3600 * speed is different between the internal phy and external phy.
3601 * This case may be result of intermediate link speed change.
3602 */
3603 if (active_external_phy > INT_PHY) {
3604 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
3605 /*
3606 * Link speed is taken from the XGXS. AN and FC result from
3607 * the external phy.
3608 */
3609 vars->link_status |= phy_vars[active_external_phy].link_status;
3610
3611 /*
3612 * if active_external_phy is first PHY and link is up - disable
3613 * disable TX on second external PHY
3614 */
3615 if (active_external_phy == EXT_PHY1) {
3616 if (params->phy[EXT_PHY2].phy_specific_func) {
3617 DP(NETIF_MSG_LINK, "Disabling TX on"
3618 " EXT_PHY2\n");
3619 params->phy[EXT_PHY2].phy_specific_func(
3620 &params->phy[EXT_PHY2],
3621 params, DISABLE_TX);
3622 }
3623 }
3624
3625 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
3626 vars->duplex = phy_vars[active_external_phy].duplex;
3627 if (params->phy[active_external_phy].supported &
3628 SUPPORTED_FIBRE)
3629 vars->link_status |= LINK_STATUS_SERDES_LINK;
3630 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
3631 active_external_phy);
3632 }
3633
3634 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3635 phy_index++) {
3636 if (params->phy[phy_index].flags &
3637 FLAGS_REARM_LATCH_SIGNAL) {
3638 bnx2x_rearm_latch_signal(bp, port,
3639 phy_index ==
3640 active_external_phy);
3641 break;
3642 }
3643 }
3644 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
3645 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
3646 vars->link_status, ext_phy_line_speed);
3647 /*
3648 * Upon link speed change set the NIG into drain mode. Comes to
3649 * deals with possible FIFO glitch due to clk change when speed
3650 * is decreased without link down indicator
3651 */
3652
3653 if (vars->phy_link_up) {
3654 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
3655 (ext_phy_line_speed != vars->line_speed)) {
3656 DP(NETIF_MSG_LINK, "Internal link speed %d is"
3657 " different than the external"
3658 " link speed %d\n", vars->line_speed,
3659 ext_phy_line_speed);
3660 vars->phy_link_up = 0;
3661 } else if (prev_line_speed != vars->line_speed) {
3662 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
3663 0);
3664 msleep(1);
3665 }
3666 }
3667
3668 /* anything 10 and over uses the bmac */
3669 link_10g = ((vars->line_speed == SPEED_10000) ||
3670 (vars->line_speed == SPEED_12000) ||
3671 (vars->line_speed == SPEED_12500) ||
3672 (vars->line_speed == SPEED_13000) ||
3673 (vars->line_speed == SPEED_15000) ||
3674 (vars->line_speed == SPEED_16000));
3675
3676 bnx2x_link_int_ack(params, vars, link_10g);
3677
3678 /*
3679 * In case external phy link is up, and internal link is down
3680 * (not initialized yet probably after link initialization, it
3681 * needs to be initialized.
3682 * Note that after link down-up as result of cable plug, the xgxs
3683 * link would probably become up again without the need
3684 * initialize it
3685 */
3686 if (!(SINGLE_MEDIA_DIRECT(params))) {
3687 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
3688 " init_preceding = %d\n", ext_phy_link_up,
3689 vars->phy_link_up,
3690 params->phy[EXT_PHY1].flags &
3691 FLAGS_INIT_XGXS_FIRST);
3692 if (!(params->phy[EXT_PHY1].flags &
3693 FLAGS_INIT_XGXS_FIRST)
3694 && ext_phy_link_up && !vars->phy_link_up) {
3695 vars->line_speed = ext_phy_line_speed;
3696 if (vars->line_speed < SPEED_1000)
3697 vars->phy_flags |= PHY_SGMII_FLAG;
3698 else
3699 vars->phy_flags &= ~PHY_SGMII_FLAG;
3700 bnx2x_init_internal_phy(&params->phy[INT_PHY],
3701 params,
3702 vars);
3703 }
3704 }
3705 /*
3706 * Link is up only if both local phy and external phy (in case of
3707 * non-direct board) are up
3708 */
3709 vars->link_up = (vars->phy_link_up &&
3710 (ext_phy_link_up ||
3711 SINGLE_MEDIA_DIRECT(params)) &&
3712 (phy_vars[active_external_phy].fault_detected == 0));
3713
3714 if (vars->link_up)
3715 rc = bnx2x_update_link_up(params, vars, link_10g);
3716 else
3717 rc = bnx2x_update_link_down(params, vars);
3718
3719 return rc;
3720 }
3721
3722
3723 /*****************************************************************************/
3724 /* External Phy section */
3725 /*****************************************************************************/
3726 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
3727 {
3728 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3729 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
3730 msleep(1);
3731 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3732 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
3733 }
3734
3735 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
3736 u32 spirom_ver, u32 ver_addr)
3737 {
3738 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
3739 (u16)(spirom_ver>>16), (u16)spirom_ver, port);
3740
3741 if (ver_addr)
3742 REG_WR(bp, ver_addr, spirom_ver);
3743 }
3744
3745 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3746 struct bnx2x_phy *phy,
3747 u8 port)
3748 {
3749 u16 fw_ver1, fw_ver2;
3750
3751 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3752 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3753 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3754 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
3755 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3756 phy->ver_addr);
3757 }
3758
3759 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3760 struct bnx2x_phy *phy,
3761 struct link_vars *vars)
3762 {
3763 u16 val;
3764 struct bnx2x *bp = params->bp;
3765 /* read modify write pause advertizing */
3766 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3767
3768 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3769
3770 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3771 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3772 if ((vars->ieee_fc &
3773 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3774 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3775 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3776 }
3777 if ((vars->ieee_fc &
3778 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3779 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3780 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3781 }
3782 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3783 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3784 }
3785
3786 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3787 struct link_params *params,
3788 struct link_vars *vars)
3789 {
3790 struct bnx2x *bp = params->bp;
3791 u16 ld_pause; /* local */
3792 u16 lp_pause; /* link partner */
3793 u16 pause_result;
3794 u8 ret = 0;
3795 /* read twice */
3796
3797 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3798
3799 if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3800 vars->flow_ctrl = phy->req_flow_ctrl;
3801 else if (phy->req_line_speed != SPEED_AUTO_NEG)
3802 vars->flow_ctrl = params->req_fc_auto_adv;
3803 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3804 ret = 1;
3805 bnx2x_cl45_read(bp, phy,
3806 MDIO_AN_DEVAD,
3807 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3808 bnx2x_cl45_read(bp, phy,
3809 MDIO_AN_DEVAD,
3810 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3811 pause_result = (ld_pause &
3812 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3813 pause_result |= (lp_pause &
3814 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3815 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3816 pause_result);
3817 bnx2x_pause_resolve(vars, pause_result);
3818 }
3819 return ret;
3820 }
3821
3822 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3823 struct bnx2x_phy *phy,
3824 struct link_vars *vars)
3825 {
3826 u16 val;
3827 bnx2x_cl45_read(bp, phy,
3828 MDIO_AN_DEVAD,
3829 MDIO_AN_REG_STATUS, &val);
3830 bnx2x_cl45_read(bp, phy,
3831 MDIO_AN_DEVAD,
3832 MDIO_AN_REG_STATUS, &val);
3833 if (val & (1<<5))
3834 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3835 if ((val & (1<<0)) == 0)
3836 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3837 }
3838
3839 /******************************************************************/
3840 /* common BCM8073/BCM8727 PHY SECTION */
3841 /******************************************************************/
3842 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3843 struct link_params *params,
3844 struct link_vars *vars)
3845 {
3846 struct bnx2x *bp = params->bp;
3847 if (phy->req_line_speed == SPEED_10 ||
3848 phy->req_line_speed == SPEED_100) {
3849 vars->flow_ctrl = phy->req_flow_ctrl;
3850 return;
3851 }
3852
3853 if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
3854 (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
3855 u16 pause_result;
3856 u16 ld_pause; /* local */
3857 u16 lp_pause; /* link partner */
3858 bnx2x_cl45_read(bp, phy,
3859 MDIO_AN_DEVAD,
3860 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3861
3862 bnx2x_cl45_read(bp, phy,
3863 MDIO_AN_DEVAD,
3864 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3865 pause_result = (ld_pause &
3866 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
3867 pause_result |= (lp_pause &
3868 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
3869
3870 bnx2x_pause_resolve(vars, pause_result);
3871 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
3872 pause_result);
3873 }
3874 }
3875 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3876 struct bnx2x_phy *phy,
3877 u8 port)
3878 {
3879 u32 count = 0;
3880 u16 fw_ver1, fw_msgout;
3881 int rc = 0;
3882
3883 /* Boot port from external ROM */
3884 /* EDC grst */
3885 bnx2x_cl45_write(bp, phy,
3886 MDIO_PMA_DEVAD,
3887 MDIO_PMA_REG_GEN_CTRL,
3888 0x0001);
3889
3890 /* ucode reboot and rst */
3891 bnx2x_cl45_write(bp, phy,
3892 MDIO_PMA_DEVAD,
3893 MDIO_PMA_REG_GEN_CTRL,
3894 0x008c);
3895
3896 bnx2x_cl45_write(bp, phy,
3897 MDIO_PMA_DEVAD,
3898 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
3899
3900 /* Reset internal microprocessor */
3901 bnx2x_cl45_write(bp, phy,
3902 MDIO_PMA_DEVAD,
3903 MDIO_PMA_REG_GEN_CTRL,
3904 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
3905
3906 /* Release srst bit */
3907 bnx2x_cl45_write(bp, phy,
3908 MDIO_PMA_DEVAD,
3909 MDIO_PMA_REG_GEN_CTRL,
3910 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
3911
3912 /* Delay 100ms per the PHY specifications */
3913 msleep(100);
3914
3915 /* 8073 sometimes taking longer to download */
3916 do {
3917 count++;
3918 if (count > 300) {
3919 DP(NETIF_MSG_LINK,
3920 "bnx2x_8073_8727_external_rom_boot port %x:"
3921 "Download failed. fw version = 0x%x\n",
3922 port, fw_ver1);
3923 rc = -EINVAL;
3924 break;
3925 }
3926
3927 bnx2x_cl45_read(bp, phy,
3928 MDIO_PMA_DEVAD,
3929 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3930 bnx2x_cl45_read(bp, phy,
3931 MDIO_PMA_DEVAD,
3932 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
3933
3934 msleep(1);
3935 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
3936 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
3937 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
3938
3939 /* Clear ser_boot_ctl bit */
3940 bnx2x_cl45_write(bp, phy,
3941 MDIO_PMA_DEVAD,
3942 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
3943 bnx2x_save_bcm_spirom_ver(bp, phy, port);
3944
3945 DP(NETIF_MSG_LINK,
3946 "bnx2x_8073_8727_external_rom_boot port %x:"
3947 "Download complete. fw version = 0x%x\n",
3948 port, fw_ver1);
3949
3950 return rc;
3951 }
3952
3953 /******************************************************************/
3954 /* BCM8073 PHY SECTION */
3955 /******************************************************************/
3956 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
3957 {
3958 /* This is only required for 8073A1, version 102 only */
3959 u16 val;
3960
3961 /* Read 8073 HW revision*/
3962 bnx2x_cl45_read(bp, phy,
3963 MDIO_PMA_DEVAD,
3964 MDIO_PMA_REG_8073_CHIP_REV, &val);
3965
3966 if (val != 1) {
3967 /* No need to workaround in 8073 A1 */
3968 return 0;
3969 }
3970
3971 bnx2x_cl45_read(bp, phy,
3972 MDIO_PMA_DEVAD,
3973 MDIO_PMA_REG_ROM_VER2, &val);
3974
3975 /* SNR should be applied only for version 0x102 */
3976 if (val != 0x102)
3977 return 0;
3978
3979 return 1;
3980 }
3981
3982 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
3983 {
3984 u16 val, cnt, cnt1 ;
3985
3986 bnx2x_cl45_read(bp, phy,
3987 MDIO_PMA_DEVAD,
3988 MDIO_PMA_REG_8073_CHIP_REV, &val);
3989
3990 if (val > 0) {
3991 /* No need to workaround in 8073 A1 */
3992 return 0;
3993 }
3994 /* XAUI workaround in 8073 A0: */
3995
3996 /*
3997 * After loading the boot ROM and restarting Autoneg, poll
3998 * Dev1, Reg $C820:
3999 */
4000
4001 for (cnt = 0; cnt < 1000; cnt++) {
4002 bnx2x_cl45_read(bp, phy,
4003 MDIO_PMA_DEVAD,
4004 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4005 &val);
4006 /*
4007 * If bit [14] = 0 or bit [13] = 0, continue on with
4008 * system initialization (XAUI work-around not required, as
4009 * these bits indicate 2.5G or 1G link up).
4010 */
4011 if (!(val & (1<<14)) || !(val & (1<<13))) {
4012 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
4013 return 0;
4014 } else if (!(val & (1<<15))) {
4015 DP(NETIF_MSG_LINK, "bit 15 went off\n");
4016 /*
4017 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
4018 * MSB (bit15) goes to 1 (indicating that the XAUI
4019 * workaround has completed), then continue on with
4020 * system initialization.
4021 */
4022 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
4023 bnx2x_cl45_read(bp, phy,
4024 MDIO_PMA_DEVAD,
4025 MDIO_PMA_REG_8073_XAUI_WA, &val);
4026 if (val & (1<<15)) {
4027 DP(NETIF_MSG_LINK,
4028 "XAUI workaround has completed\n");
4029 return 0;
4030 }
4031 msleep(3);
4032 }
4033 break;
4034 }
4035 msleep(3);
4036 }
4037 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
4038 return -EINVAL;
4039 }
4040
4041 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
4042 {
4043 /* Force KR or KX */
4044 bnx2x_cl45_write(bp, phy,
4045 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
4046 bnx2x_cl45_write(bp, phy,
4047 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
4048 bnx2x_cl45_write(bp, phy,
4049 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
4050 bnx2x_cl45_write(bp, phy,
4051 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
4052 }
4053
4054 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
4055 struct bnx2x_phy *phy,
4056 struct link_vars *vars)
4057 {
4058 u16 cl37_val;
4059 struct bnx2x *bp = params->bp;
4060 bnx2x_cl45_read(bp, phy,
4061 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
4062
4063 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4064 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4065 bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4066 if ((vars->ieee_fc &
4067 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
4068 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
4069 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
4070 }
4071 if ((vars->ieee_fc &
4072 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4073 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4074 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4075 }
4076 if ((vars->ieee_fc &
4077 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4078 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4079 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4080 }
4081 DP(NETIF_MSG_LINK,
4082 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
4083
4084 bnx2x_cl45_write(bp, phy,
4085 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
4086 msleep(500);
4087 }
4088
4089 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
4090 struct link_params *params,
4091 struct link_vars *vars)
4092 {
4093 struct bnx2x *bp = params->bp;
4094 u16 val = 0, tmp1;
4095 u8 gpio_port;
4096 DP(NETIF_MSG_LINK, "Init 8073\n");
4097
4098 if (CHIP_IS_E2(bp))
4099 gpio_port = BP_PATH(bp);
4100 else
4101 gpio_port = params->port;
4102 /* Restore normal power mode*/
4103 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4104 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4105
4106 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4107 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4108
4109 /* enable LASI */
4110 bnx2x_cl45_write(bp, phy,
4111 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
4112 bnx2x_cl45_write(bp, phy,
4113 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x0004);
4114
4115 bnx2x_8073_set_pause_cl37(params, phy, vars);
4116
4117 bnx2x_cl45_read(bp, phy,
4118 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
4119
4120 bnx2x_cl45_read(bp, phy,
4121 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
4122
4123 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
4124
4125 /* Swap polarity if required - Must be done only in non-1G mode */
4126 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4127 /* Configure the 8073 to swap _P and _N of the KR lines */
4128 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
4129 /* 10G Rx/Tx and 1G Tx signal polarity swap */
4130 bnx2x_cl45_read(bp, phy,
4131 MDIO_PMA_DEVAD,
4132 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
4133 bnx2x_cl45_write(bp, phy,
4134 MDIO_PMA_DEVAD,
4135 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
4136 (val | (3<<9)));
4137 }
4138
4139
4140 /* Enable CL37 BAM */
4141 if (REG_RD(bp, params->shmem_base +
4142 offsetof(struct shmem_region, dev_info.
4143 port_hw_config[params->port].default_cfg)) &
4144 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
4145
4146 bnx2x_cl45_read(bp, phy,
4147 MDIO_AN_DEVAD,
4148 MDIO_AN_REG_8073_BAM, &val);
4149 bnx2x_cl45_write(bp, phy,
4150 MDIO_AN_DEVAD,
4151 MDIO_AN_REG_8073_BAM, val | 1);
4152 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
4153 }
4154 if (params->loopback_mode == LOOPBACK_EXT) {
4155 bnx2x_807x_force_10G(bp, phy);
4156 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
4157 return 0;
4158 } else {
4159 bnx2x_cl45_write(bp, phy,
4160 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
4161 }
4162 if (phy->req_line_speed != SPEED_AUTO_NEG) {
4163 if (phy->req_line_speed == SPEED_10000) {
4164 val = (1<<7);
4165 } else if (phy->req_line_speed == SPEED_2500) {
4166 val = (1<<5);
4167 /*
4168 * Note that 2.5G works only when used with 1G
4169 * advertisement
4170 */
4171 } else
4172 val = (1<<5);
4173 } else {
4174 val = 0;
4175 if (phy->speed_cap_mask &
4176 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4177 val |= (1<<7);
4178
4179 /* Note that 2.5G works only when used with 1G advertisement */
4180 if (phy->speed_cap_mask &
4181 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4182 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
4183 val |= (1<<5);
4184 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
4185 }
4186
4187 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
4188 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
4189
4190 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4191 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
4192 (phy->req_line_speed == SPEED_2500)) {
4193 u16 phy_ver;
4194 /* Allow 2.5G for A1 and above */
4195 bnx2x_cl45_read(bp, phy,
4196 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
4197 &phy_ver);
4198 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4199 if (phy_ver > 0)
4200 tmp1 |= 1;
4201 else
4202 tmp1 &= 0xfffe;
4203 } else {
4204 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4205 tmp1 &= 0xfffe;
4206 }
4207
4208 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
4209 /* Add support for CL37 (passive mode) II */
4210
4211 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
4212 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
4213 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
4214 0x20 : 0x40)));
4215
4216 /* Add support for CL37 (passive mode) III */
4217 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
4218
4219 /*
4220 * The SNR will improve about 2db by changing BW and FEE main
4221 * tap. Rest commands are executed after link is up
4222 * Change FFE main cursor to 5 in EDC register
4223 */
4224 if (bnx2x_8073_is_snr_needed(bp, phy))
4225 bnx2x_cl45_write(bp, phy,
4226 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
4227 0xFB0C);
4228
4229 /* Enable FEC (Forware Error Correction) Request in the AN */
4230 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
4231 tmp1 |= (1<<15);
4232 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
4233
4234 bnx2x_ext_phy_set_pause(params, phy, vars);
4235
4236 /* Restart autoneg */
4237 msleep(500);
4238 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4239 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
4240 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
4241 return 0;
4242 }
4243
4244 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
4245 struct link_params *params,
4246 struct link_vars *vars)
4247 {
4248 struct bnx2x *bp = params->bp;
4249 u8 link_up = 0;
4250 u16 val1, val2;
4251 u16 link_status = 0;
4252 u16 an1000_status = 0;
4253
4254 bnx2x_cl45_read(bp, phy,
4255 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4256
4257 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
4258
4259 /* clear the interrupt LASI status register */
4260 bnx2x_cl45_read(bp, phy,
4261 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4262 bnx2x_cl45_read(bp, phy,
4263 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4264 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4265 /* Clear MSG-OUT */
4266 bnx2x_cl45_read(bp, phy,
4267 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4268
4269 /* Check the LASI */
4270 bnx2x_cl45_read(bp, phy,
4271 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4272
4273 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4274
4275 /* Check the link status */
4276 bnx2x_cl45_read(bp, phy,
4277 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4278 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4279
4280 bnx2x_cl45_read(bp, phy,
4281 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4282 bnx2x_cl45_read(bp, phy,
4283 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4284 link_up = ((val1 & 4) == 4);
4285 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4286
4287 if (link_up &&
4288 ((phy->req_line_speed != SPEED_10000))) {
4289 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4290 return 0;
4291 }
4292 bnx2x_cl45_read(bp, phy,
4293 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4294 bnx2x_cl45_read(bp, phy,
4295 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4296
4297 /* Check the link status on 1.1.2 */
4298 bnx2x_cl45_read(bp, phy,
4299 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4300 bnx2x_cl45_read(bp, phy,
4301 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4302 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4303 "an_link_status=0x%x\n", val2, val1, an1000_status);
4304
4305 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4306 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
4307 /*
4308 * The SNR will improve about 2dbby changing the BW and FEE main
4309 * tap. The 1st write to change FFE main tap is set before
4310 * restart AN. Change PLL Bandwidth in EDC register
4311 */
4312 bnx2x_cl45_write(bp, phy,
4313 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4314 0x26BC);
4315
4316 /* Change CDR Bandwidth in EDC register */
4317 bnx2x_cl45_write(bp, phy,
4318 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4319 0x0333);
4320 }
4321 bnx2x_cl45_read(bp, phy,
4322 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4323 &link_status);
4324
4325 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4326 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4327 link_up = 1;
4328 vars->line_speed = SPEED_10000;
4329 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4330 params->port);
4331 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4332 link_up = 1;
4333 vars->line_speed = SPEED_2500;
4334 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
4335 params->port);
4336 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4337 link_up = 1;
4338 vars->line_speed = SPEED_1000;
4339 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4340 params->port);
4341 } else {
4342 link_up = 0;
4343 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4344 params->port);
4345 }
4346
4347 if (link_up) {
4348 /* Swap polarity if required */
4349 if (params->lane_config &
4350 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
4351 /* Configure the 8073 to swap P and N of the KR lines */
4352 bnx2x_cl45_read(bp, phy,
4353 MDIO_XS_DEVAD,
4354 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
4355 /*
4356 * Set bit 3 to invert Rx in 1G mode and clear this bit
4357 * when it`s in 10G mode.
4358 */
4359 if (vars->line_speed == SPEED_1000) {
4360 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
4361 "the 8073\n");
4362 val1 |= (1<<3);
4363 } else
4364 val1 &= ~(1<<3);
4365
4366 bnx2x_cl45_write(bp, phy,
4367 MDIO_XS_DEVAD,
4368 MDIO_XS_REG_8073_RX_CTRL_PCIE,
4369 val1);
4370 }
4371 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
4372 bnx2x_8073_resolve_fc(phy, params, vars);
4373 vars->duplex = DUPLEX_FULL;
4374 }
4375 return link_up;
4376 }
4377
4378 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
4379 struct link_params *params)
4380 {
4381 struct bnx2x *bp = params->bp;
4382 u8 gpio_port;
4383 if (CHIP_IS_E2(bp))
4384 gpio_port = BP_PATH(bp);
4385 else
4386 gpio_port = params->port;
4387 DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
4388 gpio_port);
4389 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4390 MISC_REGISTERS_GPIO_OUTPUT_LOW,
4391 gpio_port);
4392 }
4393
4394 /******************************************************************/
4395 /* BCM8705 PHY SECTION */
4396 /******************************************************************/
4397 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
4398 struct link_params *params,
4399 struct link_vars *vars)
4400 {
4401 struct bnx2x *bp = params->bp;
4402 DP(NETIF_MSG_LINK, "init 8705\n");
4403 /* Restore normal power mode*/
4404 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4405 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
4406 /* HW reset */
4407 bnx2x_ext_phy_hw_reset(bp, params->port);
4408 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
4409 bnx2x_wait_reset_complete(bp, phy, params);
4410
4411 bnx2x_cl45_write(bp, phy,
4412 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
4413 bnx2x_cl45_write(bp, phy,
4414 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
4415 bnx2x_cl45_write(bp, phy,
4416 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
4417 bnx2x_cl45_write(bp, phy,
4418 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
4419 /* BCM8705 doesn't have microcode, hence the 0 */
4420 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
4421 return 0;
4422 }
4423
4424 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
4425 struct link_params *params,
4426 struct link_vars *vars)
4427 {
4428 u8 link_up = 0;
4429 u16 val1, rx_sd;
4430 struct bnx2x *bp = params->bp;
4431 DP(NETIF_MSG_LINK, "read status 8705\n");
4432 bnx2x_cl45_read(bp, phy,
4433 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4434 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4435
4436 bnx2x_cl45_read(bp, phy,
4437 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4438 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4439
4440 bnx2x_cl45_read(bp, phy,
4441 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
4442
4443 bnx2x_cl45_read(bp, phy,
4444 MDIO_PMA_DEVAD, 0xc809, &val1);
4445 bnx2x_cl45_read(bp, phy,
4446 MDIO_PMA_DEVAD, 0xc809, &val1);
4447
4448 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4449 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
4450 if (link_up) {
4451 vars->line_speed = SPEED_10000;
4452 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4453 }
4454 return link_up;
4455 }
4456
4457 /******************************************************************/
4458 /* SFP+ module Section */
4459 /******************************************************************/
4460 static u8 bnx2x_get_gpio_port(struct link_params *params)
4461 {
4462 u8 gpio_port;
4463 u32 swap_val, swap_override;
4464 struct bnx2x *bp = params->bp;
4465 if (CHIP_IS_E2(bp))
4466 gpio_port = BP_PATH(bp);
4467 else
4468 gpio_port = params->port;
4469 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
4470 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
4471 return gpio_port ^ (swap_val && swap_override);
4472 }
4473 static void bnx2x_sfp_set_transmitter(struct link_params *params,
4474 struct bnx2x_phy *phy,
4475 u8 tx_en)
4476 {
4477 u16 val;
4478 u8 port = params->port;
4479 struct bnx2x *bp = params->bp;
4480 u32 tx_en_mode;
4481
4482 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
4483 tx_en_mode = REG_RD(bp, params->shmem_base +
4484 offsetof(struct shmem_region,
4485 dev_info.port_hw_config[port].sfp_ctrl)) &
4486 PORT_HW_CFG_TX_LASER_MASK;
4487 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
4488 "mode = %x\n", tx_en, port, tx_en_mode);
4489 switch (tx_en_mode) {
4490 case PORT_HW_CFG_TX_LASER_MDIO:
4491
4492 bnx2x_cl45_read(bp, phy,
4493 MDIO_PMA_DEVAD,
4494 MDIO_PMA_REG_PHY_IDENTIFIER,
4495 &val);
4496
4497 if (tx_en)
4498 val &= ~(1<<15);
4499 else
4500 val |= (1<<15);
4501
4502 bnx2x_cl45_write(bp, phy,
4503 MDIO_PMA_DEVAD,
4504 MDIO_PMA_REG_PHY_IDENTIFIER,
4505 val);
4506 break;
4507 case PORT_HW_CFG_TX_LASER_GPIO0:
4508 case PORT_HW_CFG_TX_LASER_GPIO1:
4509 case PORT_HW_CFG_TX_LASER_GPIO2:
4510 case PORT_HW_CFG_TX_LASER_GPIO3:
4511 {
4512 u16 gpio_pin;
4513 u8 gpio_port, gpio_mode;
4514 if (tx_en)
4515 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
4516 else
4517 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
4518
4519 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
4520 gpio_port = bnx2x_get_gpio_port(params);
4521 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
4522 break;
4523 }
4524 default:
4525 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
4526 break;
4527 }
4528 }
4529
4530 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4531 struct link_params *params,
4532 u16 addr, u8 byte_cnt, u8 *o_buf)
4533 {
4534 struct bnx2x *bp = params->bp;
4535 u16 val = 0;
4536 u16 i;
4537 if (byte_cnt > 16) {
4538 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4539 " is limited to 0xf\n");
4540 return -EINVAL;
4541 }
4542 /* Set the read command byte count */
4543 bnx2x_cl45_write(bp, phy,
4544 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4545 (byte_cnt | 0xa000));
4546
4547 /* Set the read command address */
4548 bnx2x_cl45_write(bp, phy,
4549 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4550 addr);
4551
4552 /* Activate read command */
4553 bnx2x_cl45_write(bp, phy,
4554 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4555 0x2c0f);
4556
4557 /* Wait up to 500us for command complete status */
4558 for (i = 0; i < 100; i++) {
4559 bnx2x_cl45_read(bp, phy,
4560 MDIO_PMA_DEVAD,
4561 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4562 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4563 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4564 break;
4565 udelay(5);
4566 }
4567
4568 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4569 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4570 DP(NETIF_MSG_LINK,
4571 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4572 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4573 return -EINVAL;
4574 }
4575
4576 /* Read the buffer */
4577 for (i = 0; i < byte_cnt; i++) {
4578 bnx2x_cl45_read(bp, phy,
4579 MDIO_PMA_DEVAD,
4580 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
4581 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
4582 }
4583
4584 for (i = 0; i < 100; i++) {
4585 bnx2x_cl45_read(bp, phy,
4586 MDIO_PMA_DEVAD,
4587 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4588 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4589 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4590 return 0;
4591 msleep(1);
4592 }
4593 return -EINVAL;
4594 }
4595
4596 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4597 struct link_params *params,
4598 u16 addr, u8 byte_cnt, u8 *o_buf)
4599 {
4600 struct bnx2x *bp = params->bp;
4601 u16 val, i;
4602
4603 if (byte_cnt > 16) {
4604 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4605 " is limited to 0xf\n");
4606 return -EINVAL;
4607 }
4608
4609 /* Need to read from 1.8000 to clear it */
4610 bnx2x_cl45_read(bp, phy,
4611 MDIO_PMA_DEVAD,
4612 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4613 &val);
4614
4615 /* Set the read command byte count */
4616 bnx2x_cl45_write(bp, phy,
4617 MDIO_PMA_DEVAD,
4618 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4619 ((byte_cnt < 2) ? 2 : byte_cnt));
4620
4621 /* Set the read command address */
4622 bnx2x_cl45_write(bp, phy,
4623 MDIO_PMA_DEVAD,
4624 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4625 addr);
4626 /* Set the destination address */
4627 bnx2x_cl45_write(bp, phy,
4628 MDIO_PMA_DEVAD,
4629 0x8004,
4630 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
4631
4632 /* Activate read command */
4633 bnx2x_cl45_write(bp, phy,
4634 MDIO_PMA_DEVAD,
4635 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4636 0x8002);
4637 /*
4638 * Wait appropriate time for two-wire command to finish before
4639 * polling the status register
4640 */
4641 msleep(1);
4642
4643 /* Wait up to 500us for command complete status */
4644 for (i = 0; i < 100; i++) {
4645 bnx2x_cl45_read(bp, phy,
4646 MDIO_PMA_DEVAD,
4647 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4648 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4649 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4650 break;
4651 udelay(5);
4652 }
4653
4654 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4655 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4656 DP(NETIF_MSG_LINK,
4657 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4658 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4659 return -EFAULT;
4660 }
4661
4662 /* Read the buffer */
4663 for (i = 0; i < byte_cnt; i++) {
4664 bnx2x_cl45_read(bp, phy,
4665 MDIO_PMA_DEVAD,
4666 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
4667 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
4668 }
4669
4670 for (i = 0; i < 100; i++) {
4671 bnx2x_cl45_read(bp, phy,
4672 MDIO_PMA_DEVAD,
4673 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4674 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4675 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4676 return 0;
4677 msleep(1);
4678 }
4679
4680 return -EINVAL;
4681 }
4682
4683 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4684 struct link_params *params, u16 addr,
4685 u8 byte_cnt, u8 *o_buf)
4686 {
4687 int rc = -EINVAL;
4688 switch (phy->type) {
4689 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4690 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
4691 byte_cnt, o_buf);
4692 break;
4693 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4694 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
4695 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
4696 byte_cnt, o_buf);
4697 break;
4698 }
4699 return rc;
4700 }
4701
4702 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
4703 struct link_params *params,
4704 u16 *edc_mode)
4705 {
4706 struct bnx2x *bp = params->bp;
4707 u32 sync_offset = 0, phy_idx, media_types;
4708 u8 val, check_limiting_mode = 0;
4709 *edc_mode = EDC_MODE_LIMITING;
4710
4711 phy->media_type = ETH_PHY_UNSPECIFIED;
4712 /* First check for copper cable */
4713 if (bnx2x_read_sfp_module_eeprom(phy,
4714 params,
4715 SFP_EEPROM_CON_TYPE_ADDR,
4716 1,
4717 &val) != 0) {
4718 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
4719 return -EINVAL;
4720 }
4721
4722 switch (val) {
4723 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
4724 {
4725 u8 copper_module_type;
4726 phy->media_type = ETH_PHY_DA_TWINAX;
4727 /*
4728 * Check if its active cable (includes SFP+ module)
4729 * of passive cable
4730 */
4731 if (bnx2x_read_sfp_module_eeprom(phy,
4732 params,
4733 SFP_EEPROM_FC_TX_TECH_ADDR,
4734 1,
4735 &copper_module_type) !=
4736 0) {
4737 DP(NETIF_MSG_LINK,
4738 "Failed to read copper-cable-type"
4739 " from SFP+ EEPROM\n");
4740 return -EINVAL;
4741 }
4742
4743 if (copper_module_type &
4744 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
4745 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4746 check_limiting_mode = 1;
4747 } else if (copper_module_type &
4748 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
4749 DP(NETIF_MSG_LINK, "Passive Copper"
4750 " cable detected\n");
4751 *edc_mode =
4752 EDC_MODE_PASSIVE_DAC;
4753 } else {
4754 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
4755 "type 0x%x !!!\n", copper_module_type);
4756 return -EINVAL;
4757 }
4758 break;
4759 }
4760 case SFP_EEPROM_CON_TYPE_VAL_LC:
4761 phy->media_type = ETH_PHY_SFP_FIBER;
4762 DP(NETIF_MSG_LINK, "Optic module detected\n");
4763 check_limiting_mode = 1;
4764 break;
4765 default:
4766 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
4767 val);
4768 return -EINVAL;
4769 }
4770 sync_offset = params->shmem_base +
4771 offsetof(struct shmem_region,
4772 dev_info.port_hw_config[params->port].media_type);
4773 media_types = REG_RD(bp, sync_offset);
4774 /* Update media type for non-PMF sync */
4775 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
4776 if (&(params->phy[phy_idx]) == phy) {
4777 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
4778 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
4779 media_types |= ((phy->media_type &
4780 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
4781 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
4782 break;
4783 }
4784 }
4785 REG_WR(bp, sync_offset, media_types);
4786 if (check_limiting_mode) {
4787 u8 options[SFP_EEPROM_OPTIONS_SIZE];
4788 if (bnx2x_read_sfp_module_eeprom(phy,
4789 params,
4790 SFP_EEPROM_OPTIONS_ADDR,
4791 SFP_EEPROM_OPTIONS_SIZE,
4792 options) != 0) {
4793 DP(NETIF_MSG_LINK, "Failed to read Option"
4794 " field from module EEPROM\n");
4795 return -EINVAL;
4796 }
4797 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
4798 *edc_mode = EDC_MODE_LINEAR;
4799 else
4800 *edc_mode = EDC_MODE_LIMITING;
4801 }
4802 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
4803 return 0;
4804 }
4805 /*
4806 * This function read the relevant field from the module (SFP+), and verify it
4807 * is compliant with this board
4808 */
4809 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4810 struct link_params *params)
4811 {
4812 struct bnx2x *bp = params->bp;
4813 u32 val, cmd;
4814 u32 fw_resp, fw_cmd_param;
4815 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
4816 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
4817 phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
4818 val = REG_RD(bp, params->shmem_base +
4819 offsetof(struct shmem_region, dev_info.
4820 port_feature_config[params->port].config));
4821 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4822 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
4823 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
4824 return 0;
4825 }
4826
4827 if (params->feature_config_flags &
4828 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
4829 /* Use specific phy request */
4830 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
4831 } else if (params->feature_config_flags &
4832 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
4833 /* Use first phy request only in case of non-dual media*/
4834 if (DUAL_MEDIA(params)) {
4835 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4836 "verification\n");
4837 return -EINVAL;
4838 }
4839 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
4840 } else {
4841 /* No support in OPT MDL detection */
4842 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4843 "verification\n");
4844 return -EINVAL;
4845 }
4846
4847 fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
4848 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
4849 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
4850 DP(NETIF_MSG_LINK, "Approved module\n");
4851 return 0;
4852 }
4853
4854 /* format the warning message */
4855 if (bnx2x_read_sfp_module_eeprom(phy,
4856 params,
4857 SFP_EEPROM_VENDOR_NAME_ADDR,
4858 SFP_EEPROM_VENDOR_NAME_SIZE,
4859 (u8 *)vendor_name))
4860 vendor_name[0] = '\0';
4861 else
4862 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4863 if (bnx2x_read_sfp_module_eeprom(phy,
4864 params,
4865 SFP_EEPROM_PART_NO_ADDR,
4866 SFP_EEPROM_PART_NO_SIZE,
4867 (u8 *)vendor_pn))
4868 vendor_pn[0] = '\0';
4869 else
4870 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
4871
4872 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected,"
4873 " Port %d from %s part number %s\n",
4874 params->port, vendor_name, vendor_pn);
4875 phy->flags |= FLAGS_SFP_NOT_APPROVED;
4876 return -EINVAL;
4877 }
4878
4879 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
4880 struct link_params *params)
4881
4882 {
4883 u8 val;
4884 struct bnx2x *bp = params->bp;
4885 u16 timeout;
4886 /*
4887 * Initialization time after hot-plug may take up to 300ms for
4888 * some phys type ( e.g. JDSU )
4889 */
4890
4891 for (timeout = 0; timeout < 60; timeout++) {
4892 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
4893 == 0) {
4894 DP(NETIF_MSG_LINK, "SFP+ module initialization "
4895 "took %d ms\n", timeout * 5);
4896 return 0;
4897 }
4898 msleep(5);
4899 }
4900 return -EINVAL;
4901 }
4902
4903 static void bnx2x_8727_power_module(struct bnx2x *bp,
4904 struct bnx2x_phy *phy,
4905 u8 is_power_up) {
4906 /* Make sure GPIOs are not using for LED mode */
4907 u16 val;
4908 /*
4909 * In the GPIO register, bit 4 is use to determine if the GPIOs are
4910 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
4911 * output
4912 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
4913 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
4914 * where the 1st bit is the over-current(only input), and 2nd bit is
4915 * for power( only output )
4916 *
4917 * In case of NOC feature is disabled and power is up, set GPIO control
4918 * as input to enable listening of over-current indication
4919 */
4920 if (phy->flags & FLAGS_NOC)
4921 return;
4922 if (!(phy->flags &
4923 FLAGS_NOC) && is_power_up)
4924 val = (1<<4);
4925 else
4926 /*
4927 * Set GPIO control to OUTPUT, and set the power bit
4928 * to according to the is_power_up
4929 */
4930 val = ((!(is_power_up)) << 1);
4931
4932 bnx2x_cl45_write(bp, phy,
4933 MDIO_PMA_DEVAD,
4934 MDIO_PMA_REG_8727_GPIO_CTRL,
4935 val);
4936 }
4937
4938 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4939 struct bnx2x_phy *phy,
4940 u16 edc_mode)
4941 {
4942 u16 cur_limiting_mode;
4943
4944 bnx2x_cl45_read(bp, phy,
4945 MDIO_PMA_DEVAD,
4946 MDIO_PMA_REG_ROM_VER2,
4947 &cur_limiting_mode);
4948 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4949 cur_limiting_mode);
4950
4951 if (edc_mode == EDC_MODE_LIMITING) {
4952 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
4953 bnx2x_cl45_write(bp, phy,
4954 MDIO_PMA_DEVAD,
4955 MDIO_PMA_REG_ROM_VER2,
4956 EDC_MODE_LIMITING);
4957 } else { /* LRM mode ( default )*/
4958
4959 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
4960
4961 /*
4962 * Changing to LRM mode takes quite few seconds. So do it only
4963 * if current mode is limiting (default is LRM)
4964 */
4965 if (cur_limiting_mode != EDC_MODE_LIMITING)
4966 return 0;
4967
4968 bnx2x_cl45_write(bp, phy,
4969 MDIO_PMA_DEVAD,
4970 MDIO_PMA_REG_LRM_MODE,
4971 0);
4972 bnx2x_cl45_write(bp, phy,
4973 MDIO_PMA_DEVAD,
4974 MDIO_PMA_REG_ROM_VER2,
4975 0x128);
4976 bnx2x_cl45_write(bp, phy,
4977 MDIO_PMA_DEVAD,
4978 MDIO_PMA_REG_MISC_CTRL0,
4979 0x4008);
4980 bnx2x_cl45_write(bp, phy,
4981 MDIO_PMA_DEVAD,
4982 MDIO_PMA_REG_LRM_MODE,
4983 0xaaaa);
4984 }
4985 return 0;
4986 }
4987
4988 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
4989 struct bnx2x_phy *phy,
4990 u16 edc_mode)
4991 {
4992 u16 phy_identifier;
4993 u16 rom_ver2_val;
4994 bnx2x_cl45_read(bp, phy,
4995 MDIO_PMA_DEVAD,
4996 MDIO_PMA_REG_PHY_IDENTIFIER,
4997 &phy_identifier);
4998
4999 bnx2x_cl45_write(bp, phy,
5000 MDIO_PMA_DEVAD,
5001 MDIO_PMA_REG_PHY_IDENTIFIER,
5002 (phy_identifier & ~(1<<9)));
5003
5004 bnx2x_cl45_read(bp, phy,
5005 MDIO_PMA_DEVAD,
5006 MDIO_PMA_REG_ROM_VER2,
5007 &rom_ver2_val);
5008 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
5009 bnx2x_cl45_write(bp, phy,
5010 MDIO_PMA_DEVAD,
5011 MDIO_PMA_REG_ROM_VER2,
5012 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
5013
5014 bnx2x_cl45_write(bp, phy,
5015 MDIO_PMA_DEVAD,
5016 MDIO_PMA_REG_PHY_IDENTIFIER,
5017 (phy_identifier | (1<<9)));
5018
5019 return 0;
5020 }
5021
5022 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
5023 struct link_params *params,
5024 u32 action)
5025 {
5026 struct bnx2x *bp = params->bp;
5027
5028 switch (action) {
5029 case DISABLE_TX:
5030 bnx2x_sfp_set_transmitter(params, phy, 0);
5031 break;
5032 case ENABLE_TX:
5033 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
5034 bnx2x_sfp_set_transmitter(params, phy, 1);
5035 break;
5036 default:
5037 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
5038 action);
5039 return;
5040 }
5041 }
5042
5043 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
5044 u8 gpio_mode)
5045 {
5046 struct bnx2x *bp = params->bp;
5047
5048 u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
5049 offsetof(struct shmem_region,
5050 dev_info.port_hw_config[params->port].sfp_ctrl)) &
5051 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
5052 switch (fault_led_gpio) {
5053 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
5054 return;
5055 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
5056 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
5057 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
5058 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
5059 {
5060 u8 gpio_port = bnx2x_get_gpio_port(params);
5061 u16 gpio_pin = fault_led_gpio -
5062 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
5063 DP(NETIF_MSG_LINK, "Set fault module-detected led "
5064 "pin %x port %x mode %x\n",
5065 gpio_pin, gpio_port, gpio_mode);
5066 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
5067 }
5068 break;
5069 default:
5070 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
5071 fault_led_gpio);
5072 }
5073 }
5074
5075 static void bnx2x_power_sfp_module(struct link_params *params,
5076 struct bnx2x_phy *phy,
5077 u8 power)
5078 {
5079 struct bnx2x *bp = params->bp;
5080 DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
5081
5082 switch (phy->type) {
5083 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5084 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
5085 bnx2x_8727_power_module(params->bp, phy, power);
5086 break;
5087 default:
5088 break;
5089 }
5090 }
5091
5092 static void bnx2x_set_limiting_mode(struct link_params *params,
5093 struct bnx2x_phy *phy,
5094 u16 edc_mode)
5095 {
5096 switch (phy->type) {
5097 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5098 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
5099 break;
5100 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5101 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
5102 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
5103 break;
5104 }
5105 }
5106
5107 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
5108 struct link_params *params)
5109 {
5110 struct bnx2x *bp = params->bp;
5111 u16 edc_mode;
5112 int rc = 0;
5113
5114 u32 val = REG_RD(bp, params->shmem_base +
5115 offsetof(struct shmem_region, dev_info.
5116 port_feature_config[params->port].config));
5117
5118 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
5119 params->port);
5120 /* Power up module */
5121 bnx2x_power_sfp_module(params, phy, 1);
5122 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
5123 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
5124 return -EINVAL;
5125 } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
5126 /* check SFP+ module compatibility */
5127 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
5128 rc = -EINVAL;
5129 /* Turn on fault module-detected led */
5130 bnx2x_set_sfp_module_fault_led(params,
5131 MISC_REGISTERS_GPIO_HIGH);
5132
5133 /* Check if need to power down the SFP+ module */
5134 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5135 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
5136 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
5137 bnx2x_power_sfp_module(params, phy, 0);
5138 return rc;
5139 }
5140 } else {
5141 /* Turn off fault module-detected led */
5142 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
5143 }
5144
5145 /*
5146 * Check and set limiting mode / LRM mode on 8726. On 8727 it
5147 * is done automatically
5148 */
5149 bnx2x_set_limiting_mode(params, phy, edc_mode);
5150
5151 /*
5152 * Enable transmit for this module if the module is approved, or
5153 * if unapproved modules should also enable the Tx laser
5154 */
5155 if (rc == 0 ||
5156 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
5157 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5158 bnx2x_sfp_set_transmitter(params, phy, 1);
5159 else
5160 bnx2x_sfp_set_transmitter(params, phy, 0);
5161
5162 return rc;
5163 }
5164
5165 void bnx2x_handle_module_detect_int(struct link_params *params)
5166 {
5167 struct bnx2x *bp = params->bp;
5168 struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
5169 u32 gpio_val;
5170 u8 port = params->port;
5171
5172 /* Set valid module led off */
5173 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
5174
5175 /* Get current gpio val reflecting module plugged in / out*/
5176 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
5177
5178 /* Call the handling function in case module is detected */
5179 if (gpio_val == 0) {
5180 bnx2x_power_sfp_module(params, phy, 1);
5181 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5182 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
5183 port);
5184
5185 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5186 bnx2x_sfp_module_detection(phy, params);
5187 else
5188 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5189 } else {
5190 u32 val = REG_RD(bp, params->shmem_base +
5191 offsetof(struct shmem_region, dev_info.
5192 port_feature_config[params->port].
5193 config));
5194
5195 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5196 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
5197 port);
5198 /*
5199 * Module was plugged out.
5200 * Disable transmit for this module
5201 */
5202 phy->media_type = ETH_PHY_NOT_PRESENT;
5203 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5204 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5205 bnx2x_sfp_set_transmitter(params, phy, 0);
5206 }
5207 }
5208
5209 /******************************************************************/
5210 /* Used by 8706 and 8727 */
5211 /******************************************************************/
5212 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
5213 struct bnx2x_phy *phy,
5214 u16 alarm_status_offset,
5215 u16 alarm_ctrl_offset)
5216 {
5217 u16 alarm_status, val;
5218 bnx2x_cl45_read(bp, phy,
5219 MDIO_PMA_DEVAD, alarm_status_offset,
5220 &alarm_status);
5221 bnx2x_cl45_read(bp, phy,
5222 MDIO_PMA_DEVAD, alarm_status_offset,
5223 &alarm_status);
5224 /* Mask or enable the fault event. */
5225 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
5226 if (alarm_status & (1<<0))
5227 val &= ~(1<<0);
5228 else
5229 val |= (1<<0);
5230 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
5231 }
5232 /******************************************************************/
5233 /* common BCM8706/BCM8726 PHY SECTION */
5234 /******************************************************************/
5235 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
5236 struct link_params *params,
5237 struct link_vars *vars)
5238 {
5239 u8 link_up = 0;
5240 u16 val1, val2, rx_sd, pcs_status;
5241 struct bnx2x *bp = params->bp;
5242 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
5243 /* Clear RX Alarm*/
5244 bnx2x_cl45_read(bp, phy,
5245 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
5246
5247 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_REG_TX_ALARM,
5248 MDIO_PMA_REG_TX_ALARM_CTRL);
5249
5250 /* clear LASI indication*/
5251 bnx2x_cl45_read(bp, phy,
5252 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5253 bnx2x_cl45_read(bp, phy,
5254 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5255 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
5256
5257 bnx2x_cl45_read(bp, phy,
5258 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
5259 bnx2x_cl45_read(bp, phy,
5260 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
5261 bnx2x_cl45_read(bp, phy,
5262 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5263 bnx2x_cl45_read(bp, phy,
5264 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5265
5266 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
5267 " link_status 0x%x\n", rx_sd, pcs_status, val2);
5268 /*
5269 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
5270 * are set, or if the autoneg bit 1 is set
5271 */
5272 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
5273 if (link_up) {
5274 if (val2 & (1<<1))
5275 vars->line_speed = SPEED_1000;
5276 else
5277 vars->line_speed = SPEED_10000;
5278 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5279 vars->duplex = DUPLEX_FULL;
5280 }
5281
5282 /* Capture 10G link fault. Read twice to clear stale value. */
5283 if (vars->line_speed == SPEED_10000) {
5284 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
5285 MDIO_PMA_REG_TX_ALARM, &val1);
5286 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
5287 MDIO_PMA_REG_TX_ALARM, &val1);
5288 if (val1 & (1<<0))
5289 vars->fault_detected = 1;
5290 }
5291
5292 return link_up;
5293 }
5294
5295 /******************************************************************/
5296 /* BCM8706 PHY SECTION */
5297 /******************************************************************/
5298 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
5299 struct link_params *params,
5300 struct link_vars *vars)
5301 {
5302 u32 tx_en_mode;
5303 u16 cnt, val, tmp1;
5304 struct bnx2x *bp = params->bp;
5305 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5306 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5307 /* HW reset */
5308 bnx2x_ext_phy_hw_reset(bp, params->port);
5309 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
5310 bnx2x_wait_reset_complete(bp, phy, params);
5311
5312 /* Wait until fw is loaded */
5313 for (cnt = 0; cnt < 100; cnt++) {
5314 bnx2x_cl45_read(bp, phy,
5315 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
5316 if (val)
5317 break;
5318 msleep(10);
5319 }
5320 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
5321 if ((params->feature_config_flags &
5322 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5323 u8 i;
5324 u16 reg;
5325 for (i = 0; i < 4; i++) {
5326 reg = MDIO_XS_8706_REG_BANK_RX0 +
5327 i*(MDIO_XS_8706_REG_BANK_RX1 -
5328 MDIO_XS_8706_REG_BANK_RX0);
5329 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
5330 /* Clear first 3 bits of the control */
5331 val &= ~0x7;
5332 /* Set control bits according to configuration */
5333 val |= (phy->rx_preemphasis[i] & 0x7);
5334 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
5335 " reg 0x%x <-- val 0x%x\n", reg, val);
5336 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
5337 }
5338 }
5339 /* Force speed */
5340 if (phy->req_line_speed == SPEED_10000) {
5341 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
5342
5343 bnx2x_cl45_write(bp, phy,
5344 MDIO_PMA_DEVAD,
5345 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
5346 bnx2x_cl45_write(bp, phy,
5347 MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_ALARM_CTRL,
5348 0);
5349 /* Arm LASI for link and Tx fault. */
5350 bnx2x_cl45_write(bp, phy,
5351 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 3);
5352 } else {
5353 /* Force 1Gbps using autoneg with 1G advertisement */
5354
5355 /* Allow CL37 through CL73 */
5356 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
5357 bnx2x_cl45_write(bp, phy,
5358 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5359
5360 /* Enable Full-Duplex advertisement on CL37 */
5361 bnx2x_cl45_write(bp, phy,
5362 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
5363 /* Enable CL37 AN */
5364 bnx2x_cl45_write(bp, phy,
5365 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5366 /* 1G support */
5367 bnx2x_cl45_write(bp, phy,
5368 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
5369
5370 /* Enable clause 73 AN */
5371 bnx2x_cl45_write(bp, phy,
5372 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5373 bnx2x_cl45_write(bp, phy,
5374 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5375 0x0400);
5376 bnx2x_cl45_write(bp, phy,
5377 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5378 0x0004);
5379 }
5380 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5381
5382 /*
5383 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
5384 * power mode, if TX Laser is disabled
5385 */
5386
5387 tx_en_mode = REG_RD(bp, params->shmem_base +
5388 offsetof(struct shmem_region,
5389 dev_info.port_hw_config[params->port].sfp_ctrl))
5390 & PORT_HW_CFG_TX_LASER_MASK;
5391
5392 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
5393 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
5394 bnx2x_cl45_read(bp, phy,
5395 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
5396 tmp1 |= 0x1;
5397 bnx2x_cl45_write(bp, phy,
5398 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
5399 }
5400
5401 return 0;
5402 }
5403
5404 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
5405 struct link_params *params,
5406 struct link_vars *vars)
5407 {
5408 return bnx2x_8706_8726_read_status(phy, params, vars);
5409 }
5410
5411 /******************************************************************/
5412 /* BCM8726 PHY SECTION */
5413 /******************************************************************/
5414 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
5415 struct link_params *params)
5416 {
5417 struct bnx2x *bp = params->bp;
5418 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5419 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
5420 }
5421
5422 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
5423 struct link_params *params)
5424 {
5425 struct bnx2x *bp = params->bp;
5426 /* Need to wait 100ms after reset */
5427 msleep(100);
5428
5429 /* Micro controller re-boot */
5430 bnx2x_cl45_write(bp, phy,
5431 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
5432
5433 /* Set soft reset */
5434 bnx2x_cl45_write(bp, phy,
5435 MDIO_PMA_DEVAD,
5436 MDIO_PMA_REG_GEN_CTRL,
5437 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
5438
5439 bnx2x_cl45_write(bp, phy,
5440 MDIO_PMA_DEVAD,
5441 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
5442
5443 bnx2x_cl45_write(bp, phy,
5444 MDIO_PMA_DEVAD,
5445 MDIO_PMA_REG_GEN_CTRL,
5446 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
5447
5448 /* wait for 150ms for microcode load */
5449 msleep(150);
5450
5451 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
5452 bnx2x_cl45_write(bp, phy,
5453 MDIO_PMA_DEVAD,
5454 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
5455
5456 msleep(200);
5457 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5458 }
5459
5460 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
5461 struct link_params *params,
5462 struct link_vars *vars)
5463 {
5464 struct bnx2x *bp = params->bp;
5465 u16 val1;
5466 u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
5467 if (link_up) {
5468 bnx2x_cl45_read(bp, phy,
5469 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
5470 &val1);
5471 if (val1 & (1<<15)) {
5472 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5473 link_up = 0;
5474 vars->line_speed = 0;
5475 }
5476 }
5477 return link_up;
5478 }
5479
5480
5481 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
5482 struct link_params *params,
5483 struct link_vars *vars)
5484 {
5485 struct bnx2x *bp = params->bp;
5486 u32 val;
5487 u32 swap_val, swap_override, aeu_gpio_mask, offset;
5488 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
5489
5490 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
5491 bnx2x_wait_reset_complete(bp, phy, params);
5492
5493 bnx2x_8726_external_rom_boot(phy, params);
5494
5495 /*
5496 * Need to call module detected on initialization since the module
5497 * detection triggered by actual module insertion might occur before
5498 * driver is loaded, and when driver is loaded, it reset all
5499 * registers, including the transmitter
5500 */
5501 bnx2x_sfp_module_detection(phy, params);
5502
5503 if (phy->req_line_speed == SPEED_1000) {
5504 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5505 bnx2x_cl45_write(bp, phy,
5506 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5507 bnx2x_cl45_write(bp, phy,
5508 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5509 bnx2x_cl45_write(bp, phy,
5510 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
5511 bnx2x_cl45_write(bp, phy,
5512 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5513 0x400);
5514 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5515 (phy->speed_cap_mask &
5516 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
5517 ((phy->speed_cap_mask &
5518 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5519 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5520 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5521 /* Set Flow control */
5522 bnx2x_ext_phy_set_pause(params, phy, vars);
5523 bnx2x_cl45_write(bp, phy,
5524 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
5525 bnx2x_cl45_write(bp, phy,
5526 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5527 bnx2x_cl45_write(bp, phy,
5528 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
5529 bnx2x_cl45_write(bp, phy,
5530 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5531 bnx2x_cl45_write(bp, phy,
5532 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5533 /*
5534 * Enable RX-ALARM control to receive interrupt for 1G speed
5535 * change
5536 */
5537 bnx2x_cl45_write(bp, phy,
5538 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
5539 bnx2x_cl45_write(bp, phy,
5540 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5541 0x400);
5542
5543 } else { /* Default 10G. Set only LASI control */
5544 bnx2x_cl45_write(bp, phy,
5545 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5546 }
5547
5548 /* Set TX PreEmphasis if needed */
5549 if ((params->feature_config_flags &
5550 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5551 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
5552 "TX_CTRL2 0x%x\n",
5553 phy->tx_preemphasis[0],
5554 phy->tx_preemphasis[1]);
5555 bnx2x_cl45_write(bp, phy,
5556 MDIO_PMA_DEVAD,
5557 MDIO_PMA_REG_8726_TX_CTRL1,
5558 phy->tx_preemphasis[0]);
5559
5560 bnx2x_cl45_write(bp, phy,
5561 MDIO_PMA_DEVAD,
5562 MDIO_PMA_REG_8726_TX_CTRL2,
5563 phy->tx_preemphasis[1]);
5564 }
5565
5566 /* Set GPIO3 to trigger SFP+ module insertion/removal */
5567 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5568 MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port);
5569
5570 /* The GPIO should be swapped if the swap register is set and active */
5571 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5572 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5573
5574 /* Select function upon port-swap configuration */
5575 if (params->port == 0) {
5576 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5577 aeu_gpio_mask = (swap_val && swap_override) ?
5578 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
5579 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
5580 } else {
5581 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
5582 aeu_gpio_mask = (swap_val && swap_override) ?
5583 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
5584 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
5585 }
5586 val = REG_RD(bp, offset);
5587 /* add GPIO3 to group */
5588 val |= aeu_gpio_mask;
5589 REG_WR(bp, offset, val);
5590 return 0;
5591
5592 }
5593
5594 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
5595 struct link_params *params)
5596 {
5597 struct bnx2x *bp = params->bp;
5598 DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
5599 /* Set serial boot control for external load */
5600 bnx2x_cl45_write(bp, phy,
5601 MDIO_PMA_DEVAD,
5602 MDIO_PMA_REG_GEN_CTRL, 0x0001);
5603 }
5604
5605 /******************************************************************/
5606 /* BCM8727 PHY SECTION */
5607 /******************************************************************/
5608
5609 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
5610 struct link_params *params, u8 mode)
5611 {
5612 struct bnx2x *bp = params->bp;
5613 u16 led_mode_bitmask = 0;
5614 u16 gpio_pins_bitmask = 0;
5615 u16 val;
5616 /* Only NOC flavor requires to set the LED specifically */
5617 if (!(phy->flags & FLAGS_NOC))
5618 return;
5619 switch (mode) {
5620 case LED_MODE_FRONT_PANEL_OFF:
5621 case LED_MODE_OFF:
5622 led_mode_bitmask = 0;
5623 gpio_pins_bitmask = 0x03;
5624 break;
5625 case LED_MODE_ON:
5626 led_mode_bitmask = 0;
5627 gpio_pins_bitmask = 0x02;
5628 break;
5629 case LED_MODE_OPER:
5630 led_mode_bitmask = 0x60;
5631 gpio_pins_bitmask = 0x11;
5632 break;
5633 }
5634 bnx2x_cl45_read(bp, phy,
5635 MDIO_PMA_DEVAD,
5636 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5637 &val);
5638 val &= 0xff8f;
5639 val |= led_mode_bitmask;
5640 bnx2x_cl45_write(bp, phy,
5641 MDIO_PMA_DEVAD,
5642 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5643 val);
5644 bnx2x_cl45_read(bp, phy,
5645 MDIO_PMA_DEVAD,
5646 MDIO_PMA_REG_8727_GPIO_CTRL,
5647 &val);
5648 val &= 0xffe0;
5649 val |= gpio_pins_bitmask;
5650 bnx2x_cl45_write(bp, phy,
5651 MDIO_PMA_DEVAD,
5652 MDIO_PMA_REG_8727_GPIO_CTRL,
5653 val);
5654 }
5655 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
5656 struct link_params *params) {
5657 u32 swap_val, swap_override;
5658 u8 port;
5659 /*
5660 * The PHY reset is controlled by GPIO 1. Fake the port number
5661 * to cancel the swap done in set_gpio()
5662 */
5663 struct bnx2x *bp = params->bp;
5664 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5665 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5666 port = (swap_val && swap_override) ^ 1;
5667 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5668 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
5669 }
5670
5671 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
5672 struct link_params *params,
5673 struct link_vars *vars)
5674 {
5675 u32 tx_en_mode;
5676 u16 tmp1, val, mod_abs, tmp2;
5677 u16 rx_alarm_ctrl_val;
5678 u16 lasi_ctrl_val;
5679 struct bnx2x *bp = params->bp;
5680 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
5681
5682 bnx2x_wait_reset_complete(bp, phy, params);
5683 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
5684 /* Should be 0x6 to enable XS on Tx side. */
5685 lasi_ctrl_val = 0x0006;
5686
5687 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
5688 /* enable LASI */
5689 bnx2x_cl45_write(bp, phy,
5690 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5691 rx_alarm_ctrl_val);
5692 bnx2x_cl45_write(bp, phy,
5693 MDIO_PMA_DEVAD, MDIO_PMA_REG_TX_ALARM_CTRL,
5694 0);
5695 bnx2x_cl45_write(bp, phy,
5696 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
5697
5698 /*
5699 * Initially configure MOD_ABS to interrupt when module is
5700 * presence( bit 8)
5701 */
5702 bnx2x_cl45_read(bp, phy,
5703 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5704 /*
5705 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
5706 * When the EDC is off it locks onto a reference clock and avoids
5707 * becoming 'lost'
5708 */
5709 mod_abs &= ~(1<<8);
5710 if (!(phy->flags & FLAGS_NOC))
5711 mod_abs &= ~(1<<9);
5712 bnx2x_cl45_write(bp, phy,
5713 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5714
5715
5716 /* Make MOD_ABS give interrupt on change */
5717 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5718 &val);
5719 val |= (1<<12);
5720 if (phy->flags & FLAGS_NOC)
5721 val |= (3<<5);
5722
5723 /*
5724 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
5725 * status which reflect SFP+ module over-current
5726 */
5727 if (!(phy->flags & FLAGS_NOC))
5728 val &= 0xff8f; /* Reset bits 4-6 */
5729 bnx2x_cl45_write(bp, phy,
5730 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
5731
5732 bnx2x_8727_power_module(bp, phy, 1);
5733
5734 bnx2x_cl45_read(bp, phy,
5735 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
5736
5737 bnx2x_cl45_read(bp, phy,
5738 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
5739
5740 /* Set option 1G speed */
5741 if (phy->req_line_speed == SPEED_1000) {
5742 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5743 bnx2x_cl45_write(bp, phy,
5744 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5745 bnx2x_cl45_write(bp, phy,
5746 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5747 bnx2x_cl45_read(bp, phy,
5748 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
5749 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
5750 /*
5751 * Power down the XAUI until link is up in case of dual-media
5752 * and 1G
5753 */
5754 if (DUAL_MEDIA(params)) {
5755 bnx2x_cl45_read(bp, phy,
5756 MDIO_PMA_DEVAD,
5757 MDIO_PMA_REG_8727_PCS_GP, &val);
5758 val |= (3<<10);
5759 bnx2x_cl45_write(bp, phy,
5760 MDIO_PMA_DEVAD,
5761 MDIO_PMA_REG_8727_PCS_GP, val);
5762 }
5763 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5764 ((phy->speed_cap_mask &
5765 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
5766 ((phy->speed_cap_mask &
5767 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5768 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5769
5770 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5771 bnx2x_cl45_write(bp, phy,
5772 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
5773 bnx2x_cl45_write(bp, phy,
5774 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
5775 } else {
5776 /*
5777 * Since the 8727 has only single reset pin, need to set the 10G
5778 * registers although it is default
5779 */
5780 bnx2x_cl45_write(bp, phy,
5781 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
5782 0x0020);
5783 bnx2x_cl45_write(bp, phy,
5784 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
5785 bnx2x_cl45_write(bp, phy,
5786 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
5787 bnx2x_cl45_write(bp, phy,
5788 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
5789 0x0008);
5790 }
5791
5792 /*
5793 * Set 2-wire transfer rate of SFP+ module EEPROM
5794 * to 100Khz since some DACs(direct attached cables) do
5795 * not work at 400Khz.
5796 */
5797 bnx2x_cl45_write(bp, phy,
5798 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
5799 0xa001);
5800
5801 /* Set TX PreEmphasis if needed */
5802 if ((params->feature_config_flags &
5803 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5804 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
5805 phy->tx_preemphasis[0],
5806 phy->tx_preemphasis[1]);
5807 bnx2x_cl45_write(bp, phy,
5808 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
5809 phy->tx_preemphasis[0]);
5810
5811 bnx2x_cl45_write(bp, phy,
5812 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
5813 phy->tx_preemphasis[1]);
5814 }
5815
5816 /*
5817 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
5818 * power mode, if TX Laser is disabled
5819 */
5820 tx_en_mode = REG_RD(bp, params->shmem_base +
5821 offsetof(struct shmem_region,
5822 dev_info.port_hw_config[params->port].sfp_ctrl))
5823 & PORT_HW_CFG_TX_LASER_MASK;
5824
5825 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
5826
5827 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
5828 bnx2x_cl45_read(bp, phy,
5829 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
5830 tmp2 |= 0x1000;
5831 tmp2 &= 0xFFEF;
5832 bnx2x_cl45_write(bp, phy,
5833 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
5834 }
5835
5836 return 0;
5837 }
5838
5839 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
5840 struct link_params *params)
5841 {
5842 struct bnx2x *bp = params->bp;
5843 u16 mod_abs, rx_alarm_status;
5844 u32 val = REG_RD(bp, params->shmem_base +
5845 offsetof(struct shmem_region, dev_info.
5846 port_feature_config[params->port].
5847 config));
5848 bnx2x_cl45_read(bp, phy,
5849 MDIO_PMA_DEVAD,
5850 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5851 if (mod_abs & (1<<8)) {
5852
5853 /* Module is absent */
5854 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5855 "show module is absent\n");
5856 phy->media_type = ETH_PHY_NOT_PRESENT;
5857 /*
5858 * 1. Set mod_abs to detect next module
5859 * presence event
5860 * 2. Set EDC off by setting OPTXLOS signal input to low
5861 * (bit 9).
5862 * When the EDC is off it locks onto a reference clock and
5863 * avoids becoming 'lost'.
5864 */
5865 mod_abs &= ~(1<<8);
5866 if (!(phy->flags & FLAGS_NOC))
5867 mod_abs &= ~(1<<9);
5868 bnx2x_cl45_write(bp, phy,
5869 MDIO_PMA_DEVAD,
5870 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5871
5872 /*
5873 * Clear RX alarm since it stays up as long as
5874 * the mod_abs wasn't changed
5875 */
5876 bnx2x_cl45_read(bp, phy,
5877 MDIO_PMA_DEVAD,
5878 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5879
5880 } else {
5881 /* Module is present */
5882 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5883 "show module is present\n");
5884 /*
5885 * First disable transmitter, and if the module is ok, the
5886 * module_detection will enable it
5887 * 1. Set mod_abs to detect next module absent event ( bit 8)
5888 * 2. Restore the default polarity of the OPRXLOS signal and
5889 * this signal will then correctly indicate the presence or
5890 * absence of the Rx signal. (bit 9)
5891 */
5892 mod_abs |= (1<<8);
5893 if (!(phy->flags & FLAGS_NOC))
5894 mod_abs |= (1<<9);
5895 bnx2x_cl45_write(bp, phy,
5896 MDIO_PMA_DEVAD,
5897 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5898
5899 /*
5900 * Clear RX alarm since it stays up as long as the mod_abs
5901 * wasn't changed. This is need to be done before calling the
5902 * module detection, otherwise it will clear* the link update
5903 * alarm
5904 */
5905 bnx2x_cl45_read(bp, phy,
5906 MDIO_PMA_DEVAD,
5907 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5908
5909
5910 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5911 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5912 bnx2x_sfp_set_transmitter(params, phy, 0);
5913
5914 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5915 bnx2x_sfp_module_detection(phy, params);
5916 else
5917 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5918 }
5919
5920 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
5921 rx_alarm_status);
5922 /* No need to check link status in case of module plugged in/out */
5923 }
5924
5925 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
5926 struct link_params *params,
5927 struct link_vars *vars)
5928
5929 {
5930 struct bnx2x *bp = params->bp;
5931 u8 link_up = 0;
5932 u16 link_status = 0;
5933 u16 rx_alarm_status, lasi_ctrl, val1;
5934
5935 /* If PHY is not initialized, do not check link status */
5936 bnx2x_cl45_read(bp, phy,
5937 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5938 &lasi_ctrl);
5939 if (!lasi_ctrl)
5940 return 0;
5941
5942 /* Check the LASI */
5943 bnx2x_cl45_read(bp, phy,
5944 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
5945 &rx_alarm_status);
5946 vars->line_speed = 0;
5947 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
5948
5949 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_REG_TX_ALARM,
5950 MDIO_PMA_REG_TX_ALARM_CTRL);
5951
5952 bnx2x_cl45_read(bp, phy,
5953 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5954
5955 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
5956
5957 /* Clear MSG-OUT */
5958 bnx2x_cl45_read(bp, phy,
5959 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
5960
5961 /*
5962 * If a module is present and there is need to check
5963 * for over current
5964 */
5965 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
5966 /* Check over-current using 8727 GPIO0 input*/
5967 bnx2x_cl45_read(bp, phy,
5968 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
5969 &val1);
5970
5971 if ((val1 & (1<<8)) == 0) {
5972 DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
5973 " on port %d\n", params->port);
5974 netdev_err(bp->dev, "Error: Power fault on Port %d has"
5975 " been detected and the power to "
5976 "that SFP+ module has been removed"
5977 " to prevent failure of the card."
5978 " Please remove the SFP+ module and"
5979 " restart the system to clear this"
5980 " error.\n",
5981 params->port);
5982 /* Disable all RX_ALARMs except for mod_abs */
5983 bnx2x_cl45_write(bp, phy,
5984 MDIO_PMA_DEVAD,
5985 MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
5986
5987 bnx2x_cl45_read(bp, phy,
5988 MDIO_PMA_DEVAD,
5989 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5990 /* Wait for module_absent_event */
5991 val1 |= (1<<8);
5992 bnx2x_cl45_write(bp, phy,
5993 MDIO_PMA_DEVAD,
5994 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
5995 /* Clear RX alarm */
5996 bnx2x_cl45_read(bp, phy,
5997 MDIO_PMA_DEVAD,
5998 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5999 return 0;
6000 }
6001 } /* Over current check */
6002
6003 /* When module absent bit is set, check module */
6004 if (rx_alarm_status & (1<<5)) {
6005 bnx2x_8727_handle_mod_abs(phy, params);
6006 /* Enable all mod_abs and link detection bits */
6007 bnx2x_cl45_write(bp, phy,
6008 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
6009 ((1<<5) | (1<<2)));
6010 }
6011 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
6012 bnx2x_8727_specific_func(phy, params, ENABLE_TX);
6013 /* If transmitter is disabled, ignore false link up indication */
6014 bnx2x_cl45_read(bp, phy,
6015 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
6016 if (val1 & (1<<15)) {
6017 DP(NETIF_MSG_LINK, "Tx is disabled\n");
6018 return 0;
6019 }
6020
6021 bnx2x_cl45_read(bp, phy,
6022 MDIO_PMA_DEVAD,
6023 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
6024
6025 /*
6026 * Bits 0..2 --> speed detected,
6027 * Bits 13..15--> link is down
6028 */
6029 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
6030 link_up = 1;
6031 vars->line_speed = SPEED_10000;
6032 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
6033 params->port);
6034 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
6035 link_up = 1;
6036 vars->line_speed = SPEED_1000;
6037 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
6038 params->port);
6039 } else {
6040 link_up = 0;
6041 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
6042 params->port);
6043 }
6044
6045 /* Capture 10G link fault. */
6046 if (vars->line_speed == SPEED_10000) {
6047 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6048 MDIO_PMA_REG_TX_ALARM, &val1);
6049
6050 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6051 MDIO_PMA_REG_TX_ALARM, &val1);
6052
6053 if (val1 & (1<<0)) {
6054 vars->fault_detected = 1;
6055 }
6056 }
6057
6058 if (link_up) {
6059 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6060 vars->duplex = DUPLEX_FULL;
6061 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
6062 }
6063
6064 if ((DUAL_MEDIA(params)) &&
6065 (phy->req_line_speed == SPEED_1000)) {
6066 bnx2x_cl45_read(bp, phy,
6067 MDIO_PMA_DEVAD,
6068 MDIO_PMA_REG_8727_PCS_GP, &val1);
6069 /*
6070 * In case of dual-media board and 1G, power up the XAUI side,
6071 * otherwise power it down. For 10G it is done automatically
6072 */
6073 if (link_up)
6074 val1 &= ~(3<<10);
6075 else
6076 val1 |= (3<<10);
6077 bnx2x_cl45_write(bp, phy,
6078 MDIO_PMA_DEVAD,
6079 MDIO_PMA_REG_8727_PCS_GP, val1);
6080 }
6081 return link_up;
6082 }
6083
6084 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
6085 struct link_params *params)
6086 {
6087 struct bnx2x *bp = params->bp;
6088 /* Disable Transmitter */
6089 bnx2x_sfp_set_transmitter(params, phy, 0);
6090 /* Clear LASI */
6091 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
6092
6093 }
6094
6095 /******************************************************************/
6096 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
6097 /******************************************************************/
6098 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
6099 struct link_params *params)
6100 {
6101 u16 val, fw_ver1, fw_ver2, cnt, adj;
6102 struct bnx2x *bp = params->bp;
6103
6104 adj = 0;
6105 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6106 adj = -1;
6107
6108 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
6109 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
6110 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819 + adj, 0x0014);
6111 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A + adj, 0xc200);
6112 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B + adj, 0x0000);
6113 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C + adj, 0x0300);
6114 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817 + adj, 0x0009);
6115
6116 for (cnt = 0; cnt < 100; cnt++) {
6117 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818 + adj, &val);
6118 if (val & 1)
6119 break;
6120 udelay(5);
6121 }
6122 if (cnt == 100) {
6123 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
6124 bnx2x_save_spirom_version(bp, params->port, 0,
6125 phy->ver_addr);
6126 return;
6127 }
6128
6129
6130 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
6131 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819 + adj, 0x0000);
6132 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A + adj, 0xc200);
6133 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817 + adj, 0x000A);
6134 for (cnt = 0; cnt < 100; cnt++) {
6135 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818 + adj, &val);
6136 if (val & 1)
6137 break;
6138 udelay(5);
6139 }
6140 if (cnt == 100) {
6141 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
6142 bnx2x_save_spirom_version(bp, params->port, 0,
6143 phy->ver_addr);
6144 return;
6145 }
6146
6147 /* lower 16 bits of the register SPI_FW_STATUS */
6148 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B + adj, &fw_ver1);
6149 /* upper 16 bits of register SPI_FW_STATUS */
6150 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C + adj, &fw_ver2);
6151
6152 bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1,
6153 phy->ver_addr);
6154 }
6155
6156 static void bnx2x_848xx_set_led(struct bnx2x *bp,
6157 struct bnx2x_phy *phy)
6158 {
6159 u16 val, adj;
6160
6161 adj = 0;
6162 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6163 adj = -1;
6164
6165 /* PHYC_CTL_LED_CTL */
6166 bnx2x_cl45_read(bp, phy,
6167 MDIO_PMA_DEVAD,
6168 MDIO_PMA_REG_8481_LINK_SIGNAL + adj, &val);
6169 val &= 0xFE00;
6170 val |= 0x0092;
6171
6172 bnx2x_cl45_write(bp, phy,
6173 MDIO_PMA_DEVAD,
6174 MDIO_PMA_REG_8481_LINK_SIGNAL + adj, val);
6175
6176 bnx2x_cl45_write(bp, phy,
6177 MDIO_PMA_DEVAD,
6178 MDIO_PMA_REG_8481_LED1_MASK + adj,
6179 0x80);
6180
6181 bnx2x_cl45_write(bp, phy,
6182 MDIO_PMA_DEVAD,
6183 MDIO_PMA_REG_8481_LED2_MASK + adj,
6184 0x18);
6185
6186 /* Select activity source by Tx and Rx, as suggested by PHY AE */
6187 bnx2x_cl45_write(bp, phy,
6188 MDIO_PMA_DEVAD,
6189 MDIO_PMA_REG_8481_LED3_MASK + adj,
6190 0x0006);
6191
6192 /* Select the closest activity blink rate to that in 10/100/1000 */
6193 bnx2x_cl45_write(bp, phy,
6194 MDIO_PMA_DEVAD,
6195 MDIO_PMA_REG_8481_LED3_BLINK + adj,
6196 0);
6197
6198 bnx2x_cl45_read(bp, phy,
6199 MDIO_PMA_DEVAD,
6200 MDIO_PMA_REG_84823_CTL_LED_CTL_1 + adj, &val);
6201 val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
6202
6203 bnx2x_cl45_write(bp, phy,
6204 MDIO_PMA_DEVAD,
6205 MDIO_PMA_REG_84823_CTL_LED_CTL_1 + adj, val);
6206
6207 /* 'Interrupt Mask' */
6208 bnx2x_cl45_write(bp, phy,
6209 MDIO_AN_DEVAD,
6210 0xFFFB, 0xFFFD);
6211 }
6212
6213 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
6214 struct link_params *params,
6215 struct link_vars *vars)
6216 {
6217 struct bnx2x *bp = params->bp;
6218 u16 autoneg_val, an_1000_val, an_10_100_val;
6219 /*
6220 * This phy uses the NIG latch mechanism since link indication
6221 * arrives through its LED4 and not via its LASI signal, so we
6222 * get steady signal instead of clear on read
6223 */
6224 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
6225 1 << NIG_LATCH_BC_ENABLE_MI_INT);
6226
6227 bnx2x_cl45_write(bp, phy,
6228 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
6229
6230 bnx2x_848xx_set_led(bp, phy);
6231
6232 /* set 1000 speed advertisement */
6233 bnx2x_cl45_read(bp, phy,
6234 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6235 &an_1000_val);
6236
6237 bnx2x_ext_phy_set_pause(params, phy, vars);
6238 bnx2x_cl45_read(bp, phy,
6239 MDIO_AN_DEVAD,
6240 MDIO_AN_REG_8481_LEGACY_AN_ADV,
6241 &an_10_100_val);
6242 bnx2x_cl45_read(bp, phy,
6243 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
6244 &autoneg_val);
6245 /* Disable forced speed */
6246 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
6247 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
6248
6249 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6250 (phy->speed_cap_mask &
6251 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6252 (phy->req_line_speed == SPEED_1000)) {
6253 an_1000_val |= (1<<8);
6254 autoneg_val |= (1<<9 | 1<<12);
6255 if (phy->req_duplex == DUPLEX_FULL)
6256 an_1000_val |= (1<<9);
6257 DP(NETIF_MSG_LINK, "Advertising 1G\n");
6258 } else
6259 an_1000_val &= ~((1<<8) | (1<<9));
6260
6261 bnx2x_cl45_write(bp, phy,
6262 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
6263 an_1000_val);
6264
6265 /* set 10 speed advertisement */
6266 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6267 (phy->speed_cap_mask &
6268 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
6269 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
6270 an_10_100_val |= (1<<7);
6271 /* Enable autoneg and restart autoneg for legacy speeds */
6272 autoneg_val |= (1<<9 | 1<<12);
6273
6274 if (phy->req_duplex == DUPLEX_FULL)
6275 an_10_100_val |= (1<<8);
6276 DP(NETIF_MSG_LINK, "Advertising 100M\n");
6277 }
6278 /* set 10 speed advertisement */
6279 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6280 (phy->speed_cap_mask &
6281 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
6282 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
6283 an_10_100_val |= (1<<5);
6284 autoneg_val |= (1<<9 | 1<<12);
6285 if (phy->req_duplex == DUPLEX_FULL)
6286 an_10_100_val |= (1<<6);
6287 DP(NETIF_MSG_LINK, "Advertising 10M\n");
6288 }
6289
6290 /* Only 10/100 are allowed to work in FORCE mode */
6291 if (phy->req_line_speed == SPEED_100) {
6292 autoneg_val |= (1<<13);
6293 /* Enabled AUTO-MDIX when autoneg is disabled */
6294 bnx2x_cl45_write(bp, phy,
6295 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6296 (1<<15 | 1<<9 | 7<<0));
6297 DP(NETIF_MSG_LINK, "Setting 100M force\n");
6298 }
6299 if (phy->req_line_speed == SPEED_10) {
6300 /* Enabled AUTO-MDIX when autoneg is disabled */
6301 bnx2x_cl45_write(bp, phy,
6302 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
6303 (1<<15 | 1<<9 | 7<<0));
6304 DP(NETIF_MSG_LINK, "Setting 10M force\n");
6305 }
6306
6307 bnx2x_cl45_write(bp, phy,
6308 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
6309 an_10_100_val);
6310
6311 if (phy->req_duplex == DUPLEX_FULL)
6312 autoneg_val |= (1<<8);
6313
6314 bnx2x_cl45_write(bp, phy,
6315 MDIO_AN_DEVAD,
6316 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
6317
6318 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
6319 (phy->speed_cap_mask &
6320 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
6321 (phy->req_line_speed == SPEED_10000)) {
6322 DP(NETIF_MSG_LINK, "Advertising 10G\n");
6323 /* Restart autoneg for 10G*/
6324
6325 bnx2x_cl45_write(bp, phy,
6326 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
6327 0x3200);
6328 } else if (phy->req_line_speed != SPEED_10 &&
6329 phy->req_line_speed != SPEED_100) {
6330 bnx2x_cl45_write(bp, phy,
6331 MDIO_AN_DEVAD,
6332 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
6333 1);
6334 }
6335 /* Save spirom version */
6336 bnx2x_save_848xx_spirom_version(phy, params);
6337
6338 return 0;
6339 }
6340
6341 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
6342 struct link_params *params,
6343 struct link_vars *vars)
6344 {
6345 struct bnx2x *bp = params->bp;
6346 /* Restore normal power mode*/
6347 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6348 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6349
6350 /* HW reset */
6351 bnx2x_ext_phy_hw_reset(bp, params->port);
6352 bnx2x_wait_reset_complete(bp, phy, params);
6353
6354 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6355 return bnx2x_848xx_cmn_config_init(phy, params, vars);
6356 }
6357
6358 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
6359 struct link_params *params,
6360 struct link_vars *vars)
6361 {
6362 struct bnx2x *bp = params->bp;
6363 u8 port, initialize = 1;
6364 u16 val, adj;
6365 u16 temp;
6366 u32 actual_phy_selection, cms_enable;
6367 int rc = 0;
6368
6369 /* This is just for MDIO_CTL_REG_84823_MEDIA register. */
6370 adj = 0;
6371 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6372 adj = 3;
6373
6374 msleep(1);
6375 if (CHIP_IS_E2(bp))
6376 port = BP_PATH(bp);
6377 else
6378 port = params->port;
6379 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6380 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
6381 port);
6382 bnx2x_wait_reset_complete(bp, phy, params);
6383 /* Wait for GPHY to come out of reset */
6384 msleep(50);
6385 /*
6386 * BCM84823 requires that XGXS links up first @ 10G for normal behavior
6387 */
6388 temp = vars->line_speed;
6389 vars->line_speed = SPEED_10000;
6390 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
6391 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
6392 vars->line_speed = temp;
6393
6394 /* Set dual-media configuration according to configuration */
6395
6396 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6397 MDIO_CTL_REG_84823_MEDIA + adj, &val);
6398 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
6399 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
6400 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
6401 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
6402 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
6403 val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI |
6404 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L;
6405
6406 actual_phy_selection = bnx2x_phy_selection(params);
6407
6408 switch (actual_phy_selection) {
6409 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6410 /* Do nothing. Essentially this is like the priority copper */
6411 break;
6412 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6413 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
6414 break;
6415 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6416 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
6417 break;
6418 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6419 /* Do nothing here. The first PHY won't be initialized at all */
6420 break;
6421 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6422 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
6423 initialize = 0;
6424 break;
6425 }
6426 if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
6427 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
6428
6429 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6430 MDIO_CTL_REG_84823_MEDIA + adj, val);
6431 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
6432 params->multi_phy_config, val);
6433
6434 if (initialize)
6435 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
6436 else
6437 bnx2x_save_848xx_spirom_version(phy, params);
6438 cms_enable = REG_RD(bp, params->shmem_base +
6439 offsetof(struct shmem_region,
6440 dev_info.port_hw_config[params->port].default_cfg)) &
6441 PORT_HW_CFG_ENABLE_CMS_MASK;
6442
6443 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6444 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
6445 if (cms_enable)
6446 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
6447 else
6448 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
6449 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6450 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
6451
6452
6453 return rc;
6454 }
6455
6456 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
6457 struct link_params *params,
6458 struct link_vars *vars)
6459 {
6460 struct bnx2x *bp = params->bp;
6461 u16 val, val1, val2, adj;
6462 u8 link_up = 0;
6463
6464 /* Reg offset adjustment for 84833 */
6465 adj = 0;
6466 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
6467 adj = -1;
6468
6469 /* Check 10G-BaseT link status */
6470 /* Check PMD signal ok */
6471 bnx2x_cl45_read(bp, phy,
6472 MDIO_AN_DEVAD, 0xFFFA, &val1);
6473 bnx2x_cl45_read(bp, phy,
6474 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL + adj,
6475 &val2);
6476 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
6477
6478 /* Check link 10G */
6479 if (val2 & (1<<11)) {
6480 vars->line_speed = SPEED_10000;
6481 vars->duplex = DUPLEX_FULL;
6482 link_up = 1;
6483 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6484 } else { /* Check Legacy speed link */
6485 u16 legacy_status, legacy_speed;
6486
6487 /* Enable expansion register 0x42 (Operation mode status) */
6488 bnx2x_cl45_write(bp, phy,
6489 MDIO_AN_DEVAD,
6490 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
6491
6492 /* Get legacy speed operation status */
6493 bnx2x_cl45_read(bp, phy,
6494 MDIO_AN_DEVAD,
6495 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
6496 &legacy_status);
6497
6498 DP(NETIF_MSG_LINK, "Legacy speed status"
6499 " = 0x%x\n", legacy_status);
6500 link_up = ((legacy_status & (1<<11)) == (1<<11));
6501 if (link_up) {
6502 legacy_speed = (legacy_status & (3<<9));
6503 if (legacy_speed == (0<<9))
6504 vars->line_speed = SPEED_10;
6505 else if (legacy_speed == (1<<9))
6506 vars->line_speed = SPEED_100;
6507 else if (legacy_speed == (2<<9))
6508 vars->line_speed = SPEED_1000;
6509 else /* Should not happen */
6510 vars->line_speed = 0;
6511
6512 if (legacy_status & (1<<8))
6513 vars->duplex = DUPLEX_FULL;
6514 else
6515 vars->duplex = DUPLEX_HALF;
6516
6517 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
6518 " is_duplex_full= %d\n", vars->line_speed,
6519 (vars->duplex == DUPLEX_FULL));
6520 /* Check legacy speed AN resolution */
6521 bnx2x_cl45_read(bp, phy,
6522 MDIO_AN_DEVAD,
6523 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
6524 &val);
6525 if (val & (1<<5))
6526 vars->link_status |=
6527 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6528 bnx2x_cl45_read(bp, phy,
6529 MDIO_AN_DEVAD,
6530 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
6531 &val);
6532 if ((val & (1<<0)) == 0)
6533 vars->link_status |=
6534 LINK_STATUS_PARALLEL_DETECTION_USED;
6535 }
6536 }
6537 if (link_up) {
6538 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
6539 vars->line_speed);
6540 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6541 }
6542
6543 return link_up;
6544 }
6545
6546
6547 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
6548 {
6549 int status = 0;
6550 u32 spirom_ver;
6551 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
6552 status = bnx2x_format_ver(spirom_ver, str, len);
6553 return status;
6554 }
6555
6556 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
6557 struct link_params *params)
6558 {
6559 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6560 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
6561 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6562 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
6563 }
6564
6565 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
6566 struct link_params *params)
6567 {
6568 bnx2x_cl45_write(params->bp, phy,
6569 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6570 bnx2x_cl45_write(params->bp, phy,
6571 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
6572 }
6573
6574 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
6575 struct link_params *params)
6576 {
6577 struct bnx2x *bp = params->bp;
6578 u8 port;
6579 if (CHIP_IS_E2(bp))
6580 port = BP_PATH(bp);
6581 else
6582 port = params->port;
6583 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6584 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6585 port);
6586 }
6587
6588 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6589 struct link_params *params, u8 mode)
6590 {
6591 struct bnx2x *bp = params->bp;
6592 u16 val;
6593
6594 switch (mode) {
6595 case LED_MODE_OFF:
6596
6597 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", params->port);
6598
6599 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6600 SHARED_HW_CFG_LED_EXTPHY1) {
6601
6602 /* Set LED masks */
6603 bnx2x_cl45_write(bp, phy,
6604 MDIO_PMA_DEVAD,
6605 MDIO_PMA_REG_8481_LED1_MASK,
6606 0x0);
6607
6608 bnx2x_cl45_write(bp, phy,
6609 MDIO_PMA_DEVAD,
6610 MDIO_PMA_REG_8481_LED2_MASK,
6611 0x0);
6612
6613 bnx2x_cl45_write(bp, phy,
6614 MDIO_PMA_DEVAD,
6615 MDIO_PMA_REG_8481_LED3_MASK,
6616 0x0);
6617
6618 bnx2x_cl45_write(bp, phy,
6619 MDIO_PMA_DEVAD,
6620 MDIO_PMA_REG_8481_LED5_MASK,
6621 0x0);
6622
6623 } else {
6624 bnx2x_cl45_write(bp, phy,
6625 MDIO_PMA_DEVAD,
6626 MDIO_PMA_REG_8481_LED1_MASK,
6627 0x0);
6628 }
6629 break;
6630 case LED_MODE_FRONT_PANEL_OFF:
6631
6632 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
6633 params->port);
6634
6635 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6636 SHARED_HW_CFG_LED_EXTPHY1) {
6637
6638 /* Set LED masks */
6639 bnx2x_cl45_write(bp, phy,
6640 MDIO_PMA_DEVAD,
6641 MDIO_PMA_REG_8481_LED1_MASK,
6642 0x0);
6643
6644 bnx2x_cl45_write(bp, phy,
6645 MDIO_PMA_DEVAD,
6646 MDIO_PMA_REG_8481_LED2_MASK,
6647 0x0);
6648
6649 bnx2x_cl45_write(bp, phy,
6650 MDIO_PMA_DEVAD,
6651 MDIO_PMA_REG_8481_LED3_MASK,
6652 0x0);
6653
6654 bnx2x_cl45_write(bp, phy,
6655 MDIO_PMA_DEVAD,
6656 MDIO_PMA_REG_8481_LED5_MASK,
6657 0x20);
6658
6659 } else {
6660 bnx2x_cl45_write(bp, phy,
6661 MDIO_PMA_DEVAD,
6662 MDIO_PMA_REG_8481_LED1_MASK,
6663 0x0);
6664 }
6665 break;
6666 case LED_MODE_ON:
6667
6668 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", params->port);
6669
6670 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6671 SHARED_HW_CFG_LED_EXTPHY1) {
6672 /* Set control reg */
6673 bnx2x_cl45_read(bp, phy,
6674 MDIO_PMA_DEVAD,
6675 MDIO_PMA_REG_8481_LINK_SIGNAL,
6676 &val);
6677 val &= 0x8000;
6678 val |= 0x2492;
6679
6680 bnx2x_cl45_write(bp, phy,
6681 MDIO_PMA_DEVAD,
6682 MDIO_PMA_REG_8481_LINK_SIGNAL,
6683 val);
6684
6685 /* Set LED masks */
6686 bnx2x_cl45_write(bp, phy,
6687 MDIO_PMA_DEVAD,
6688 MDIO_PMA_REG_8481_LED1_MASK,
6689 0x0);
6690
6691 bnx2x_cl45_write(bp, phy,
6692 MDIO_PMA_DEVAD,
6693 MDIO_PMA_REG_8481_LED2_MASK,
6694 0x20);
6695
6696 bnx2x_cl45_write(bp, phy,
6697 MDIO_PMA_DEVAD,
6698 MDIO_PMA_REG_8481_LED3_MASK,
6699 0x20);
6700
6701 bnx2x_cl45_write(bp, phy,
6702 MDIO_PMA_DEVAD,
6703 MDIO_PMA_REG_8481_LED5_MASK,
6704 0x0);
6705 } else {
6706 bnx2x_cl45_write(bp, phy,
6707 MDIO_PMA_DEVAD,
6708 MDIO_PMA_REG_8481_LED1_MASK,
6709 0x20);
6710 }
6711 break;
6712
6713 case LED_MODE_OPER:
6714
6715 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", params->port);
6716
6717 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6718 SHARED_HW_CFG_LED_EXTPHY1) {
6719
6720 /* Set control reg */
6721 bnx2x_cl45_read(bp, phy,
6722 MDIO_PMA_DEVAD,
6723 MDIO_PMA_REG_8481_LINK_SIGNAL,
6724 &val);
6725
6726 if (!((val &
6727 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
6728 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
6729 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
6730 bnx2x_cl45_write(bp, phy,
6731 MDIO_PMA_DEVAD,
6732 MDIO_PMA_REG_8481_LINK_SIGNAL,
6733 0xa492);
6734 }
6735
6736 /* Set LED masks */
6737 bnx2x_cl45_write(bp, phy,
6738 MDIO_PMA_DEVAD,
6739 MDIO_PMA_REG_8481_LED1_MASK,
6740 0x10);
6741
6742 bnx2x_cl45_write(bp, phy,
6743 MDIO_PMA_DEVAD,
6744 MDIO_PMA_REG_8481_LED2_MASK,
6745 0x80);
6746
6747 bnx2x_cl45_write(bp, phy,
6748 MDIO_PMA_DEVAD,
6749 MDIO_PMA_REG_8481_LED3_MASK,
6750 0x98);
6751
6752 bnx2x_cl45_write(bp, phy,
6753 MDIO_PMA_DEVAD,
6754 MDIO_PMA_REG_8481_LED5_MASK,
6755 0x40);
6756
6757 } else {
6758 bnx2x_cl45_write(bp, phy,
6759 MDIO_PMA_DEVAD,
6760 MDIO_PMA_REG_8481_LED1_MASK,
6761 0x80);
6762
6763 /* Tell LED3 to blink on source */
6764 bnx2x_cl45_read(bp, phy,
6765 MDIO_PMA_DEVAD,
6766 MDIO_PMA_REG_8481_LINK_SIGNAL,
6767 &val);
6768 val &= ~(7<<6);
6769 val |= (1<<6); /* A83B[8:6]= 1 */
6770 bnx2x_cl45_write(bp, phy,
6771 MDIO_PMA_DEVAD,
6772 MDIO_PMA_REG_8481_LINK_SIGNAL,
6773 val);
6774 }
6775 break;
6776 }
6777 }
6778 /******************************************************************/
6779 /* SFX7101 PHY SECTION */
6780 /******************************************************************/
6781 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
6782 struct link_params *params)
6783 {
6784 struct bnx2x *bp = params->bp;
6785 /* SFX7101_XGXS_TEST1 */
6786 bnx2x_cl45_write(bp, phy,
6787 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
6788 }
6789
6790 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
6791 struct link_params *params,
6792 struct link_vars *vars)
6793 {
6794 u16 fw_ver1, fw_ver2, val;
6795 struct bnx2x *bp = params->bp;
6796 DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
6797
6798 /* Restore normal power mode*/
6799 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6800 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6801 /* HW reset */
6802 bnx2x_ext_phy_hw_reset(bp, params->port);
6803 bnx2x_wait_reset_complete(bp, phy, params);
6804
6805 bnx2x_cl45_write(bp, phy,
6806 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
6807 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
6808 bnx2x_cl45_write(bp, phy,
6809 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
6810
6811 bnx2x_ext_phy_set_pause(params, phy, vars);
6812 /* Restart autoneg */
6813 bnx2x_cl45_read(bp, phy,
6814 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
6815 val |= 0x200;
6816 bnx2x_cl45_write(bp, phy,
6817 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
6818
6819 /* Save spirom version */
6820 bnx2x_cl45_read(bp, phy,
6821 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
6822
6823 bnx2x_cl45_read(bp, phy,
6824 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
6825 bnx2x_save_spirom_version(bp, params->port,
6826 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
6827 return 0;
6828 }
6829
6830 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
6831 struct link_params *params,
6832 struct link_vars *vars)
6833 {
6834 struct bnx2x *bp = params->bp;
6835 u8 link_up;
6836 u16 val1, val2;
6837 bnx2x_cl45_read(bp, phy,
6838 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
6839 bnx2x_cl45_read(bp, phy,
6840 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
6841 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
6842 val2, val1);
6843 bnx2x_cl45_read(bp, phy,
6844 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6845 bnx2x_cl45_read(bp, phy,
6846 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6847 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
6848 val2, val1);
6849 link_up = ((val1 & 4) == 4);
6850 /* if link is up print the AN outcome of the SFX7101 PHY */
6851 if (link_up) {
6852 bnx2x_cl45_read(bp, phy,
6853 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
6854 &val2);
6855 vars->line_speed = SPEED_10000;
6856 vars->duplex = DUPLEX_FULL;
6857 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
6858 val2, (val2 & (1<<14)));
6859 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6860 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6861 }
6862 return link_up;
6863 }
6864
6865 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6866 {
6867 if (*len < 5)
6868 return -EINVAL;
6869 str[0] = (spirom_ver & 0xFF);
6870 str[1] = (spirom_ver & 0xFF00) >> 8;
6871 str[2] = (spirom_ver & 0xFF0000) >> 16;
6872 str[3] = (spirom_ver & 0xFF000000) >> 24;
6873 str[4] = '\0';
6874 *len -= 5;
6875 return 0;
6876 }
6877
6878 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
6879 {
6880 u16 val, cnt;
6881
6882 bnx2x_cl45_read(bp, phy,
6883 MDIO_PMA_DEVAD,
6884 MDIO_PMA_REG_7101_RESET, &val);
6885
6886 for (cnt = 0; cnt < 10; cnt++) {
6887 msleep(50);
6888 /* Writes a self-clearing reset */
6889 bnx2x_cl45_write(bp, phy,
6890 MDIO_PMA_DEVAD,
6891 MDIO_PMA_REG_7101_RESET,
6892 (val | (1<<15)));
6893 /* Wait for clear */
6894 bnx2x_cl45_read(bp, phy,
6895 MDIO_PMA_DEVAD,
6896 MDIO_PMA_REG_7101_RESET, &val);
6897
6898 if ((val & (1<<15)) == 0)
6899 break;
6900 }
6901 }
6902
6903 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
6904 struct link_params *params) {
6905 /* Low power mode is controlled by GPIO 2 */
6906 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
6907 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6908 /* The PHY reset is controlled by GPIO 1 */
6909 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6910 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6911 }
6912
6913 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
6914 struct link_params *params, u8 mode)
6915 {
6916 u16 val = 0;
6917 struct bnx2x *bp = params->bp;
6918 switch (mode) {
6919 case LED_MODE_FRONT_PANEL_OFF:
6920 case LED_MODE_OFF:
6921 val = 2;
6922 break;
6923 case LED_MODE_ON:
6924 val = 1;
6925 break;
6926 case LED_MODE_OPER:
6927 val = 0;
6928 break;
6929 }
6930 bnx2x_cl45_write(bp, phy,
6931 MDIO_PMA_DEVAD,
6932 MDIO_PMA_REG_7107_LINK_LED_CNTL,
6933 val);
6934 }
6935
6936 /******************************************************************/
6937 /* STATIC PHY DECLARATION */
6938 /******************************************************************/
6939
6940 static struct bnx2x_phy phy_null = {
6941 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
6942 .addr = 0,
6943 .flags = FLAGS_INIT_XGXS_FIRST,
6944 .def_md_devad = 0,
6945 .reserved = 0,
6946 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6947 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6948 .mdio_ctrl = 0,
6949 .supported = 0,
6950 .media_type = ETH_PHY_NOT_PRESENT,
6951 .ver_addr = 0,
6952 .req_flow_ctrl = 0,
6953 .req_line_speed = 0,
6954 .speed_cap_mask = 0,
6955 .req_duplex = 0,
6956 .rsrv = 0,
6957 .config_init = (config_init_t)NULL,
6958 .read_status = (read_status_t)NULL,
6959 .link_reset = (link_reset_t)NULL,
6960 .config_loopback = (config_loopback_t)NULL,
6961 .format_fw_ver = (format_fw_ver_t)NULL,
6962 .hw_reset = (hw_reset_t)NULL,
6963 .set_link_led = (set_link_led_t)NULL,
6964 .phy_specific_func = (phy_specific_func_t)NULL
6965 };
6966
6967 static struct bnx2x_phy phy_serdes = {
6968 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
6969 .addr = 0xff,
6970 .flags = 0,
6971 .def_md_devad = 0,
6972 .reserved = 0,
6973 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6974 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6975 .mdio_ctrl = 0,
6976 .supported = (SUPPORTED_10baseT_Half |
6977 SUPPORTED_10baseT_Full |
6978 SUPPORTED_100baseT_Half |
6979 SUPPORTED_100baseT_Full |
6980 SUPPORTED_1000baseT_Full |
6981 SUPPORTED_2500baseX_Full |
6982 SUPPORTED_TP |
6983 SUPPORTED_Autoneg |
6984 SUPPORTED_Pause |
6985 SUPPORTED_Asym_Pause),
6986 .media_type = ETH_PHY_BASE_T,
6987 .ver_addr = 0,
6988 .req_flow_ctrl = 0,
6989 .req_line_speed = 0,
6990 .speed_cap_mask = 0,
6991 .req_duplex = 0,
6992 .rsrv = 0,
6993 .config_init = (config_init_t)bnx2x_init_serdes,
6994 .read_status = (read_status_t)bnx2x_link_settings_status,
6995 .link_reset = (link_reset_t)bnx2x_int_link_reset,
6996 .config_loopback = (config_loopback_t)NULL,
6997 .format_fw_ver = (format_fw_ver_t)NULL,
6998 .hw_reset = (hw_reset_t)NULL,
6999 .set_link_led = (set_link_led_t)NULL,
7000 .phy_specific_func = (phy_specific_func_t)NULL
7001 };
7002
7003 static struct bnx2x_phy phy_xgxs = {
7004 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
7005 .addr = 0xff,
7006 .flags = 0,
7007 .def_md_devad = 0,
7008 .reserved = 0,
7009 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7010 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7011 .mdio_ctrl = 0,
7012 .supported = (SUPPORTED_10baseT_Half |
7013 SUPPORTED_10baseT_Full |
7014 SUPPORTED_100baseT_Half |
7015 SUPPORTED_100baseT_Full |
7016 SUPPORTED_1000baseT_Full |
7017 SUPPORTED_2500baseX_Full |
7018 SUPPORTED_10000baseT_Full |
7019 SUPPORTED_FIBRE |
7020 SUPPORTED_Autoneg |
7021 SUPPORTED_Pause |
7022 SUPPORTED_Asym_Pause),
7023 .media_type = ETH_PHY_CX4,
7024 .ver_addr = 0,
7025 .req_flow_ctrl = 0,
7026 .req_line_speed = 0,
7027 .speed_cap_mask = 0,
7028 .req_duplex = 0,
7029 .rsrv = 0,
7030 .config_init = (config_init_t)bnx2x_init_xgxs,
7031 .read_status = (read_status_t)bnx2x_link_settings_status,
7032 .link_reset = (link_reset_t)bnx2x_int_link_reset,
7033 .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
7034 .format_fw_ver = (format_fw_ver_t)NULL,
7035 .hw_reset = (hw_reset_t)NULL,
7036 .set_link_led = (set_link_led_t)NULL,
7037 .phy_specific_func = (phy_specific_func_t)NULL
7038 };
7039
7040 static struct bnx2x_phy phy_7101 = {
7041 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
7042 .addr = 0xff,
7043 .flags = FLAGS_FAN_FAILURE_DET_REQ,
7044 .def_md_devad = 0,
7045 .reserved = 0,
7046 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7047 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7048 .mdio_ctrl = 0,
7049 .supported = (SUPPORTED_10000baseT_Full |
7050 SUPPORTED_TP |
7051 SUPPORTED_Autoneg |
7052 SUPPORTED_Pause |
7053 SUPPORTED_Asym_Pause),
7054 .media_type = ETH_PHY_BASE_T,
7055 .ver_addr = 0,
7056 .req_flow_ctrl = 0,
7057 .req_line_speed = 0,
7058 .speed_cap_mask = 0,
7059 .req_duplex = 0,
7060 .rsrv = 0,
7061 .config_init = (config_init_t)bnx2x_7101_config_init,
7062 .read_status = (read_status_t)bnx2x_7101_read_status,
7063 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
7064 .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
7065 .format_fw_ver = (format_fw_ver_t)bnx2x_7101_format_ver,
7066 .hw_reset = (hw_reset_t)bnx2x_7101_hw_reset,
7067 .set_link_led = (set_link_led_t)bnx2x_7101_set_link_led,
7068 .phy_specific_func = (phy_specific_func_t)NULL
7069 };
7070 static struct bnx2x_phy phy_8073 = {
7071 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
7072 .addr = 0xff,
7073 .flags = FLAGS_HW_LOCK_REQUIRED,
7074 .def_md_devad = 0,
7075 .reserved = 0,
7076 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7077 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7078 .mdio_ctrl = 0,
7079 .supported = (SUPPORTED_10000baseT_Full |
7080 SUPPORTED_2500baseX_Full |
7081 SUPPORTED_1000baseT_Full |
7082 SUPPORTED_FIBRE |
7083 SUPPORTED_Autoneg |
7084 SUPPORTED_Pause |
7085 SUPPORTED_Asym_Pause),
7086 .media_type = ETH_PHY_KR,
7087 .ver_addr = 0,
7088 .req_flow_ctrl = 0,
7089 .req_line_speed = 0,
7090 .speed_cap_mask = 0,
7091 .req_duplex = 0,
7092 .rsrv = 0,
7093 .config_init = (config_init_t)bnx2x_8073_config_init,
7094 .read_status = (read_status_t)bnx2x_8073_read_status,
7095 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
7096 .config_loopback = (config_loopback_t)NULL,
7097 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
7098 .hw_reset = (hw_reset_t)NULL,
7099 .set_link_led = (set_link_led_t)NULL,
7100 .phy_specific_func = (phy_specific_func_t)NULL
7101 };
7102 static struct bnx2x_phy phy_8705 = {
7103 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
7104 .addr = 0xff,
7105 .flags = FLAGS_INIT_XGXS_FIRST,
7106 .def_md_devad = 0,
7107 .reserved = 0,
7108 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7109 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7110 .mdio_ctrl = 0,
7111 .supported = (SUPPORTED_10000baseT_Full |
7112 SUPPORTED_FIBRE |
7113 SUPPORTED_Pause |
7114 SUPPORTED_Asym_Pause),
7115 .media_type = ETH_PHY_XFP_FIBER,
7116 .ver_addr = 0,
7117 .req_flow_ctrl = 0,
7118 .req_line_speed = 0,
7119 .speed_cap_mask = 0,
7120 .req_duplex = 0,
7121 .rsrv = 0,
7122 .config_init = (config_init_t)bnx2x_8705_config_init,
7123 .read_status = (read_status_t)bnx2x_8705_read_status,
7124 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
7125 .config_loopback = (config_loopback_t)NULL,
7126 .format_fw_ver = (format_fw_ver_t)bnx2x_null_format_ver,
7127 .hw_reset = (hw_reset_t)NULL,
7128 .set_link_led = (set_link_led_t)NULL,
7129 .phy_specific_func = (phy_specific_func_t)NULL
7130 };
7131 static struct bnx2x_phy phy_8706 = {
7132 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
7133 .addr = 0xff,
7134 .flags = FLAGS_INIT_XGXS_FIRST,
7135 .def_md_devad = 0,
7136 .reserved = 0,
7137 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7138 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7139 .mdio_ctrl = 0,
7140 .supported = (SUPPORTED_10000baseT_Full |
7141 SUPPORTED_1000baseT_Full |
7142 SUPPORTED_FIBRE |
7143 SUPPORTED_Pause |
7144 SUPPORTED_Asym_Pause),
7145 .media_type = ETH_PHY_SFP_FIBER,
7146 .ver_addr = 0,
7147 .req_flow_ctrl = 0,
7148 .req_line_speed = 0,
7149 .speed_cap_mask = 0,
7150 .req_duplex = 0,
7151 .rsrv = 0,
7152 .config_init = (config_init_t)bnx2x_8706_config_init,
7153 .read_status = (read_status_t)bnx2x_8706_read_status,
7154 .link_reset = (link_reset_t)bnx2x_common_ext_link_reset,
7155 .config_loopback = (config_loopback_t)NULL,
7156 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
7157 .hw_reset = (hw_reset_t)NULL,
7158 .set_link_led = (set_link_led_t)NULL,
7159 .phy_specific_func = (phy_specific_func_t)NULL
7160 };
7161
7162 static struct bnx2x_phy phy_8726 = {
7163 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
7164 .addr = 0xff,
7165 .flags = (FLAGS_HW_LOCK_REQUIRED |
7166 FLAGS_INIT_XGXS_FIRST),
7167 .def_md_devad = 0,
7168 .reserved = 0,
7169 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7170 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7171 .mdio_ctrl = 0,
7172 .supported = (SUPPORTED_10000baseT_Full |
7173 SUPPORTED_1000baseT_Full |
7174 SUPPORTED_Autoneg |
7175 SUPPORTED_FIBRE |
7176 SUPPORTED_Pause |
7177 SUPPORTED_Asym_Pause),
7178 .media_type = ETH_PHY_NOT_PRESENT,
7179 .ver_addr = 0,
7180 .req_flow_ctrl = 0,
7181 .req_line_speed = 0,
7182 .speed_cap_mask = 0,
7183 .req_duplex = 0,
7184 .rsrv = 0,
7185 .config_init = (config_init_t)bnx2x_8726_config_init,
7186 .read_status = (read_status_t)bnx2x_8726_read_status,
7187 .link_reset = (link_reset_t)bnx2x_8726_link_reset,
7188 .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
7189 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
7190 .hw_reset = (hw_reset_t)NULL,
7191 .set_link_led = (set_link_led_t)NULL,
7192 .phy_specific_func = (phy_specific_func_t)NULL
7193 };
7194
7195 static struct bnx2x_phy phy_8727 = {
7196 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
7197 .addr = 0xff,
7198 .flags = FLAGS_FAN_FAILURE_DET_REQ,
7199 .def_md_devad = 0,
7200 .reserved = 0,
7201 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7202 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7203 .mdio_ctrl = 0,
7204 .supported = (SUPPORTED_10000baseT_Full |
7205 SUPPORTED_1000baseT_Full |
7206 SUPPORTED_FIBRE |
7207 SUPPORTED_Pause |
7208 SUPPORTED_Asym_Pause),
7209 .media_type = ETH_PHY_NOT_PRESENT,
7210 .ver_addr = 0,
7211 .req_flow_ctrl = 0,
7212 .req_line_speed = 0,
7213 .speed_cap_mask = 0,
7214 .req_duplex = 0,
7215 .rsrv = 0,
7216 .config_init = (config_init_t)bnx2x_8727_config_init,
7217 .read_status = (read_status_t)bnx2x_8727_read_status,
7218 .link_reset = (link_reset_t)bnx2x_8727_link_reset,
7219 .config_loopback = (config_loopback_t)NULL,
7220 .format_fw_ver = (format_fw_ver_t)bnx2x_format_ver,
7221 .hw_reset = (hw_reset_t)bnx2x_8727_hw_reset,
7222 .set_link_led = (set_link_led_t)bnx2x_8727_set_link_led,
7223 .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
7224 };
7225 static struct bnx2x_phy phy_8481 = {
7226 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
7227 .addr = 0xff,
7228 .flags = FLAGS_FAN_FAILURE_DET_REQ |
7229 FLAGS_REARM_LATCH_SIGNAL,
7230 .def_md_devad = 0,
7231 .reserved = 0,
7232 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7233 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7234 .mdio_ctrl = 0,
7235 .supported = (SUPPORTED_10baseT_Half |
7236 SUPPORTED_10baseT_Full |
7237 SUPPORTED_100baseT_Half |
7238 SUPPORTED_100baseT_Full |
7239 SUPPORTED_1000baseT_Full |
7240 SUPPORTED_10000baseT_Full |
7241 SUPPORTED_TP |
7242 SUPPORTED_Autoneg |
7243 SUPPORTED_Pause |
7244 SUPPORTED_Asym_Pause),
7245 .media_type = ETH_PHY_BASE_T,
7246 .ver_addr = 0,
7247 .req_flow_ctrl = 0,
7248 .req_line_speed = 0,
7249 .speed_cap_mask = 0,
7250 .req_duplex = 0,
7251 .rsrv = 0,
7252 .config_init = (config_init_t)bnx2x_8481_config_init,
7253 .read_status = (read_status_t)bnx2x_848xx_read_status,
7254 .link_reset = (link_reset_t)bnx2x_8481_link_reset,
7255 .config_loopback = (config_loopback_t)NULL,
7256 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
7257 .hw_reset = (hw_reset_t)bnx2x_8481_hw_reset,
7258 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
7259 .phy_specific_func = (phy_specific_func_t)NULL
7260 };
7261
7262 static struct bnx2x_phy phy_84823 = {
7263 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
7264 .addr = 0xff,
7265 .flags = FLAGS_FAN_FAILURE_DET_REQ |
7266 FLAGS_REARM_LATCH_SIGNAL,
7267 .def_md_devad = 0,
7268 .reserved = 0,
7269 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7270 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7271 .mdio_ctrl = 0,
7272 .supported = (SUPPORTED_10baseT_Half |
7273 SUPPORTED_10baseT_Full |
7274 SUPPORTED_100baseT_Half |
7275 SUPPORTED_100baseT_Full |
7276 SUPPORTED_1000baseT_Full |
7277 SUPPORTED_10000baseT_Full |
7278 SUPPORTED_TP |
7279 SUPPORTED_Autoneg |
7280 SUPPORTED_Pause |
7281 SUPPORTED_Asym_Pause),
7282 .media_type = ETH_PHY_BASE_T,
7283 .ver_addr = 0,
7284 .req_flow_ctrl = 0,
7285 .req_line_speed = 0,
7286 .speed_cap_mask = 0,
7287 .req_duplex = 0,
7288 .rsrv = 0,
7289 .config_init = (config_init_t)bnx2x_848x3_config_init,
7290 .read_status = (read_status_t)bnx2x_848xx_read_status,
7291 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
7292 .config_loopback = (config_loopback_t)NULL,
7293 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
7294 .hw_reset = (hw_reset_t)NULL,
7295 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
7296 .phy_specific_func = (phy_specific_func_t)NULL
7297 };
7298
7299 static struct bnx2x_phy phy_84833 = {
7300 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
7301 .addr = 0xff,
7302 .flags = FLAGS_FAN_FAILURE_DET_REQ |
7303 FLAGS_REARM_LATCH_SIGNAL,
7304 .def_md_devad = 0,
7305 .reserved = 0,
7306 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7307 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
7308 .mdio_ctrl = 0,
7309 .supported = (SUPPORTED_10baseT_Half |
7310 SUPPORTED_10baseT_Full |
7311 SUPPORTED_100baseT_Half |
7312 SUPPORTED_100baseT_Full |
7313 SUPPORTED_1000baseT_Full |
7314 SUPPORTED_10000baseT_Full |
7315 SUPPORTED_TP |
7316 SUPPORTED_Autoneg |
7317 SUPPORTED_Pause |
7318 SUPPORTED_Asym_Pause),
7319 .media_type = ETH_PHY_BASE_T,
7320 .ver_addr = 0,
7321 .req_flow_ctrl = 0,
7322 .req_line_speed = 0,
7323 .speed_cap_mask = 0,
7324 .req_duplex = 0,
7325 .rsrv = 0,
7326 .config_init = (config_init_t)bnx2x_848x3_config_init,
7327 .read_status = (read_status_t)bnx2x_848xx_read_status,
7328 .link_reset = (link_reset_t)bnx2x_848x3_link_reset,
7329 .config_loopback = (config_loopback_t)NULL,
7330 .format_fw_ver = (format_fw_ver_t)bnx2x_848xx_format_ver,
7331 .hw_reset = (hw_reset_t)NULL,
7332 .set_link_led = (set_link_led_t)bnx2x_848xx_set_link_led,
7333 .phy_specific_func = (phy_specific_func_t)NULL
7334 };
7335
7336 /*****************************************************************/
7337 /* */
7338 /* Populate the phy according. Main function: bnx2x_populate_phy */
7339 /* */
7340 /*****************************************************************/
7341
7342 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
7343 struct bnx2x_phy *phy, u8 port,
7344 u8 phy_index)
7345 {
7346 /* Get the 4 lanes xgxs config rx and tx */
7347 u32 rx = 0, tx = 0, i;
7348 for (i = 0; i < 2; i++) {
7349 /*
7350 * INT_PHY and EXT_PHY1 share the same value location in the
7351 * shmem. When num_phys is greater than 1, than this value
7352 * applies only to EXT_PHY1
7353 */
7354 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
7355 rx = REG_RD(bp, shmem_base +
7356 offsetof(struct shmem_region,
7357 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
7358
7359 tx = REG_RD(bp, shmem_base +
7360 offsetof(struct shmem_region,
7361 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
7362 } else {
7363 rx = REG_RD(bp, shmem_base +
7364 offsetof(struct shmem_region,
7365 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7366
7367 tx = REG_RD(bp, shmem_base +
7368 offsetof(struct shmem_region,
7369 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
7370 }
7371
7372 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
7373 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
7374
7375 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
7376 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
7377 }
7378 }
7379
7380 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
7381 u8 phy_index, u8 port)
7382 {
7383 u32 ext_phy_config = 0;
7384 switch (phy_index) {
7385 case EXT_PHY1:
7386 ext_phy_config = REG_RD(bp, shmem_base +
7387 offsetof(struct shmem_region,
7388 dev_info.port_hw_config[port].external_phy_config));
7389 break;
7390 case EXT_PHY2:
7391 ext_phy_config = REG_RD(bp, shmem_base +
7392 offsetof(struct shmem_region,
7393 dev_info.port_hw_config[port].external_phy_config2));
7394 break;
7395 default:
7396 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
7397 return -EINVAL;
7398 }
7399
7400 return ext_phy_config;
7401 }
7402 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
7403 struct bnx2x_phy *phy)
7404 {
7405 u32 phy_addr;
7406 u32 chip_id;
7407 u32 switch_cfg = (REG_RD(bp, shmem_base +
7408 offsetof(struct shmem_region,
7409 dev_info.port_feature_config[port].link_config)) &
7410 PORT_FEATURE_CONNECTED_SWITCH_MASK);
7411 chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
7412 switch (switch_cfg) {
7413 case SWITCH_CFG_1G:
7414 phy_addr = REG_RD(bp,
7415 NIG_REG_SERDES0_CTRL_PHY_ADDR +
7416 port * 0x10);
7417 *phy = phy_serdes;
7418 break;
7419 case SWITCH_CFG_10G:
7420 phy_addr = REG_RD(bp,
7421 NIG_REG_XGXS0_CTRL_PHY_ADDR +
7422 port * 0x18);
7423 *phy = phy_xgxs;
7424 break;
7425 default:
7426 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
7427 return -EINVAL;
7428 }
7429 phy->addr = (u8)phy_addr;
7430 phy->mdio_ctrl = bnx2x_get_emac_base(bp,
7431 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
7432 port);
7433 if (CHIP_IS_E2(bp))
7434 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
7435 else
7436 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
7437
7438 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
7439 port, phy->addr, phy->mdio_ctrl);
7440
7441 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
7442 return 0;
7443 }
7444
7445 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
7446 u8 phy_index,
7447 u32 shmem_base,
7448 u32 shmem2_base,
7449 u8 port,
7450 struct bnx2x_phy *phy)
7451 {
7452 u32 ext_phy_config, phy_type, config2;
7453 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
7454 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
7455 phy_index, port);
7456 phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7457 /* Select the phy type */
7458 switch (phy_type) {
7459 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7460 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
7461 *phy = phy_8073;
7462 break;
7463 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7464 *phy = phy_8705;
7465 break;
7466 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7467 *phy = phy_8706;
7468 break;
7469 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7470 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7471 *phy = phy_8726;
7472 break;
7473 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
7474 /* BCM8727_NOC => BCM8727 no over current */
7475 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7476 *phy = phy_8727;
7477 phy->flags |= FLAGS_NOC;
7478 break;
7479 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7480 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7481 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7482 *phy = phy_8727;
7483 break;
7484 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
7485 *phy = phy_8481;
7486 break;
7487 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
7488 *phy = phy_84823;
7489 break;
7490 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
7491 *phy = phy_84833;
7492 break;
7493 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7494 *phy = phy_7101;
7495 break;
7496 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7497 *phy = phy_null;
7498 return -EINVAL;
7499 default:
7500 *phy = phy_null;
7501 return 0;
7502 }
7503
7504 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
7505 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
7506
7507 /*
7508 * The shmem address of the phy version is located on different
7509 * structures. In case this structure is too old, do not set
7510 * the address
7511 */
7512 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
7513 dev_info.shared_hw_config.config2));
7514 if (phy_index == EXT_PHY1) {
7515 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
7516 port_mb[port].ext_phy_fw_version);
7517
7518 /* Check specific mdc mdio settings */
7519 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
7520 mdc_mdio_access = config2 &
7521 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
7522 } else {
7523 u32 size = REG_RD(bp, shmem2_base);
7524
7525 if (size >
7526 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
7527 phy->ver_addr = shmem2_base +
7528 offsetof(struct shmem2_region,
7529 ext_phy_fw_version2[port]);
7530 }
7531 /* Check specific mdc mdio settings */
7532 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
7533 mdc_mdio_access = (config2 &
7534 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
7535 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
7536 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
7537 }
7538 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
7539
7540 /*
7541 * In case mdc/mdio_access of the external phy is different than the
7542 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
7543 * to prevent one port interfere with another port's CL45 operations.
7544 */
7545 if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
7546 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
7547 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
7548 phy_type, port, phy_index);
7549 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n",
7550 phy->addr, phy->mdio_ctrl);
7551 return 0;
7552 }
7553
7554 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
7555 u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
7556 {
7557 int status = 0;
7558 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
7559 if (phy_index == INT_PHY)
7560 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
7561 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
7562 port, phy);
7563 return status;
7564 }
7565
7566 static void bnx2x_phy_def_cfg(struct link_params *params,
7567 struct bnx2x_phy *phy,
7568 u8 phy_index)
7569 {
7570 struct bnx2x *bp = params->bp;
7571 u32 link_config;
7572 /* Populate the default phy configuration for MF mode */
7573 if (phy_index == EXT_PHY2) {
7574 link_config = REG_RD(bp, params->shmem_base +
7575 offsetof(struct shmem_region, dev_info.
7576 port_feature_config[params->port].link_config2));
7577 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7578 offsetof(struct shmem_region,
7579 dev_info.
7580 port_hw_config[params->port].speed_capability_mask2));
7581 } else {
7582 link_config = REG_RD(bp, params->shmem_base +
7583 offsetof(struct shmem_region, dev_info.
7584 port_feature_config[params->port].link_config));
7585 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7586 offsetof(struct shmem_region,
7587 dev_info.
7588 port_hw_config[params->port].speed_capability_mask));
7589 }
7590 DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
7591 " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
7592
7593 phy->req_duplex = DUPLEX_FULL;
7594 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
7595 case PORT_FEATURE_LINK_SPEED_10M_HALF:
7596 phy->req_duplex = DUPLEX_HALF;
7597 case PORT_FEATURE_LINK_SPEED_10M_FULL:
7598 phy->req_line_speed = SPEED_10;
7599 break;
7600 case PORT_FEATURE_LINK_SPEED_100M_HALF:
7601 phy->req_duplex = DUPLEX_HALF;
7602 case PORT_FEATURE_LINK_SPEED_100M_FULL:
7603 phy->req_line_speed = SPEED_100;
7604 break;
7605 case PORT_FEATURE_LINK_SPEED_1G:
7606 phy->req_line_speed = SPEED_1000;
7607 break;
7608 case PORT_FEATURE_LINK_SPEED_2_5G:
7609 phy->req_line_speed = SPEED_2500;
7610 break;
7611 case PORT_FEATURE_LINK_SPEED_10G_CX4:
7612 phy->req_line_speed = SPEED_10000;
7613 break;
7614 default:
7615 phy->req_line_speed = SPEED_AUTO_NEG;
7616 break;
7617 }
7618
7619 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
7620 case PORT_FEATURE_FLOW_CONTROL_AUTO:
7621 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
7622 break;
7623 case PORT_FEATURE_FLOW_CONTROL_TX:
7624 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
7625 break;
7626 case PORT_FEATURE_FLOW_CONTROL_RX:
7627 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
7628 break;
7629 case PORT_FEATURE_FLOW_CONTROL_BOTH:
7630 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
7631 break;
7632 default:
7633 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7634 break;
7635 }
7636 }
7637
7638 u32 bnx2x_phy_selection(struct link_params *params)
7639 {
7640 u32 phy_config_swapped, prio_cfg;
7641 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
7642
7643 phy_config_swapped = params->multi_phy_config &
7644 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7645
7646 prio_cfg = params->multi_phy_config &
7647 PORT_HW_CFG_PHY_SELECTION_MASK;
7648
7649 if (phy_config_swapped) {
7650 switch (prio_cfg) {
7651 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7652 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
7653 break;
7654 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7655 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
7656 break;
7657 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
7658 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
7659 break;
7660 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
7661 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
7662 break;
7663 }
7664 } else
7665 return_cfg = prio_cfg;
7666
7667 return return_cfg;
7668 }
7669
7670
7671 int bnx2x_phy_probe(struct link_params *params)
7672 {
7673 u8 phy_index, actual_phy_idx, link_cfg_idx;
7674 u32 phy_config_swapped, sync_offset, media_types;
7675 struct bnx2x *bp = params->bp;
7676 struct bnx2x_phy *phy;
7677 params->num_phys = 0;
7678 DP(NETIF_MSG_LINK, "Begin phy probe\n");
7679 phy_config_swapped = params->multi_phy_config &
7680 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7681
7682 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
7683 phy_index++) {
7684 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7685 actual_phy_idx = phy_index;
7686 if (phy_config_swapped) {
7687 if (phy_index == EXT_PHY1)
7688 actual_phy_idx = EXT_PHY2;
7689 else if (phy_index == EXT_PHY2)
7690 actual_phy_idx = EXT_PHY1;
7691 }
7692 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
7693 " actual_phy_idx %x\n", phy_config_swapped,
7694 phy_index, actual_phy_idx);
7695 phy = &params->phy[actual_phy_idx];
7696 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
7697 params->shmem2_base, params->port,
7698 phy) != 0) {
7699 params->num_phys = 0;
7700 DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
7701 phy_index);
7702 for (phy_index = INT_PHY;
7703 phy_index < MAX_PHYS;
7704 phy_index++)
7705 *phy = phy_null;
7706 return -EINVAL;
7707 }
7708 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
7709 break;
7710
7711 sync_offset = params->shmem_base +
7712 offsetof(struct shmem_region,
7713 dev_info.port_hw_config[params->port].media_type);
7714 media_types = REG_RD(bp, sync_offset);
7715
7716 /*
7717 * Update media type for non-PMF sync only for the first time
7718 * In case the media type changes afterwards, it will be updated
7719 * using the update_status function
7720 */
7721 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7722 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
7723 actual_phy_idx))) == 0) {
7724 media_types |= ((phy->media_type &
7725 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7726 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
7727 actual_phy_idx));
7728 }
7729 REG_WR(bp, sync_offset, media_types);
7730
7731 bnx2x_phy_def_cfg(params, phy, phy_index);
7732 params->num_phys++;
7733 }
7734
7735 DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
7736 return 0;
7737 }
7738
7739 static void set_phy_vars(struct link_params *params)
7740 {
7741 struct bnx2x *bp = params->bp;
7742 u8 actual_phy_idx, phy_index, link_cfg_idx;
7743 u8 phy_config_swapped = params->multi_phy_config &
7744 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7745 for (phy_index = INT_PHY; phy_index < params->num_phys;
7746 phy_index++) {
7747 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7748 actual_phy_idx = phy_index;
7749 if (phy_config_swapped) {
7750 if (phy_index == EXT_PHY1)
7751 actual_phy_idx = EXT_PHY2;
7752 else if (phy_index == EXT_PHY2)
7753 actual_phy_idx = EXT_PHY1;
7754 }
7755 params->phy[actual_phy_idx].req_flow_ctrl =
7756 params->req_flow_ctrl[link_cfg_idx];
7757
7758 params->phy[actual_phy_idx].req_line_speed =
7759 params->req_line_speed[link_cfg_idx];
7760
7761 params->phy[actual_phy_idx].speed_cap_mask =
7762 params->speed_cap_mask[link_cfg_idx];
7763
7764 params->phy[actual_phy_idx].req_duplex =
7765 params->req_duplex[link_cfg_idx];
7766
7767 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
7768 " speed_cap_mask %x\n",
7769 params->phy[actual_phy_idx].req_flow_ctrl,
7770 params->phy[actual_phy_idx].req_line_speed,
7771 params->phy[actual_phy_idx].speed_cap_mask);
7772 }
7773 }
7774
7775 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7776 {
7777 struct bnx2x *bp = params->bp;
7778 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
7779 DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
7780 params->req_line_speed[0], params->req_flow_ctrl[0]);
7781 DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
7782 params->req_line_speed[1], params->req_flow_ctrl[1]);
7783 vars->link_status = 0;
7784 vars->phy_link_up = 0;
7785 vars->link_up = 0;
7786 vars->line_speed = 0;
7787 vars->duplex = DUPLEX_FULL;
7788 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7789 vars->mac_type = MAC_TYPE_NONE;
7790 vars->phy_flags = 0;
7791
7792 /* disable attentions */
7793 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
7794 (NIG_MASK_XGXS0_LINK_STATUS |
7795 NIG_MASK_XGXS0_LINK10G |
7796 NIG_MASK_SERDES0_LINK_STATUS |
7797 NIG_MASK_MI_INT));
7798
7799 bnx2x_emac_init(params, vars);
7800
7801 if (params->num_phys == 0) {
7802 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
7803 return -EINVAL;
7804 }
7805 set_phy_vars(params);
7806
7807 DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
7808 if (params->loopback_mode == LOOPBACK_BMAC) {
7809
7810 vars->link_up = 1;
7811 vars->line_speed = SPEED_10000;
7812 vars->duplex = DUPLEX_FULL;
7813 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7814 vars->mac_type = MAC_TYPE_BMAC;
7815
7816 vars->phy_flags = PHY_XGXS_FLAG;
7817
7818 bnx2x_xgxs_deassert(params);
7819
7820 /* set bmac loopback */
7821 bnx2x_bmac_enable(params, vars, 1);
7822
7823 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7824
7825 } else if (params->loopback_mode == LOOPBACK_EMAC) {
7826
7827 vars->link_up = 1;
7828 vars->line_speed = SPEED_1000;
7829 vars->duplex = DUPLEX_FULL;
7830 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7831 vars->mac_type = MAC_TYPE_EMAC;
7832
7833 vars->phy_flags = PHY_XGXS_FLAG;
7834
7835 bnx2x_xgxs_deassert(params);
7836 /* set bmac loopback */
7837 bnx2x_emac_enable(params, vars, 1);
7838 bnx2x_emac_program(params, vars);
7839 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7840
7841 } else if ((params->loopback_mode == LOOPBACK_XGXS) ||
7842 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
7843
7844 vars->link_up = 1;
7845 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7846 vars->duplex = DUPLEX_FULL;
7847 if (params->req_line_speed[0] == SPEED_1000) {
7848 vars->line_speed = SPEED_1000;
7849 vars->mac_type = MAC_TYPE_EMAC;
7850 } else {
7851 vars->line_speed = SPEED_10000;
7852 vars->mac_type = MAC_TYPE_BMAC;
7853 }
7854
7855 bnx2x_xgxs_deassert(params);
7856 bnx2x_link_initialize(params, vars);
7857
7858 if (params->req_line_speed[0] == SPEED_1000) {
7859 bnx2x_emac_program(params, vars);
7860 bnx2x_emac_enable(params, vars, 0);
7861 } else
7862 bnx2x_bmac_enable(params, vars, 0);
7863 if (params->loopback_mode == LOOPBACK_XGXS) {
7864 /* set 10G XGXS loopback */
7865 params->phy[INT_PHY].config_loopback(
7866 &params->phy[INT_PHY],
7867 params);
7868
7869 } else {
7870 /* set external phy loopback */
7871 u8 phy_index;
7872 for (phy_index = EXT_PHY1;
7873 phy_index < params->num_phys; phy_index++) {
7874 if (params->phy[phy_index].config_loopback)
7875 params->phy[phy_index].config_loopback(
7876 &params->phy[phy_index],
7877 params);
7878 }
7879 }
7880 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7881
7882 bnx2x_set_led(params, vars,
7883 LED_MODE_OPER, vars->line_speed);
7884 } else
7885 /* No loopback */
7886 {
7887 if (params->switch_cfg == SWITCH_CFG_10G)
7888 bnx2x_xgxs_deassert(params);
7889 else
7890 bnx2x_serdes_deassert(bp, params->port);
7891
7892 bnx2x_link_initialize(params, vars);
7893 msleep(30);
7894 bnx2x_link_int_enable(params);
7895 }
7896 return 0;
7897 }
7898
7899 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
7900 u8 reset_ext_phy)
7901 {
7902 struct bnx2x *bp = params->bp;
7903 u8 phy_index, port = params->port, clear_latch_ind = 0;
7904 DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
7905 /* disable attentions */
7906 vars->link_status = 0;
7907 bnx2x_update_mng(params, vars->link_status);
7908 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
7909 (NIG_MASK_XGXS0_LINK_STATUS |
7910 NIG_MASK_XGXS0_LINK10G |
7911 NIG_MASK_SERDES0_LINK_STATUS |
7912 NIG_MASK_MI_INT));
7913
7914 /* activate nig drain */
7915 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7916
7917 /* disable nig egress interface */
7918 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7919 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7920
7921 /* Stop BigMac rx */
7922 bnx2x_bmac_rx_disable(bp, port);
7923
7924 /* disable emac */
7925 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7926
7927 msleep(10);
7928 /* The PHY reset is controlled by GPIO 1
7929 * Hold it as vars low
7930 */
7931 /* clear link led */
7932 bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
7933
7934 if (reset_ext_phy) {
7935 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
7936 phy_index++) {
7937 if (params->phy[phy_index].link_reset)
7938 params->phy[phy_index].link_reset(
7939 &params->phy[phy_index],
7940 params);
7941 if (params->phy[phy_index].flags &
7942 FLAGS_REARM_LATCH_SIGNAL)
7943 clear_latch_ind = 1;
7944 }
7945 }
7946
7947 if (clear_latch_ind) {
7948 /* Clear latching indication */
7949 bnx2x_rearm_latch_signal(bp, port, 0);
7950 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
7951 1 << NIG_LATCH_BC_ENABLE_MI_INT);
7952 }
7953 if (params->phy[INT_PHY].link_reset)
7954 params->phy[INT_PHY].link_reset(
7955 &params->phy[INT_PHY], params);
7956 /* reset BigMac */
7957 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7958 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
7959
7960 /* disable nig ingress interface */
7961 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
7962 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
7963 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7964 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7965 vars->link_up = 0;
7966 return 0;
7967 }
7968
7969 /****************************************************************************/
7970 /* Common function */
7971 /****************************************************************************/
7972 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
7973 u32 shmem_base_path[],
7974 u32 shmem2_base_path[], u8 phy_index,
7975 u32 chip_id)
7976 {
7977 struct bnx2x_phy phy[PORT_MAX];
7978 struct bnx2x_phy *phy_blk[PORT_MAX];
7979 u16 val;
7980 s8 port = 0;
7981 s8 port_of_path = 0;
7982 u32 swap_val, swap_override;
7983 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7984 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7985 port ^= (swap_val && swap_override);
7986 bnx2x_ext_phy_hw_reset(bp, port);
7987 /* PART1 - Reset both phys */
7988 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7989 u32 shmem_base, shmem2_base;
7990 /* In E2, same phy is using for port0 of the two paths */
7991 if (CHIP_IS_E2(bp)) {
7992 shmem_base = shmem_base_path[port];
7993 shmem2_base = shmem2_base_path[port];
7994 port_of_path = 0;
7995 } else {
7996 shmem_base = shmem_base_path[0];
7997 shmem2_base = shmem2_base_path[0];
7998 port_of_path = port;
7999 }
8000
8001 /* Extract the ext phy address for the port */
8002 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8003 port_of_path, &phy[port]) !=
8004 0) {
8005 DP(NETIF_MSG_LINK, "populate_phy failed\n");
8006 return -EINVAL;
8007 }
8008 /* disable attentions */
8009 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
8010 port_of_path*4,
8011 (NIG_MASK_XGXS0_LINK_STATUS |
8012 NIG_MASK_XGXS0_LINK10G |
8013 NIG_MASK_SERDES0_LINK_STATUS |
8014 NIG_MASK_MI_INT));
8015
8016 /* Need to take the phy out of low power mode in order
8017 to write to access its registers */
8018 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8019 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
8020 port);
8021
8022 /* Reset the phy */
8023 bnx2x_cl45_write(bp, &phy[port],
8024 MDIO_PMA_DEVAD,
8025 MDIO_PMA_REG_CTRL,
8026 1<<15);
8027 }
8028
8029 /* Add delay of 150ms after reset */
8030 msleep(150);
8031
8032 if (phy[PORT_0].addr & 0x1) {
8033 phy_blk[PORT_0] = &(phy[PORT_1]);
8034 phy_blk[PORT_1] = &(phy[PORT_0]);
8035 } else {
8036 phy_blk[PORT_0] = &(phy[PORT_0]);
8037 phy_blk[PORT_1] = &(phy[PORT_1]);
8038 }
8039
8040 /* PART2 - Download firmware to both phys */
8041 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8042 if (CHIP_IS_E2(bp))
8043 port_of_path = 0;
8044 else
8045 port_of_path = port;
8046
8047 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
8048 phy_blk[port]->addr);
8049 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
8050 port_of_path))
8051 return -EINVAL;
8052
8053 /* Only set bit 10 = 1 (Tx power down) */
8054 bnx2x_cl45_read(bp, phy_blk[port],
8055 MDIO_PMA_DEVAD,
8056 MDIO_PMA_REG_TX_POWER_DOWN, &val);
8057
8058 /* Phase1 of TX_POWER_DOWN reset */
8059 bnx2x_cl45_write(bp, phy_blk[port],
8060 MDIO_PMA_DEVAD,
8061 MDIO_PMA_REG_TX_POWER_DOWN,
8062 (val | 1<<10));
8063 }
8064
8065 /*
8066 * Toggle Transmitter: Power down and then up with 600ms delay
8067 * between
8068 */
8069 msleep(600);
8070
8071 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
8072 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8073 /* Phase2 of POWER_DOWN_RESET */
8074 /* Release bit 10 (Release Tx power down) */
8075 bnx2x_cl45_read(bp, phy_blk[port],
8076 MDIO_PMA_DEVAD,
8077 MDIO_PMA_REG_TX_POWER_DOWN, &val);
8078
8079 bnx2x_cl45_write(bp, phy_blk[port],
8080 MDIO_PMA_DEVAD,
8081 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
8082 msleep(15);
8083
8084 /* Read modify write the SPI-ROM version select register */
8085 bnx2x_cl45_read(bp, phy_blk[port],
8086 MDIO_PMA_DEVAD,
8087 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
8088 bnx2x_cl45_write(bp, phy_blk[port],
8089 MDIO_PMA_DEVAD,
8090 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
8091
8092 /* set GPIO2 back to LOW */
8093 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8094 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8095 }
8096 return 0;
8097 }
8098 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
8099 u32 shmem_base_path[],
8100 u32 shmem2_base_path[], u8 phy_index,
8101 u32 chip_id)
8102 {
8103 u32 val;
8104 s8 port;
8105 struct bnx2x_phy phy;
8106 /* Use port1 because of the static port-swap */
8107 /* Enable the module detection interrupt */
8108 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
8109 val |= ((1<<MISC_REGISTERS_GPIO_3)|
8110 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
8111 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
8112
8113 bnx2x_ext_phy_hw_reset(bp, 0);
8114 msleep(5);
8115 for (port = 0; port < PORT_MAX; port++) {
8116 u32 shmem_base, shmem2_base;
8117
8118 /* In E2, same phy is using for port0 of the two paths */
8119 if (CHIP_IS_E2(bp)) {
8120 shmem_base = shmem_base_path[port];
8121 shmem2_base = shmem2_base_path[port];
8122 } else {
8123 shmem_base = shmem_base_path[0];
8124 shmem2_base = shmem2_base_path[0];
8125 }
8126 /* Extract the ext phy address for the port */
8127 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8128 port, &phy) !=
8129 0) {
8130 DP(NETIF_MSG_LINK, "populate phy failed\n");
8131 return -EINVAL;
8132 }
8133
8134 /* Reset phy*/
8135 bnx2x_cl45_write(bp, &phy,
8136 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
8137
8138
8139 /* Set fault module detected LED on */
8140 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
8141 MISC_REGISTERS_GPIO_HIGH,
8142 port);
8143 }
8144
8145 return 0;
8146 }
8147 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
8148 u8 *io_gpio, u8 *io_port)
8149 {
8150
8151 u32 phy_gpio_reset = REG_RD(bp, shmem_base +
8152 offsetof(struct shmem_region,
8153 dev_info.port_hw_config[PORT_0].default_cfg));
8154 switch (phy_gpio_reset) {
8155 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
8156 *io_gpio = 0;
8157 *io_port = 0;
8158 break;
8159 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
8160 *io_gpio = 1;
8161 *io_port = 0;
8162 break;
8163 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
8164 *io_gpio = 2;
8165 *io_port = 0;
8166 break;
8167 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
8168 *io_gpio = 3;
8169 *io_port = 0;
8170 break;
8171 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
8172 *io_gpio = 0;
8173 *io_port = 1;
8174 break;
8175 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
8176 *io_gpio = 1;
8177 *io_port = 1;
8178 break;
8179 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
8180 *io_gpio = 2;
8181 *io_port = 1;
8182 break;
8183 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
8184 *io_gpio = 3;
8185 *io_port = 1;
8186 break;
8187 default:
8188 /* Don't override the io_gpio and io_port */
8189 break;
8190 }
8191 }
8192
8193 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
8194 u32 shmem_base_path[],
8195 u32 shmem2_base_path[], u8 phy_index,
8196 u32 chip_id)
8197 {
8198 s8 port, reset_gpio;
8199 u32 swap_val, swap_override;
8200 struct bnx2x_phy phy[PORT_MAX];
8201 struct bnx2x_phy *phy_blk[PORT_MAX];
8202 s8 port_of_path;
8203 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8204 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8205
8206 reset_gpio = MISC_REGISTERS_GPIO_1;
8207 port = 1;
8208
8209 /*
8210 * Retrieve the reset gpio/port which control the reset.
8211 * Default is GPIO1, PORT1
8212 */
8213 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
8214 (u8 *)&reset_gpio, (u8 *)&port);
8215
8216 /* Calculate the port based on port swap */
8217 port ^= (swap_val && swap_override);
8218
8219 /* Initiate PHY reset*/
8220 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
8221 port);
8222 msleep(1);
8223 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
8224 port);
8225
8226 msleep(5);
8227
8228 /* PART1 - Reset both phys */
8229 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8230 u32 shmem_base, shmem2_base;
8231
8232 /* In E2, same phy is using for port0 of the two paths */
8233 if (CHIP_IS_E2(bp)) {
8234 shmem_base = shmem_base_path[port];
8235 shmem2_base = shmem2_base_path[port];
8236 port_of_path = 0;
8237 } else {
8238 shmem_base = shmem_base_path[0];
8239 shmem2_base = shmem2_base_path[0];
8240 port_of_path = port;
8241 }
8242
8243 /* Extract the ext phy address for the port */
8244 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8245 port_of_path, &phy[port]) !=
8246 0) {
8247 DP(NETIF_MSG_LINK, "populate phy failed\n");
8248 return -EINVAL;
8249 }
8250 /* disable attentions */
8251 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
8252 port_of_path*4,
8253 (NIG_MASK_XGXS0_LINK_STATUS |
8254 NIG_MASK_XGXS0_LINK10G |
8255 NIG_MASK_SERDES0_LINK_STATUS |
8256 NIG_MASK_MI_INT));
8257
8258
8259 /* Reset the phy */
8260 bnx2x_cl45_write(bp, &phy[port],
8261 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8262 }
8263
8264 /* Add delay of 150ms after reset */
8265 msleep(150);
8266 if (phy[PORT_0].addr & 0x1) {
8267 phy_blk[PORT_0] = &(phy[PORT_1]);
8268 phy_blk[PORT_1] = &(phy[PORT_0]);
8269 } else {
8270 phy_blk[PORT_0] = &(phy[PORT_0]);
8271 phy_blk[PORT_1] = &(phy[PORT_1]);
8272 }
8273 /* PART2 - Download firmware to both phys */
8274 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
8275 if (CHIP_IS_E2(bp))
8276 port_of_path = 0;
8277 else
8278 port_of_path = port;
8279 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
8280 phy_blk[port]->addr);
8281 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
8282 port_of_path))
8283 return -EINVAL;
8284
8285 }
8286 return 0;
8287 }
8288
8289 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
8290 u32 shmem2_base_path[], u8 phy_index,
8291 u32 ext_phy_type, u32 chip_id)
8292 {
8293 int rc = 0;
8294
8295 switch (ext_phy_type) {
8296 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
8297 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
8298 shmem2_base_path,
8299 phy_index, chip_id);
8300 break;
8301 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8302 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8303 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
8304 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
8305 shmem2_base_path,
8306 phy_index, chip_id);
8307 break;
8308
8309 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8310 /*
8311 * GPIO1 affects both ports, so there's need to pull
8312 * it for single port alone
8313 */
8314 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
8315 shmem2_base_path,
8316 phy_index, chip_id);
8317 break;
8318 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
8319 rc = -EINVAL;
8320 break;
8321 default:
8322 DP(NETIF_MSG_LINK,
8323 "ext_phy 0x%x common init not required\n",
8324 ext_phy_type);
8325 break;
8326 }
8327
8328 if (rc != 0)
8329 netdev_err(bp->dev, "Warning: PHY was not initialized,"
8330 " Port %d\n",
8331 0);
8332 return rc;
8333 }
8334
8335 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
8336 u32 shmem2_base_path[], u32 chip_id)
8337 {
8338 int rc = 0;
8339 u32 phy_ver;
8340 u8 phy_index;
8341 u32 ext_phy_type, ext_phy_config;
8342 DP(NETIF_MSG_LINK, "Begin common phy init\n");
8343
8344 /* Check if common init was already done */
8345 phy_ver = REG_RD(bp, shmem_base_path[0] +
8346 offsetof(struct shmem_region,
8347 port_mb[PORT_0].ext_phy_fw_version));
8348 if (phy_ver) {
8349 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
8350 phy_ver);
8351 return 0;
8352 }
8353
8354 /* Read the ext_phy_type for arbitrary port(0) */
8355 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8356 phy_index++) {
8357 ext_phy_config = bnx2x_get_ext_phy_config(bp,
8358 shmem_base_path[0],
8359 phy_index, 0);
8360 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8361 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
8362 shmem2_base_path,
8363 phy_index, ext_phy_type,
8364 chip_id);
8365 }
8366 return rc;
8367 }
8368
8369 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
8370 {
8371 u8 phy_index;
8372 struct bnx2x_phy phy;
8373 for (phy_index = INT_PHY; phy_index < MAX_PHYS;
8374 phy_index++) {
8375 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8376 0, &phy) != 0) {
8377 DP(NETIF_MSG_LINK, "populate phy failed\n");
8378 return 0;
8379 }
8380
8381 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
8382 return 1;
8383 }
8384 return 0;
8385 }
8386
8387 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
8388 u32 shmem_base,
8389 u32 shmem2_base,
8390 u8 port)
8391 {
8392 u8 phy_index, fan_failure_det_req = 0;
8393 struct bnx2x_phy phy;
8394 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8395 phy_index++) {
8396 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
8397 port, &phy)
8398 != 0) {
8399 DP(NETIF_MSG_LINK, "populate phy failed\n");
8400 return 0;
8401 }
8402 fan_failure_det_req |= (phy.flags &
8403 FLAGS_FAN_FAILURE_DET_REQ);
8404 }
8405 return fan_failure_det_req;
8406 }
8407
8408 void bnx2x_hw_reset_phy(struct link_params *params)
8409 {
8410 u8 phy_index;
8411 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
8412 phy_index++) {
8413 if (params->phy[phy_index].hw_reset) {
8414 params->phy[phy_index].hw_reset(
8415 &params->phy[phy_index],
8416 params);
8417 params->phy[phy_index] = phy_null;
8418 }
8419 }
8420 }
kernel source for telekom puls (alcatel/mediatek)