1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004-2009 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/firmware.h>
50 #include <linux/log2.h>
51 #include <linux/list.h>
53 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
60 #define DRV_MODULE_NAME "bnx2"
61 #define PFX DRV_MODULE_NAME ": "
62 #define DRV_MODULE_VERSION "2.0.2"
63 #define DRV_MODULE_RELDATE "Aug 21, 2009"
64 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j3.fw"
65 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
66 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j3.fw"
67 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j3.fw"
68 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j3.fw"
70 #define RUN_AT(x) (jiffies + (x))
72 /* Time in jiffies before concluding the transmitter is hung. */
73 #define TX_TIMEOUT (5*HZ)
75 static char version
[] __devinitdata
=
76 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
78 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
79 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
80 MODULE_LICENSE("GPL");
81 MODULE_VERSION(DRV_MODULE_VERSION
);
82 MODULE_FIRMWARE(FW_MIPS_FILE_06
);
83 MODULE_FIRMWARE(FW_RV2P_FILE_06
);
84 MODULE_FIRMWARE(FW_MIPS_FILE_09
);
85 MODULE_FIRMWARE(FW_RV2P_FILE_09
);
86 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax
);
88 static int disable_msi
= 0;
90 module_param(disable_msi
, int, 0);
91 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
107 /* indexed by board_t, above */
110 } board_info
[] __devinitdata
= {
111 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
112 { "HP NC370T Multifunction Gigabit Server Adapter" },
113 { "HP NC370i Multifunction Gigabit Server Adapter" },
114 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
115 { "HP NC370F Multifunction Gigabit Server Adapter" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
117 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
118 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
119 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
120 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
121 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
124 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl
) = {
125 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5706
,
126 PCI_VENDOR_ID_HP
, 0x3101, 0, 0, NC370T
},
127 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5706
,
128 PCI_VENDOR_ID_HP
, 0x3106, 0, 0, NC370I
},
129 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5706
,
130 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BCM5706
},
131 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5708
,
132 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BCM5708
},
133 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5706S
,
134 PCI_VENDOR_ID_HP
, 0x3102, 0, 0, NC370F
},
135 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5706S
,
136 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BCM5706S
},
137 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5708S
,
138 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BCM5708S
},
139 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5709
,
140 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BCM5709
},
141 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_NX2_5709S
,
142 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BCM5709S
},
143 { PCI_VENDOR_ID_BROADCOM
, 0x163b,
144 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BCM5716
},
145 { PCI_VENDOR_ID_BROADCOM
, 0x163c,
146 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, BCM5716S
},
150 static const struct flash_spec flash_table
[] =
152 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
153 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
155 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
156 BUFFERED_FLAGS
, SEEPROM_PAGE_BITS
, SEEPROM_PAGE_SIZE
,
157 SEEPROM_BYTE_ADDR_MASK
, SEEPROM_TOTAL_SIZE
,
159 /* Expansion entry 0001 */
160 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
161 NONBUFFERED_FLAGS
, SAIFUN_FLASH_PAGE_BITS
, SAIFUN_FLASH_PAGE_SIZE
,
162 SAIFUN_FLASH_BYTE_ADDR_MASK
, 0,
164 /* Saifun SA25F010 (non-buffered flash) */
165 /* strap, cfg1, & write1 need updates */
166 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
167 NONBUFFERED_FLAGS
, SAIFUN_FLASH_PAGE_BITS
, SAIFUN_FLASH_PAGE_SIZE
,
168 SAIFUN_FLASH_BYTE_ADDR_MASK
, SAIFUN_FLASH_BASE_TOTAL_SIZE
*2,
169 "Non-buffered flash (128kB)"},
170 /* Saifun SA25F020 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
173 NONBUFFERED_FLAGS
, SAIFUN_FLASH_PAGE_BITS
, SAIFUN_FLASH_PAGE_SIZE
,
174 SAIFUN_FLASH_BYTE_ADDR_MASK
, SAIFUN_FLASH_BASE_TOTAL_SIZE
*4,
175 "Non-buffered flash (256kB)"},
176 /* Expansion entry 0100 */
177 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
178 NONBUFFERED_FLAGS
, SAIFUN_FLASH_PAGE_BITS
, SAIFUN_FLASH_PAGE_SIZE
,
179 SAIFUN_FLASH_BYTE_ADDR_MASK
, 0,
181 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
182 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
183 NONBUFFERED_FLAGS
, ST_MICRO_FLASH_PAGE_BITS
, ST_MICRO_FLASH_PAGE_SIZE
,
184 ST_MICRO_FLASH_BYTE_ADDR_MASK
, ST_MICRO_FLASH_BASE_TOTAL_SIZE
*2,
185 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
186 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
187 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
188 NONBUFFERED_FLAGS
, ST_MICRO_FLASH_PAGE_BITS
, ST_MICRO_FLASH_PAGE_SIZE
,
189 ST_MICRO_FLASH_BYTE_ADDR_MASK
, ST_MICRO_FLASH_BASE_TOTAL_SIZE
*4,
190 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
191 /* Saifun SA25F005 (non-buffered flash) */
192 /* strap, cfg1, & write1 need updates */
193 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
194 NONBUFFERED_FLAGS
, SAIFUN_FLASH_PAGE_BITS
, SAIFUN_FLASH_PAGE_SIZE
,
195 SAIFUN_FLASH_BYTE_ADDR_MASK
, SAIFUN_FLASH_BASE_TOTAL_SIZE
,
196 "Non-buffered flash (64kB)"},
198 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
199 BUFFERED_FLAGS
, SEEPROM_PAGE_BITS
, SEEPROM_PAGE_SIZE
,
200 SEEPROM_BYTE_ADDR_MASK
, SEEPROM_TOTAL_SIZE
,
202 /* Expansion entry 1001 */
203 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
204 NONBUFFERED_FLAGS
, SAIFUN_FLASH_PAGE_BITS
, SAIFUN_FLASH_PAGE_SIZE
,
205 SAIFUN_FLASH_BYTE_ADDR_MASK
, 0,
207 /* Expansion entry 1010 */
208 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
209 NONBUFFERED_FLAGS
, SAIFUN_FLASH_PAGE_BITS
, SAIFUN_FLASH_PAGE_SIZE
,
210 SAIFUN_FLASH_BYTE_ADDR_MASK
, 0,
212 /* ATMEL AT45DB011B (buffered flash) */
213 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
214 BUFFERED_FLAGS
, BUFFERED_FLASH_PAGE_BITS
, BUFFERED_FLASH_PAGE_SIZE
,
215 BUFFERED_FLASH_BYTE_ADDR_MASK
, BUFFERED_FLASH_TOTAL_SIZE
,
216 "Buffered flash (128kB)"},
217 /* Expansion entry 1100 */
218 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
219 NONBUFFERED_FLAGS
, SAIFUN_FLASH_PAGE_BITS
, SAIFUN_FLASH_PAGE_SIZE
,
220 SAIFUN_FLASH_BYTE_ADDR_MASK
, 0,
222 /* Expansion entry 1101 */
223 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
224 NONBUFFERED_FLAGS
, SAIFUN_FLASH_PAGE_BITS
, SAIFUN_FLASH_PAGE_SIZE
,
225 SAIFUN_FLASH_BYTE_ADDR_MASK
, 0,
227 /* Ateml Expansion entry 1110 */
228 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
229 BUFFERED_FLAGS
, BUFFERED_FLASH_PAGE_BITS
, BUFFERED_FLASH_PAGE_SIZE
,
230 BUFFERED_FLASH_BYTE_ADDR_MASK
, 0,
231 "Entry 1110 (Atmel)"},
232 /* ATMEL AT45DB021B (buffered flash) */
233 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
234 BUFFERED_FLAGS
, BUFFERED_FLASH_PAGE_BITS
, BUFFERED_FLASH_PAGE_SIZE
,
235 BUFFERED_FLASH_BYTE_ADDR_MASK
, BUFFERED_FLASH_TOTAL_SIZE
*2,
236 "Buffered flash (256kB)"},
239 static const struct flash_spec flash_5709
= {
240 .flags
= BNX2_NV_BUFFERED
,
241 .page_bits
= BCM5709_FLASH_PAGE_BITS
,
242 .page_size
= BCM5709_FLASH_PAGE_SIZE
,
243 .addr_mask
= BCM5709_FLASH_BYTE_ADDR_MASK
,
244 .total_size
= BUFFERED_FLASH_TOTAL_SIZE
*2,
245 .name
= "5709 Buffered flash (256kB)",
248 MODULE_DEVICE_TABLE(pci
, bnx2_pci_tbl
);
250 static inline u32
bnx2_tx_avail(struct bnx2
*bp
, struct bnx2_tx_ring_info
*txr
)
256 /* The ring uses 256 indices for 255 entries, one of them
257 * needs to be skipped.
259 diff
= txr
->tx_prod
- txr
->tx_cons
;
260 if (unlikely(diff
>= TX_DESC_CNT
)) {
262 if (diff
== TX_DESC_CNT
)
263 diff
= MAX_TX_DESC_CNT
;
265 return (bp
->tx_ring_size
- diff
);
269 bnx2_reg_rd_ind(struct bnx2
*bp
, u32 offset
)
273 spin_lock_bh(&bp
->indirect_lock
);
274 REG_WR(bp
, BNX2_PCICFG_REG_WINDOW_ADDRESS
, offset
);
275 val
= REG_RD(bp
, BNX2_PCICFG_REG_WINDOW
);
276 spin_unlock_bh(&bp
->indirect_lock
);
281 bnx2_reg_wr_ind(struct bnx2
*bp
, u32 offset
, u32 val
)
283 spin_lock_bh(&bp
->indirect_lock
);
284 REG_WR(bp
, BNX2_PCICFG_REG_WINDOW_ADDRESS
, offset
);
285 REG_WR(bp
, BNX2_PCICFG_REG_WINDOW
, val
);
286 spin_unlock_bh(&bp
->indirect_lock
);
290 bnx2_shmem_wr(struct bnx2
*bp
, u32 offset
, u32 val
)
292 bnx2_reg_wr_ind(bp
, bp
->shmem_base
+ offset
, val
);
296 bnx2_shmem_rd(struct bnx2
*bp
, u32 offset
)
298 return (bnx2_reg_rd_ind(bp
, bp
->shmem_base
+ offset
));
302 bnx2_ctx_wr(struct bnx2
*bp
, u32 cid_addr
, u32 offset
, u32 val
)
305 spin_lock_bh(&bp
->indirect_lock
);
306 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
309 REG_WR(bp
, BNX2_CTX_CTX_DATA
, val
);
310 REG_WR(bp
, BNX2_CTX_CTX_CTRL
,
311 offset
| BNX2_CTX_CTX_CTRL_WRITE_REQ
);
312 for (i
= 0; i
< 5; i
++) {
313 val
= REG_RD(bp
, BNX2_CTX_CTX_CTRL
);
314 if ((val
& BNX2_CTX_CTX_CTRL_WRITE_REQ
) == 0)
319 REG_WR(bp
, BNX2_CTX_DATA_ADR
, offset
);
320 REG_WR(bp
, BNX2_CTX_DATA
, val
);
322 spin_unlock_bh(&bp
->indirect_lock
);
327 bnx2_drv_ctl(struct net_device
*dev
, struct drv_ctl_info
*info
)
329 struct bnx2
*bp
= netdev_priv(dev
);
330 struct drv_ctl_io
*io
= &info
->data
.io
;
333 case DRV_CTL_IO_WR_CMD
:
334 bnx2_reg_wr_ind(bp
, io
->offset
, io
->data
);
336 case DRV_CTL_IO_RD_CMD
:
337 io
->data
= bnx2_reg_rd_ind(bp
, io
->offset
);
339 case DRV_CTL_CTX_WR_CMD
:
340 bnx2_ctx_wr(bp
, io
->cid_addr
, io
->offset
, io
->data
);
348 static void bnx2_setup_cnic_irq_info(struct bnx2
*bp
)
350 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
351 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[0];
354 if (bp
->flags
& BNX2_FLAG_USING_MSIX
) {
355 cp
->drv_state
|= CNIC_DRV_STATE_USING_MSIX
;
356 bnapi
->cnic_present
= 0;
357 sb_id
= bp
->irq_nvecs
;
358 cp
->irq_arr
[0].irq_flags
|= CNIC_IRQ_FL_MSIX
;
360 cp
->drv_state
&= ~CNIC_DRV_STATE_USING_MSIX
;
361 bnapi
->cnic_tag
= bnapi
->last_status_idx
;
362 bnapi
->cnic_present
= 1;
364 cp
->irq_arr
[0].irq_flags
&= ~CNIC_IRQ_FL_MSIX
;
367 cp
->irq_arr
[0].vector
= bp
->irq_tbl
[sb_id
].vector
;
368 cp
->irq_arr
[0].status_blk
= (void *)
369 ((unsigned long) bnapi
->status_blk
.msi
+
370 (BNX2_SBLK_MSIX_ALIGN_SIZE
* sb_id
));
371 cp
->irq_arr
[0].status_blk_num
= sb_id
;
375 static int bnx2_register_cnic(struct net_device
*dev
, struct cnic_ops
*ops
,
378 struct bnx2
*bp
= netdev_priv(dev
);
379 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
384 if (cp
->drv_state
& CNIC_DRV_STATE_REGD
)
387 bp
->cnic_data
= data
;
388 rcu_assign_pointer(bp
->cnic_ops
, ops
);
391 cp
->drv_state
= CNIC_DRV_STATE_REGD
;
393 bnx2_setup_cnic_irq_info(bp
);
398 static int bnx2_unregister_cnic(struct net_device
*dev
)
400 struct bnx2
*bp
= netdev_priv(dev
);
401 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[0];
402 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
404 mutex_lock(&bp
->cnic_lock
);
406 bnapi
->cnic_present
= 0;
407 rcu_assign_pointer(bp
->cnic_ops
, NULL
);
408 mutex_unlock(&bp
->cnic_lock
);
413 struct cnic_eth_dev
*bnx2_cnic_probe(struct net_device
*dev
)
415 struct bnx2
*bp
= netdev_priv(dev
);
416 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
418 cp
->drv_owner
= THIS_MODULE
;
419 cp
->chip_id
= bp
->chip_id
;
421 cp
->io_base
= bp
->regview
;
422 cp
->drv_ctl
= bnx2_drv_ctl
;
423 cp
->drv_register_cnic
= bnx2_register_cnic
;
424 cp
->drv_unregister_cnic
= bnx2_unregister_cnic
;
428 EXPORT_SYMBOL(bnx2_cnic_probe
);
431 bnx2_cnic_stop(struct bnx2
*bp
)
433 struct cnic_ops
*c_ops
;
434 struct cnic_ctl_info info
;
436 mutex_lock(&bp
->cnic_lock
);
437 c_ops
= bp
->cnic_ops
;
439 info
.cmd
= CNIC_CTL_STOP_CMD
;
440 c_ops
->cnic_ctl(bp
->cnic_data
, &info
);
442 mutex_unlock(&bp
->cnic_lock
);
446 bnx2_cnic_start(struct bnx2
*bp
)
448 struct cnic_ops
*c_ops
;
449 struct cnic_ctl_info info
;
451 mutex_lock(&bp
->cnic_lock
);
452 c_ops
= bp
->cnic_ops
;
454 if (!(bp
->flags
& BNX2_FLAG_USING_MSIX
)) {
455 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[0];
457 bnapi
->cnic_tag
= bnapi
->last_status_idx
;
459 info
.cmd
= CNIC_CTL_START_CMD
;
460 c_ops
->cnic_ctl(bp
->cnic_data
, &info
);
462 mutex_unlock(&bp
->cnic_lock
);
468 bnx2_cnic_stop(struct bnx2
*bp
)
473 bnx2_cnic_start(struct bnx2
*bp
)
480 bnx2_read_phy(struct bnx2
*bp
, u32 reg
, u32
*val
)
485 if (bp
->phy_flags
& BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING
) {
486 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
487 val1
&= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL
;
489 REG_WR(bp
, BNX2_EMAC_MDIO_MODE
, val1
);
490 REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
495 val1
= (bp
->phy_addr
<< 21) | (reg
<< 16) |
496 BNX2_EMAC_MDIO_COMM_COMMAND_READ
| BNX2_EMAC_MDIO_COMM_DISEXT
|
497 BNX2_EMAC_MDIO_COMM_START_BUSY
;
498 REG_WR(bp
, BNX2_EMAC_MDIO_COMM
, val1
);
500 for (i
= 0; i
< 50; i
++) {
503 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_COMM
);
504 if (!(val1
& BNX2_EMAC_MDIO_COMM_START_BUSY
)) {
507 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_COMM
);
508 val1
&= BNX2_EMAC_MDIO_COMM_DATA
;
514 if (val1
& BNX2_EMAC_MDIO_COMM_START_BUSY
) {
523 if (bp
->phy_flags
& BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING
) {
524 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
525 val1
|= BNX2_EMAC_MDIO_MODE_AUTO_POLL
;
527 REG_WR(bp
, BNX2_EMAC_MDIO_MODE
, val1
);
528 REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
537 bnx2_write_phy(struct bnx2
*bp
, u32 reg
, u32 val
)
542 if (bp
->phy_flags
& BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING
) {
543 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
544 val1
&= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL
;
546 REG_WR(bp
, BNX2_EMAC_MDIO_MODE
, val1
);
547 REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
552 val1
= (bp
->phy_addr
<< 21) | (reg
<< 16) | val
|
553 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE
|
554 BNX2_EMAC_MDIO_COMM_START_BUSY
| BNX2_EMAC_MDIO_COMM_DISEXT
;
555 REG_WR(bp
, BNX2_EMAC_MDIO_COMM
, val1
);
557 for (i
= 0; i
< 50; i
++) {
560 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_COMM
);
561 if (!(val1
& BNX2_EMAC_MDIO_COMM_START_BUSY
)) {
567 if (val1
& BNX2_EMAC_MDIO_COMM_START_BUSY
)
572 if (bp
->phy_flags
& BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING
) {
573 val1
= REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
574 val1
|= BNX2_EMAC_MDIO_MODE_AUTO_POLL
;
576 REG_WR(bp
, BNX2_EMAC_MDIO_MODE
, val1
);
577 REG_RD(bp
, BNX2_EMAC_MDIO_MODE
);
586 bnx2_disable_int(struct bnx2
*bp
)
589 struct bnx2_napi
*bnapi
;
591 for (i
= 0; i
< bp
->irq_nvecs
; i
++) {
592 bnapi
= &bp
->bnx2_napi
[i
];
593 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
, bnapi
->int_num
|
594 BNX2_PCICFG_INT_ACK_CMD_MASK_INT
);
596 REG_RD(bp
, BNX2_PCICFG_INT_ACK_CMD
);
600 bnx2_enable_int(struct bnx2
*bp
)
603 struct bnx2_napi
*bnapi
;
605 for (i
= 0; i
< bp
->irq_nvecs
; i
++) {
606 bnapi
= &bp
->bnx2_napi
[i
];
608 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
, bnapi
->int_num
|
609 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID
|
610 BNX2_PCICFG_INT_ACK_CMD_MASK_INT
|
611 bnapi
->last_status_idx
);
613 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
, bnapi
->int_num
|
614 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID
|
615 bnapi
->last_status_idx
);
617 REG_WR(bp
, BNX2_HC_COMMAND
, bp
->hc_cmd
| BNX2_HC_COMMAND_COAL_NOW
);
621 bnx2_disable_int_sync(struct bnx2
*bp
)
625 atomic_inc(&bp
->intr_sem
);
626 if (!netif_running(bp
->dev
))
629 bnx2_disable_int(bp
);
630 for (i
= 0; i
< bp
->irq_nvecs
; i
++)
631 synchronize_irq(bp
->irq_tbl
[i
].vector
);
635 bnx2_napi_disable(struct bnx2
*bp
)
639 for (i
= 0; i
< bp
->irq_nvecs
; i
++)
640 napi_disable(&bp
->bnx2_napi
[i
].napi
);
644 bnx2_napi_enable(struct bnx2
*bp
)
648 for (i
= 0; i
< bp
->irq_nvecs
; i
++)
649 napi_enable(&bp
->bnx2_napi
[i
].napi
);
653 bnx2_netif_stop(struct bnx2
*bp
)
656 bnx2_disable_int_sync(bp
);
657 if (netif_running(bp
->dev
)) {
658 bnx2_napi_disable(bp
);
659 netif_tx_disable(bp
->dev
);
660 bp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
665 bnx2_netif_start(struct bnx2
*bp
)
667 if (atomic_dec_and_test(&bp
->intr_sem
)) {
668 if (netif_running(bp
->dev
)) {
669 netif_tx_wake_all_queues(bp
->dev
);
670 bnx2_napi_enable(bp
);
678 bnx2_free_tx_mem(struct bnx2
*bp
)
682 for (i
= 0; i
< bp
->num_tx_rings
; i
++) {
683 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[i
];
684 struct bnx2_tx_ring_info
*txr
= &bnapi
->tx_ring
;
686 if (txr
->tx_desc_ring
) {
687 pci_free_consistent(bp
->pdev
, TXBD_RING_SIZE
,
689 txr
->tx_desc_mapping
);
690 txr
->tx_desc_ring
= NULL
;
692 kfree(txr
->tx_buf_ring
);
693 txr
->tx_buf_ring
= NULL
;
698 bnx2_free_rx_mem(struct bnx2
*bp
)
702 for (i
= 0; i
< bp
->num_rx_rings
; i
++) {
703 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[i
];
704 struct bnx2_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
707 for (j
= 0; j
< bp
->rx_max_ring
; j
++) {
708 if (rxr
->rx_desc_ring
[j
])
709 pci_free_consistent(bp
->pdev
, RXBD_RING_SIZE
,
710 rxr
->rx_desc_ring
[j
],
711 rxr
->rx_desc_mapping
[j
]);
712 rxr
->rx_desc_ring
[j
] = NULL
;
714 vfree(rxr
->rx_buf_ring
);
715 rxr
->rx_buf_ring
= NULL
;
717 for (j
= 0; j
< bp
->rx_max_pg_ring
; j
++) {
718 if (rxr
->rx_pg_desc_ring
[j
])
719 pci_free_consistent(bp
->pdev
, RXBD_RING_SIZE
,
720 rxr
->rx_pg_desc_ring
[j
],
721 rxr
->rx_pg_desc_mapping
[j
]);
722 rxr
->rx_pg_desc_ring
[j
] = NULL
;
724 vfree(rxr
->rx_pg_ring
);
725 rxr
->rx_pg_ring
= NULL
;
730 bnx2_alloc_tx_mem(struct bnx2
*bp
)
734 for (i
= 0; i
< bp
->num_tx_rings
; i
++) {
735 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[i
];
736 struct bnx2_tx_ring_info
*txr
= &bnapi
->tx_ring
;
738 txr
->tx_buf_ring
= kzalloc(SW_TXBD_RING_SIZE
, GFP_KERNEL
);
739 if (txr
->tx_buf_ring
== NULL
)
743 pci_alloc_consistent(bp
->pdev
, TXBD_RING_SIZE
,
744 &txr
->tx_desc_mapping
);
745 if (txr
->tx_desc_ring
== NULL
)
752 bnx2_alloc_rx_mem(struct bnx2
*bp
)
756 for (i
= 0; i
< bp
->num_rx_rings
; i
++) {
757 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[i
];
758 struct bnx2_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
762 vmalloc(SW_RXBD_RING_SIZE
* bp
->rx_max_ring
);
763 if (rxr
->rx_buf_ring
== NULL
)
766 memset(rxr
->rx_buf_ring
, 0,
767 SW_RXBD_RING_SIZE
* bp
->rx_max_ring
);
769 for (j
= 0; j
< bp
->rx_max_ring
; j
++) {
770 rxr
->rx_desc_ring
[j
] =
771 pci_alloc_consistent(bp
->pdev
, RXBD_RING_SIZE
,
772 &rxr
->rx_desc_mapping
[j
]);
773 if (rxr
->rx_desc_ring
[j
] == NULL
)
778 if (bp
->rx_pg_ring_size
) {
779 rxr
->rx_pg_ring
= vmalloc(SW_RXPG_RING_SIZE
*
781 if (rxr
->rx_pg_ring
== NULL
)
784 memset(rxr
->rx_pg_ring
, 0, SW_RXPG_RING_SIZE
*
788 for (j
= 0; j
< bp
->rx_max_pg_ring
; j
++) {
789 rxr
->rx_pg_desc_ring
[j
] =
790 pci_alloc_consistent(bp
->pdev
, RXBD_RING_SIZE
,
791 &rxr
->rx_pg_desc_mapping
[j
]);
792 if (rxr
->rx_pg_desc_ring
[j
] == NULL
)
801 bnx2_free_mem(struct bnx2
*bp
)
804 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[0];
806 bnx2_free_tx_mem(bp
);
807 bnx2_free_rx_mem(bp
);
809 for (i
= 0; i
< bp
->ctx_pages
; i
++) {
810 if (bp
->ctx_blk
[i
]) {
811 pci_free_consistent(bp
->pdev
, BCM_PAGE_SIZE
,
813 bp
->ctx_blk_mapping
[i
]);
814 bp
->ctx_blk
[i
] = NULL
;
817 if (bnapi
->status_blk
.msi
) {
818 pci_free_consistent(bp
->pdev
, bp
->status_stats_size
,
819 bnapi
->status_blk
.msi
,
820 bp
->status_blk_mapping
);
821 bnapi
->status_blk
.msi
= NULL
;
822 bp
->stats_blk
= NULL
;
827 bnx2_alloc_mem(struct bnx2
*bp
)
829 int i
, status_blk_size
, err
;
830 struct bnx2_napi
*bnapi
;
833 /* Combine status and statistics blocks into one allocation. */
834 status_blk_size
= L1_CACHE_ALIGN(sizeof(struct status_block
));
835 if (bp
->flags
& BNX2_FLAG_MSIX_CAP
)
836 status_blk_size
= L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC
*
837 BNX2_SBLK_MSIX_ALIGN_SIZE
);
838 bp
->status_stats_size
= status_blk_size
+
839 sizeof(struct statistics_block
);
841 status_blk
= pci_alloc_consistent(bp
->pdev
, bp
->status_stats_size
,
842 &bp
->status_blk_mapping
);
843 if (status_blk
== NULL
)
846 memset(status_blk
, 0, bp
->status_stats_size
);
848 bnapi
= &bp
->bnx2_napi
[0];
849 bnapi
->status_blk
.msi
= status_blk
;
850 bnapi
->hw_tx_cons_ptr
=
851 &bnapi
->status_blk
.msi
->status_tx_quick_consumer_index0
;
852 bnapi
->hw_rx_cons_ptr
=
853 &bnapi
->status_blk
.msi
->status_rx_quick_consumer_index0
;
854 if (bp
->flags
& BNX2_FLAG_MSIX_CAP
) {
855 for (i
= 1; i
< BNX2_MAX_MSIX_VEC
; i
++) {
856 struct status_block_msix
*sblk
;
858 bnapi
= &bp
->bnx2_napi
[i
];
860 sblk
= (void *) (status_blk
+
861 BNX2_SBLK_MSIX_ALIGN_SIZE
* i
);
862 bnapi
->status_blk
.msix
= sblk
;
863 bnapi
->hw_tx_cons_ptr
=
864 &sblk
->status_tx_quick_consumer_index
;
865 bnapi
->hw_rx_cons_ptr
=
866 &sblk
->status_rx_quick_consumer_index
;
867 bnapi
->int_num
= i
<< 24;
871 bp
->stats_blk
= status_blk
+ status_blk_size
;
873 bp
->stats_blk_mapping
= bp
->status_blk_mapping
+ status_blk_size
;
875 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
876 bp
->ctx_pages
= 0x2000 / BCM_PAGE_SIZE
;
877 if (bp
->ctx_pages
== 0)
879 for (i
= 0; i
< bp
->ctx_pages
; i
++) {
880 bp
->ctx_blk
[i
] = pci_alloc_consistent(bp
->pdev
,
882 &bp
->ctx_blk_mapping
[i
]);
883 if (bp
->ctx_blk
[i
] == NULL
)
888 err
= bnx2_alloc_rx_mem(bp
);
892 err
= bnx2_alloc_tx_mem(bp
);
904 bnx2_report_fw_link(struct bnx2
*bp
)
906 u32 fw_link_status
= 0;
908 if (bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
)
914 switch (bp
->line_speed
) {
916 if (bp
->duplex
== DUPLEX_HALF
)
917 fw_link_status
= BNX2_LINK_STATUS_10HALF
;
919 fw_link_status
= BNX2_LINK_STATUS_10FULL
;
922 if (bp
->duplex
== DUPLEX_HALF
)
923 fw_link_status
= BNX2_LINK_STATUS_100HALF
;
925 fw_link_status
= BNX2_LINK_STATUS_100FULL
;
928 if (bp
->duplex
== DUPLEX_HALF
)
929 fw_link_status
= BNX2_LINK_STATUS_1000HALF
;
931 fw_link_status
= BNX2_LINK_STATUS_1000FULL
;
934 if (bp
->duplex
== DUPLEX_HALF
)
935 fw_link_status
= BNX2_LINK_STATUS_2500HALF
;
937 fw_link_status
= BNX2_LINK_STATUS_2500FULL
;
941 fw_link_status
|= BNX2_LINK_STATUS_LINK_UP
;
944 fw_link_status
|= BNX2_LINK_STATUS_AN_ENABLED
;
946 bnx2_read_phy(bp
, bp
->mii_bmsr
, &bmsr
);
947 bnx2_read_phy(bp
, bp
->mii_bmsr
, &bmsr
);
949 if (!(bmsr
& BMSR_ANEGCOMPLETE
) ||
950 bp
->phy_flags
& BNX2_PHY_FLAG_PARALLEL_DETECT
)
951 fw_link_status
|= BNX2_LINK_STATUS_PARALLEL_DET
;
953 fw_link_status
|= BNX2_LINK_STATUS_AN_COMPLETE
;
957 fw_link_status
= BNX2_LINK_STATUS_LINK_DOWN
;
959 bnx2_shmem_wr(bp
, BNX2_LINK_STATUS
, fw_link_status
);
963 bnx2_xceiver_str(struct bnx2
*bp
)
965 return ((bp
->phy_port
== PORT_FIBRE
) ? "SerDes" :
966 ((bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) ? "Remote Copper" :
971 bnx2_report_link(struct bnx2
*bp
)
974 netif_carrier_on(bp
->dev
);
975 printk(KERN_INFO PFX
"%s NIC %s Link is Up, ", bp
->dev
->name
,
976 bnx2_xceiver_str(bp
));
978 printk("%d Mbps ", bp
->line_speed
);
980 if (bp
->duplex
== DUPLEX_FULL
)
981 printk("full duplex");
983 printk("half duplex");
986 if (bp
->flow_ctrl
& FLOW_CTRL_RX
) {
987 printk(", receive ");
988 if (bp
->flow_ctrl
& FLOW_CTRL_TX
)
989 printk("& transmit ");
992 printk(", transmit ");
994 printk("flow control ON");
999 netif_carrier_off(bp
->dev
);
1000 printk(KERN_ERR PFX
"%s NIC %s Link is Down\n", bp
->dev
->name
,
1001 bnx2_xceiver_str(bp
));
1004 bnx2_report_fw_link(bp
);
1008 bnx2_resolve_flow_ctrl(struct bnx2
*bp
)
1010 u32 local_adv
, remote_adv
;
1013 if ((bp
->autoneg
& (AUTONEG_SPEED
| AUTONEG_FLOW_CTRL
)) !=
1014 (AUTONEG_SPEED
| AUTONEG_FLOW_CTRL
)) {
1016 if (bp
->duplex
== DUPLEX_FULL
) {
1017 bp
->flow_ctrl
= bp
->req_flow_ctrl
;
1022 if (bp
->duplex
!= DUPLEX_FULL
) {
1026 if ((bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) &&
1027 (CHIP_NUM(bp
) == CHIP_NUM_5708
)) {
1030 bnx2_read_phy(bp
, BCM5708S_1000X_STAT1
, &val
);
1031 if (val
& BCM5708S_1000X_STAT1_TX_PAUSE
)
1032 bp
->flow_ctrl
|= FLOW_CTRL_TX
;
1033 if (val
& BCM5708S_1000X_STAT1_RX_PAUSE
)
1034 bp
->flow_ctrl
|= FLOW_CTRL_RX
;
1038 bnx2_read_phy(bp
, bp
->mii_adv
, &local_adv
);
1039 bnx2_read_phy(bp
, bp
->mii_lpa
, &remote_adv
);
1041 if (bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) {
1042 u32 new_local_adv
= 0;
1043 u32 new_remote_adv
= 0;
1045 if (local_adv
& ADVERTISE_1000XPAUSE
)
1046 new_local_adv
|= ADVERTISE_PAUSE_CAP
;
1047 if (local_adv
& ADVERTISE_1000XPSE_ASYM
)
1048 new_local_adv
|= ADVERTISE_PAUSE_ASYM
;
1049 if (remote_adv
& ADVERTISE_1000XPAUSE
)
1050 new_remote_adv
|= ADVERTISE_PAUSE_CAP
;
1051 if (remote_adv
& ADVERTISE_1000XPSE_ASYM
)
1052 new_remote_adv
|= ADVERTISE_PAUSE_ASYM
;
1054 local_adv
= new_local_adv
;
1055 remote_adv
= new_remote_adv
;
1058 /* See Table 28B-3 of 802.3ab-1999 spec. */
1059 if (local_adv
& ADVERTISE_PAUSE_CAP
) {
1060 if(local_adv
& ADVERTISE_PAUSE_ASYM
) {
1061 if (remote_adv
& ADVERTISE_PAUSE_CAP
) {
1062 bp
->flow_ctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1064 else if (remote_adv
& ADVERTISE_PAUSE_ASYM
) {
1065 bp
->flow_ctrl
= FLOW_CTRL_RX
;
1069 if (remote_adv
& ADVERTISE_PAUSE_CAP
) {
1070 bp
->flow_ctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1074 else if (local_adv
& ADVERTISE_PAUSE_ASYM
) {
1075 if ((remote_adv
& ADVERTISE_PAUSE_CAP
) &&
1076 (remote_adv
& ADVERTISE_PAUSE_ASYM
)) {
1078 bp
->flow_ctrl
= FLOW_CTRL_TX
;
1084 bnx2_5709s_linkup(struct bnx2
*bp
)
1090 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
, MII_BNX2_BLK_ADDR_GP_STATUS
);
1091 bnx2_read_phy(bp
, MII_BNX2_GP_TOP_AN_STATUS1
, &val
);
1092 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
, MII_BNX2_BLK_ADDR_COMBO_IEEEB0
);
1094 if ((bp
->autoneg
& AUTONEG_SPEED
) == 0) {
1095 bp
->line_speed
= bp
->req_line_speed
;
1096 bp
->duplex
= bp
->req_duplex
;
1099 speed
= val
& MII_BNX2_GP_TOP_AN_SPEED_MSK
;
1101 case MII_BNX2_GP_TOP_AN_SPEED_10
:
1102 bp
->line_speed
= SPEED_10
;
1104 case MII_BNX2_GP_TOP_AN_SPEED_100
:
1105 bp
->line_speed
= SPEED_100
;
1107 case MII_BNX2_GP_TOP_AN_SPEED_1G
:
1108 case MII_BNX2_GP_TOP_AN_SPEED_1GKV
:
1109 bp
->line_speed
= SPEED_1000
;
1111 case MII_BNX2_GP_TOP_AN_SPEED_2_5G
:
1112 bp
->line_speed
= SPEED_2500
;
1115 if (val
& MII_BNX2_GP_TOP_AN_FD
)
1116 bp
->duplex
= DUPLEX_FULL
;
1118 bp
->duplex
= DUPLEX_HALF
;
1123 bnx2_5708s_linkup(struct bnx2
*bp
)
1128 bnx2_read_phy(bp
, BCM5708S_1000X_STAT1
, &val
);
1129 switch (val
& BCM5708S_1000X_STAT1_SPEED_MASK
) {
1130 case BCM5708S_1000X_STAT1_SPEED_10
:
1131 bp
->line_speed
= SPEED_10
;
1133 case BCM5708S_1000X_STAT1_SPEED_100
:
1134 bp
->line_speed
= SPEED_100
;
1136 case BCM5708S_1000X_STAT1_SPEED_1G
:
1137 bp
->line_speed
= SPEED_1000
;
1139 case BCM5708S_1000X_STAT1_SPEED_2G5
:
1140 bp
->line_speed
= SPEED_2500
;
1143 if (val
& BCM5708S_1000X_STAT1_FD
)
1144 bp
->duplex
= DUPLEX_FULL
;
1146 bp
->duplex
= DUPLEX_HALF
;
1152 bnx2_5706s_linkup(struct bnx2
*bp
)
1154 u32 bmcr
, local_adv
, remote_adv
, common
;
1157 bp
->line_speed
= SPEED_1000
;
1159 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
1160 if (bmcr
& BMCR_FULLDPLX
) {
1161 bp
->duplex
= DUPLEX_FULL
;
1164 bp
->duplex
= DUPLEX_HALF
;
1167 if (!(bmcr
& BMCR_ANENABLE
)) {
1171 bnx2_read_phy(bp
, bp
->mii_adv
, &local_adv
);
1172 bnx2_read_phy(bp
, bp
->mii_lpa
, &remote_adv
);
1174 common
= local_adv
& remote_adv
;
1175 if (common
& (ADVERTISE_1000XHALF
| ADVERTISE_1000XFULL
)) {
1177 if (common
& ADVERTISE_1000XFULL
) {
1178 bp
->duplex
= DUPLEX_FULL
;
1181 bp
->duplex
= DUPLEX_HALF
;
1189 bnx2_copper_linkup(struct bnx2
*bp
)
1193 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
1194 if (bmcr
& BMCR_ANENABLE
) {
1195 u32 local_adv
, remote_adv
, common
;
1197 bnx2_read_phy(bp
, MII_CTRL1000
, &local_adv
);
1198 bnx2_read_phy(bp
, MII_STAT1000
, &remote_adv
);
1200 common
= local_adv
& (remote_adv
>> 2);
1201 if (common
& ADVERTISE_1000FULL
) {
1202 bp
->line_speed
= SPEED_1000
;
1203 bp
->duplex
= DUPLEX_FULL
;
1205 else if (common
& ADVERTISE_1000HALF
) {
1206 bp
->line_speed
= SPEED_1000
;
1207 bp
->duplex
= DUPLEX_HALF
;
1210 bnx2_read_phy(bp
, bp
->mii_adv
, &local_adv
);
1211 bnx2_read_phy(bp
, bp
->mii_lpa
, &remote_adv
);
1213 common
= local_adv
& remote_adv
;
1214 if (common
& ADVERTISE_100FULL
) {
1215 bp
->line_speed
= SPEED_100
;
1216 bp
->duplex
= DUPLEX_FULL
;
1218 else if (common
& ADVERTISE_100HALF
) {
1219 bp
->line_speed
= SPEED_100
;
1220 bp
->duplex
= DUPLEX_HALF
;
1222 else if (common
& ADVERTISE_10FULL
) {
1223 bp
->line_speed
= SPEED_10
;
1224 bp
->duplex
= DUPLEX_FULL
;
1226 else if (common
& ADVERTISE_10HALF
) {
1227 bp
->line_speed
= SPEED_10
;
1228 bp
->duplex
= DUPLEX_HALF
;
1237 if (bmcr
& BMCR_SPEED100
) {
1238 bp
->line_speed
= SPEED_100
;
1241 bp
->line_speed
= SPEED_10
;
1243 if (bmcr
& BMCR_FULLDPLX
) {
1244 bp
->duplex
= DUPLEX_FULL
;
1247 bp
->duplex
= DUPLEX_HALF
;
1255 bnx2_init_rx_context(struct bnx2
*bp
, u32 cid
)
1257 u32 val
, rx_cid_addr
= GET_CID_ADDR(cid
);
1259 val
= BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE
;
1260 val
|= BNX2_L2CTX_CTX_TYPE_SIZE_L2
;
1263 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
1264 u32 lo_water
, hi_water
;
1266 if (bp
->flow_ctrl
& FLOW_CTRL_TX
)
1267 lo_water
= BNX2_L2CTX_LO_WATER_MARK_DEFAULT
;
1269 lo_water
= BNX2_L2CTX_LO_WATER_MARK_DIS
;
1270 if (lo_water
>= bp
->rx_ring_size
)
1273 hi_water
= bp
->rx_ring_size
/ 4;
1275 if (hi_water
<= lo_water
)
1278 hi_water
/= BNX2_L2CTX_HI_WATER_MARK_SCALE
;
1279 lo_water
/= BNX2_L2CTX_LO_WATER_MARK_SCALE
;
1283 else if (hi_water
== 0)
1285 val
|= lo_water
| (hi_water
<< BNX2_L2CTX_HI_WATER_MARK_SHIFT
);
1287 bnx2_ctx_wr(bp
, rx_cid_addr
, BNX2_L2CTX_CTX_TYPE
, val
);
1291 bnx2_init_all_rx_contexts(struct bnx2
*bp
)
1296 for (i
= 0, cid
= RX_CID
; i
< bp
->num_rx_rings
; i
++, cid
++) {
1299 bnx2_init_rx_context(bp
, cid
);
1304 bnx2_set_mac_link(struct bnx2
*bp
)
1308 REG_WR(bp
, BNX2_EMAC_TX_LENGTHS
, 0x2620);
1309 if (bp
->link_up
&& (bp
->line_speed
== SPEED_1000
) &&
1310 (bp
->duplex
== DUPLEX_HALF
)) {
1311 REG_WR(bp
, BNX2_EMAC_TX_LENGTHS
, 0x26ff);
1314 /* Configure the EMAC mode register. */
1315 val
= REG_RD(bp
, BNX2_EMAC_MODE
);
1317 val
&= ~(BNX2_EMAC_MODE_PORT
| BNX2_EMAC_MODE_HALF_DUPLEX
|
1318 BNX2_EMAC_MODE_MAC_LOOP
| BNX2_EMAC_MODE_FORCE_LINK
|
1319 BNX2_EMAC_MODE_25G_MODE
);
1322 switch (bp
->line_speed
) {
1324 if (CHIP_NUM(bp
) != CHIP_NUM_5706
) {
1325 val
|= BNX2_EMAC_MODE_PORT_MII_10M
;
1330 val
|= BNX2_EMAC_MODE_PORT_MII
;
1333 val
|= BNX2_EMAC_MODE_25G_MODE
;
1336 val
|= BNX2_EMAC_MODE_PORT_GMII
;
1341 val
|= BNX2_EMAC_MODE_PORT_GMII
;
1344 /* Set the MAC to operate in the appropriate duplex mode. */
1345 if (bp
->duplex
== DUPLEX_HALF
)
1346 val
|= BNX2_EMAC_MODE_HALF_DUPLEX
;
1347 REG_WR(bp
, BNX2_EMAC_MODE
, val
);
1349 /* Enable/disable rx PAUSE. */
1350 bp
->rx_mode
&= ~BNX2_EMAC_RX_MODE_FLOW_EN
;
1352 if (bp
->flow_ctrl
& FLOW_CTRL_RX
)
1353 bp
->rx_mode
|= BNX2_EMAC_RX_MODE_FLOW_EN
;
1354 REG_WR(bp
, BNX2_EMAC_RX_MODE
, bp
->rx_mode
);
1356 /* Enable/disable tx PAUSE. */
1357 val
= REG_RD(bp
, BNX2_EMAC_TX_MODE
);
1358 val
&= ~BNX2_EMAC_TX_MODE_FLOW_EN
;
1360 if (bp
->flow_ctrl
& FLOW_CTRL_TX
)
1361 val
|= BNX2_EMAC_TX_MODE_FLOW_EN
;
1362 REG_WR(bp
, BNX2_EMAC_TX_MODE
, val
);
1364 /* Acknowledge the interrupt. */
1365 REG_WR(bp
, BNX2_EMAC_STATUS
, BNX2_EMAC_STATUS_LINK_CHANGE
);
1367 if (CHIP_NUM(bp
) == CHIP_NUM_5709
)
1368 bnx2_init_all_rx_contexts(bp
);
1372 bnx2_enable_bmsr1(struct bnx2
*bp
)
1374 if ((bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) &&
1375 (CHIP_NUM(bp
) == CHIP_NUM_5709
))
1376 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
,
1377 MII_BNX2_BLK_ADDR_GP_STATUS
);
1381 bnx2_disable_bmsr1(struct bnx2
*bp
)
1383 if ((bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) &&
1384 (CHIP_NUM(bp
) == CHIP_NUM_5709
))
1385 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
,
1386 MII_BNX2_BLK_ADDR_COMBO_IEEEB0
);
1390 bnx2_test_and_enable_2g5(struct bnx2
*bp
)
1395 if (!(bp
->phy_flags
& BNX2_PHY_FLAG_2_5G_CAPABLE
))
1398 if (bp
->autoneg
& AUTONEG_SPEED
)
1399 bp
->advertising
|= ADVERTISED_2500baseX_Full
;
1401 if (CHIP_NUM(bp
) == CHIP_NUM_5709
)
1402 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
, MII_BNX2_BLK_ADDR_OVER1G
);
1404 bnx2_read_phy(bp
, bp
->mii_up1
, &up1
);
1405 if (!(up1
& BCM5708S_UP1_2G5
)) {
1406 up1
|= BCM5708S_UP1_2G5
;
1407 bnx2_write_phy(bp
, bp
->mii_up1
, up1
);
1411 if (CHIP_NUM(bp
) == CHIP_NUM_5709
)
1412 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
,
1413 MII_BNX2_BLK_ADDR_COMBO_IEEEB0
);
1419 bnx2_test_and_disable_2g5(struct bnx2
*bp
)
1424 if (!(bp
->phy_flags
& BNX2_PHY_FLAG_2_5G_CAPABLE
))
1427 if (CHIP_NUM(bp
) == CHIP_NUM_5709
)
1428 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
, MII_BNX2_BLK_ADDR_OVER1G
);
1430 bnx2_read_phy(bp
, bp
->mii_up1
, &up1
);
1431 if (up1
& BCM5708S_UP1_2G5
) {
1432 up1
&= ~BCM5708S_UP1_2G5
;
1433 bnx2_write_phy(bp
, bp
->mii_up1
, up1
);
1437 if (CHIP_NUM(bp
) == CHIP_NUM_5709
)
1438 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
,
1439 MII_BNX2_BLK_ADDR_COMBO_IEEEB0
);
1445 bnx2_enable_forced_2g5(struct bnx2
*bp
)
1449 if (!(bp
->phy_flags
& BNX2_PHY_FLAG_2_5G_CAPABLE
))
1452 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
1455 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
,
1456 MII_BNX2_BLK_ADDR_SERDES_DIG
);
1457 bnx2_read_phy(bp
, MII_BNX2_SERDES_DIG_MISC1
, &val
);
1458 val
&= ~MII_BNX2_SD_MISC1_FORCE_MSK
;
1459 val
|= MII_BNX2_SD_MISC1_FORCE
| MII_BNX2_SD_MISC1_FORCE_2_5G
;
1460 bnx2_write_phy(bp
, MII_BNX2_SERDES_DIG_MISC1
, val
);
1462 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
,
1463 MII_BNX2_BLK_ADDR_COMBO_IEEEB0
);
1464 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
1466 } else if (CHIP_NUM(bp
) == CHIP_NUM_5708
) {
1467 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
1468 bmcr
|= BCM5708S_BMCR_FORCE_2500
;
1471 if (bp
->autoneg
& AUTONEG_SPEED
) {
1472 bmcr
&= ~BMCR_ANENABLE
;
1473 if (bp
->req_duplex
== DUPLEX_FULL
)
1474 bmcr
|= BMCR_FULLDPLX
;
1476 bnx2_write_phy(bp
, bp
->mii_bmcr
, bmcr
);
1480 bnx2_disable_forced_2g5(struct bnx2
*bp
)
1484 if (!(bp
->phy_flags
& BNX2_PHY_FLAG_2_5G_CAPABLE
))
1487 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
1490 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
,
1491 MII_BNX2_BLK_ADDR_SERDES_DIG
);
1492 bnx2_read_phy(bp
, MII_BNX2_SERDES_DIG_MISC1
, &val
);
1493 val
&= ~MII_BNX2_SD_MISC1_FORCE
;
1494 bnx2_write_phy(bp
, MII_BNX2_SERDES_DIG_MISC1
, val
);
1496 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
,
1497 MII_BNX2_BLK_ADDR_COMBO_IEEEB0
);
1498 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
1500 } else if (CHIP_NUM(bp
) == CHIP_NUM_5708
) {
1501 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
1502 bmcr
&= ~BCM5708S_BMCR_FORCE_2500
;
1505 if (bp
->autoneg
& AUTONEG_SPEED
)
1506 bmcr
|= BMCR_SPEED1000
| BMCR_ANENABLE
| BMCR_ANRESTART
;
1507 bnx2_write_phy(bp
, bp
->mii_bmcr
, bmcr
);
1511 bnx2_5706s_force_link_dn(struct bnx2
*bp
, int start
)
1515 bnx2_write_phy(bp
, MII_BNX2_DSP_ADDRESS
, MII_EXPAND_SERDES_CTL
);
1516 bnx2_read_phy(bp
, MII_BNX2_DSP_RW_PORT
, &val
);
1518 bnx2_write_phy(bp
, MII_BNX2_DSP_RW_PORT
, val
& 0xff0f);
1520 bnx2_write_phy(bp
, MII_BNX2_DSP_RW_PORT
, val
| 0xc0);
1524 bnx2_set_link(struct bnx2
*bp
)
1529 if (bp
->loopback
== MAC_LOOPBACK
|| bp
->loopback
== PHY_LOOPBACK
) {
1534 if (bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
)
1537 link_up
= bp
->link_up
;
1539 bnx2_enable_bmsr1(bp
);
1540 bnx2_read_phy(bp
, bp
->mii_bmsr1
, &bmsr
);
1541 bnx2_read_phy(bp
, bp
->mii_bmsr1
, &bmsr
);
1542 bnx2_disable_bmsr1(bp
);
1544 if ((bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) &&
1545 (CHIP_NUM(bp
) == CHIP_NUM_5706
)) {
1548 if (bp
->phy_flags
& BNX2_PHY_FLAG_FORCED_DOWN
) {
1549 bnx2_5706s_force_link_dn(bp
, 0);
1550 bp
->phy_flags
&= ~BNX2_PHY_FLAG_FORCED_DOWN
;
1552 val
= REG_RD(bp
, BNX2_EMAC_STATUS
);
1554 bnx2_write_phy(bp
, MII_BNX2_MISC_SHADOW
, MISC_SHDW_AN_DBG
);
1555 bnx2_read_phy(bp
, MII_BNX2_MISC_SHADOW
, &an_dbg
);
1556 bnx2_read_phy(bp
, MII_BNX2_MISC_SHADOW
, &an_dbg
);
1558 if ((val
& BNX2_EMAC_STATUS_LINK
) &&
1559 !(an_dbg
& MISC_SHDW_AN_DBG_NOSYNC
))
1560 bmsr
|= BMSR_LSTATUS
;
1562 bmsr
&= ~BMSR_LSTATUS
;
1565 if (bmsr
& BMSR_LSTATUS
) {
1568 if (bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) {
1569 if (CHIP_NUM(bp
) == CHIP_NUM_5706
)
1570 bnx2_5706s_linkup(bp
);
1571 else if (CHIP_NUM(bp
) == CHIP_NUM_5708
)
1572 bnx2_5708s_linkup(bp
);
1573 else if (CHIP_NUM(bp
) == CHIP_NUM_5709
)
1574 bnx2_5709s_linkup(bp
);
1577 bnx2_copper_linkup(bp
);
1579 bnx2_resolve_flow_ctrl(bp
);
1582 if ((bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) &&
1583 (bp
->autoneg
& AUTONEG_SPEED
))
1584 bnx2_disable_forced_2g5(bp
);
1586 if (bp
->phy_flags
& BNX2_PHY_FLAG_PARALLEL_DETECT
) {
1589 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
1590 bmcr
|= BMCR_ANENABLE
;
1591 bnx2_write_phy(bp
, bp
->mii_bmcr
, bmcr
);
1593 bp
->phy_flags
&= ~BNX2_PHY_FLAG_PARALLEL_DETECT
;
1598 if (bp
->link_up
!= link_up
) {
1599 bnx2_report_link(bp
);
1602 bnx2_set_mac_link(bp
);
1608 bnx2_reset_phy(struct bnx2
*bp
)
1613 bnx2_write_phy(bp
, bp
->mii_bmcr
, BMCR_RESET
);
1615 #define PHY_RESET_MAX_WAIT 100
1616 for (i
= 0; i
< PHY_RESET_MAX_WAIT
; i
++) {
1619 bnx2_read_phy(bp
, bp
->mii_bmcr
, ®
);
1620 if (!(reg
& BMCR_RESET
)) {
1625 if (i
== PHY_RESET_MAX_WAIT
) {
1632 bnx2_phy_get_pause_adv(struct bnx2
*bp
)
1636 if ((bp
->req_flow_ctrl
& (FLOW_CTRL_RX
| FLOW_CTRL_TX
)) ==
1637 (FLOW_CTRL_RX
| FLOW_CTRL_TX
)) {
1639 if (bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) {
1640 adv
= ADVERTISE_1000XPAUSE
;
1643 adv
= ADVERTISE_PAUSE_CAP
;
1646 else if (bp
->req_flow_ctrl
& FLOW_CTRL_TX
) {
1647 if (bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) {
1648 adv
= ADVERTISE_1000XPSE_ASYM
;
1651 adv
= ADVERTISE_PAUSE_ASYM
;
1654 else if (bp
->req_flow_ctrl
& FLOW_CTRL_RX
) {
1655 if (bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) {
1656 adv
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1659 adv
= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1665 static int bnx2_fw_sync(struct bnx2
*, u32
, int, int);
1668 bnx2_setup_remote_phy(struct bnx2
*bp
, u8 port
)
1669 __releases(&bp
->phy_lock
)
1670 __acquires(&bp
->phy_lock
)
1672 u32 speed_arg
= 0, pause_adv
;
1674 pause_adv
= bnx2_phy_get_pause_adv(bp
);
1676 if (bp
->autoneg
& AUTONEG_SPEED
) {
1677 speed_arg
|= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG
;
1678 if (bp
->advertising
& ADVERTISED_10baseT_Half
)
1679 speed_arg
|= BNX2_NETLINK_SET_LINK_SPEED_10HALF
;
1680 if (bp
->advertising
& ADVERTISED_10baseT_Full
)
1681 speed_arg
|= BNX2_NETLINK_SET_LINK_SPEED_10FULL
;
1682 if (bp
->advertising
& ADVERTISED_100baseT_Half
)
1683 speed_arg
|= BNX2_NETLINK_SET_LINK_SPEED_100HALF
;
1684 if (bp
->advertising
& ADVERTISED_100baseT_Full
)
1685 speed_arg
|= BNX2_NETLINK_SET_LINK_SPEED_100FULL
;
1686 if (bp
->advertising
& ADVERTISED_1000baseT_Full
)
1687 speed_arg
|= BNX2_NETLINK_SET_LINK_SPEED_1GFULL
;
1688 if (bp
->advertising
& ADVERTISED_2500baseX_Full
)
1689 speed_arg
|= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL
;
1691 if (bp
->req_line_speed
== SPEED_2500
)
1692 speed_arg
= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL
;
1693 else if (bp
->req_line_speed
== SPEED_1000
)
1694 speed_arg
= BNX2_NETLINK_SET_LINK_SPEED_1GFULL
;
1695 else if (bp
->req_line_speed
== SPEED_100
) {
1696 if (bp
->req_duplex
== DUPLEX_FULL
)
1697 speed_arg
= BNX2_NETLINK_SET_LINK_SPEED_100FULL
;
1699 speed_arg
= BNX2_NETLINK_SET_LINK_SPEED_100HALF
;
1700 } else if (bp
->req_line_speed
== SPEED_10
) {
1701 if (bp
->req_duplex
== DUPLEX_FULL
)
1702 speed_arg
= BNX2_NETLINK_SET_LINK_SPEED_10FULL
;
1704 speed_arg
= BNX2_NETLINK_SET_LINK_SPEED_10HALF
;
1708 if (pause_adv
& (ADVERTISE_1000XPAUSE
| ADVERTISE_PAUSE_CAP
))
1709 speed_arg
|= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE
;
1710 if (pause_adv
& (ADVERTISE_1000XPSE_ASYM
| ADVERTISE_PAUSE_ASYM
))
1711 speed_arg
|= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE
;
1713 if (port
== PORT_TP
)
1714 speed_arg
|= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE
|
1715 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED
;
1717 bnx2_shmem_wr(bp
, BNX2_DRV_MB_ARG0
, speed_arg
);
1719 spin_unlock_bh(&bp
->phy_lock
);
1720 bnx2_fw_sync(bp
, BNX2_DRV_MSG_CODE_CMD_SET_LINK
, 1, 0);
1721 spin_lock_bh(&bp
->phy_lock
);
1727 bnx2_setup_serdes_phy(struct bnx2
*bp
, u8 port
)
1728 __releases(&bp
->phy_lock
)
1729 __acquires(&bp
->phy_lock
)
1734 if (bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
)
1735 return (bnx2_setup_remote_phy(bp
, port
));
1737 if (!(bp
->autoneg
& AUTONEG_SPEED
)) {
1739 int force_link_down
= 0;
1741 if (bp
->req_line_speed
== SPEED_2500
) {
1742 if (!bnx2_test_and_enable_2g5(bp
))
1743 force_link_down
= 1;
1744 } else if (bp
->req_line_speed
== SPEED_1000
) {
1745 if (bnx2_test_and_disable_2g5(bp
))
1746 force_link_down
= 1;
1748 bnx2_read_phy(bp
, bp
->mii_adv
, &adv
);
1749 adv
&= ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
);
1751 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
1752 new_bmcr
= bmcr
& ~BMCR_ANENABLE
;
1753 new_bmcr
|= BMCR_SPEED1000
;
1755 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
1756 if (bp
->req_line_speed
== SPEED_2500
)
1757 bnx2_enable_forced_2g5(bp
);
1758 else if (bp
->req_line_speed
== SPEED_1000
) {
1759 bnx2_disable_forced_2g5(bp
);
1760 new_bmcr
&= ~0x2000;
1763 } else if (CHIP_NUM(bp
) == CHIP_NUM_5708
) {
1764 if (bp
->req_line_speed
== SPEED_2500
)
1765 new_bmcr
|= BCM5708S_BMCR_FORCE_2500
;
1767 new_bmcr
= bmcr
& ~BCM5708S_BMCR_FORCE_2500
;
1770 if (bp
->req_duplex
== DUPLEX_FULL
) {
1771 adv
|= ADVERTISE_1000XFULL
;
1772 new_bmcr
|= BMCR_FULLDPLX
;
1775 adv
|= ADVERTISE_1000XHALF
;
1776 new_bmcr
&= ~BMCR_FULLDPLX
;
1778 if ((new_bmcr
!= bmcr
) || (force_link_down
)) {
1779 /* Force a link down visible on the other side */
1781 bnx2_write_phy(bp
, bp
->mii_adv
, adv
&
1782 ~(ADVERTISE_1000XFULL
|
1783 ADVERTISE_1000XHALF
));
1784 bnx2_write_phy(bp
, bp
->mii_bmcr
, bmcr
|
1785 BMCR_ANRESTART
| BMCR_ANENABLE
);
1788 netif_carrier_off(bp
->dev
);
1789 bnx2_write_phy(bp
, bp
->mii_bmcr
, new_bmcr
);
1790 bnx2_report_link(bp
);
1792 bnx2_write_phy(bp
, bp
->mii_adv
, adv
);
1793 bnx2_write_phy(bp
, bp
->mii_bmcr
, new_bmcr
);
1795 bnx2_resolve_flow_ctrl(bp
);
1796 bnx2_set_mac_link(bp
);
1801 bnx2_test_and_enable_2g5(bp
);
1803 if (bp
->advertising
& ADVERTISED_1000baseT_Full
)
1804 new_adv
|= ADVERTISE_1000XFULL
;
1806 new_adv
|= bnx2_phy_get_pause_adv(bp
);
1808 bnx2_read_phy(bp
, bp
->mii_adv
, &adv
);
1809 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
1811 bp
->serdes_an_pending
= 0;
1812 if ((adv
!= new_adv
) || ((bmcr
& BMCR_ANENABLE
) == 0)) {
1813 /* Force a link down visible on the other side */
1815 bnx2_write_phy(bp
, bp
->mii_bmcr
, BMCR_LOOPBACK
);
1816 spin_unlock_bh(&bp
->phy_lock
);
1818 spin_lock_bh(&bp
->phy_lock
);
1821 bnx2_write_phy(bp
, bp
->mii_adv
, new_adv
);
1822 bnx2_write_phy(bp
, bp
->mii_bmcr
, bmcr
| BMCR_ANRESTART
|
1824 /* Speed up link-up time when the link partner
1825 * does not autonegotiate which is very common
1826 * in blade servers. Some blade servers use
1827 * IPMI for kerboard input and it's important
1828 * to minimize link disruptions. Autoneg. involves
1829 * exchanging base pages plus 3 next pages and
1830 * normally completes in about 120 msec.
1832 bp
->current_interval
= BNX2_SERDES_AN_TIMEOUT
;
1833 bp
->serdes_an_pending
= 1;
1834 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
1836 bnx2_resolve_flow_ctrl(bp
);
1837 bnx2_set_mac_link(bp
);
1843 #define ETHTOOL_ALL_FIBRE_SPEED \
1844 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1845 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1846 (ADVERTISED_1000baseT_Full)
1848 #define ETHTOOL_ALL_COPPER_SPEED \
1849 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1850 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1851 ADVERTISED_1000baseT_Full)
1853 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1854 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1856 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1859 bnx2_set_default_remote_link(struct bnx2
*bp
)
1863 if (bp
->phy_port
== PORT_TP
)
1864 link
= bnx2_shmem_rd(bp
, BNX2_RPHY_COPPER_LINK
);
1866 link
= bnx2_shmem_rd(bp
, BNX2_RPHY_SERDES_LINK
);
1868 if (link
& BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG
) {
1869 bp
->req_line_speed
= 0;
1870 bp
->autoneg
|= AUTONEG_SPEED
;
1871 bp
->advertising
= ADVERTISED_Autoneg
;
1872 if (link
& BNX2_NETLINK_SET_LINK_SPEED_10HALF
)
1873 bp
->advertising
|= ADVERTISED_10baseT_Half
;
1874 if (link
& BNX2_NETLINK_SET_LINK_SPEED_10FULL
)
1875 bp
->advertising
|= ADVERTISED_10baseT_Full
;
1876 if (link
& BNX2_NETLINK_SET_LINK_SPEED_100HALF
)
1877 bp
->advertising
|= ADVERTISED_100baseT_Half
;
1878 if (link
& BNX2_NETLINK_SET_LINK_SPEED_100FULL
)
1879 bp
->advertising
|= ADVERTISED_100baseT_Full
;
1880 if (link
& BNX2_NETLINK_SET_LINK_SPEED_1GFULL
)
1881 bp
->advertising
|= ADVERTISED_1000baseT_Full
;
1882 if (link
& BNX2_NETLINK_SET_LINK_SPEED_2G5FULL
)
1883 bp
->advertising
|= ADVERTISED_2500baseX_Full
;
1886 bp
->advertising
= 0;
1887 bp
->req_duplex
= DUPLEX_FULL
;
1888 if (link
& BNX2_NETLINK_SET_LINK_SPEED_10
) {
1889 bp
->req_line_speed
= SPEED_10
;
1890 if (link
& BNX2_NETLINK_SET_LINK_SPEED_10HALF
)
1891 bp
->req_duplex
= DUPLEX_HALF
;
1893 if (link
& BNX2_NETLINK_SET_LINK_SPEED_100
) {
1894 bp
->req_line_speed
= SPEED_100
;
1895 if (link
& BNX2_NETLINK_SET_LINK_SPEED_100HALF
)
1896 bp
->req_duplex
= DUPLEX_HALF
;
1898 if (link
& BNX2_NETLINK_SET_LINK_SPEED_1GFULL
)
1899 bp
->req_line_speed
= SPEED_1000
;
1900 if (link
& BNX2_NETLINK_SET_LINK_SPEED_2G5FULL
)
1901 bp
->req_line_speed
= SPEED_2500
;
1906 bnx2_set_default_link(struct bnx2
*bp
)
1908 if (bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
) {
1909 bnx2_set_default_remote_link(bp
);
1913 bp
->autoneg
= AUTONEG_SPEED
| AUTONEG_FLOW_CTRL
;
1914 bp
->req_line_speed
= 0;
1915 if (bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) {
1918 bp
->advertising
= ETHTOOL_ALL_FIBRE_SPEED
| ADVERTISED_Autoneg
;
1920 reg
= bnx2_shmem_rd(bp
, BNX2_PORT_HW_CFG_CONFIG
);
1921 reg
&= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK
;
1922 if (reg
== BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G
) {
1924 bp
->req_line_speed
= bp
->line_speed
= SPEED_1000
;
1925 bp
->req_duplex
= DUPLEX_FULL
;
1928 bp
->advertising
= ETHTOOL_ALL_COPPER_SPEED
| ADVERTISED_Autoneg
;
1932 bnx2_send_heart_beat(struct bnx2
*bp
)
1937 spin_lock(&bp
->indirect_lock
);
1938 msg
= (u32
) (++bp
->fw_drv_pulse_wr_seq
& BNX2_DRV_PULSE_SEQ_MASK
);
1939 addr
= bp
->shmem_base
+ BNX2_DRV_PULSE_MB
;
1940 REG_WR(bp
, BNX2_PCICFG_REG_WINDOW_ADDRESS
, addr
);
1941 REG_WR(bp
, BNX2_PCICFG_REG_WINDOW
, msg
);
1942 spin_unlock(&bp
->indirect_lock
);
1946 bnx2_remote_phy_event(struct bnx2
*bp
)
1949 u8 link_up
= bp
->link_up
;
1952 msg
= bnx2_shmem_rd(bp
, BNX2_LINK_STATUS
);
1954 if (msg
& BNX2_LINK_STATUS_HEART_BEAT_EXPIRED
)
1955 bnx2_send_heart_beat(bp
);
1957 msg
&= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED
;
1959 if ((msg
& BNX2_LINK_STATUS_LINK_UP
) == BNX2_LINK_STATUS_LINK_DOWN
)
1965 speed
= msg
& BNX2_LINK_STATUS_SPEED_MASK
;
1966 bp
->duplex
= DUPLEX_FULL
;
1968 case BNX2_LINK_STATUS_10HALF
:
1969 bp
->duplex
= DUPLEX_HALF
;
1970 case BNX2_LINK_STATUS_10FULL
:
1971 bp
->line_speed
= SPEED_10
;
1973 case BNX2_LINK_STATUS_100HALF
:
1974 bp
->duplex
= DUPLEX_HALF
;
1975 case BNX2_LINK_STATUS_100BASE_T4
:
1976 case BNX2_LINK_STATUS_100FULL
:
1977 bp
->line_speed
= SPEED_100
;
1979 case BNX2_LINK_STATUS_1000HALF
:
1980 bp
->duplex
= DUPLEX_HALF
;
1981 case BNX2_LINK_STATUS_1000FULL
:
1982 bp
->line_speed
= SPEED_1000
;
1984 case BNX2_LINK_STATUS_2500HALF
:
1985 bp
->duplex
= DUPLEX_HALF
;
1986 case BNX2_LINK_STATUS_2500FULL
:
1987 bp
->line_speed
= SPEED_2500
;
1995 if ((bp
->autoneg
& (AUTONEG_SPEED
| AUTONEG_FLOW_CTRL
)) !=
1996 (AUTONEG_SPEED
| AUTONEG_FLOW_CTRL
)) {
1997 if (bp
->duplex
== DUPLEX_FULL
)
1998 bp
->flow_ctrl
= bp
->req_flow_ctrl
;
2000 if (msg
& BNX2_LINK_STATUS_TX_FC_ENABLED
)
2001 bp
->flow_ctrl
|= FLOW_CTRL_TX
;
2002 if (msg
& BNX2_LINK_STATUS_RX_FC_ENABLED
)
2003 bp
->flow_ctrl
|= FLOW_CTRL_RX
;
2006 old_port
= bp
->phy_port
;
2007 if (msg
& BNX2_LINK_STATUS_SERDES_LINK
)
2008 bp
->phy_port
= PORT_FIBRE
;
2010 bp
->phy_port
= PORT_TP
;
2012 if (old_port
!= bp
->phy_port
)
2013 bnx2_set_default_link(bp
);
2016 if (bp
->link_up
!= link_up
)
2017 bnx2_report_link(bp
);
2019 bnx2_set_mac_link(bp
);
2023 bnx2_set_remote_link(struct bnx2
*bp
)
2027 evt_code
= bnx2_shmem_rd(bp
, BNX2_FW_EVT_CODE_MB
);
2029 case BNX2_FW_EVT_CODE_LINK_EVENT
:
2030 bnx2_remote_phy_event(bp
);
2032 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT
:
2034 bnx2_send_heart_beat(bp
);
2041 bnx2_setup_copper_phy(struct bnx2
*bp
)
2042 __releases(&bp
->phy_lock
)
2043 __acquires(&bp
->phy_lock
)
2048 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
2050 if (bp
->autoneg
& AUTONEG_SPEED
) {
2051 u32 adv_reg
, adv1000_reg
;
2052 u32 new_adv_reg
= 0;
2053 u32 new_adv1000_reg
= 0;
2055 bnx2_read_phy(bp
, bp
->mii_adv
, &adv_reg
);
2056 adv_reg
&= (PHY_ALL_10_100_SPEED
| ADVERTISE_PAUSE_CAP
|
2057 ADVERTISE_PAUSE_ASYM
);
2059 bnx2_read_phy(bp
, MII_CTRL1000
, &adv1000_reg
);
2060 adv1000_reg
&= PHY_ALL_1000_SPEED
;
2062 if (bp
->advertising
& ADVERTISED_10baseT_Half
)
2063 new_adv_reg
|= ADVERTISE_10HALF
;
2064 if (bp
->advertising
& ADVERTISED_10baseT_Full
)
2065 new_adv_reg
|= ADVERTISE_10FULL
;
2066 if (bp
->advertising
& ADVERTISED_100baseT_Half
)
2067 new_adv_reg
|= ADVERTISE_100HALF
;
2068 if (bp
->advertising
& ADVERTISED_100baseT_Full
)
2069 new_adv_reg
|= ADVERTISE_100FULL
;
2070 if (bp
->advertising
& ADVERTISED_1000baseT_Full
)
2071 new_adv1000_reg
|= ADVERTISE_1000FULL
;
2073 new_adv_reg
|= ADVERTISE_CSMA
;
2075 new_adv_reg
|= bnx2_phy_get_pause_adv(bp
);
2077 if ((adv1000_reg
!= new_adv1000_reg
) ||
2078 (adv_reg
!= new_adv_reg
) ||
2079 ((bmcr
& BMCR_ANENABLE
) == 0)) {
2081 bnx2_write_phy(bp
, bp
->mii_adv
, new_adv_reg
);
2082 bnx2_write_phy(bp
, MII_CTRL1000
, new_adv1000_reg
);
2083 bnx2_write_phy(bp
, bp
->mii_bmcr
, BMCR_ANRESTART
|
2086 else if (bp
->link_up
) {
2087 /* Flow ctrl may have changed from auto to forced */
2088 /* or vice-versa. */
2090 bnx2_resolve_flow_ctrl(bp
);
2091 bnx2_set_mac_link(bp
);
2097 if (bp
->req_line_speed
== SPEED_100
) {
2098 new_bmcr
|= BMCR_SPEED100
;
2100 if (bp
->req_duplex
== DUPLEX_FULL
) {
2101 new_bmcr
|= BMCR_FULLDPLX
;
2103 if (new_bmcr
!= bmcr
) {
2106 bnx2_read_phy(bp
, bp
->mii_bmsr
, &bmsr
);
2107 bnx2_read_phy(bp
, bp
->mii_bmsr
, &bmsr
);
2109 if (bmsr
& BMSR_LSTATUS
) {
2110 /* Force link down */
2111 bnx2_write_phy(bp
, bp
->mii_bmcr
, BMCR_LOOPBACK
);
2112 spin_unlock_bh(&bp
->phy_lock
);
2114 spin_lock_bh(&bp
->phy_lock
);
2116 bnx2_read_phy(bp
, bp
->mii_bmsr
, &bmsr
);
2117 bnx2_read_phy(bp
, bp
->mii_bmsr
, &bmsr
);
2120 bnx2_write_phy(bp
, bp
->mii_bmcr
, new_bmcr
);
2122 /* Normally, the new speed is setup after the link has
2123 * gone down and up again. In some cases, link will not go
2124 * down so we need to set up the new speed here.
2126 if (bmsr
& BMSR_LSTATUS
) {
2127 bp
->line_speed
= bp
->req_line_speed
;
2128 bp
->duplex
= bp
->req_duplex
;
2129 bnx2_resolve_flow_ctrl(bp
);
2130 bnx2_set_mac_link(bp
);
2133 bnx2_resolve_flow_ctrl(bp
);
2134 bnx2_set_mac_link(bp
);
2140 bnx2_setup_phy(struct bnx2
*bp
, u8 port
)
2141 __releases(&bp
->phy_lock
)
2142 __acquires(&bp
->phy_lock
)
2144 if (bp
->loopback
== MAC_LOOPBACK
)
2147 if (bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) {
2148 return (bnx2_setup_serdes_phy(bp
, port
));
2151 return (bnx2_setup_copper_phy(bp
));
2156 bnx2_init_5709s_phy(struct bnx2
*bp
, int reset_phy
)
2160 bp
->mii_bmcr
= MII_BMCR
+ 0x10;
2161 bp
->mii_bmsr
= MII_BMSR
+ 0x10;
2162 bp
->mii_bmsr1
= MII_BNX2_GP_TOP_AN_STATUS1
;
2163 bp
->mii_adv
= MII_ADVERTISE
+ 0x10;
2164 bp
->mii_lpa
= MII_LPA
+ 0x10;
2165 bp
->mii_up1
= MII_BNX2_OVER1G_UP1
;
2167 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
, MII_BNX2_BLK_ADDR_AER
);
2168 bnx2_write_phy(bp
, MII_BNX2_AER_AER
, MII_BNX2_AER_AER_AN_MMD
);
2170 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
, MII_BNX2_BLK_ADDR_COMBO_IEEEB0
);
2174 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
, MII_BNX2_BLK_ADDR_SERDES_DIG
);
2176 bnx2_read_phy(bp
, MII_BNX2_SERDES_DIG_1000XCTL1
, &val
);
2177 val
&= ~MII_BNX2_SD_1000XCTL1_AUTODET
;
2178 val
|= MII_BNX2_SD_1000XCTL1_FIBER
;
2179 bnx2_write_phy(bp
, MII_BNX2_SERDES_DIG_1000XCTL1
, val
);
2181 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
, MII_BNX2_BLK_ADDR_OVER1G
);
2182 bnx2_read_phy(bp
, MII_BNX2_OVER1G_UP1
, &val
);
2183 if (bp
->phy_flags
& BNX2_PHY_FLAG_2_5G_CAPABLE
)
2184 val
|= BCM5708S_UP1_2G5
;
2186 val
&= ~BCM5708S_UP1_2G5
;
2187 bnx2_write_phy(bp
, MII_BNX2_OVER1G_UP1
, val
);
2189 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
, MII_BNX2_BLK_ADDR_BAM_NXTPG
);
2190 bnx2_read_phy(bp
, MII_BNX2_BAM_NXTPG_CTL
, &val
);
2191 val
|= MII_BNX2_NXTPG_CTL_T2
| MII_BNX2_NXTPG_CTL_BAM
;
2192 bnx2_write_phy(bp
, MII_BNX2_BAM_NXTPG_CTL
, val
);
2194 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
, MII_BNX2_BLK_ADDR_CL73_USERB0
);
2196 val
= MII_BNX2_CL73_BAM_EN
| MII_BNX2_CL73_BAM_STA_MGR_EN
|
2197 MII_BNX2_CL73_BAM_NP_AFT_BP_EN
;
2198 bnx2_write_phy(bp
, MII_BNX2_CL73_BAM_CTL1
, val
);
2200 bnx2_write_phy(bp
, MII_BNX2_BLK_ADDR
, MII_BNX2_BLK_ADDR_COMBO_IEEEB0
);
2206 bnx2_init_5708s_phy(struct bnx2
*bp
, int reset_phy
)
2213 bp
->mii_up1
= BCM5708S_UP1
;
2215 bnx2_write_phy(bp
, BCM5708S_BLK_ADDR
, BCM5708S_BLK_ADDR_DIG3
);
2216 bnx2_write_phy(bp
, BCM5708S_DIG_3_0
, BCM5708S_DIG_3_0_USE_IEEE
);
2217 bnx2_write_phy(bp
, BCM5708S_BLK_ADDR
, BCM5708S_BLK_ADDR_DIG
);
2219 bnx2_read_phy(bp
, BCM5708S_1000X_CTL1
, &val
);
2220 val
|= BCM5708S_1000X_CTL1_FIBER_MODE
| BCM5708S_1000X_CTL1_AUTODET_EN
;
2221 bnx2_write_phy(bp
, BCM5708S_1000X_CTL1
, val
);
2223 bnx2_read_phy(bp
, BCM5708S_1000X_CTL2
, &val
);
2224 val
|= BCM5708S_1000X_CTL2_PLLEL_DET_EN
;
2225 bnx2_write_phy(bp
, BCM5708S_1000X_CTL2
, val
);
2227 if (bp
->phy_flags
& BNX2_PHY_FLAG_2_5G_CAPABLE
) {
2228 bnx2_read_phy(bp
, BCM5708S_UP1
, &val
);
2229 val
|= BCM5708S_UP1_2G5
;
2230 bnx2_write_phy(bp
, BCM5708S_UP1
, val
);
2233 if ((CHIP_ID(bp
) == CHIP_ID_5708_A0
) ||
2234 (CHIP_ID(bp
) == CHIP_ID_5708_B0
) ||
2235 (CHIP_ID(bp
) == CHIP_ID_5708_B1
)) {
2236 /* increase tx signal amplitude */
2237 bnx2_write_phy(bp
, BCM5708S_BLK_ADDR
,
2238 BCM5708S_BLK_ADDR_TX_MISC
);
2239 bnx2_read_phy(bp
, BCM5708S_TX_ACTL1
, &val
);
2240 val
&= ~BCM5708S_TX_ACTL1_DRIVER_VCM
;
2241 bnx2_write_phy(bp
, BCM5708S_TX_ACTL1
, val
);
2242 bnx2_write_phy(bp
, BCM5708S_BLK_ADDR
, BCM5708S_BLK_ADDR_DIG
);
2245 val
= bnx2_shmem_rd(bp
, BNX2_PORT_HW_CFG_CONFIG
) &
2246 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK
;
2251 is_backplane
= bnx2_shmem_rd(bp
, BNX2_SHARED_HW_CFG_CONFIG
);
2252 if (is_backplane
& BNX2_SHARED_HW_CFG_PHY_BACKPLANE
) {
2253 bnx2_write_phy(bp
, BCM5708S_BLK_ADDR
,
2254 BCM5708S_BLK_ADDR_TX_MISC
);
2255 bnx2_write_phy(bp
, BCM5708S_TX_ACTL3
, val
);
2256 bnx2_write_phy(bp
, BCM5708S_BLK_ADDR
,
2257 BCM5708S_BLK_ADDR_DIG
);
2264 bnx2_init_5706s_phy(struct bnx2
*bp
, int reset_phy
)
2269 bp
->phy_flags
&= ~BNX2_PHY_FLAG_PARALLEL_DETECT
;
2271 if (CHIP_NUM(bp
) == CHIP_NUM_5706
)
2272 REG_WR(bp
, BNX2_MISC_GP_HW_CTL0
, 0x300);
2274 if (bp
->dev
->mtu
> 1500) {
2277 /* Set extended packet length bit */
2278 bnx2_write_phy(bp
, 0x18, 0x7);
2279 bnx2_read_phy(bp
, 0x18, &val
);
2280 bnx2_write_phy(bp
, 0x18, (val
& 0xfff8) | 0x4000);
2282 bnx2_write_phy(bp
, 0x1c, 0x6c00);
2283 bnx2_read_phy(bp
, 0x1c, &val
);
2284 bnx2_write_phy(bp
, 0x1c, (val
& 0x3ff) | 0xec02);
2289 bnx2_write_phy(bp
, 0x18, 0x7);
2290 bnx2_read_phy(bp
, 0x18, &val
);
2291 bnx2_write_phy(bp
, 0x18, val
& ~0x4007);
2293 bnx2_write_phy(bp
, 0x1c, 0x6c00);
2294 bnx2_read_phy(bp
, 0x1c, &val
);
2295 bnx2_write_phy(bp
, 0x1c, (val
& 0x3fd) | 0xec00);
2302 bnx2_init_copper_phy(struct bnx2
*bp
, int reset_phy
)
2309 if (bp
->phy_flags
& BNX2_PHY_FLAG_CRC_FIX
) {
2310 bnx2_write_phy(bp
, 0x18, 0x0c00);
2311 bnx2_write_phy(bp
, 0x17, 0x000a);
2312 bnx2_write_phy(bp
, 0x15, 0x310b);
2313 bnx2_write_phy(bp
, 0x17, 0x201f);
2314 bnx2_write_phy(bp
, 0x15, 0x9506);
2315 bnx2_write_phy(bp
, 0x17, 0x401f);
2316 bnx2_write_phy(bp
, 0x15, 0x14e2);
2317 bnx2_write_phy(bp
, 0x18, 0x0400);
2320 if (bp
->phy_flags
& BNX2_PHY_FLAG_DIS_EARLY_DAC
) {
2321 bnx2_write_phy(bp
, MII_BNX2_DSP_ADDRESS
,
2322 MII_BNX2_DSP_EXPAND_REG
| 0x8);
2323 bnx2_read_phy(bp
, MII_BNX2_DSP_RW_PORT
, &val
);
2325 bnx2_write_phy(bp
, MII_BNX2_DSP_RW_PORT
, val
);
2328 if (bp
->dev
->mtu
> 1500) {
2329 /* Set extended packet length bit */
2330 bnx2_write_phy(bp
, 0x18, 0x7);
2331 bnx2_read_phy(bp
, 0x18, &val
);
2332 bnx2_write_phy(bp
, 0x18, val
| 0x4000);
2334 bnx2_read_phy(bp
, 0x10, &val
);
2335 bnx2_write_phy(bp
, 0x10, val
| 0x1);
2338 bnx2_write_phy(bp
, 0x18, 0x7);
2339 bnx2_read_phy(bp
, 0x18, &val
);
2340 bnx2_write_phy(bp
, 0x18, val
& ~0x4007);
2342 bnx2_read_phy(bp
, 0x10, &val
);
2343 bnx2_write_phy(bp
, 0x10, val
& ~0x1);
2346 /* ethernet@wirespeed */
2347 bnx2_write_phy(bp
, 0x18, 0x7007);
2348 bnx2_read_phy(bp
, 0x18, &val
);
2349 bnx2_write_phy(bp
, 0x18, val
| (1 << 15) | (1 << 4));
2355 bnx2_init_phy(struct bnx2
*bp
, int reset_phy
)
2356 __releases(&bp
->phy_lock
)
2357 __acquires(&bp
->phy_lock
)
2362 bp
->phy_flags
&= ~BNX2_PHY_FLAG_INT_MODE_MASK
;
2363 bp
->phy_flags
|= BNX2_PHY_FLAG_INT_MODE_LINK_READY
;
2365 bp
->mii_bmcr
= MII_BMCR
;
2366 bp
->mii_bmsr
= MII_BMSR
;
2367 bp
->mii_bmsr1
= MII_BMSR
;
2368 bp
->mii_adv
= MII_ADVERTISE
;
2369 bp
->mii_lpa
= MII_LPA
;
2371 REG_WR(bp
, BNX2_EMAC_ATTENTION_ENA
, BNX2_EMAC_ATTENTION_ENA_LINK
);
2373 if (bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
)
2376 bnx2_read_phy(bp
, MII_PHYSID1
, &val
);
2377 bp
->phy_id
= val
<< 16;
2378 bnx2_read_phy(bp
, MII_PHYSID2
, &val
);
2379 bp
->phy_id
|= val
& 0xffff;
2381 if (bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) {
2382 if (CHIP_NUM(bp
) == CHIP_NUM_5706
)
2383 rc
= bnx2_init_5706s_phy(bp
, reset_phy
);
2384 else if (CHIP_NUM(bp
) == CHIP_NUM_5708
)
2385 rc
= bnx2_init_5708s_phy(bp
, reset_phy
);
2386 else if (CHIP_NUM(bp
) == CHIP_NUM_5709
)
2387 rc
= bnx2_init_5709s_phy(bp
, reset_phy
);
2390 rc
= bnx2_init_copper_phy(bp
, reset_phy
);
2395 rc
= bnx2_setup_phy(bp
, bp
->phy_port
);
2401 bnx2_set_mac_loopback(struct bnx2
*bp
)
2405 mac_mode
= REG_RD(bp
, BNX2_EMAC_MODE
);
2406 mac_mode
&= ~BNX2_EMAC_MODE_PORT
;
2407 mac_mode
|= BNX2_EMAC_MODE_MAC_LOOP
| BNX2_EMAC_MODE_FORCE_LINK
;
2408 REG_WR(bp
, BNX2_EMAC_MODE
, mac_mode
);
2413 static int bnx2_test_link(struct bnx2
*);
2416 bnx2_set_phy_loopback(struct bnx2
*bp
)
2421 spin_lock_bh(&bp
->phy_lock
);
2422 rc
= bnx2_write_phy(bp
, bp
->mii_bmcr
, BMCR_LOOPBACK
| BMCR_FULLDPLX
|
2424 spin_unlock_bh(&bp
->phy_lock
);
2428 for (i
= 0; i
< 10; i
++) {
2429 if (bnx2_test_link(bp
) == 0)
2434 mac_mode
= REG_RD(bp
, BNX2_EMAC_MODE
);
2435 mac_mode
&= ~(BNX2_EMAC_MODE_PORT
| BNX2_EMAC_MODE_HALF_DUPLEX
|
2436 BNX2_EMAC_MODE_MAC_LOOP
| BNX2_EMAC_MODE_FORCE_LINK
|
2437 BNX2_EMAC_MODE_25G_MODE
);
2439 mac_mode
|= BNX2_EMAC_MODE_PORT_GMII
;
2440 REG_WR(bp
, BNX2_EMAC_MODE
, mac_mode
);
2446 bnx2_fw_sync(struct bnx2
*bp
, u32 msg_data
, int ack
, int silent
)
2452 msg_data
|= bp
->fw_wr_seq
;
2454 bnx2_shmem_wr(bp
, BNX2_DRV_MB
, msg_data
);
2459 /* wait for an acknowledgement. */
2460 for (i
= 0; i
< (BNX2_FW_ACK_TIME_OUT_MS
/ 10); i
++) {
2463 val
= bnx2_shmem_rd(bp
, BNX2_FW_MB
);
2465 if ((val
& BNX2_FW_MSG_ACK
) == (msg_data
& BNX2_DRV_MSG_SEQ
))
2468 if ((msg_data
& BNX2_DRV_MSG_DATA
) == BNX2_DRV_MSG_DATA_WAIT0
)
2471 /* If we timed out, inform the firmware that this is the case. */
2472 if ((val
& BNX2_FW_MSG_ACK
) != (msg_data
& BNX2_DRV_MSG_SEQ
)) {
2474 printk(KERN_ERR PFX
"fw sync timeout, reset code = "
2477 msg_data
&= ~BNX2_DRV_MSG_CODE
;
2478 msg_data
|= BNX2_DRV_MSG_CODE_FW_TIMEOUT
;
2480 bnx2_shmem_wr(bp
, BNX2_DRV_MB
, msg_data
);
2485 if ((val
& BNX2_FW_MSG_STATUS_MASK
) != BNX2_FW_MSG_STATUS_OK
)
2492 bnx2_init_5709_context(struct bnx2
*bp
)
2497 val
= BNX2_CTX_COMMAND_ENABLED
| BNX2_CTX_COMMAND_MEM_INIT
| (1 << 12);
2498 val
|= (BCM_PAGE_BITS
- 8) << 16;
2499 REG_WR(bp
, BNX2_CTX_COMMAND
, val
);
2500 for (i
= 0; i
< 10; i
++) {
2501 val
= REG_RD(bp
, BNX2_CTX_COMMAND
);
2502 if (!(val
& BNX2_CTX_COMMAND_MEM_INIT
))
2506 if (val
& BNX2_CTX_COMMAND_MEM_INIT
)
2509 for (i
= 0; i
< bp
->ctx_pages
; i
++) {
2513 memset(bp
->ctx_blk
[i
], 0, BCM_PAGE_SIZE
);
2517 REG_WR(bp
, BNX2_CTX_HOST_PAGE_TBL_DATA0
,
2518 (bp
->ctx_blk_mapping
[i
] & 0xffffffff) |
2519 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID
);
2520 REG_WR(bp
, BNX2_CTX_HOST_PAGE_TBL_DATA1
,
2521 (u64
) bp
->ctx_blk_mapping
[i
] >> 32);
2522 REG_WR(bp
, BNX2_CTX_HOST_PAGE_TBL_CTRL
, i
|
2523 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ
);
2524 for (j
= 0; j
< 10; j
++) {
2526 val
= REG_RD(bp
, BNX2_CTX_HOST_PAGE_TBL_CTRL
);
2527 if (!(val
& BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ
))
2531 if (val
& BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ
) {
2540 bnx2_init_context(struct bnx2
*bp
)
2546 u32 vcid_addr
, pcid_addr
, offset
;
2551 if (CHIP_ID(bp
) == CHIP_ID_5706_A0
) {
2554 vcid_addr
= GET_PCID_ADDR(vcid
);
2556 new_vcid
= 0x60 + (vcid
& 0xf0) + (vcid
& 0x7);
2561 pcid_addr
= GET_PCID_ADDR(new_vcid
);
2564 vcid_addr
= GET_CID_ADDR(vcid
);
2565 pcid_addr
= vcid_addr
;
2568 for (i
= 0; i
< (CTX_SIZE
/ PHY_CTX_SIZE
); i
++) {
2569 vcid_addr
+= (i
<< PHY_CTX_SHIFT
);
2570 pcid_addr
+= (i
<< PHY_CTX_SHIFT
);
2572 REG_WR(bp
, BNX2_CTX_VIRT_ADDR
, vcid_addr
);
2573 REG_WR(bp
, BNX2_CTX_PAGE_TBL
, pcid_addr
);
2575 /* Zero out the context. */
2576 for (offset
= 0; offset
< PHY_CTX_SIZE
; offset
+= 4)
2577 bnx2_ctx_wr(bp
, vcid_addr
, offset
, 0);
2583 bnx2_alloc_bad_rbuf(struct bnx2
*bp
)
2589 good_mbuf
= kmalloc(512 * sizeof(u16
), GFP_KERNEL
);
2590 if (good_mbuf
== NULL
) {
2591 printk(KERN_ERR PFX
"Failed to allocate memory in "
2592 "bnx2_alloc_bad_rbuf\n");
2596 REG_WR(bp
, BNX2_MISC_ENABLE_SET_BITS
,
2597 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE
);
2601 /* Allocate a bunch of mbufs and save the good ones in an array. */
2602 val
= bnx2_reg_rd_ind(bp
, BNX2_RBUF_STATUS1
);
2603 while (val
& BNX2_RBUF_STATUS1_FREE_COUNT
) {
2604 bnx2_reg_wr_ind(bp
, BNX2_RBUF_COMMAND
,
2605 BNX2_RBUF_COMMAND_ALLOC_REQ
);
2607 val
= bnx2_reg_rd_ind(bp
, BNX2_RBUF_FW_BUF_ALLOC
);
2609 val
&= BNX2_RBUF_FW_BUF_ALLOC_VALUE
;
2611 /* The addresses with Bit 9 set are bad memory blocks. */
2612 if (!(val
& (1 << 9))) {
2613 good_mbuf
[good_mbuf_cnt
] = (u16
) val
;
2617 val
= bnx2_reg_rd_ind(bp
, BNX2_RBUF_STATUS1
);
2620 /* Free the good ones back to the mbuf pool thus discarding
2621 * all the bad ones. */
2622 while (good_mbuf_cnt
) {
2625 val
= good_mbuf
[good_mbuf_cnt
];
2626 val
= (val
<< 9) | val
| 1;
2628 bnx2_reg_wr_ind(bp
, BNX2_RBUF_FW_BUF_FREE
, val
);
2635 bnx2_set_mac_addr(struct bnx2
*bp
, u8
*mac_addr
, u32 pos
)
2639 val
= (mac_addr
[0] << 8) | mac_addr
[1];
2641 REG_WR(bp
, BNX2_EMAC_MAC_MATCH0
+ (pos
* 8), val
);
2643 val
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
2644 (mac_addr
[4] << 8) | mac_addr
[5];
2646 REG_WR(bp
, BNX2_EMAC_MAC_MATCH1
+ (pos
* 8), val
);
2650 bnx2_alloc_rx_page(struct bnx2
*bp
, struct bnx2_rx_ring_info
*rxr
, u16 index
)
2653 struct sw_pg
*rx_pg
= &rxr
->rx_pg_ring
[index
];
2654 struct rx_bd
*rxbd
=
2655 &rxr
->rx_pg_desc_ring
[RX_RING(index
)][RX_IDX(index
)];
2656 struct page
*page
= alloc_page(GFP_ATOMIC
);
2660 mapping
= pci_map_page(bp
->pdev
, page
, 0, PAGE_SIZE
,
2661 PCI_DMA_FROMDEVICE
);
2662 if (pci_dma_mapping_error(bp
->pdev
, mapping
)) {
2668 pci_unmap_addr_set(rx_pg
, mapping
, mapping
);
2669 rxbd
->rx_bd_haddr_hi
= (u64
) mapping
>> 32;
2670 rxbd
->rx_bd_haddr_lo
= (u64
) mapping
& 0xffffffff;
2675 bnx2_free_rx_page(struct bnx2
*bp
, struct bnx2_rx_ring_info
*rxr
, u16 index
)
2677 struct sw_pg
*rx_pg
= &rxr
->rx_pg_ring
[index
];
2678 struct page
*page
= rx_pg
->page
;
2683 pci_unmap_page(bp
->pdev
, pci_unmap_addr(rx_pg
, mapping
), PAGE_SIZE
,
2684 PCI_DMA_FROMDEVICE
);
2691 bnx2_alloc_rx_skb(struct bnx2
*bp
, struct bnx2_rx_ring_info
*rxr
, u16 index
)
2693 struct sk_buff
*skb
;
2694 struct sw_bd
*rx_buf
= &rxr
->rx_buf_ring
[index
];
2696 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(index
)][RX_IDX(index
)];
2697 unsigned long align
;
2699 skb
= netdev_alloc_skb(bp
->dev
, bp
->rx_buf_size
);
2704 if (unlikely((align
= (unsigned long) skb
->data
& (BNX2_RX_ALIGN
- 1))))
2705 skb_reserve(skb
, BNX2_RX_ALIGN
- align
);
2707 mapping
= pci_map_single(bp
->pdev
, skb
->data
, bp
->rx_buf_use_size
,
2708 PCI_DMA_FROMDEVICE
);
2709 if (pci_dma_mapping_error(bp
->pdev
, mapping
)) {
2715 pci_unmap_addr_set(rx_buf
, mapping
, mapping
);
2717 rxbd
->rx_bd_haddr_hi
= (u64
) mapping
>> 32;
2718 rxbd
->rx_bd_haddr_lo
= (u64
) mapping
& 0xffffffff;
2720 rxr
->rx_prod_bseq
+= bp
->rx_buf_use_size
;
2726 bnx2_phy_event_is_set(struct bnx2
*bp
, struct bnx2_napi
*bnapi
, u32 event
)
2728 struct status_block
*sblk
= bnapi
->status_blk
.msi
;
2729 u32 new_link_state
, old_link_state
;
2732 new_link_state
= sblk
->status_attn_bits
& event
;
2733 old_link_state
= sblk
->status_attn_bits_ack
& event
;
2734 if (new_link_state
!= old_link_state
) {
2736 REG_WR(bp
, BNX2_PCICFG_STATUS_BIT_SET_CMD
, event
);
2738 REG_WR(bp
, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD
, event
);
2746 bnx2_phy_int(struct bnx2
*bp
, struct bnx2_napi
*bnapi
)
2748 spin_lock(&bp
->phy_lock
);
2750 if (bnx2_phy_event_is_set(bp
, bnapi
, STATUS_ATTN_BITS_LINK_STATE
))
2752 if (bnx2_phy_event_is_set(bp
, bnapi
, STATUS_ATTN_BITS_TIMER_ABORT
))
2753 bnx2_set_remote_link(bp
);
2755 spin_unlock(&bp
->phy_lock
);
2760 bnx2_get_hw_tx_cons(struct bnx2_napi
*bnapi
)
2764 /* Tell compiler that status block fields can change. */
2766 cons
= *bnapi
->hw_tx_cons_ptr
;
2768 if (unlikely((cons
& MAX_TX_DESC_CNT
) == MAX_TX_DESC_CNT
))
2774 bnx2_tx_int(struct bnx2
*bp
, struct bnx2_napi
*bnapi
, int budget
)
2776 struct bnx2_tx_ring_info
*txr
= &bnapi
->tx_ring
;
2777 u16 hw_cons
, sw_cons
, sw_ring_cons
;
2778 int tx_pkt
= 0, index
;
2779 struct netdev_queue
*txq
;
2781 index
= (bnapi
- bp
->bnx2_napi
);
2782 txq
= netdev_get_tx_queue(bp
->dev
, index
);
2784 hw_cons
= bnx2_get_hw_tx_cons(bnapi
);
2785 sw_cons
= txr
->tx_cons
;
2787 while (sw_cons
!= hw_cons
) {
2788 struct sw_tx_bd
*tx_buf
;
2789 struct sk_buff
*skb
;
2792 sw_ring_cons
= TX_RING_IDX(sw_cons
);
2794 tx_buf
= &txr
->tx_buf_ring
[sw_ring_cons
];
2797 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2798 prefetch(&skb
->end
);
2800 /* partial BD completions possible with TSO packets */
2801 if (tx_buf
->is_gso
) {
2802 u16 last_idx
, last_ring_idx
;
2804 last_idx
= sw_cons
+ tx_buf
->nr_frags
+ 1;
2805 last_ring_idx
= sw_ring_cons
+ tx_buf
->nr_frags
+ 1;
2806 if (unlikely(last_ring_idx
>= MAX_TX_DESC_CNT
)) {
2809 if (((s16
) ((s16
) last_idx
- (s16
) hw_cons
)) > 0) {
2814 skb_dma_unmap(&bp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
2817 last
= tx_buf
->nr_frags
;
2819 for (i
= 0; i
< last
; i
++) {
2820 sw_cons
= NEXT_TX_BD(sw_cons
);
2823 sw_cons
= NEXT_TX_BD(sw_cons
);
2827 if (tx_pkt
== budget
)
2830 if (hw_cons
== sw_cons
)
2831 hw_cons
= bnx2_get_hw_tx_cons(bnapi
);
2834 txr
->hw_tx_cons
= hw_cons
;
2835 txr
->tx_cons
= sw_cons
;
2837 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2838 * before checking for netif_tx_queue_stopped(). Without the
2839 * memory barrier, there is a small possibility that bnx2_start_xmit()
2840 * will miss it and cause the queue to be stopped forever.
2844 if (unlikely(netif_tx_queue_stopped(txq
)) &&
2845 (bnx2_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
2846 __netif_tx_lock(txq
, smp_processor_id());
2847 if ((netif_tx_queue_stopped(txq
)) &&
2848 (bnx2_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
))
2849 netif_tx_wake_queue(txq
);
2850 __netif_tx_unlock(txq
);
2857 bnx2_reuse_rx_skb_pages(struct bnx2
*bp
, struct bnx2_rx_ring_info
*rxr
,
2858 struct sk_buff
*skb
, int count
)
2860 struct sw_pg
*cons_rx_pg
, *prod_rx_pg
;
2861 struct rx_bd
*cons_bd
, *prod_bd
;
2864 u16 cons
= rxr
->rx_pg_cons
;
2866 cons_rx_pg
= &rxr
->rx_pg_ring
[cons
];
2868 /* The caller was unable to allocate a new page to replace the
2869 * last one in the frags array, so we need to recycle that page
2870 * and then free the skb.
2874 struct skb_shared_info
*shinfo
;
2876 shinfo
= skb_shinfo(skb
);
2878 page
= shinfo
->frags
[shinfo
->nr_frags
].page
;
2879 shinfo
->frags
[shinfo
->nr_frags
].page
= NULL
;
2881 cons_rx_pg
->page
= page
;
2885 hw_prod
= rxr
->rx_pg_prod
;
2887 for (i
= 0; i
< count
; i
++) {
2888 prod
= RX_PG_RING_IDX(hw_prod
);
2890 prod_rx_pg
= &rxr
->rx_pg_ring
[prod
];
2891 cons_rx_pg
= &rxr
->rx_pg_ring
[cons
];
2892 cons_bd
= &rxr
->rx_pg_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
2893 prod_bd
= &rxr
->rx_pg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
2896 prod_rx_pg
->page
= cons_rx_pg
->page
;
2897 cons_rx_pg
->page
= NULL
;
2898 pci_unmap_addr_set(prod_rx_pg
, mapping
,
2899 pci_unmap_addr(cons_rx_pg
, mapping
));
2901 prod_bd
->rx_bd_haddr_hi
= cons_bd
->rx_bd_haddr_hi
;
2902 prod_bd
->rx_bd_haddr_lo
= cons_bd
->rx_bd_haddr_lo
;
2905 cons
= RX_PG_RING_IDX(NEXT_RX_BD(cons
));
2906 hw_prod
= NEXT_RX_BD(hw_prod
);
2908 rxr
->rx_pg_prod
= hw_prod
;
2909 rxr
->rx_pg_cons
= cons
;
2913 bnx2_reuse_rx_skb(struct bnx2
*bp
, struct bnx2_rx_ring_info
*rxr
,
2914 struct sk_buff
*skb
, u16 cons
, u16 prod
)
2916 struct sw_bd
*cons_rx_buf
, *prod_rx_buf
;
2917 struct rx_bd
*cons_bd
, *prod_bd
;
2919 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
2920 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
2922 pci_dma_sync_single_for_device(bp
->pdev
,
2923 pci_unmap_addr(cons_rx_buf
, mapping
),
2924 BNX2_RX_OFFSET
+ BNX2_RX_COPY_THRESH
, PCI_DMA_FROMDEVICE
);
2926 rxr
->rx_prod_bseq
+= bp
->rx_buf_use_size
;
2928 prod_rx_buf
->skb
= skb
;
2933 pci_unmap_addr_set(prod_rx_buf
, mapping
,
2934 pci_unmap_addr(cons_rx_buf
, mapping
));
2936 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
2937 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
2938 prod_bd
->rx_bd_haddr_hi
= cons_bd
->rx_bd_haddr_hi
;
2939 prod_bd
->rx_bd_haddr_lo
= cons_bd
->rx_bd_haddr_lo
;
2943 bnx2_rx_skb(struct bnx2
*bp
, struct bnx2_rx_ring_info
*rxr
, struct sk_buff
*skb
,
2944 unsigned int len
, unsigned int hdr_len
, dma_addr_t dma_addr
,
2948 u16 prod
= ring_idx
& 0xffff;
2950 err
= bnx2_alloc_rx_skb(bp
, rxr
, prod
);
2951 if (unlikely(err
)) {
2952 bnx2_reuse_rx_skb(bp
, rxr
, skb
, (u16
) (ring_idx
>> 16), prod
);
2954 unsigned int raw_len
= len
+ 4;
2955 int pages
= PAGE_ALIGN(raw_len
- hdr_len
) >> PAGE_SHIFT
;
2957 bnx2_reuse_rx_skb_pages(bp
, rxr
, NULL
, pages
);
2962 skb_reserve(skb
, BNX2_RX_OFFSET
);
2963 pci_unmap_single(bp
->pdev
, dma_addr
, bp
->rx_buf_use_size
,
2964 PCI_DMA_FROMDEVICE
);
2970 unsigned int i
, frag_len
, frag_size
, pages
;
2971 struct sw_pg
*rx_pg
;
2972 u16 pg_cons
= rxr
->rx_pg_cons
;
2973 u16 pg_prod
= rxr
->rx_pg_prod
;
2975 frag_size
= len
+ 4 - hdr_len
;
2976 pages
= PAGE_ALIGN(frag_size
) >> PAGE_SHIFT
;
2977 skb_put(skb
, hdr_len
);
2979 for (i
= 0; i
< pages
; i
++) {
2980 dma_addr_t mapping_old
;
2982 frag_len
= min(frag_size
, (unsigned int) PAGE_SIZE
);
2983 if (unlikely(frag_len
<= 4)) {
2984 unsigned int tail
= 4 - frag_len
;
2986 rxr
->rx_pg_cons
= pg_cons
;
2987 rxr
->rx_pg_prod
= pg_prod
;
2988 bnx2_reuse_rx_skb_pages(bp
, rxr
, NULL
,
2995 &skb_shinfo(skb
)->frags
[i
- 1];
2997 skb
->data_len
-= tail
;
2998 skb
->truesize
-= tail
;
3002 rx_pg
= &rxr
->rx_pg_ring
[pg_cons
];
3004 /* Don't unmap yet. If we're unable to allocate a new
3005 * page, we need to recycle the page and the DMA addr.
3007 mapping_old
= pci_unmap_addr(rx_pg
, mapping
);
3011 skb_fill_page_desc(skb
, i
, rx_pg
->page
, 0, frag_len
);
3014 err
= bnx2_alloc_rx_page(bp
, rxr
,
3015 RX_PG_RING_IDX(pg_prod
));
3016 if (unlikely(err
)) {
3017 rxr
->rx_pg_cons
= pg_cons
;
3018 rxr
->rx_pg_prod
= pg_prod
;
3019 bnx2_reuse_rx_skb_pages(bp
, rxr
, skb
,
3024 pci_unmap_page(bp
->pdev
, mapping_old
,
3025 PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
3027 frag_size
-= frag_len
;
3028 skb
->data_len
+= frag_len
;
3029 skb
->truesize
+= frag_len
;
3030 skb
->len
+= frag_len
;
3032 pg_prod
= NEXT_RX_BD(pg_prod
);
3033 pg_cons
= RX_PG_RING_IDX(NEXT_RX_BD(pg_cons
));
3035 rxr
->rx_pg_prod
= pg_prod
;
3036 rxr
->rx_pg_cons
= pg_cons
;
3042 bnx2_get_hw_rx_cons(struct bnx2_napi
*bnapi
)
3046 /* Tell compiler that status block fields can change. */
3048 cons
= *bnapi
->hw_rx_cons_ptr
;
3050 if (unlikely((cons
& MAX_RX_DESC_CNT
) == MAX_RX_DESC_CNT
))
3056 bnx2_rx_int(struct bnx2
*bp
, struct bnx2_napi
*bnapi
, int budget
)
3058 struct bnx2_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
3059 u16 hw_cons
, sw_cons
, sw_ring_cons
, sw_prod
, sw_ring_prod
;
3060 struct l2_fhdr
*rx_hdr
;
3061 int rx_pkt
= 0, pg_ring_used
= 0;
3063 hw_cons
= bnx2_get_hw_rx_cons(bnapi
);
3064 sw_cons
= rxr
->rx_cons
;
3065 sw_prod
= rxr
->rx_prod
;
3067 /* Memory barrier necessary as speculative reads of the rx
3068 * buffer can be ahead of the index in the status block
3071 while (sw_cons
!= hw_cons
) {
3072 unsigned int len
, hdr_len
;
3074 struct sw_bd
*rx_buf
;
3075 struct sk_buff
*skb
;
3076 dma_addr_t dma_addr
;
3078 int hw_vlan __maybe_unused
= 0;
3080 sw_ring_cons
= RX_RING_IDX(sw_cons
);
3081 sw_ring_prod
= RX_RING_IDX(sw_prod
);
3083 rx_buf
= &rxr
->rx_buf_ring
[sw_ring_cons
];
3088 dma_addr
= pci_unmap_addr(rx_buf
, mapping
);
3090 pci_dma_sync_single_for_cpu(bp
->pdev
, dma_addr
,
3091 BNX2_RX_OFFSET
+ BNX2_RX_COPY_THRESH
,
3092 PCI_DMA_FROMDEVICE
);
3094 rx_hdr
= (struct l2_fhdr
*) skb
->data
;
3095 len
= rx_hdr
->l2_fhdr_pkt_len
;
3096 status
= rx_hdr
->l2_fhdr_status
;
3099 if (status
& L2_FHDR_STATUS_SPLIT
) {
3100 hdr_len
= rx_hdr
->l2_fhdr_ip_xsum
;
3102 } else if (len
> bp
->rx_jumbo_thresh
) {
3103 hdr_len
= bp
->rx_jumbo_thresh
;
3107 if (unlikely(status
& (L2_FHDR_ERRORS_BAD_CRC
|
3108 L2_FHDR_ERRORS_PHY_DECODE
|
3109 L2_FHDR_ERRORS_ALIGNMENT
|
3110 L2_FHDR_ERRORS_TOO_SHORT
|
3111 L2_FHDR_ERRORS_GIANT_FRAME
))) {
3113 bnx2_reuse_rx_skb(bp
, rxr
, skb
, sw_ring_cons
,
3118 pages
= PAGE_ALIGN(len
- hdr_len
) >> PAGE_SHIFT
;
3120 bnx2_reuse_rx_skb_pages(bp
, rxr
, NULL
, pages
);
3127 if (len
<= bp
->rx_copy_thresh
) {
3128 struct sk_buff
*new_skb
;
3130 new_skb
= netdev_alloc_skb(bp
->dev
, len
+ 6);
3131 if (new_skb
== NULL
) {
3132 bnx2_reuse_rx_skb(bp
, rxr
, skb
, sw_ring_cons
,
3138 skb_copy_from_linear_data_offset(skb
,
3140 new_skb
->data
, len
+ 6);
3141 skb_reserve(new_skb
, 6);
3142 skb_put(new_skb
, len
);
3144 bnx2_reuse_rx_skb(bp
, rxr
, skb
,
3145 sw_ring_cons
, sw_ring_prod
);
3148 } else if (unlikely(bnx2_rx_skb(bp
, rxr
, skb
, len
, hdr_len
,
3149 dma_addr
, (sw_ring_cons
<< 16) | sw_ring_prod
)))
3152 if ((status
& L2_FHDR_STATUS_L2_VLAN_TAG
) &&
3153 !(bp
->rx_mode
& BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG
)) {
3154 vtag
= rx_hdr
->l2_fhdr_vlan_tag
;
3161 struct vlan_ethhdr
*ve
= (struct vlan_ethhdr
*)
3164 memmove(ve
, skb
->data
+ 4, ETH_ALEN
* 2);
3165 ve
->h_vlan_proto
= htons(ETH_P_8021Q
);
3166 ve
->h_vlan_TCI
= htons(vtag
);
3171 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
3173 if ((len
> (bp
->dev
->mtu
+ ETH_HLEN
)) &&
3174 (ntohs(skb
->protocol
) != 0x8100)) {
3181 skb
->ip_summed
= CHECKSUM_NONE
;
3183 (status
& (L2_FHDR_STATUS_TCP_SEGMENT
|
3184 L2_FHDR_STATUS_UDP_DATAGRAM
))) {
3186 if (likely((status
& (L2_FHDR_ERRORS_TCP_XSUM
|
3187 L2_FHDR_ERRORS_UDP_XSUM
)) == 0))
3188 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3191 skb_record_rx_queue(skb
, bnapi
- &bp
->bnx2_napi
[0]);
3195 vlan_hwaccel_receive_skb(skb
, bp
->vlgrp
, vtag
);
3198 netif_receive_skb(skb
);
3203 sw_cons
= NEXT_RX_BD(sw_cons
);
3204 sw_prod
= NEXT_RX_BD(sw_prod
);
3206 if ((rx_pkt
== budget
))
3209 /* Refresh hw_cons to see if there is new work */
3210 if (sw_cons
== hw_cons
) {
3211 hw_cons
= bnx2_get_hw_rx_cons(bnapi
);
3215 rxr
->rx_cons
= sw_cons
;
3216 rxr
->rx_prod
= sw_prod
;
3219 REG_WR16(bp
, rxr
->rx_pg_bidx_addr
, rxr
->rx_pg_prod
);
3221 REG_WR16(bp
, rxr
->rx_bidx_addr
, sw_prod
);
3223 REG_WR(bp
, rxr
->rx_bseq_addr
, rxr
->rx_prod_bseq
);
3231 /* MSI ISR - The only difference between this and the INTx ISR
3232 * is that the MSI interrupt is always serviced.
3235 bnx2_msi(int irq
, void *dev_instance
)
3237 struct bnx2_napi
*bnapi
= dev_instance
;
3238 struct bnx2
*bp
= bnapi
->bp
;
3240 prefetch(bnapi
->status_blk
.msi
);
3241 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
,
3242 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM
|
3243 BNX2_PCICFG_INT_ACK_CMD_MASK_INT
);
3245 /* Return here if interrupt is disabled. */
3246 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
3249 napi_schedule(&bnapi
->napi
);
3255 bnx2_msi_1shot(int irq
, void *dev_instance
)
3257 struct bnx2_napi
*bnapi
= dev_instance
;
3258 struct bnx2
*bp
= bnapi
->bp
;
3260 prefetch(bnapi
->status_blk
.msi
);
3262 /* Return here if interrupt is disabled. */
3263 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
3266 napi_schedule(&bnapi
->napi
);
3272 bnx2_interrupt(int irq
, void *dev_instance
)
3274 struct bnx2_napi
*bnapi
= dev_instance
;
3275 struct bnx2
*bp
= bnapi
->bp
;
3276 struct status_block
*sblk
= bnapi
->status_blk
.msi
;
3278 /* When using INTx, it is possible for the interrupt to arrive
3279 * at the CPU before the status block posted prior to the
3280 * interrupt. Reading a register will flush the status block.
3281 * When using MSI, the MSI message will always complete after
3282 * the status block write.
3284 if ((sblk
->status_idx
== bnapi
->last_status_idx
) &&
3285 (REG_RD(bp
, BNX2_PCICFG_MISC_STATUS
) &
3286 BNX2_PCICFG_MISC_STATUS_INTA_VALUE
))
3289 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
,
3290 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM
|
3291 BNX2_PCICFG_INT_ACK_CMD_MASK_INT
);
3293 /* Read back to deassert IRQ immediately to avoid too many
3294 * spurious interrupts.
3296 REG_RD(bp
, BNX2_PCICFG_INT_ACK_CMD
);
3298 /* Return here if interrupt is shared and is disabled. */
3299 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
3302 if (napi_schedule_prep(&bnapi
->napi
)) {
3303 bnapi
->last_status_idx
= sblk
->status_idx
;
3304 __napi_schedule(&bnapi
->napi
);
3311 bnx2_has_fast_work(struct bnx2_napi
*bnapi
)
3313 struct bnx2_tx_ring_info
*txr
= &bnapi
->tx_ring
;
3314 struct bnx2_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
3316 if ((bnx2_get_hw_rx_cons(bnapi
) != rxr
->rx_cons
) ||
3317 (bnx2_get_hw_tx_cons(bnapi
) != txr
->hw_tx_cons
))
3322 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3323 STATUS_ATTN_BITS_TIMER_ABORT)
3326 bnx2_has_work(struct bnx2_napi
*bnapi
)
3328 struct status_block
*sblk
= bnapi
->status_blk
.msi
;
3330 if (bnx2_has_fast_work(bnapi
))
3334 if (bnapi
->cnic_present
&& (bnapi
->cnic_tag
!= sblk
->status_idx
))
3338 if ((sblk
->status_attn_bits
& STATUS_ATTN_EVENTS
) !=
3339 (sblk
->status_attn_bits_ack
& STATUS_ATTN_EVENTS
))
3346 bnx2_chk_missed_msi(struct bnx2
*bp
)
3348 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[0];
3351 if (bnx2_has_work(bnapi
)) {
3352 msi_ctrl
= REG_RD(bp
, BNX2_PCICFG_MSI_CONTROL
);
3353 if (!(msi_ctrl
& BNX2_PCICFG_MSI_CONTROL_ENABLE
))
3356 if (bnapi
->last_status_idx
== bp
->idle_chk_status_idx
) {
3357 REG_WR(bp
, BNX2_PCICFG_MSI_CONTROL
, msi_ctrl
&
3358 ~BNX2_PCICFG_MSI_CONTROL_ENABLE
);
3359 REG_WR(bp
, BNX2_PCICFG_MSI_CONTROL
, msi_ctrl
);
3360 bnx2_msi(bp
->irq_tbl
[0].vector
, bnapi
);
3364 bp
->idle_chk_status_idx
= bnapi
->last_status_idx
;
3368 static void bnx2_poll_cnic(struct bnx2
*bp
, struct bnx2_napi
*bnapi
)
3370 struct cnic_ops
*c_ops
;
3372 if (!bnapi
->cnic_present
)
3376 c_ops
= rcu_dereference(bp
->cnic_ops
);
3378 bnapi
->cnic_tag
= c_ops
->cnic_handler(bp
->cnic_data
,
3379 bnapi
->status_blk
.msi
);
3384 static void bnx2_poll_link(struct bnx2
*bp
, struct bnx2_napi
*bnapi
)
3386 struct status_block
*sblk
= bnapi
->status_blk
.msi
;
3387 u32 status_attn_bits
= sblk
->status_attn_bits
;
3388 u32 status_attn_bits_ack
= sblk
->status_attn_bits_ack
;
3390 if ((status_attn_bits
& STATUS_ATTN_EVENTS
) !=
3391 (status_attn_bits_ack
& STATUS_ATTN_EVENTS
)) {
3393 bnx2_phy_int(bp
, bnapi
);
3395 /* This is needed to take care of transient status
3396 * during link changes.
3398 REG_WR(bp
, BNX2_HC_COMMAND
,
3399 bp
->hc_cmd
| BNX2_HC_COMMAND_COAL_NOW_WO_INT
);
3400 REG_RD(bp
, BNX2_HC_COMMAND
);
3404 static int bnx2_poll_work(struct bnx2
*bp
, struct bnx2_napi
*bnapi
,
3405 int work_done
, int budget
)
3407 struct bnx2_tx_ring_info
*txr
= &bnapi
->tx_ring
;
3408 struct bnx2_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
3410 if (bnx2_get_hw_tx_cons(bnapi
) != txr
->hw_tx_cons
)
3411 bnx2_tx_int(bp
, bnapi
, 0);
3413 if (bnx2_get_hw_rx_cons(bnapi
) != rxr
->rx_cons
)
3414 work_done
+= bnx2_rx_int(bp
, bnapi
, budget
- work_done
);
3419 static int bnx2_poll_msix(struct napi_struct
*napi
, int budget
)
3421 struct bnx2_napi
*bnapi
= container_of(napi
, struct bnx2_napi
, napi
);
3422 struct bnx2
*bp
= bnapi
->bp
;
3424 struct status_block_msix
*sblk
= bnapi
->status_blk
.msix
;
3427 work_done
= bnx2_poll_work(bp
, bnapi
, work_done
, budget
);
3428 if (unlikely(work_done
>= budget
))
3431 bnapi
->last_status_idx
= sblk
->status_idx
;
3432 /* status idx must be read before checking for more work. */
3434 if (likely(!bnx2_has_fast_work(bnapi
))) {
3436 napi_complete(napi
);
3437 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
, bnapi
->int_num
|
3438 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID
|
3439 bnapi
->last_status_idx
);
3446 static int bnx2_poll(struct napi_struct
*napi
, int budget
)
3448 struct bnx2_napi
*bnapi
= container_of(napi
, struct bnx2_napi
, napi
);
3449 struct bnx2
*bp
= bnapi
->bp
;
3451 struct status_block
*sblk
= bnapi
->status_blk
.msi
;
3454 bnx2_poll_link(bp
, bnapi
);
3456 work_done
= bnx2_poll_work(bp
, bnapi
, work_done
, budget
);
3459 bnx2_poll_cnic(bp
, bnapi
);
3462 /* bnapi->last_status_idx is used below to tell the hw how
3463 * much work has been processed, so we must read it before
3464 * checking for more work.
3466 bnapi
->last_status_idx
= sblk
->status_idx
;
3468 if (unlikely(work_done
>= budget
))
3472 if (likely(!bnx2_has_work(bnapi
))) {
3473 napi_complete(napi
);
3474 if (likely(bp
->flags
& BNX2_FLAG_USING_MSI_OR_MSIX
)) {
3475 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
,
3476 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID
|
3477 bnapi
->last_status_idx
);
3480 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
,
3481 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID
|
3482 BNX2_PCICFG_INT_ACK_CMD_MASK_INT
|
3483 bnapi
->last_status_idx
);
3485 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
,
3486 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID
|
3487 bnapi
->last_status_idx
);
3495 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3496 * from set_multicast.
3499 bnx2_set_rx_mode(struct net_device
*dev
)
3501 struct bnx2
*bp
= netdev_priv(dev
);
3502 u32 rx_mode
, sort_mode
;
3503 struct netdev_hw_addr
*ha
;
3506 if (!netif_running(dev
))
3509 spin_lock_bh(&bp
->phy_lock
);
3511 rx_mode
= bp
->rx_mode
& ~(BNX2_EMAC_RX_MODE_PROMISCUOUS
|
3512 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG
);
3513 sort_mode
= 1 | BNX2_RPM_SORT_USER0_BC_EN
;
3515 if (!bp
->vlgrp
&& (bp
->flags
& BNX2_FLAG_CAN_KEEP_VLAN
))
3516 rx_mode
|= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG
;
3518 if (bp
->flags
& BNX2_FLAG_CAN_KEEP_VLAN
)
3519 rx_mode
|= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG
;
3521 if (dev
->flags
& IFF_PROMISC
) {
3522 /* Promiscuous mode. */
3523 rx_mode
|= BNX2_EMAC_RX_MODE_PROMISCUOUS
;
3524 sort_mode
|= BNX2_RPM_SORT_USER0_PROM_EN
|
3525 BNX2_RPM_SORT_USER0_PROM_VLAN
;
3527 else if (dev
->flags
& IFF_ALLMULTI
) {
3528 for (i
= 0; i
< NUM_MC_HASH_REGISTERS
; i
++) {
3529 REG_WR(bp
, BNX2_EMAC_MULTICAST_HASH0
+ (i
* 4),
3532 sort_mode
|= BNX2_RPM_SORT_USER0_MC_EN
;
3535 /* Accept one or more multicast(s). */
3536 struct dev_mc_list
*mclist
;
3537 u32 mc_filter
[NUM_MC_HASH_REGISTERS
];
3542 memset(mc_filter
, 0, 4 * NUM_MC_HASH_REGISTERS
);
3544 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
3545 i
++, mclist
= mclist
->next
) {
3547 crc
= ether_crc_le(ETH_ALEN
, mclist
->dmi_addr
);
3549 regidx
= (bit
& 0xe0) >> 5;
3551 mc_filter
[regidx
] |= (1 << bit
);
3554 for (i
= 0; i
< NUM_MC_HASH_REGISTERS
; i
++) {
3555 REG_WR(bp
, BNX2_EMAC_MULTICAST_HASH0
+ (i
* 4),
3559 sort_mode
|= BNX2_RPM_SORT_USER0_MC_HSH_EN
;
3562 if (dev
->uc
.count
> BNX2_MAX_UNICAST_ADDRESSES
) {
3563 rx_mode
|= BNX2_EMAC_RX_MODE_PROMISCUOUS
;
3564 sort_mode
|= BNX2_RPM_SORT_USER0_PROM_EN
|
3565 BNX2_RPM_SORT_USER0_PROM_VLAN
;
3566 } else if (!(dev
->flags
& IFF_PROMISC
)) {
3567 /* Add all entries into to the match filter list */
3569 list_for_each_entry(ha
, &dev
->uc
.list
, list
) {
3570 bnx2_set_mac_addr(bp
, ha
->addr
,
3571 i
+ BNX2_START_UNICAST_ADDRESS_INDEX
);
3573 (i
+ BNX2_START_UNICAST_ADDRESS_INDEX
));
3579 if (rx_mode
!= bp
->rx_mode
) {
3580 bp
->rx_mode
= rx_mode
;
3581 REG_WR(bp
, BNX2_EMAC_RX_MODE
, rx_mode
);
3584 REG_WR(bp
, BNX2_RPM_SORT_USER0
, 0x0);
3585 REG_WR(bp
, BNX2_RPM_SORT_USER0
, sort_mode
);
3586 REG_WR(bp
, BNX2_RPM_SORT_USER0
, sort_mode
| BNX2_RPM_SORT_USER0_ENA
);
3588 spin_unlock_bh(&bp
->phy_lock
);
3591 static int __devinit
3592 check_fw_section(const struct firmware
*fw
,
3593 const struct bnx2_fw_file_section
*section
,
3594 u32 alignment
, bool non_empty
)
3596 u32 offset
= be32_to_cpu(section
->offset
);
3597 u32 len
= be32_to_cpu(section
->len
);
3599 if ((offset
== 0 && len
!= 0) || offset
>= fw
->size
|| offset
& 3)
3601 if ((non_empty
&& len
== 0) || len
> fw
->size
- offset
||
3602 len
& (alignment
- 1))
3607 static int __devinit
3608 check_mips_fw_entry(const struct firmware
*fw
,
3609 const struct bnx2_mips_fw_file_entry
*entry
)
3611 if (check_fw_section(fw
, &entry
->text
, 4, true) ||
3612 check_fw_section(fw
, &entry
->data
, 4, false) ||
3613 check_fw_section(fw
, &entry
->rodata
, 4, false))
3618 static int __devinit
3619 bnx2_request_firmware(struct bnx2
*bp
)
3621 const char *mips_fw_file
, *rv2p_fw_file
;
3622 const struct bnx2_mips_fw_file
*mips_fw
;
3623 const struct bnx2_rv2p_fw_file
*rv2p_fw
;
3626 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
3627 mips_fw_file
= FW_MIPS_FILE_09
;
3628 if ((CHIP_ID(bp
) == CHIP_ID_5709_A0
) ||
3629 (CHIP_ID(bp
) == CHIP_ID_5709_A1
))
3630 rv2p_fw_file
= FW_RV2P_FILE_09_Ax
;
3632 rv2p_fw_file
= FW_RV2P_FILE_09
;
3634 mips_fw_file
= FW_MIPS_FILE_06
;
3635 rv2p_fw_file
= FW_RV2P_FILE_06
;
3638 rc
= request_firmware(&bp
->mips_firmware
, mips_fw_file
, &bp
->pdev
->dev
);
3640 printk(KERN_ERR PFX
"Can't load firmware file \"%s\"\n",
3645 rc
= request_firmware(&bp
->rv2p_firmware
, rv2p_fw_file
, &bp
->pdev
->dev
);
3647 printk(KERN_ERR PFX
"Can't load firmware file \"%s\"\n",
3651 mips_fw
= (const struct bnx2_mips_fw_file
*) bp
->mips_firmware
->data
;
3652 rv2p_fw
= (const struct bnx2_rv2p_fw_file
*) bp
->rv2p_firmware
->data
;
3653 if (bp
->mips_firmware
->size
< sizeof(*mips_fw
) ||
3654 check_mips_fw_entry(bp
->mips_firmware
, &mips_fw
->com
) ||
3655 check_mips_fw_entry(bp
->mips_firmware
, &mips_fw
->cp
) ||
3656 check_mips_fw_entry(bp
->mips_firmware
, &mips_fw
->rxp
) ||
3657 check_mips_fw_entry(bp
->mips_firmware
, &mips_fw
->tpat
) ||
3658 check_mips_fw_entry(bp
->mips_firmware
, &mips_fw
->txp
)) {
3659 printk(KERN_ERR PFX
"Firmware file \"%s\" is invalid\n",
3663 if (bp
->rv2p_firmware
->size
< sizeof(*rv2p_fw
) ||
3664 check_fw_section(bp
->rv2p_firmware
, &rv2p_fw
->proc1
.rv2p
, 8, true) ||
3665 check_fw_section(bp
->rv2p_firmware
, &rv2p_fw
->proc2
.rv2p
, 8, true)) {
3666 printk(KERN_ERR PFX
"Firmware file \"%s\" is invalid\n",
3675 rv2p_fw_fixup(u32 rv2p_proc
, int idx
, u32 loc
, u32 rv2p_code
)
3678 case RV2P_P1_FIXUP_PAGE_SIZE_IDX
:
3679 rv2p_code
&= ~RV2P_BD_PAGE_SIZE_MSK
;
3680 rv2p_code
|= RV2P_BD_PAGE_SIZE
;
3687 load_rv2p_fw(struct bnx2
*bp
, u32 rv2p_proc
,
3688 const struct bnx2_rv2p_fw_file_entry
*fw_entry
)
3690 u32 rv2p_code_len
, file_offset
;
3695 rv2p_code_len
= be32_to_cpu(fw_entry
->rv2p
.len
);
3696 file_offset
= be32_to_cpu(fw_entry
->rv2p
.offset
);
3698 rv2p_code
= (__be32
*)(bp
->rv2p_firmware
->data
+ file_offset
);
3700 if (rv2p_proc
== RV2P_PROC1
) {
3701 cmd
= BNX2_RV2P_PROC1_ADDR_CMD_RDWR
;
3702 addr
= BNX2_RV2P_PROC1_ADDR_CMD
;
3704 cmd
= BNX2_RV2P_PROC2_ADDR_CMD_RDWR
;
3705 addr
= BNX2_RV2P_PROC2_ADDR_CMD
;
3708 for (i
= 0; i
< rv2p_code_len
; i
+= 8) {
3709 REG_WR(bp
, BNX2_RV2P_INSTR_HIGH
, be32_to_cpu(*rv2p_code
));
3711 REG_WR(bp
, BNX2_RV2P_INSTR_LOW
, be32_to_cpu(*rv2p_code
));
3714 val
= (i
/ 8) | cmd
;
3715 REG_WR(bp
, addr
, val
);
3718 rv2p_code
= (__be32
*)(bp
->rv2p_firmware
->data
+ file_offset
);
3719 for (i
= 0; i
< 8; i
++) {
3722 loc
= be32_to_cpu(fw_entry
->fixup
[i
]);
3723 if (loc
&& ((loc
* 4) < rv2p_code_len
)) {
3724 code
= be32_to_cpu(*(rv2p_code
+ loc
- 1));
3725 REG_WR(bp
, BNX2_RV2P_INSTR_HIGH
, code
);
3726 code
= be32_to_cpu(*(rv2p_code
+ loc
));
3727 code
= rv2p_fw_fixup(rv2p_proc
, i
, loc
, code
);
3728 REG_WR(bp
, BNX2_RV2P_INSTR_LOW
, code
);
3730 val
= (loc
/ 2) | cmd
;
3731 REG_WR(bp
, addr
, val
);
3735 /* Reset the processor, un-stall is done later. */
3736 if (rv2p_proc
== RV2P_PROC1
) {
3737 REG_WR(bp
, BNX2_RV2P_COMMAND
, BNX2_RV2P_COMMAND_PROC1_RESET
);
3740 REG_WR(bp
, BNX2_RV2P_COMMAND
, BNX2_RV2P_COMMAND_PROC2_RESET
);
3747 load_cpu_fw(struct bnx2
*bp
, const struct cpu_reg
*cpu_reg
,
3748 const struct bnx2_mips_fw_file_entry
*fw_entry
)
3750 u32 addr
, len
, file_offset
;
3756 val
= bnx2_reg_rd_ind(bp
, cpu_reg
->mode
);
3757 val
|= cpu_reg
->mode_value_halt
;
3758 bnx2_reg_wr_ind(bp
, cpu_reg
->mode
, val
);
3759 bnx2_reg_wr_ind(bp
, cpu_reg
->state
, cpu_reg
->state_value_clear
);
3761 /* Load the Text area. */
3762 addr
= be32_to_cpu(fw_entry
->text
.addr
);
3763 len
= be32_to_cpu(fw_entry
->text
.len
);
3764 file_offset
= be32_to_cpu(fw_entry
->text
.offset
);
3765 data
= (__be32
*)(bp
->mips_firmware
->data
+ file_offset
);
3767 offset
= cpu_reg
->spad_base
+ (addr
- cpu_reg
->mips_view_base
);
3771 for (j
= 0; j
< (len
/ 4); j
++, offset
+= 4)
3772 bnx2_reg_wr_ind(bp
, offset
, be32_to_cpu(data
[j
]));
3775 /* Load the Data area. */
3776 addr
= be32_to_cpu(fw_entry
->data
.addr
);
3777 len
= be32_to_cpu(fw_entry
->data
.len
);
3778 file_offset
= be32_to_cpu(fw_entry
->data
.offset
);
3779 data
= (__be32
*)(bp
->mips_firmware
->data
+ file_offset
);
3781 offset
= cpu_reg
->spad_base
+ (addr
- cpu_reg
->mips_view_base
);
3785 for (j
= 0; j
< (len
/ 4); j
++, offset
+= 4)
3786 bnx2_reg_wr_ind(bp
, offset
, be32_to_cpu(data
[j
]));
3789 /* Load the Read-Only area. */
3790 addr
= be32_to_cpu(fw_entry
->rodata
.addr
);
3791 len
= be32_to_cpu(fw_entry
->rodata
.len
);
3792 file_offset
= be32_to_cpu(fw_entry
->rodata
.offset
);
3793 data
= (__be32
*)(bp
->mips_firmware
->data
+ file_offset
);
3795 offset
= cpu_reg
->spad_base
+ (addr
- cpu_reg
->mips_view_base
);
3799 for (j
= 0; j
< (len
/ 4); j
++, offset
+= 4)
3800 bnx2_reg_wr_ind(bp
, offset
, be32_to_cpu(data
[j
]));
3803 /* Clear the pre-fetch instruction. */
3804 bnx2_reg_wr_ind(bp
, cpu_reg
->inst
, 0);
3806 val
= be32_to_cpu(fw_entry
->start_addr
);
3807 bnx2_reg_wr_ind(bp
, cpu_reg
->pc
, val
);
3809 /* Start the CPU. */
3810 val
= bnx2_reg_rd_ind(bp
, cpu_reg
->mode
);
3811 val
&= ~cpu_reg
->mode_value_halt
;
3812 bnx2_reg_wr_ind(bp
, cpu_reg
->state
, cpu_reg
->state_value_clear
);
3813 bnx2_reg_wr_ind(bp
, cpu_reg
->mode
, val
);
3819 bnx2_init_cpus(struct bnx2
*bp
)
3821 const struct bnx2_mips_fw_file
*mips_fw
=
3822 (const struct bnx2_mips_fw_file
*) bp
->mips_firmware
->data
;
3823 const struct bnx2_rv2p_fw_file
*rv2p_fw
=
3824 (const struct bnx2_rv2p_fw_file
*) bp
->rv2p_firmware
->data
;
3827 /* Initialize the RV2P processor. */
3828 load_rv2p_fw(bp
, RV2P_PROC1
, &rv2p_fw
->proc1
);
3829 load_rv2p_fw(bp
, RV2P_PROC2
, &rv2p_fw
->proc2
);
3831 /* Initialize the RX Processor. */
3832 rc
= load_cpu_fw(bp
, &cpu_reg_rxp
, &mips_fw
->rxp
);
3836 /* Initialize the TX Processor. */
3837 rc
= load_cpu_fw(bp
, &cpu_reg_txp
, &mips_fw
->txp
);
3841 /* Initialize the TX Patch-up Processor. */
3842 rc
= load_cpu_fw(bp
, &cpu_reg_tpat
, &mips_fw
->tpat
);
3846 /* Initialize the Completion Processor. */
3847 rc
= load_cpu_fw(bp
, &cpu_reg_com
, &mips_fw
->com
);
3851 /* Initialize the Command Processor. */
3852 rc
= load_cpu_fw(bp
, &cpu_reg_cp
, &mips_fw
->cp
);
3859 bnx2_set_power_state(struct bnx2
*bp
, pci_power_t state
)
3863 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
3869 pci_write_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
,
3870 (pmcsr
& ~PCI_PM_CTRL_STATE_MASK
) |
3871 PCI_PM_CTRL_PME_STATUS
);
3873 if (pmcsr
& PCI_PM_CTRL_STATE_MASK
)
3874 /* delay required during transition out of D3hot */
3877 val
= REG_RD(bp
, BNX2_EMAC_MODE
);
3878 val
|= BNX2_EMAC_MODE_MPKT_RCVD
| BNX2_EMAC_MODE_ACPI_RCVD
;
3879 val
&= ~BNX2_EMAC_MODE_MPKT
;
3880 REG_WR(bp
, BNX2_EMAC_MODE
, val
);
3882 val
= REG_RD(bp
, BNX2_RPM_CONFIG
);
3883 val
&= ~BNX2_RPM_CONFIG_ACPI_ENA
;
3884 REG_WR(bp
, BNX2_RPM_CONFIG
, val
);
3895 autoneg
= bp
->autoneg
;
3896 advertising
= bp
->advertising
;
3898 if (bp
->phy_port
== PORT_TP
) {
3899 bp
->autoneg
= AUTONEG_SPEED
;
3900 bp
->advertising
= ADVERTISED_10baseT_Half
|
3901 ADVERTISED_10baseT_Full
|
3902 ADVERTISED_100baseT_Half
|
3903 ADVERTISED_100baseT_Full
|
3907 spin_lock_bh(&bp
->phy_lock
);
3908 bnx2_setup_phy(bp
, bp
->phy_port
);
3909 spin_unlock_bh(&bp
->phy_lock
);
3911 bp
->autoneg
= autoneg
;
3912 bp
->advertising
= advertising
;
3914 bnx2_set_mac_addr(bp
, bp
->dev
->dev_addr
, 0);
3916 val
= REG_RD(bp
, BNX2_EMAC_MODE
);
3918 /* Enable port mode. */
3919 val
&= ~BNX2_EMAC_MODE_PORT
;
3920 val
|= BNX2_EMAC_MODE_MPKT_RCVD
|
3921 BNX2_EMAC_MODE_ACPI_RCVD
|
3922 BNX2_EMAC_MODE_MPKT
;
3923 if (bp
->phy_port
== PORT_TP
)
3924 val
|= BNX2_EMAC_MODE_PORT_MII
;
3926 val
|= BNX2_EMAC_MODE_PORT_GMII
;
3927 if (bp
->line_speed
== SPEED_2500
)
3928 val
|= BNX2_EMAC_MODE_25G_MODE
;
3931 REG_WR(bp
, BNX2_EMAC_MODE
, val
);
3933 /* receive all multicast */
3934 for (i
= 0; i
< NUM_MC_HASH_REGISTERS
; i
++) {
3935 REG_WR(bp
, BNX2_EMAC_MULTICAST_HASH0
+ (i
* 4),
3938 REG_WR(bp
, BNX2_EMAC_RX_MODE
,
3939 BNX2_EMAC_RX_MODE_SORT_MODE
);
3941 val
= 1 | BNX2_RPM_SORT_USER0_BC_EN
|
3942 BNX2_RPM_SORT_USER0_MC_EN
;
3943 REG_WR(bp
, BNX2_RPM_SORT_USER0
, 0x0);
3944 REG_WR(bp
, BNX2_RPM_SORT_USER0
, val
);
3945 REG_WR(bp
, BNX2_RPM_SORT_USER0
, val
|
3946 BNX2_RPM_SORT_USER0_ENA
);
3948 /* Need to enable EMAC and RPM for WOL. */
3949 REG_WR(bp
, BNX2_MISC_ENABLE_SET_BITS
,
3950 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE
|
3951 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE
|
3952 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE
);
3954 val
= REG_RD(bp
, BNX2_RPM_CONFIG
);
3955 val
&= ~BNX2_RPM_CONFIG_ACPI_ENA
;
3956 REG_WR(bp
, BNX2_RPM_CONFIG
, val
);
3958 wol_msg
= BNX2_DRV_MSG_CODE_SUSPEND_WOL
;
3961 wol_msg
= BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL
;
3964 if (!(bp
->flags
& BNX2_FLAG_NO_WOL
))
3965 bnx2_fw_sync(bp
, BNX2_DRV_MSG_DATA_WAIT3
| wol_msg
,
3968 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
3969 if ((CHIP_ID(bp
) == CHIP_ID_5706_A0
) ||
3970 (CHIP_ID(bp
) == CHIP_ID_5706_A1
)) {
3979 pmcsr
|= PCI_PM_CTRL_PME_ENABLE
;
3981 pci_write_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
,
3984 /* No more memory access after this point until
3985 * device is brought back to D0.
3997 bnx2_acquire_nvram_lock(struct bnx2
*bp
)
4002 /* Request access to the flash interface. */
4003 REG_WR(bp
, BNX2_NVM_SW_ARB
, BNX2_NVM_SW_ARB_ARB_REQ_SET2
);
4004 for (j
= 0; j
< NVRAM_TIMEOUT_COUNT
; j
++) {
4005 val
= REG_RD(bp
, BNX2_NVM_SW_ARB
);
4006 if (val
& BNX2_NVM_SW_ARB_ARB_ARB2
)
4012 if (j
>= NVRAM_TIMEOUT_COUNT
)
4019 bnx2_release_nvram_lock(struct bnx2
*bp
)
4024 /* Relinquish nvram interface. */
4025 REG_WR(bp
, BNX2_NVM_SW_ARB
, BNX2_NVM_SW_ARB_ARB_REQ_CLR2
);
4027 for (j
= 0; j
< NVRAM_TIMEOUT_COUNT
; j
++) {
4028 val
= REG_RD(bp
, BNX2_NVM_SW_ARB
);
4029 if (!(val
& BNX2_NVM_SW_ARB_ARB_ARB2
))
4035 if (j
>= NVRAM_TIMEOUT_COUNT
)
4043 bnx2_enable_nvram_write(struct bnx2
*bp
)
4047 val
= REG_RD(bp
, BNX2_MISC_CFG
);
4048 REG_WR(bp
, BNX2_MISC_CFG
, val
| BNX2_MISC_CFG_NVM_WR_EN_PCI
);
4050 if (bp
->flash_info
->flags
& BNX2_NV_WREN
) {
4053 REG_WR(bp
, BNX2_NVM_COMMAND
, BNX2_NVM_COMMAND_DONE
);
4054 REG_WR(bp
, BNX2_NVM_COMMAND
,
4055 BNX2_NVM_COMMAND_WREN
| BNX2_NVM_COMMAND_DOIT
);
4057 for (j
= 0; j
< NVRAM_TIMEOUT_COUNT
; j
++) {
4060 val
= REG_RD(bp
, BNX2_NVM_COMMAND
);
4061 if (val
& BNX2_NVM_COMMAND_DONE
)
4065 if (j
>= NVRAM_TIMEOUT_COUNT
)
4072 bnx2_disable_nvram_write(struct bnx2
*bp
)
4076 val
= REG_RD(bp
, BNX2_MISC_CFG
);
4077 REG_WR(bp
, BNX2_MISC_CFG
, val
& ~BNX2_MISC_CFG_NVM_WR_EN
);
4082 bnx2_enable_nvram_access(struct bnx2
*bp
)
4086 val
= REG_RD(bp
, BNX2_NVM_ACCESS_ENABLE
);
4087 /* Enable both bits, even on read. */
4088 REG_WR(bp
, BNX2_NVM_ACCESS_ENABLE
,
4089 val
| BNX2_NVM_ACCESS_ENABLE_EN
| BNX2_NVM_ACCESS_ENABLE_WR_EN
);
4093 bnx2_disable_nvram_access(struct bnx2
*bp
)
4097 val
= REG_RD(bp
, BNX2_NVM_ACCESS_ENABLE
);
4098 /* Disable both bits, even after read. */
4099 REG_WR(bp
, BNX2_NVM_ACCESS_ENABLE
,
4100 val
& ~(BNX2_NVM_ACCESS_ENABLE_EN
|
4101 BNX2_NVM_ACCESS_ENABLE_WR_EN
));
4105 bnx2_nvram_erase_page(struct bnx2
*bp
, u32 offset
)
4110 if (bp
->flash_info
->flags
& BNX2_NV_BUFFERED
)
4111 /* Buffered flash, no erase needed */
4114 /* Build an erase command */
4115 cmd
= BNX2_NVM_COMMAND_ERASE
| BNX2_NVM_COMMAND_WR
|
4116 BNX2_NVM_COMMAND_DOIT
;
4118 /* Need to clear DONE bit separately. */
4119 REG_WR(bp
, BNX2_NVM_COMMAND
, BNX2_NVM_COMMAND_DONE
);
4121 /* Address of the NVRAM to read from. */
4122 REG_WR(bp
, BNX2_NVM_ADDR
, offset
& BNX2_NVM_ADDR_NVM_ADDR_VALUE
);
4124 /* Issue an erase command. */
4125 REG_WR(bp
, BNX2_NVM_COMMAND
, cmd
);
4127 /* Wait for completion. */
4128 for (j
= 0; j
< NVRAM_TIMEOUT_COUNT
; j
++) {
4133 val
= REG_RD(bp
, BNX2_NVM_COMMAND
);
4134 if (val
& BNX2_NVM_COMMAND_DONE
)
4138 if (j
>= NVRAM_TIMEOUT_COUNT
)
4145 bnx2_nvram_read_dword(struct bnx2
*bp
, u32 offset
, u8
*ret_val
, u32 cmd_flags
)
4150 /* Build the command word. */
4151 cmd
= BNX2_NVM_COMMAND_DOIT
| cmd_flags
;
4153 /* Calculate an offset of a buffered flash, not needed for 5709. */
4154 if (bp
->flash_info
->flags
& BNX2_NV_TRANSLATE
) {
4155 offset
= ((offset
/ bp
->flash_info
->page_size
) <<
4156 bp
->flash_info
->page_bits
) +
4157 (offset
% bp
->flash_info
->page_size
);
4160 /* Need to clear DONE bit separately. */
4161 REG_WR(bp
, BNX2_NVM_COMMAND
, BNX2_NVM_COMMAND_DONE
);
4163 /* Address of the NVRAM to read from. */
4164 REG_WR(bp
, BNX2_NVM_ADDR
, offset
& BNX2_NVM_ADDR_NVM_ADDR_VALUE
);
4166 /* Issue a read command. */
4167 REG_WR(bp
, BNX2_NVM_COMMAND
, cmd
);
4169 /* Wait for completion. */
4170 for (j
= 0; j
< NVRAM_TIMEOUT_COUNT
; j
++) {
4175 val
= REG_RD(bp
, BNX2_NVM_COMMAND
);
4176 if (val
& BNX2_NVM_COMMAND_DONE
) {
4177 __be32 v
= cpu_to_be32(REG_RD(bp
, BNX2_NVM_READ
));
4178 memcpy(ret_val
, &v
, 4);
4182 if (j
>= NVRAM_TIMEOUT_COUNT
)
4190 bnx2_nvram_write_dword(struct bnx2
*bp
, u32 offset
, u8
*val
, u32 cmd_flags
)
4196 /* Build the command word. */
4197 cmd
= BNX2_NVM_COMMAND_DOIT
| BNX2_NVM_COMMAND_WR
| cmd_flags
;
4199 /* Calculate an offset of a buffered flash, not needed for 5709. */
4200 if (bp
->flash_info
->flags
& BNX2_NV_TRANSLATE
) {
4201 offset
= ((offset
/ bp
->flash_info
->page_size
) <<
4202 bp
->flash_info
->page_bits
) +
4203 (offset
% bp
->flash_info
->page_size
);
4206 /* Need to clear DONE bit separately. */
4207 REG_WR(bp
, BNX2_NVM_COMMAND
, BNX2_NVM_COMMAND_DONE
);
4209 memcpy(&val32
, val
, 4);
4211 /* Write the data. */
4212 REG_WR(bp
, BNX2_NVM_WRITE
, be32_to_cpu(val32
));
4214 /* Address of the NVRAM to write to. */
4215 REG_WR(bp
, BNX2_NVM_ADDR
, offset
& BNX2_NVM_ADDR_NVM_ADDR_VALUE
);
4217 /* Issue the write command. */
4218 REG_WR(bp
, BNX2_NVM_COMMAND
, cmd
);
4220 /* Wait for completion. */
4221 for (j
= 0; j
< NVRAM_TIMEOUT_COUNT
; j
++) {
4224 if (REG_RD(bp
, BNX2_NVM_COMMAND
) & BNX2_NVM_COMMAND_DONE
)
4227 if (j
>= NVRAM_TIMEOUT_COUNT
)
4234 bnx2_init_nvram(struct bnx2
*bp
)
4237 int j
, entry_count
, rc
= 0;
4238 const struct flash_spec
*flash
;
4240 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
4241 bp
->flash_info
= &flash_5709
;
4242 goto get_flash_size
;
4245 /* Determine the selected interface. */
4246 val
= REG_RD(bp
, BNX2_NVM_CFG1
);
4248 entry_count
= ARRAY_SIZE(flash_table
);
4250 if (val
& 0x40000000) {
4252 /* Flash interface has been reconfigured */
4253 for (j
= 0, flash
= &flash_table
[0]; j
< entry_count
;
4255 if ((val
& FLASH_BACKUP_STRAP_MASK
) ==
4256 (flash
->config1
& FLASH_BACKUP_STRAP_MASK
)) {
4257 bp
->flash_info
= flash
;
4264 /* Not yet been reconfigured */
4266 if (val
& (1 << 23))
4267 mask
= FLASH_BACKUP_STRAP_MASK
;
4269 mask
= FLASH_STRAP_MASK
;
4271 for (j
= 0, flash
= &flash_table
[0]; j
< entry_count
;
4274 if ((val
& mask
) == (flash
->strapping
& mask
)) {
4275 bp
->flash_info
= flash
;
4277 /* Request access to the flash interface. */
4278 if ((rc
= bnx2_acquire_nvram_lock(bp
)) != 0)
4281 /* Enable access to flash interface */
4282 bnx2_enable_nvram_access(bp
);
4284 /* Reconfigure the flash interface */
4285 REG_WR(bp
, BNX2_NVM_CFG1
, flash
->config1
);
4286 REG_WR(bp
, BNX2_NVM_CFG2
, flash
->config2
);
4287 REG_WR(bp
, BNX2_NVM_CFG3
, flash
->config3
);
4288 REG_WR(bp
, BNX2_NVM_WRITE1
, flash
->write1
);
4290 /* Disable access to flash interface */
4291 bnx2_disable_nvram_access(bp
);
4292 bnx2_release_nvram_lock(bp
);
4297 } /* if (val & 0x40000000) */
4299 if (j
== entry_count
) {
4300 bp
->flash_info
= NULL
;
4301 printk(KERN_ALERT PFX
"Unknown flash/EEPROM type.\n");
4306 val
= bnx2_shmem_rd(bp
, BNX2_SHARED_HW_CFG_CONFIG2
);
4307 val
&= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK
;
4309 bp
->flash_size
= val
;
4311 bp
->flash_size
= bp
->flash_info
->total_size
;
4317 bnx2_nvram_read(struct bnx2
*bp
, u32 offset
, u8
*ret_buf
,
4321 u32 cmd_flags
, offset32
, len32
, extra
;
4326 /* Request access to the flash interface. */
4327 if ((rc
= bnx2_acquire_nvram_lock(bp
)) != 0)
4330 /* Enable access to flash interface */
4331 bnx2_enable_nvram_access(bp
);
4344 pre_len
= 4 - (offset
& 3);
4346 if (pre_len
>= len32
) {
4348 cmd_flags
= BNX2_NVM_COMMAND_FIRST
|
4349 BNX2_NVM_COMMAND_LAST
;
4352 cmd_flags
= BNX2_NVM_COMMAND_FIRST
;
4355 rc
= bnx2_nvram_read_dword(bp
, offset32
, buf
, cmd_flags
);
4360 memcpy(ret_buf
, buf
+ (offset
& 3), pre_len
);
4367 extra
= 4 - (len32
& 3);
4368 len32
= (len32
+ 4) & ~3;
4375 cmd_flags
= BNX2_NVM_COMMAND_LAST
;
4377 cmd_flags
= BNX2_NVM_COMMAND_FIRST
|
4378 BNX2_NVM_COMMAND_LAST
;
4380 rc
= bnx2_nvram_read_dword(bp
, offset32
, buf
, cmd_flags
);
4382 memcpy(ret_buf
, buf
, 4 - extra
);
4384 else if (len32
> 0) {
4387 /* Read the first word. */
4391 cmd_flags
= BNX2_NVM_COMMAND_FIRST
;
4393 rc
= bnx2_nvram_read_dword(bp
, offset32
, ret_buf
, cmd_flags
);
4395 /* Advance to the next dword. */
4400 while (len32
> 4 && rc
== 0) {
4401 rc
= bnx2_nvram_read_dword(bp
, offset32
, ret_buf
, 0);
4403 /* Advance to the next dword. */
4412 cmd_flags
= BNX2_NVM_COMMAND_LAST
;
4413 rc
= bnx2_nvram_read_dword(bp
, offset32
, buf
, cmd_flags
);
4415 memcpy(ret_buf
, buf
, 4 - extra
);
4418 /* Disable access to flash interface */
4419 bnx2_disable_nvram_access(bp
);
4421 bnx2_release_nvram_lock(bp
);
4427 bnx2_nvram_write(struct bnx2
*bp
, u32 offset
, u8
*data_buf
,
4430 u32 written
, offset32
, len32
;
4431 u8
*buf
, start
[4], end
[4], *align_buf
= NULL
, *flash_buffer
= NULL
;
4433 int align_start
, align_end
;
4438 align_start
= align_end
= 0;
4440 if ((align_start
= (offset32
& 3))) {
4442 len32
+= align_start
;
4445 if ((rc
= bnx2_nvram_read(bp
, offset32
, start
, 4)))
4450 align_end
= 4 - (len32
& 3);
4452 if ((rc
= bnx2_nvram_read(bp
, offset32
+ len32
- 4, end
, 4)))
4456 if (align_start
|| align_end
) {
4457 align_buf
= kmalloc(len32
, GFP_KERNEL
);
4458 if (align_buf
== NULL
)
4461 memcpy(align_buf
, start
, 4);
4464 memcpy(align_buf
+ len32
- 4, end
, 4);
4466 memcpy(align_buf
+ align_start
, data_buf
, buf_size
);
4470 if (!(bp
->flash_info
->flags
& BNX2_NV_BUFFERED
)) {
4471 flash_buffer
= kmalloc(264, GFP_KERNEL
);
4472 if (flash_buffer
== NULL
) {
4474 goto nvram_write_end
;
4479 while ((written
< len32
) && (rc
== 0)) {
4480 u32 page_start
, page_end
, data_start
, data_end
;
4481 u32 addr
, cmd_flags
;
4484 /* Find the page_start addr */
4485 page_start
= offset32
+ written
;
4486 page_start
-= (page_start
% bp
->flash_info
->page_size
);
4487 /* Find the page_end addr */
4488 page_end
= page_start
+ bp
->flash_info
->page_size
;
4489 /* Find the data_start addr */
4490 data_start
= (written
== 0) ? offset32
: page_start
;
4491 /* Find the data_end addr */
4492 data_end
= (page_end
> offset32
+ len32
) ?
4493 (offset32
+ len32
) : page_end
;
4495 /* Request access to the flash interface. */
4496 if ((rc
= bnx2_acquire_nvram_lock(bp
)) != 0)
4497 goto nvram_write_end
;
4499 /* Enable access to flash interface */
4500 bnx2_enable_nvram_access(bp
);
4502 cmd_flags
= BNX2_NVM_COMMAND_FIRST
;
4503 if (!(bp
->flash_info
->flags
& BNX2_NV_BUFFERED
)) {
4506 /* Read the whole page into the buffer
4507 * (non-buffer flash only) */
4508 for (j
= 0; j
< bp
->flash_info
->page_size
; j
+= 4) {
4509 if (j
== (bp
->flash_info
->page_size
- 4)) {
4510 cmd_flags
|= BNX2_NVM_COMMAND_LAST
;
4512 rc
= bnx2_nvram_read_dword(bp
,
4518 goto nvram_write_end
;
4524 /* Enable writes to flash interface (unlock write-protect) */
4525 if ((rc
= bnx2_enable_nvram_write(bp
)) != 0)
4526 goto nvram_write_end
;
4528 /* Loop to write back the buffer data from page_start to
4531 if (!(bp
->flash_info
->flags
& BNX2_NV_BUFFERED
)) {
4532 /* Erase the page */
4533 if ((rc
= bnx2_nvram_erase_page(bp
, page_start
)) != 0)
4534 goto nvram_write_end
;
4536 /* Re-enable the write again for the actual write */
4537 bnx2_enable_nvram_write(bp
);
4539 for (addr
= page_start
; addr
< data_start
;
4540 addr
+= 4, i
+= 4) {
4542 rc
= bnx2_nvram_write_dword(bp
, addr
,
4543 &flash_buffer
[i
], cmd_flags
);
4546 goto nvram_write_end
;
4552 /* Loop to write the new data from data_start to data_end */
4553 for (addr
= data_start
; addr
< data_end
; addr
+= 4, i
+= 4) {
4554 if ((addr
== page_end
- 4) ||
4555 ((bp
->flash_info
->flags
& BNX2_NV_BUFFERED
) &&
4556 (addr
== data_end
- 4))) {
4558 cmd_flags
|= BNX2_NVM_COMMAND_LAST
;
4560 rc
= bnx2_nvram_write_dword(bp
, addr
, buf
,
4564 goto nvram_write_end
;
4570 /* Loop to write back the buffer data from data_end
4572 if (!(bp
->flash_info
->flags
& BNX2_NV_BUFFERED
)) {
4573 for (addr
= data_end
; addr
< page_end
;
4574 addr
+= 4, i
+= 4) {
4576 if (addr
== page_end
-4) {
4577 cmd_flags
= BNX2_NVM_COMMAND_LAST
;
4579 rc
= bnx2_nvram_write_dword(bp
, addr
,
4580 &flash_buffer
[i
], cmd_flags
);
4583 goto nvram_write_end
;
4589 /* Disable writes to flash interface (lock write-protect) */
4590 bnx2_disable_nvram_write(bp
);
4592 /* Disable access to flash interface */
4593 bnx2_disable_nvram_access(bp
);
4594 bnx2_release_nvram_lock(bp
);
4596 /* Increment written */
4597 written
+= data_end
- data_start
;
4601 kfree(flash_buffer
);
4607 bnx2_init_fw_cap(struct bnx2
*bp
)
4611 bp
->phy_flags
&= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP
;
4612 bp
->flags
&= ~BNX2_FLAG_CAN_KEEP_VLAN
;
4614 if (!(bp
->flags
& BNX2_FLAG_ASF_ENABLE
))
4615 bp
->flags
|= BNX2_FLAG_CAN_KEEP_VLAN
;
4617 val
= bnx2_shmem_rd(bp
, BNX2_FW_CAP_MB
);
4618 if ((val
& BNX2_FW_CAP_SIGNATURE_MASK
) != BNX2_FW_CAP_SIGNATURE
)
4621 if ((val
& BNX2_FW_CAP_CAN_KEEP_VLAN
) == BNX2_FW_CAP_CAN_KEEP_VLAN
) {
4622 bp
->flags
|= BNX2_FLAG_CAN_KEEP_VLAN
;
4623 sig
|= BNX2_DRV_ACK_CAP_SIGNATURE
| BNX2_FW_CAP_CAN_KEEP_VLAN
;
4626 if ((bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) &&
4627 (val
& BNX2_FW_CAP_REMOTE_PHY_CAPABLE
)) {
4630 bp
->phy_flags
|= BNX2_PHY_FLAG_REMOTE_PHY_CAP
;
4632 link
= bnx2_shmem_rd(bp
, BNX2_LINK_STATUS
);
4633 if (link
& BNX2_LINK_STATUS_SERDES_LINK
)
4634 bp
->phy_port
= PORT_FIBRE
;
4636 bp
->phy_port
= PORT_TP
;
4638 sig
|= BNX2_DRV_ACK_CAP_SIGNATURE
|
4639 BNX2_FW_CAP_REMOTE_PHY_CAPABLE
;
4642 if (netif_running(bp
->dev
) && sig
)
4643 bnx2_shmem_wr(bp
, BNX2_DRV_ACK_CAP_MB
, sig
);
4647 bnx2_setup_msix_tbl(struct bnx2
*bp
)
4649 REG_WR(bp
, BNX2_PCI_GRC_WINDOW_ADDR
, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN
);
4651 REG_WR(bp
, BNX2_PCI_GRC_WINDOW2_ADDR
, BNX2_MSIX_TABLE_ADDR
);
4652 REG_WR(bp
, BNX2_PCI_GRC_WINDOW3_ADDR
, BNX2_MSIX_PBA_ADDR
);
4656 bnx2_reset_chip(struct bnx2
*bp
, u32 reset_code
)
4662 /* Wait for the current PCI transaction to complete before
4663 * issuing a reset. */
4664 REG_WR(bp
, BNX2_MISC_ENABLE_CLR_BITS
,
4665 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE
|
4666 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE
|
4667 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE
|
4668 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE
);
4669 val
= REG_RD(bp
, BNX2_MISC_ENABLE_CLR_BITS
);
4672 /* Wait for the firmware to tell us it is ok to issue a reset. */
4673 bnx2_fw_sync(bp
, BNX2_DRV_MSG_DATA_WAIT0
| reset_code
, 1, 1);
4675 /* Deposit a driver reset signature so the firmware knows that
4676 * this is a soft reset. */
4677 bnx2_shmem_wr(bp
, BNX2_DRV_RESET_SIGNATURE
,
4678 BNX2_DRV_RESET_SIGNATURE_MAGIC
);
4680 /* Do a dummy read to force the chip to complete all current transaction
4681 * before we issue a reset. */
4682 val
= REG_RD(bp
, BNX2_MISC_ID
);
4684 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
4685 REG_WR(bp
, BNX2_MISC_COMMAND
, BNX2_MISC_COMMAND_SW_RESET
);
4686 REG_RD(bp
, BNX2_MISC_COMMAND
);
4689 val
= BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA
|
4690 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP
;
4692 pci_write_config_dword(bp
->pdev
, BNX2_PCICFG_MISC_CONFIG
, val
);
4695 val
= BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ
|
4696 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA
|
4697 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP
;
4700 REG_WR(bp
, BNX2_PCICFG_MISC_CONFIG
, val
);
4702 /* Reading back any register after chip reset will hang the
4703 * bus on 5706 A0 and A1. The msleep below provides plenty
4704 * of margin for write posting.
4706 if ((CHIP_ID(bp
) == CHIP_ID_5706_A0
) ||
4707 (CHIP_ID(bp
) == CHIP_ID_5706_A1
))
4710 /* Reset takes approximate 30 usec */
4711 for (i
= 0; i
< 10; i
++) {
4712 val
= REG_RD(bp
, BNX2_PCICFG_MISC_CONFIG
);
4713 if ((val
& (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ
|
4714 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY
)) == 0)
4719 if (val
& (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ
|
4720 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY
)) {
4721 printk(KERN_ERR PFX
"Chip reset did not complete\n");
4726 /* Make sure byte swapping is properly configured. */
4727 val
= REG_RD(bp
, BNX2_PCI_SWAP_DIAG0
);
4728 if (val
!= 0x01020304) {
4729 printk(KERN_ERR PFX
"Chip not in correct endian mode\n");
4733 /* Wait for the firmware to finish its initialization. */
4734 rc
= bnx2_fw_sync(bp
, BNX2_DRV_MSG_DATA_WAIT1
| reset_code
, 1, 0);
4738 spin_lock_bh(&bp
->phy_lock
);
4739 old_port
= bp
->phy_port
;
4740 bnx2_init_fw_cap(bp
);
4741 if ((bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
) &&
4742 old_port
!= bp
->phy_port
)
4743 bnx2_set_default_remote_link(bp
);
4744 spin_unlock_bh(&bp
->phy_lock
);
4746 if (CHIP_ID(bp
) == CHIP_ID_5706_A0
) {
4747 /* Adjust the voltage regular to two steps lower. The default
4748 * of this register is 0x0000000e. */
4749 REG_WR(bp
, BNX2_MISC_VREG_CONTROL
, 0x000000fa);
4751 /* Remove bad rbuf memory from the free pool. */
4752 rc
= bnx2_alloc_bad_rbuf(bp
);
4755 if (bp
->flags
& BNX2_FLAG_USING_MSIX
)
4756 bnx2_setup_msix_tbl(bp
);
4762 bnx2_init_chip(struct bnx2
*bp
)
4767 /* Make sure the interrupt is not active. */
4768 REG_WR(bp
, BNX2_PCICFG_INT_ACK_CMD
, BNX2_PCICFG_INT_ACK_CMD_MASK_INT
);
4770 val
= BNX2_DMA_CONFIG_DATA_BYTE_SWAP
|
4771 BNX2_DMA_CONFIG_DATA_WORD_SWAP
|
4773 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP
|
4775 BNX2_DMA_CONFIG_CNTL_WORD_SWAP
|
4776 DMA_READ_CHANS
<< 12 |
4777 DMA_WRITE_CHANS
<< 16;
4779 val
|= (0x2 << 20) | (1 << 11);
4781 if ((bp
->flags
& BNX2_FLAG_PCIX
) && (bp
->bus_speed_mhz
== 133))
4784 if ((CHIP_NUM(bp
) == CHIP_NUM_5706
) &&
4785 (CHIP_ID(bp
) != CHIP_ID_5706_A0
) && !(bp
->flags
& BNX2_FLAG_PCIX
))
4786 val
|= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA
;
4788 REG_WR(bp
, BNX2_DMA_CONFIG
, val
);
4790 if (CHIP_ID(bp
) == CHIP_ID_5706_A0
) {
4791 val
= REG_RD(bp
, BNX2_TDMA_CONFIG
);
4792 val
|= BNX2_TDMA_CONFIG_ONE_DMA
;
4793 REG_WR(bp
, BNX2_TDMA_CONFIG
, val
);
4796 if (bp
->flags
& BNX2_FLAG_PCIX
) {
4799 pci_read_config_word(bp
->pdev
, bp
->pcix_cap
+ PCI_X_CMD
,
4801 pci_write_config_word(bp
->pdev
, bp
->pcix_cap
+ PCI_X_CMD
,
4802 val16
& ~PCI_X_CMD_ERO
);
4805 REG_WR(bp
, BNX2_MISC_ENABLE_SET_BITS
,
4806 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE
|
4807 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE
|
4808 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE
);
4810 /* Initialize context mapping and zero out the quick contexts. The
4811 * context block must have already been enabled. */
4812 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
4813 rc
= bnx2_init_5709_context(bp
);
4817 bnx2_init_context(bp
);
4819 if ((rc
= bnx2_init_cpus(bp
)) != 0)
4822 bnx2_init_nvram(bp
);
4824 bnx2_set_mac_addr(bp
, bp
->dev
->dev_addr
, 0);
4826 val
= REG_RD(bp
, BNX2_MQ_CONFIG
);
4827 val
&= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE
;
4828 val
|= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256
;
4829 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
4830 val
|= BNX2_MQ_CONFIG_BIN_MQ_MODE
;
4831 if (CHIP_REV(bp
) == CHIP_REV_Ax
)
4832 val
|= BNX2_MQ_CONFIG_HALT_DIS
;
4835 REG_WR(bp
, BNX2_MQ_CONFIG
, val
);
4837 val
= 0x10000 + (MAX_CID_CNT
* MB_KERNEL_CTX_SIZE
);
4838 REG_WR(bp
, BNX2_MQ_KNL_BYP_WIND_START
, val
);
4839 REG_WR(bp
, BNX2_MQ_KNL_WIND_END
, val
);
4841 val
= (BCM_PAGE_BITS
- 8) << 24;
4842 REG_WR(bp
, BNX2_RV2P_CONFIG
, val
);
4844 /* Configure page size. */
4845 val
= REG_RD(bp
, BNX2_TBDR_CONFIG
);
4846 val
&= ~BNX2_TBDR_CONFIG_PAGE_SIZE
;
4847 val
|= (BCM_PAGE_BITS
- 8) << 24 | 0x40;
4848 REG_WR(bp
, BNX2_TBDR_CONFIG
, val
);
4850 val
= bp
->mac_addr
[0] +
4851 (bp
->mac_addr
[1] << 8) +
4852 (bp
->mac_addr
[2] << 16) +
4854 (bp
->mac_addr
[4] << 8) +
4855 (bp
->mac_addr
[5] << 16);
4856 REG_WR(bp
, BNX2_EMAC_BACKOFF_SEED
, val
);
4858 /* Program the MTU. Also include 4 bytes for CRC32. */
4860 val
= mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
4861 if (val
> (MAX_ETHERNET_PACKET_SIZE
+ 4))
4862 val
|= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA
;
4863 REG_WR(bp
, BNX2_EMAC_RX_MTU_SIZE
, val
);
4868 bnx2_reg_wr_ind(bp
, BNX2_RBUF_CONFIG
, BNX2_RBUF_CONFIG_VAL(mtu
));
4869 bnx2_reg_wr_ind(bp
, BNX2_RBUF_CONFIG2
, BNX2_RBUF_CONFIG2_VAL(mtu
));
4870 bnx2_reg_wr_ind(bp
, BNX2_RBUF_CONFIG3
, BNX2_RBUF_CONFIG3_VAL(mtu
));
4872 memset(bp
->bnx2_napi
[0].status_blk
.msi
, 0, bp
->status_stats_size
);
4873 for (i
= 0; i
< BNX2_MAX_MSIX_VEC
; i
++)
4874 bp
->bnx2_napi
[i
].last_status_idx
= 0;
4876 bp
->idle_chk_status_idx
= 0xffff;
4878 bp
->rx_mode
= BNX2_EMAC_RX_MODE_SORT_MODE
;
4880 /* Set up how to generate a link change interrupt. */
4881 REG_WR(bp
, BNX2_EMAC_ATTENTION_ENA
, BNX2_EMAC_ATTENTION_ENA_LINK
);
4883 REG_WR(bp
, BNX2_HC_STATUS_ADDR_L
,
4884 (u64
) bp
->status_blk_mapping
& 0xffffffff);
4885 REG_WR(bp
, BNX2_HC_STATUS_ADDR_H
, (u64
) bp
->status_blk_mapping
>> 32);
4887 REG_WR(bp
, BNX2_HC_STATISTICS_ADDR_L
,
4888 (u64
) bp
->stats_blk_mapping
& 0xffffffff);
4889 REG_WR(bp
, BNX2_HC_STATISTICS_ADDR_H
,
4890 (u64
) bp
->stats_blk_mapping
>> 32);
4892 REG_WR(bp
, BNX2_HC_TX_QUICK_CONS_TRIP
,
4893 (bp
->tx_quick_cons_trip_int
<< 16) | bp
->tx_quick_cons_trip
);
4895 REG_WR(bp
, BNX2_HC_RX_QUICK_CONS_TRIP
,
4896 (bp
->rx_quick_cons_trip_int
<< 16) | bp
->rx_quick_cons_trip
);
4898 REG_WR(bp
, BNX2_HC_COMP_PROD_TRIP
,
4899 (bp
->comp_prod_trip_int
<< 16) | bp
->comp_prod_trip
);
4901 REG_WR(bp
, BNX2_HC_TX_TICKS
, (bp
->tx_ticks_int
<< 16) | bp
->tx_ticks
);
4903 REG_WR(bp
, BNX2_HC_RX_TICKS
, (bp
->rx_ticks_int
<< 16) | bp
->rx_ticks
);
4905 REG_WR(bp
, BNX2_HC_COM_TICKS
,
4906 (bp
->com_ticks_int
<< 16) | bp
->com_ticks
);
4908 REG_WR(bp
, BNX2_HC_CMD_TICKS
,
4909 (bp
->cmd_ticks_int
<< 16) | bp
->cmd_ticks
);
4911 if (bp
->flags
& BNX2_FLAG_BROKEN_STATS
)
4912 REG_WR(bp
, BNX2_HC_STATS_TICKS
, 0);
4914 REG_WR(bp
, BNX2_HC_STATS_TICKS
, bp
->stats_ticks
);
4915 REG_WR(bp
, BNX2_HC_STAT_COLLECT_TICKS
, 0xbb8); /* 3ms */
4917 if (CHIP_ID(bp
) == CHIP_ID_5706_A1
)
4918 val
= BNX2_HC_CONFIG_COLLECT_STATS
;
4920 val
= BNX2_HC_CONFIG_RX_TMR_MODE
| BNX2_HC_CONFIG_TX_TMR_MODE
|
4921 BNX2_HC_CONFIG_COLLECT_STATS
;
4924 if (bp
->irq_nvecs
> 1) {
4925 REG_WR(bp
, BNX2_HC_MSIX_BIT_VECTOR
,
4926 BNX2_HC_MSIX_BIT_VECTOR_VAL
);
4928 val
|= BNX2_HC_CONFIG_SB_ADDR_INC_128B
;
4931 if (bp
->flags
& BNX2_FLAG_ONE_SHOT_MSI
)
4932 val
|= BNX2_HC_CONFIG_ONE_SHOT
| BNX2_HC_CONFIG_USE_INT_PARAM
;
4934 REG_WR(bp
, BNX2_HC_CONFIG
, val
);
4936 for (i
= 1; i
< bp
->irq_nvecs
; i
++) {
4937 u32 base
= ((i
- 1) * BNX2_HC_SB_CONFIG_SIZE
) +
4938 BNX2_HC_SB_CONFIG_1
;
4941 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE
|
4942 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE
|
4943 BNX2_HC_SB_CONFIG_1_ONE_SHOT
);
4945 REG_WR(bp
, base
+ BNX2_HC_TX_QUICK_CONS_TRIP_OFF
,
4946 (bp
->tx_quick_cons_trip_int
<< 16) |
4947 bp
->tx_quick_cons_trip
);
4949 REG_WR(bp
, base
+ BNX2_HC_TX_TICKS_OFF
,
4950 (bp
->tx_ticks_int
<< 16) | bp
->tx_ticks
);
4952 REG_WR(bp
, base
+ BNX2_HC_RX_QUICK_CONS_TRIP_OFF
,
4953 (bp
->rx_quick_cons_trip_int
<< 16) |
4954 bp
->rx_quick_cons_trip
);
4956 REG_WR(bp
, base
+ BNX2_HC_RX_TICKS_OFF
,
4957 (bp
->rx_ticks_int
<< 16) | bp
->rx_ticks
);
4960 /* Clear internal stats counters. */
4961 REG_WR(bp
, BNX2_HC_COMMAND
, BNX2_HC_COMMAND_CLR_STAT_NOW
);
4963 REG_WR(bp
, BNX2_HC_ATTN_BITS_ENABLE
, STATUS_ATTN_EVENTS
);
4965 /* Initialize the receive filter. */
4966 bnx2_set_rx_mode(bp
->dev
);
4968 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
4969 val
= REG_RD(bp
, BNX2_MISC_NEW_CORE_CTL
);
4970 val
|= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE
;
4971 REG_WR(bp
, BNX2_MISC_NEW_CORE_CTL
, val
);
4973 rc
= bnx2_fw_sync(bp
, BNX2_DRV_MSG_DATA_WAIT2
| BNX2_DRV_MSG_CODE_RESET
,
4976 REG_WR(bp
, BNX2_MISC_ENABLE_SET_BITS
, BNX2_MISC_ENABLE_DEFAULT
);
4977 REG_RD(bp
, BNX2_MISC_ENABLE_SET_BITS
);
4981 bp
->hc_cmd
= REG_RD(bp
, BNX2_HC_COMMAND
);
4987 bnx2_clear_ring_states(struct bnx2
*bp
)
4989 struct bnx2_napi
*bnapi
;
4990 struct bnx2_tx_ring_info
*txr
;
4991 struct bnx2_rx_ring_info
*rxr
;
4994 for (i
= 0; i
< BNX2_MAX_MSIX_VEC
; i
++) {
4995 bnapi
= &bp
->bnx2_napi
[i
];
4996 txr
= &bnapi
->tx_ring
;
4997 rxr
= &bnapi
->rx_ring
;
5000 txr
->hw_tx_cons
= 0;
5001 rxr
->rx_prod_bseq
= 0;
5004 rxr
->rx_pg_prod
= 0;
5005 rxr
->rx_pg_cons
= 0;
5010 bnx2_init_tx_context(struct bnx2
*bp
, u32 cid
, struct bnx2_tx_ring_info
*txr
)
5012 u32 val
, offset0
, offset1
, offset2
, offset3
;
5013 u32 cid_addr
= GET_CID_ADDR(cid
);
5015 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
5016 offset0
= BNX2_L2CTX_TYPE_XI
;
5017 offset1
= BNX2_L2CTX_CMD_TYPE_XI
;
5018 offset2
= BNX2_L2CTX_TBDR_BHADDR_HI_XI
;
5019 offset3
= BNX2_L2CTX_TBDR_BHADDR_LO_XI
;
5021 offset0
= BNX2_L2CTX_TYPE
;
5022 offset1
= BNX2_L2CTX_CMD_TYPE
;
5023 offset2
= BNX2_L2CTX_TBDR_BHADDR_HI
;
5024 offset3
= BNX2_L2CTX_TBDR_BHADDR_LO
;
5026 val
= BNX2_L2CTX_TYPE_TYPE_L2
| BNX2_L2CTX_TYPE_SIZE_L2
;
5027 bnx2_ctx_wr(bp
, cid_addr
, offset0
, val
);
5029 val
= BNX2_L2CTX_CMD_TYPE_TYPE_L2
| (8 << 16);
5030 bnx2_ctx_wr(bp
, cid_addr
, offset1
, val
);
5032 val
= (u64
) txr
->tx_desc_mapping
>> 32;
5033 bnx2_ctx_wr(bp
, cid_addr
, offset2
, val
);
5035 val
= (u64
) txr
->tx_desc_mapping
& 0xffffffff;
5036 bnx2_ctx_wr(bp
, cid_addr
, offset3
, val
);
5040 bnx2_init_tx_ring(struct bnx2
*bp
, int ring_num
)
5044 struct bnx2_napi
*bnapi
;
5045 struct bnx2_tx_ring_info
*txr
;
5047 bnapi
= &bp
->bnx2_napi
[ring_num
];
5048 txr
= &bnapi
->tx_ring
;
5053 cid
= TX_TSS_CID
+ ring_num
- 1;
5055 bp
->tx_wake_thresh
= bp
->tx_ring_size
/ 2;
5057 txbd
= &txr
->tx_desc_ring
[MAX_TX_DESC_CNT
];
5059 txbd
->tx_bd_haddr_hi
= (u64
) txr
->tx_desc_mapping
>> 32;
5060 txbd
->tx_bd_haddr_lo
= (u64
) txr
->tx_desc_mapping
& 0xffffffff;
5063 txr
->tx_prod_bseq
= 0;
5065 txr
->tx_bidx_addr
= MB_GET_CID_ADDR(cid
) + BNX2_L2CTX_TX_HOST_BIDX
;
5066 txr
->tx_bseq_addr
= MB_GET_CID_ADDR(cid
) + BNX2_L2CTX_TX_HOST_BSEQ
;
5068 bnx2_init_tx_context(bp
, cid
, txr
);
5072 bnx2_init_rxbd_rings(struct rx_bd
*rx_ring
[], dma_addr_t dma
[], u32 buf_size
,
5078 for (i
= 0; i
< num_rings
; i
++) {
5081 rxbd
= &rx_ring
[i
][0];
5082 for (j
= 0; j
< MAX_RX_DESC_CNT
; j
++, rxbd
++) {
5083 rxbd
->rx_bd_len
= buf_size
;
5084 rxbd
->rx_bd_flags
= RX_BD_FLAGS_START
| RX_BD_FLAGS_END
;
5086 if (i
== (num_rings
- 1))
5090 rxbd
->rx_bd_haddr_hi
= (u64
) dma
[j
] >> 32;
5091 rxbd
->rx_bd_haddr_lo
= (u64
) dma
[j
] & 0xffffffff;
5096 bnx2_init_rx_ring(struct bnx2
*bp
, int ring_num
)
5099 u16 prod
, ring_prod
;
5100 u32 cid
, rx_cid_addr
, val
;
5101 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[ring_num
];
5102 struct bnx2_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
5107 cid
= RX_RSS_CID
+ ring_num
- 1;
5109 rx_cid_addr
= GET_CID_ADDR(cid
);
5111 bnx2_init_rxbd_rings(rxr
->rx_desc_ring
, rxr
->rx_desc_mapping
,
5112 bp
->rx_buf_use_size
, bp
->rx_max_ring
);
5114 bnx2_init_rx_context(bp
, cid
);
5116 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
5117 val
= REG_RD(bp
, BNX2_MQ_MAP_L2_5
);
5118 REG_WR(bp
, BNX2_MQ_MAP_L2_5
, val
| BNX2_MQ_MAP_L2_5_ARM
);
5121 bnx2_ctx_wr(bp
, rx_cid_addr
, BNX2_L2CTX_PG_BUF_SIZE
, 0);
5122 if (bp
->rx_pg_ring_size
) {
5123 bnx2_init_rxbd_rings(rxr
->rx_pg_desc_ring
,
5124 rxr
->rx_pg_desc_mapping
,
5125 PAGE_SIZE
, bp
->rx_max_pg_ring
);
5126 val
= (bp
->rx_buf_use_size
<< 16) | PAGE_SIZE
;
5127 bnx2_ctx_wr(bp
, rx_cid_addr
, BNX2_L2CTX_PG_BUF_SIZE
, val
);
5128 bnx2_ctx_wr(bp
, rx_cid_addr
, BNX2_L2CTX_RBDC_KEY
,
5129 BNX2_L2CTX_RBDC_JUMBO_KEY
- ring_num
);
5131 val
= (u64
) rxr
->rx_pg_desc_mapping
[0] >> 32;
5132 bnx2_ctx_wr(bp
, rx_cid_addr
, BNX2_L2CTX_NX_PG_BDHADDR_HI
, val
);
5134 val
= (u64
) rxr
->rx_pg_desc_mapping
[0] & 0xffffffff;
5135 bnx2_ctx_wr(bp
, rx_cid_addr
, BNX2_L2CTX_NX_PG_BDHADDR_LO
, val
);
5137 if (CHIP_NUM(bp
) == CHIP_NUM_5709
)
5138 REG_WR(bp
, BNX2_MQ_MAP_L2_3
, BNX2_MQ_MAP_L2_3_DEFAULT
);
5141 val
= (u64
) rxr
->rx_desc_mapping
[0] >> 32;
5142 bnx2_ctx_wr(bp
, rx_cid_addr
, BNX2_L2CTX_NX_BDHADDR_HI
, val
);
5144 val
= (u64
) rxr
->rx_desc_mapping
[0] & 0xffffffff;
5145 bnx2_ctx_wr(bp
, rx_cid_addr
, BNX2_L2CTX_NX_BDHADDR_LO
, val
);
5147 ring_prod
= prod
= rxr
->rx_pg_prod
;
5148 for (i
= 0; i
< bp
->rx_pg_ring_size
; i
++) {
5149 if (bnx2_alloc_rx_page(bp
, rxr
, ring_prod
) < 0)
5151 prod
= NEXT_RX_BD(prod
);
5152 ring_prod
= RX_PG_RING_IDX(prod
);
5154 rxr
->rx_pg_prod
= prod
;
5156 ring_prod
= prod
= rxr
->rx_prod
;
5157 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
5158 if (bnx2_alloc_rx_skb(bp
, rxr
, ring_prod
) < 0)
5160 prod
= NEXT_RX_BD(prod
);
5161 ring_prod
= RX_RING_IDX(prod
);
5163 rxr
->rx_prod
= prod
;
5165 rxr
->rx_bidx_addr
= MB_GET_CID_ADDR(cid
) + BNX2_L2CTX_HOST_BDIDX
;
5166 rxr
->rx_bseq_addr
= MB_GET_CID_ADDR(cid
) + BNX2_L2CTX_HOST_BSEQ
;
5167 rxr
->rx_pg_bidx_addr
= MB_GET_CID_ADDR(cid
) + BNX2_L2CTX_HOST_PG_BDIDX
;
5169 REG_WR16(bp
, rxr
->rx_pg_bidx_addr
, rxr
->rx_pg_prod
);
5170 REG_WR16(bp
, rxr
->rx_bidx_addr
, prod
);
5172 REG_WR(bp
, rxr
->rx_bseq_addr
, rxr
->rx_prod_bseq
);
5176 bnx2_init_all_rings(struct bnx2
*bp
)
5181 bnx2_clear_ring_states(bp
);
5183 REG_WR(bp
, BNX2_TSCH_TSS_CFG
, 0);
5184 for (i
= 0; i
< bp
->num_tx_rings
; i
++)
5185 bnx2_init_tx_ring(bp
, i
);
5187 if (bp
->num_tx_rings
> 1)
5188 REG_WR(bp
, BNX2_TSCH_TSS_CFG
, ((bp
->num_tx_rings
- 1) << 24) |
5191 REG_WR(bp
, BNX2_RLUP_RSS_CONFIG
, 0);
5192 bnx2_reg_wr_ind(bp
, BNX2_RXP_SCRATCH_RSS_TBL_SZ
, 0);
5194 for (i
= 0; i
< bp
->num_rx_rings
; i
++)
5195 bnx2_init_rx_ring(bp
, i
);
5197 if (bp
->num_rx_rings
> 1) {
5199 u8
*tbl
= (u8
*) &tbl_32
;
5201 bnx2_reg_wr_ind(bp
, BNX2_RXP_SCRATCH_RSS_TBL_SZ
,
5202 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES
);
5204 for (i
= 0; i
< BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES
; i
++) {
5205 tbl
[i
% 4] = i
% (bp
->num_rx_rings
- 1);
5208 BNX2_RXP_SCRATCH_RSS_TBL
+ i
,
5209 cpu_to_be32(tbl_32
));
5212 val
= BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI
|
5213 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI
;
5215 REG_WR(bp
, BNX2_RLUP_RSS_CONFIG
, val
);
5220 static u32
bnx2_find_max_ring(u32 ring_size
, u32 max_size
)
5222 u32 max
, num_rings
= 1;
5224 while (ring_size
> MAX_RX_DESC_CNT
) {
5225 ring_size
-= MAX_RX_DESC_CNT
;
5228 /* round to next power of 2 */
5230 while ((max
& num_rings
) == 0)
5233 if (num_rings
!= max
)
5240 bnx2_set_rx_ring_size(struct bnx2
*bp
, u32 size
)
5242 u32 rx_size
, rx_space
, jumbo_size
;
5244 /* 8 for CRC and VLAN */
5245 rx_size
= bp
->dev
->mtu
+ ETH_HLEN
+ BNX2_RX_OFFSET
+ 8;
5247 rx_space
= SKB_DATA_ALIGN(rx_size
+ BNX2_RX_ALIGN
) + NET_SKB_PAD
+
5248 sizeof(struct skb_shared_info
);
5250 bp
->rx_copy_thresh
= BNX2_RX_COPY_THRESH
;
5251 bp
->rx_pg_ring_size
= 0;
5252 bp
->rx_max_pg_ring
= 0;
5253 bp
->rx_max_pg_ring_idx
= 0;
5254 if ((rx_space
> PAGE_SIZE
) && !(bp
->flags
& BNX2_FLAG_JUMBO_BROKEN
)) {
5255 int pages
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
5257 jumbo_size
= size
* pages
;
5258 if (jumbo_size
> MAX_TOTAL_RX_PG_DESC_CNT
)
5259 jumbo_size
= MAX_TOTAL_RX_PG_DESC_CNT
;
5261 bp
->rx_pg_ring_size
= jumbo_size
;
5262 bp
->rx_max_pg_ring
= bnx2_find_max_ring(jumbo_size
,
5264 bp
->rx_max_pg_ring_idx
= (bp
->rx_max_pg_ring
* RX_DESC_CNT
) - 1;
5265 rx_size
= BNX2_RX_COPY_THRESH
+ BNX2_RX_OFFSET
;
5266 bp
->rx_copy_thresh
= 0;
5269 bp
->rx_buf_use_size
= rx_size
;
5271 bp
->rx_buf_size
= bp
->rx_buf_use_size
+ BNX2_RX_ALIGN
;
5272 bp
->rx_jumbo_thresh
= rx_size
- BNX2_RX_OFFSET
;
5273 bp
->rx_ring_size
= size
;
5274 bp
->rx_max_ring
= bnx2_find_max_ring(size
, MAX_RX_RINGS
);
5275 bp
->rx_max_ring_idx
= (bp
->rx_max_ring
* RX_DESC_CNT
) - 1;
5279 bnx2_free_tx_skbs(struct bnx2
*bp
)
5283 for (i
= 0; i
< bp
->num_tx_rings
; i
++) {
5284 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[i
];
5285 struct bnx2_tx_ring_info
*txr
= &bnapi
->tx_ring
;
5288 if (txr
->tx_buf_ring
== NULL
)
5291 for (j
= 0; j
< TX_DESC_CNT
; ) {
5292 struct sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
5293 struct sk_buff
*skb
= tx_buf
->skb
;
5300 skb_dma_unmap(&bp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
5304 j
+= skb_shinfo(skb
)->nr_frags
+ 1;
5311 bnx2_free_rx_skbs(struct bnx2
*bp
)
5315 for (i
= 0; i
< bp
->num_rx_rings
; i
++) {
5316 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[i
];
5317 struct bnx2_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
5320 if (rxr
->rx_buf_ring
== NULL
)
5323 for (j
= 0; j
< bp
->rx_max_ring_idx
; j
++) {
5324 struct sw_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
5325 struct sk_buff
*skb
= rx_buf
->skb
;
5330 pci_unmap_single(bp
->pdev
,
5331 pci_unmap_addr(rx_buf
, mapping
),
5332 bp
->rx_buf_use_size
,
5333 PCI_DMA_FROMDEVICE
);
5339 for (j
= 0; j
< bp
->rx_max_pg_ring_idx
; j
++)
5340 bnx2_free_rx_page(bp
, rxr
, j
);
5345 bnx2_free_skbs(struct bnx2
*bp
)
5347 bnx2_free_tx_skbs(bp
);
5348 bnx2_free_rx_skbs(bp
);
5352 bnx2_reset_nic(struct bnx2
*bp
, u32 reset_code
)
5356 rc
= bnx2_reset_chip(bp
, reset_code
);
5361 if ((rc
= bnx2_init_chip(bp
)) != 0)
5364 bnx2_init_all_rings(bp
);
5369 bnx2_init_nic(struct bnx2
*bp
, int reset_phy
)
5373 if ((rc
= bnx2_reset_nic(bp
, BNX2_DRV_MSG_CODE_RESET
)) != 0)
5376 spin_lock_bh(&bp
->phy_lock
);
5377 bnx2_init_phy(bp
, reset_phy
);
5379 if (bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
)
5380 bnx2_remote_phy_event(bp
);
5381 spin_unlock_bh(&bp
->phy_lock
);
5386 bnx2_shutdown_chip(struct bnx2
*bp
)
5390 if (bp
->flags
& BNX2_FLAG_NO_WOL
)
5391 reset_code
= BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN
;
5393 reset_code
= BNX2_DRV_MSG_CODE_SUSPEND_WOL
;
5395 reset_code
= BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL
;
5397 return bnx2_reset_chip(bp
, reset_code
);
5401 bnx2_test_registers(struct bnx2
*bp
)
5405 static const struct {
5408 #define BNX2_FL_NOT_5709 1
5412 { 0x006c, 0, 0x00000000, 0x0000003f },
5413 { 0x0090, 0, 0xffffffff, 0x00000000 },
5414 { 0x0094, 0, 0x00000000, 0x00000000 },
5416 { 0x0404, BNX2_FL_NOT_5709
, 0x00003f00, 0x00000000 },
5417 { 0x0418, BNX2_FL_NOT_5709
, 0x00000000, 0xffffffff },
5418 { 0x041c, BNX2_FL_NOT_5709
, 0x00000000, 0xffffffff },
5419 { 0x0420, BNX2_FL_NOT_5709
, 0x00000000, 0x80ffffff },
5420 { 0x0424, BNX2_FL_NOT_5709
, 0x00000000, 0x00000000 },
5421 { 0x0428, BNX2_FL_NOT_5709
, 0x00000000, 0x00000001 },
5422 { 0x0450, BNX2_FL_NOT_5709
, 0x00000000, 0x0000ffff },
5423 { 0x0454, BNX2_FL_NOT_5709
, 0x00000000, 0xffffffff },
5424 { 0x0458, BNX2_FL_NOT_5709
, 0x00000000, 0xffffffff },
5426 { 0x0808, BNX2_FL_NOT_5709
, 0x00000000, 0xffffffff },
5427 { 0x0854, BNX2_FL_NOT_5709
, 0x00000000, 0xffffffff },
5428 { 0x0868, BNX2_FL_NOT_5709
, 0x00000000, 0x77777777 },
5429 { 0x086c, BNX2_FL_NOT_5709
, 0x00000000, 0x77777777 },
5430 { 0x0870, BNX2_FL_NOT_5709
, 0x00000000, 0x77777777 },
5431 { 0x0874, BNX2_FL_NOT_5709
, 0x00000000, 0x77777777 },
5433 { 0x0c00, BNX2_FL_NOT_5709
, 0x00000000, 0x00000001 },
5434 { 0x0c04, BNX2_FL_NOT_5709
, 0x00000000, 0x03ff0001 },
5435 { 0x0c08, BNX2_FL_NOT_5709
, 0x0f0ff073, 0x00000000 },
5437 { 0x1000, 0, 0x00000000, 0x00000001 },
5438 { 0x1004, BNX2_FL_NOT_5709
, 0x00000000, 0x000f0001 },
5440 { 0x1408, 0, 0x01c00800, 0x00000000 },
5441 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5442 { 0x14a8, 0, 0x00000000, 0x000001ff },
5443 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5444 { 0x14b0, 0, 0x00000002, 0x00000001 },
5445 { 0x14b8, 0, 0x00000000, 0x00000000 },
5446 { 0x14c0, 0, 0x00000000, 0x00000009 },
5447 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5448 { 0x14cc, 0, 0x00000000, 0x00000001 },
5449 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5451 { 0x1800, 0, 0x00000000, 0x00000001 },
5452 { 0x1804, 0, 0x00000000, 0x00000003 },
5454 { 0x2800, 0, 0x00000000, 0x00000001 },
5455 { 0x2804, 0, 0x00000000, 0x00003f01 },
5456 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5457 { 0x2810, 0, 0xffff0000, 0x00000000 },
5458 { 0x2814, 0, 0xffff0000, 0x00000000 },
5459 { 0x2818, 0, 0xffff0000, 0x00000000 },
5460 { 0x281c, 0, 0xffff0000, 0x00000000 },
5461 { 0x2834, 0, 0xffffffff, 0x00000000 },
5462 { 0x2840, 0, 0x00000000, 0xffffffff },
5463 { 0x2844, 0, 0x00000000, 0xffffffff },
5464 { 0x2848, 0, 0xffffffff, 0x00000000 },
5465 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5467 { 0x2c00, 0, 0x00000000, 0x00000011 },
5468 { 0x2c04, 0, 0x00000000, 0x00030007 },
5470 { 0x3c00, 0, 0x00000000, 0x00000001 },
5471 { 0x3c04, 0, 0x00000000, 0x00070000 },
5472 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5473 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5474 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5475 { 0x3c14, 0, 0x00000000, 0xffffffff },
5476 { 0x3c18, 0, 0x00000000, 0xffffffff },
5477 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5478 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5480 { 0x5004, 0, 0x00000000, 0x0000007f },
5481 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5483 { 0x5c00, 0, 0x00000000, 0x00000001 },
5484 { 0x5c04, 0, 0x00000000, 0x0003000f },
5485 { 0x5c08, 0, 0x00000003, 0x00000000 },
5486 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5487 { 0x5c10, 0, 0x00000000, 0xffffffff },
5488 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5489 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5490 { 0x5c88, 0, 0x00000000, 0x00077373 },
5491 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5493 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5494 { 0x680c, 0, 0xffffffff, 0x00000000 },
5495 { 0x6810, 0, 0xffffffff, 0x00000000 },
5496 { 0x6814, 0, 0xffffffff, 0x00000000 },
5497 { 0x6818, 0, 0xffffffff, 0x00000000 },
5498 { 0x681c, 0, 0xffffffff, 0x00000000 },
5499 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5500 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5501 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5502 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5503 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5504 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5505 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5506 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5507 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5508 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5509 { 0x684c, 0, 0xffffffff, 0x00000000 },
5510 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5511 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5512 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5513 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5514 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5515 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5517 { 0xffff, 0, 0x00000000, 0x00000000 },
5522 if (CHIP_NUM(bp
) == CHIP_NUM_5709
)
5525 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
5526 u32 offset
, rw_mask
, ro_mask
, save_val
, val
;
5527 u16 flags
= reg_tbl
[i
].flags
;
5529 if (is_5709
&& (flags
& BNX2_FL_NOT_5709
))
5532 offset
= (u32
) reg_tbl
[i
].offset
;
5533 rw_mask
= reg_tbl
[i
].rw_mask
;
5534 ro_mask
= reg_tbl
[i
].ro_mask
;
5536 save_val
= readl(bp
->regview
+ offset
);
5538 writel(0, bp
->regview
+ offset
);
5540 val
= readl(bp
->regview
+ offset
);
5541 if ((val
& rw_mask
) != 0) {
5545 if ((val
& ro_mask
) != (save_val
& ro_mask
)) {
5549 writel(0xffffffff, bp
->regview
+ offset
);
5551 val
= readl(bp
->regview
+ offset
);
5552 if ((val
& rw_mask
) != rw_mask
) {
5556 if ((val
& ro_mask
) != (save_val
& ro_mask
)) {
5560 writel(save_val
, bp
->regview
+ offset
);
5564 writel(save_val
, bp
->regview
+ offset
);
5572 bnx2_do_mem_test(struct bnx2
*bp
, u32 start
, u32 size
)
5574 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0x55555555,
5575 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5578 for (i
= 0; i
< sizeof(test_pattern
) / 4; i
++) {
5581 for (offset
= 0; offset
< size
; offset
+= 4) {
5583 bnx2_reg_wr_ind(bp
, start
+ offset
, test_pattern
[i
]);
5585 if (bnx2_reg_rd_ind(bp
, start
+ offset
) !=
5595 bnx2_test_memory(struct bnx2
*bp
)
5599 static struct mem_entry
{
5602 } mem_tbl_5706
[] = {
5603 { 0x60000, 0x4000 },
5604 { 0xa0000, 0x3000 },
5605 { 0xe0000, 0x4000 },
5606 { 0x120000, 0x4000 },
5607 { 0x1a0000, 0x4000 },
5608 { 0x160000, 0x4000 },
5612 { 0x60000, 0x4000 },
5613 { 0xa0000, 0x3000 },
5614 { 0xe0000, 0x4000 },
5615 { 0x120000, 0x4000 },
5616 { 0x1a0000, 0x4000 },
5619 struct mem_entry
*mem_tbl
;
5621 if (CHIP_NUM(bp
) == CHIP_NUM_5709
)
5622 mem_tbl
= mem_tbl_5709
;
5624 mem_tbl
= mem_tbl_5706
;
5626 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
5627 if ((ret
= bnx2_do_mem_test(bp
, mem_tbl
[i
].offset
,
5628 mem_tbl
[i
].len
)) != 0) {
5636 #define BNX2_MAC_LOOPBACK 0
5637 #define BNX2_PHY_LOOPBACK 1
5640 bnx2_run_loopback(struct bnx2
*bp
, int loopback_mode
)
5642 unsigned int pkt_size
, num_pkts
, i
;
5643 struct sk_buff
*skb
, *rx_skb
;
5644 unsigned char *packet
;
5645 u16 rx_start_idx
, rx_idx
;
5648 struct sw_bd
*rx_buf
;
5649 struct l2_fhdr
*rx_hdr
;
5651 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[0], *tx_napi
;
5652 struct bnx2_tx_ring_info
*txr
= &bnapi
->tx_ring
;
5653 struct bnx2_rx_ring_info
*rxr
= &bnapi
->rx_ring
;
5657 txr
= &tx_napi
->tx_ring
;
5658 rxr
= &bnapi
->rx_ring
;
5659 if (loopback_mode
== BNX2_MAC_LOOPBACK
) {
5660 bp
->loopback
= MAC_LOOPBACK
;
5661 bnx2_set_mac_loopback(bp
);
5663 else if (loopback_mode
== BNX2_PHY_LOOPBACK
) {
5664 if (bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
)
5667 bp
->loopback
= PHY_LOOPBACK
;
5668 bnx2_set_phy_loopback(bp
);
5673 pkt_size
= min(bp
->dev
->mtu
+ ETH_HLEN
, bp
->rx_jumbo_thresh
- 4);
5674 skb
= netdev_alloc_skb(bp
->dev
, pkt_size
);
5677 packet
= skb_put(skb
, pkt_size
);
5678 memcpy(packet
, bp
->dev
->dev_addr
, 6);
5679 memset(packet
+ 6, 0x0, 8);
5680 for (i
= 14; i
< pkt_size
; i
++)
5681 packet
[i
] = (unsigned char) (i
& 0xff);
5683 if (skb_dma_map(&bp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
5687 map
= skb_shinfo(skb
)->dma_head
;
5689 REG_WR(bp
, BNX2_HC_COMMAND
,
5690 bp
->hc_cmd
| BNX2_HC_COMMAND_COAL_NOW_WO_INT
);
5692 REG_RD(bp
, BNX2_HC_COMMAND
);
5695 rx_start_idx
= bnx2_get_hw_rx_cons(bnapi
);
5699 txbd
= &txr
->tx_desc_ring
[TX_RING_IDX(txr
->tx_prod
)];
5701 txbd
->tx_bd_haddr_hi
= (u64
) map
>> 32;
5702 txbd
->tx_bd_haddr_lo
= (u64
) map
& 0xffffffff;
5703 txbd
->tx_bd_mss_nbytes
= pkt_size
;
5704 txbd
->tx_bd_vlan_tag_flags
= TX_BD_FLAGS_START
| TX_BD_FLAGS_END
;
5707 txr
->tx_prod
= NEXT_TX_BD(txr
->tx_prod
);
5708 txr
->tx_prod_bseq
+= pkt_size
;
5710 REG_WR16(bp
, txr
->tx_bidx_addr
, txr
->tx_prod
);
5711 REG_WR(bp
, txr
->tx_bseq_addr
, txr
->tx_prod_bseq
);
5715 REG_WR(bp
, BNX2_HC_COMMAND
,
5716 bp
->hc_cmd
| BNX2_HC_COMMAND_COAL_NOW_WO_INT
);
5718 REG_RD(bp
, BNX2_HC_COMMAND
);
5722 skb_dma_unmap(&bp
->pdev
->dev
, skb
, DMA_TO_DEVICE
);
5725 if (bnx2_get_hw_tx_cons(tx_napi
) != txr
->tx_prod
)
5726 goto loopback_test_done
;
5728 rx_idx
= bnx2_get_hw_rx_cons(bnapi
);
5729 if (rx_idx
!= rx_start_idx
+ num_pkts
) {
5730 goto loopback_test_done
;
5733 rx_buf
= &rxr
->rx_buf_ring
[rx_start_idx
];
5734 rx_skb
= rx_buf
->skb
;
5736 rx_hdr
= (struct l2_fhdr
*) rx_skb
->data
;
5737 skb_reserve(rx_skb
, BNX2_RX_OFFSET
);
5739 pci_dma_sync_single_for_cpu(bp
->pdev
,
5740 pci_unmap_addr(rx_buf
, mapping
),
5741 bp
->rx_buf_size
, PCI_DMA_FROMDEVICE
);
5743 if (rx_hdr
->l2_fhdr_status
&
5744 (L2_FHDR_ERRORS_BAD_CRC
|
5745 L2_FHDR_ERRORS_PHY_DECODE
|
5746 L2_FHDR_ERRORS_ALIGNMENT
|
5747 L2_FHDR_ERRORS_TOO_SHORT
|
5748 L2_FHDR_ERRORS_GIANT_FRAME
)) {
5750 goto loopback_test_done
;
5753 if ((rx_hdr
->l2_fhdr_pkt_len
- 4) != pkt_size
) {
5754 goto loopback_test_done
;
5757 for (i
= 14; i
< pkt_size
; i
++) {
5758 if (*(rx_skb
->data
+ i
) != (unsigned char) (i
& 0xff)) {
5759 goto loopback_test_done
;
5770 #define BNX2_MAC_LOOPBACK_FAILED 1
5771 #define BNX2_PHY_LOOPBACK_FAILED 2
5772 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5773 BNX2_PHY_LOOPBACK_FAILED)
5776 bnx2_test_loopback(struct bnx2
*bp
)
5780 if (!netif_running(bp
->dev
))
5781 return BNX2_LOOPBACK_FAILED
;
5783 bnx2_reset_nic(bp
, BNX2_DRV_MSG_CODE_RESET
);
5784 spin_lock_bh(&bp
->phy_lock
);
5785 bnx2_init_phy(bp
, 1);
5786 spin_unlock_bh(&bp
->phy_lock
);
5787 if (bnx2_run_loopback(bp
, BNX2_MAC_LOOPBACK
))
5788 rc
|= BNX2_MAC_LOOPBACK_FAILED
;
5789 if (bnx2_run_loopback(bp
, BNX2_PHY_LOOPBACK
))
5790 rc
|= BNX2_PHY_LOOPBACK_FAILED
;
5794 #define NVRAM_SIZE 0x200
5795 #define CRC32_RESIDUAL 0xdebb20e3
5798 bnx2_test_nvram(struct bnx2
*bp
)
5800 __be32 buf
[NVRAM_SIZE
/ 4];
5801 u8
*data
= (u8
*) buf
;
5805 if ((rc
= bnx2_nvram_read(bp
, 0, data
, 4)) != 0)
5806 goto test_nvram_done
;
5808 magic
= be32_to_cpu(buf
[0]);
5809 if (magic
!= 0x669955aa) {
5811 goto test_nvram_done
;
5814 if ((rc
= bnx2_nvram_read(bp
, 0x100, data
, NVRAM_SIZE
)) != 0)
5815 goto test_nvram_done
;
5817 csum
= ether_crc_le(0x100, data
);
5818 if (csum
!= CRC32_RESIDUAL
) {
5820 goto test_nvram_done
;
5823 csum
= ether_crc_le(0x100, data
+ 0x100);
5824 if (csum
!= CRC32_RESIDUAL
) {
5833 bnx2_test_link(struct bnx2
*bp
)
5837 if (!netif_running(bp
->dev
))
5840 if (bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
) {
5845 spin_lock_bh(&bp
->phy_lock
);
5846 bnx2_enable_bmsr1(bp
);
5847 bnx2_read_phy(bp
, bp
->mii_bmsr1
, &bmsr
);
5848 bnx2_read_phy(bp
, bp
->mii_bmsr1
, &bmsr
);
5849 bnx2_disable_bmsr1(bp
);
5850 spin_unlock_bh(&bp
->phy_lock
);
5852 if (bmsr
& BMSR_LSTATUS
) {
5859 bnx2_test_intr(struct bnx2
*bp
)
5864 if (!netif_running(bp
->dev
))
5867 status_idx
= REG_RD(bp
, BNX2_PCICFG_INT_ACK_CMD
) & 0xffff;
5869 /* This register is not touched during run-time. */
5870 REG_WR(bp
, BNX2_HC_COMMAND
, bp
->hc_cmd
| BNX2_HC_COMMAND_COAL_NOW
);
5871 REG_RD(bp
, BNX2_HC_COMMAND
);
5873 for (i
= 0; i
< 10; i
++) {
5874 if ((REG_RD(bp
, BNX2_PCICFG_INT_ACK_CMD
) & 0xffff) !=
5880 msleep_interruptible(10);
5888 /* Determining link for parallel detection. */
5890 bnx2_5706_serdes_has_link(struct bnx2
*bp
)
5892 u32 mode_ctl
, an_dbg
, exp
;
5894 if (bp
->phy_flags
& BNX2_PHY_FLAG_NO_PARALLEL
)
5897 bnx2_write_phy(bp
, MII_BNX2_MISC_SHADOW
, MISC_SHDW_MODE_CTL
);
5898 bnx2_read_phy(bp
, MII_BNX2_MISC_SHADOW
, &mode_ctl
);
5900 if (!(mode_ctl
& MISC_SHDW_MODE_CTL_SIG_DET
))
5903 bnx2_write_phy(bp
, MII_BNX2_MISC_SHADOW
, MISC_SHDW_AN_DBG
);
5904 bnx2_read_phy(bp
, MII_BNX2_MISC_SHADOW
, &an_dbg
);
5905 bnx2_read_phy(bp
, MII_BNX2_MISC_SHADOW
, &an_dbg
);
5907 if (an_dbg
& (MISC_SHDW_AN_DBG_NOSYNC
| MISC_SHDW_AN_DBG_RUDI_INVALID
))
5910 bnx2_write_phy(bp
, MII_BNX2_DSP_ADDRESS
, MII_EXPAND_REG1
);
5911 bnx2_read_phy(bp
, MII_BNX2_DSP_RW_PORT
, &exp
);
5912 bnx2_read_phy(bp
, MII_BNX2_DSP_RW_PORT
, &exp
);
5914 if (exp
& MII_EXPAND_REG1_RUDI_C
) /* receiving CONFIG */
5921 bnx2_5706_serdes_timer(struct bnx2
*bp
)
5925 spin_lock(&bp
->phy_lock
);
5926 if (bp
->serdes_an_pending
) {
5927 bp
->serdes_an_pending
--;
5929 } else if ((bp
->link_up
== 0) && (bp
->autoneg
& AUTONEG_SPEED
)) {
5932 bp
->current_interval
= BNX2_TIMER_INTERVAL
;
5934 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
5936 if (bmcr
& BMCR_ANENABLE
) {
5937 if (bnx2_5706_serdes_has_link(bp
)) {
5938 bmcr
&= ~BMCR_ANENABLE
;
5939 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
5940 bnx2_write_phy(bp
, bp
->mii_bmcr
, bmcr
);
5941 bp
->phy_flags
|= BNX2_PHY_FLAG_PARALLEL_DETECT
;
5945 else if ((bp
->link_up
) && (bp
->autoneg
& AUTONEG_SPEED
) &&
5946 (bp
->phy_flags
& BNX2_PHY_FLAG_PARALLEL_DETECT
)) {
5949 bnx2_write_phy(bp
, 0x17, 0x0f01);
5950 bnx2_read_phy(bp
, 0x15, &phy2
);
5954 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
5955 bmcr
|= BMCR_ANENABLE
;
5956 bnx2_write_phy(bp
, bp
->mii_bmcr
, bmcr
);
5958 bp
->phy_flags
&= ~BNX2_PHY_FLAG_PARALLEL_DETECT
;
5961 bp
->current_interval
= BNX2_TIMER_INTERVAL
;
5966 bnx2_write_phy(bp
, MII_BNX2_MISC_SHADOW
, MISC_SHDW_AN_DBG
);
5967 bnx2_read_phy(bp
, MII_BNX2_MISC_SHADOW
, &val
);
5968 bnx2_read_phy(bp
, MII_BNX2_MISC_SHADOW
, &val
);
5970 if (bp
->link_up
&& (val
& MISC_SHDW_AN_DBG_NOSYNC
)) {
5971 if (!(bp
->phy_flags
& BNX2_PHY_FLAG_FORCED_DOWN
)) {
5972 bnx2_5706s_force_link_dn(bp
, 1);
5973 bp
->phy_flags
|= BNX2_PHY_FLAG_FORCED_DOWN
;
5976 } else if (!bp
->link_up
&& !(val
& MISC_SHDW_AN_DBG_NOSYNC
))
5979 spin_unlock(&bp
->phy_lock
);
5983 bnx2_5708_serdes_timer(struct bnx2
*bp
)
5985 if (bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
)
5988 if ((bp
->phy_flags
& BNX2_PHY_FLAG_2_5G_CAPABLE
) == 0) {
5989 bp
->serdes_an_pending
= 0;
5993 spin_lock(&bp
->phy_lock
);
5994 if (bp
->serdes_an_pending
)
5995 bp
->serdes_an_pending
--;
5996 else if ((bp
->link_up
== 0) && (bp
->autoneg
& AUTONEG_SPEED
)) {
5999 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
6000 if (bmcr
& BMCR_ANENABLE
) {
6001 bnx2_enable_forced_2g5(bp
);
6002 bp
->current_interval
= BNX2_SERDES_FORCED_TIMEOUT
;
6004 bnx2_disable_forced_2g5(bp
);
6005 bp
->serdes_an_pending
= 2;
6006 bp
->current_interval
= BNX2_TIMER_INTERVAL
;
6010 bp
->current_interval
= BNX2_TIMER_INTERVAL
;
6012 spin_unlock(&bp
->phy_lock
);
6016 bnx2_timer(unsigned long data
)
6018 struct bnx2
*bp
= (struct bnx2
*) data
;
6020 if (!netif_running(bp
->dev
))
6023 if (atomic_read(&bp
->intr_sem
) != 0)
6024 goto bnx2_restart_timer
;
6026 if ((bp
->flags
& (BNX2_FLAG_USING_MSI
| BNX2_FLAG_ONE_SHOT_MSI
)) ==
6027 BNX2_FLAG_USING_MSI
)
6028 bnx2_chk_missed_msi(bp
);
6030 bnx2_send_heart_beat(bp
);
6032 bp
->stats_blk
->stat_FwRxDrop
=
6033 bnx2_reg_rd_ind(bp
, BNX2_FW_RX_DROP_COUNT
);
6035 /* workaround occasional corrupted counters */
6036 if ((bp
->flags
& BNX2_FLAG_BROKEN_STATS
) && bp
->stats_ticks
)
6037 REG_WR(bp
, BNX2_HC_COMMAND
, bp
->hc_cmd
|
6038 BNX2_HC_COMMAND_STATS_NOW
);
6040 if (bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) {
6041 if (CHIP_NUM(bp
) == CHIP_NUM_5706
)
6042 bnx2_5706_serdes_timer(bp
);
6044 bnx2_5708_serdes_timer(bp
);
6048 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
6052 bnx2_request_irq(struct bnx2
*bp
)
6054 unsigned long flags
;
6055 struct bnx2_irq
*irq
;
6058 if (bp
->flags
& BNX2_FLAG_USING_MSI_OR_MSIX
)
6061 flags
= IRQF_SHARED
;
6063 for (i
= 0; i
< bp
->irq_nvecs
; i
++) {
6064 irq
= &bp
->irq_tbl
[i
];
6065 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
6075 bnx2_free_irq(struct bnx2
*bp
)
6077 struct bnx2_irq
*irq
;
6080 for (i
= 0; i
< bp
->irq_nvecs
; i
++) {
6081 irq
= &bp
->irq_tbl
[i
];
6083 free_irq(irq
->vector
, &bp
->bnx2_napi
[i
]);
6086 if (bp
->flags
& BNX2_FLAG_USING_MSI
)
6087 pci_disable_msi(bp
->pdev
);
6088 else if (bp
->flags
& BNX2_FLAG_USING_MSIX
)
6089 pci_disable_msix(bp
->pdev
);
6091 bp
->flags
&= ~(BNX2_FLAG_USING_MSI_OR_MSIX
| BNX2_FLAG_ONE_SHOT_MSI
);
6095 bnx2_enable_msix(struct bnx2
*bp
, int msix_vecs
)
6098 struct msix_entry msix_ent
[BNX2_MAX_MSIX_VEC
];
6099 struct net_device
*dev
= bp
->dev
;
6100 const int len
= sizeof(bp
->irq_tbl
[0].name
);
6102 bnx2_setup_msix_tbl(bp
);
6103 REG_WR(bp
, BNX2_PCI_MSIX_CONTROL
, BNX2_MAX_MSIX_HW_VEC
- 1);
6104 REG_WR(bp
, BNX2_PCI_MSIX_TBL_OFF_BIR
, BNX2_PCI_GRC_WINDOW2_BASE
);
6105 REG_WR(bp
, BNX2_PCI_MSIX_PBA_OFF_BIT
, BNX2_PCI_GRC_WINDOW3_BASE
);
6107 for (i
= 0; i
< BNX2_MAX_MSIX_VEC
; i
++) {
6108 msix_ent
[i
].entry
= i
;
6109 msix_ent
[i
].vector
= 0;
6112 rc
= pci_enable_msix(bp
->pdev
, msix_ent
, BNX2_MAX_MSIX_VEC
);
6116 bp
->irq_nvecs
= msix_vecs
;
6117 bp
->flags
|= BNX2_FLAG_USING_MSIX
| BNX2_FLAG_ONE_SHOT_MSI
;
6118 for (i
= 0; i
< BNX2_MAX_MSIX_VEC
; i
++) {
6119 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
6120 snprintf(bp
->irq_tbl
[i
].name
, len
, "%s-%d", dev
->name
, i
);
6121 bp
->irq_tbl
[i
].handler
= bnx2_msi_1shot
;
6126 bnx2_setup_int_mode(struct bnx2
*bp
, int dis_msi
)
6128 int cpus
= num_online_cpus();
6129 int msix_vecs
= min(cpus
+ 1, RX_MAX_RINGS
);
6131 bp
->irq_tbl
[0].handler
= bnx2_interrupt
;
6132 strcpy(bp
->irq_tbl
[0].name
, bp
->dev
->name
);
6134 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
6136 if ((bp
->flags
& BNX2_FLAG_MSIX_CAP
) && !dis_msi
&& cpus
> 1)
6137 bnx2_enable_msix(bp
, msix_vecs
);
6139 if ((bp
->flags
& BNX2_FLAG_MSI_CAP
) && !dis_msi
&&
6140 !(bp
->flags
& BNX2_FLAG_USING_MSIX
)) {
6141 if (pci_enable_msi(bp
->pdev
) == 0) {
6142 bp
->flags
|= BNX2_FLAG_USING_MSI
;
6143 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
6144 bp
->flags
|= BNX2_FLAG_ONE_SHOT_MSI
;
6145 bp
->irq_tbl
[0].handler
= bnx2_msi_1shot
;
6147 bp
->irq_tbl
[0].handler
= bnx2_msi
;
6149 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
6153 bp
->num_tx_rings
= rounddown_pow_of_two(bp
->irq_nvecs
);
6154 bp
->dev
->real_num_tx_queues
= bp
->num_tx_rings
;
6156 bp
->num_rx_rings
= bp
->irq_nvecs
;
6159 /* Called with rtnl_lock */
6161 bnx2_open(struct net_device
*dev
)
6163 struct bnx2
*bp
= netdev_priv(dev
);
6166 netif_carrier_off(dev
);
6168 bnx2_set_power_state(bp
, PCI_D0
);
6169 bnx2_disable_int(bp
);
6171 bnx2_setup_int_mode(bp
, disable_msi
);
6172 bnx2_napi_enable(bp
);
6173 rc
= bnx2_alloc_mem(bp
);
6177 rc
= bnx2_request_irq(bp
);
6181 rc
= bnx2_init_nic(bp
, 1);
6185 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
6187 atomic_set(&bp
->intr_sem
, 0);
6189 bnx2_enable_int(bp
);
6191 if (bp
->flags
& BNX2_FLAG_USING_MSI
) {
6192 /* Test MSI to make sure it is working
6193 * If MSI test fails, go back to INTx mode
6195 if (bnx2_test_intr(bp
) != 0) {
6196 printk(KERN_WARNING PFX
"%s: No interrupt was generated"
6197 " using MSI, switching to INTx mode. Please"
6198 " report this failure to the PCI maintainer"
6199 " and include system chipset information.\n",
6202 bnx2_disable_int(bp
);
6205 bnx2_setup_int_mode(bp
, 1);
6207 rc
= bnx2_init_nic(bp
, 0);
6210 rc
= bnx2_request_irq(bp
);
6213 del_timer_sync(&bp
->timer
);
6216 bnx2_enable_int(bp
);
6219 if (bp
->flags
& BNX2_FLAG_USING_MSI
)
6220 printk(KERN_INFO PFX
"%s: using MSI\n", dev
->name
);
6221 else if (bp
->flags
& BNX2_FLAG_USING_MSIX
)
6222 printk(KERN_INFO PFX
"%s: using MSIX\n", dev
->name
);
6224 netif_tx_start_all_queues(dev
);
6229 bnx2_napi_disable(bp
);
6237 bnx2_reset_task(struct work_struct
*work
)
6239 struct bnx2
*bp
= container_of(work
, struct bnx2
, reset_task
);
6241 if (!netif_running(bp
->dev
))
6244 bnx2_netif_stop(bp
);
6246 bnx2_init_nic(bp
, 1);
6248 atomic_set(&bp
->intr_sem
, 1);
6249 bnx2_netif_start(bp
);
6253 bnx2_tx_timeout(struct net_device
*dev
)
6255 struct bnx2
*bp
= netdev_priv(dev
);
6257 /* This allows the netif to be shutdown gracefully before resetting */
6258 schedule_work(&bp
->reset_task
);
6262 /* Called with rtnl_lock */
6264 bnx2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*vlgrp
)
6266 struct bnx2
*bp
= netdev_priv(dev
);
6268 if (netif_running(dev
))
6269 bnx2_netif_stop(bp
);
6273 if (!netif_running(dev
))
6276 bnx2_set_rx_mode(dev
);
6277 if (bp
->flags
& BNX2_FLAG_CAN_KEEP_VLAN
)
6278 bnx2_fw_sync(bp
, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE
, 0, 1);
6280 bnx2_netif_start(bp
);
6284 /* Called with netif_tx_lock.
6285 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6286 * netif_wake_queue().
6289 bnx2_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
6291 struct bnx2
*bp
= netdev_priv(dev
);
6294 struct sw_tx_bd
*tx_buf
;
6295 u32 len
, vlan_tag_flags
, last_frag
, mss
;
6296 u16 prod
, ring_prod
;
6298 struct bnx2_napi
*bnapi
;
6299 struct bnx2_tx_ring_info
*txr
;
6300 struct netdev_queue
*txq
;
6301 struct skb_shared_info
*sp
;
6303 /* Determine which tx ring we will be placed on */
6304 i
= skb_get_queue_mapping(skb
);
6305 bnapi
= &bp
->bnx2_napi
[i
];
6306 txr
= &bnapi
->tx_ring
;
6307 txq
= netdev_get_tx_queue(dev
, i
);
6309 if (unlikely(bnx2_tx_avail(bp
, txr
) <
6310 (skb_shinfo(skb
)->nr_frags
+ 1))) {
6311 netif_tx_stop_queue(txq
);
6312 printk(KERN_ERR PFX
"%s: BUG! Tx ring full when queue awake!\n",
6315 return NETDEV_TX_BUSY
;
6317 len
= skb_headlen(skb
);
6318 prod
= txr
->tx_prod
;
6319 ring_prod
= TX_RING_IDX(prod
);
6322 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6323 vlan_tag_flags
|= TX_BD_FLAGS_TCP_UDP_CKSUM
;
6327 if (bp
->vlgrp
&& vlan_tx_tag_present(skb
)) {
6329 (TX_BD_FLAGS_VLAN_TAG
| (vlan_tx_tag_get(skb
) << 16));
6332 if ((mss
= skb_shinfo(skb
)->gso_size
)) {
6336 vlan_tag_flags
|= TX_BD_FLAGS_SW_LSO
;
6338 tcp_opt_len
= tcp_optlen(skb
);
6340 if (skb_shinfo(skb
)->gso_type
& SKB_GSO_TCPV6
) {
6341 u32 tcp_off
= skb_transport_offset(skb
) -
6342 sizeof(struct ipv6hdr
) - ETH_HLEN
;
6344 vlan_tag_flags
|= ((tcp_opt_len
>> 2) << 8) |
6345 TX_BD_FLAGS_SW_FLAGS
;
6346 if (likely(tcp_off
== 0))
6347 vlan_tag_flags
&= ~TX_BD_FLAGS_TCP6_OFF0_MSK
;
6350 vlan_tag_flags
|= ((tcp_off
& 0x3) <<
6351 TX_BD_FLAGS_TCP6_OFF0_SHL
) |
6352 ((tcp_off
& 0x10) <<
6353 TX_BD_FLAGS_TCP6_OFF4_SHL
);
6354 mss
|= (tcp_off
& 0xc) << TX_BD_TCP6_OFF2_SHL
;
6358 if (tcp_opt_len
|| (iph
->ihl
> 5)) {
6359 vlan_tag_flags
|= ((iph
->ihl
- 5) +
6360 (tcp_opt_len
>> 2)) << 8;
6366 if (skb_dma_map(&bp
->pdev
->dev
, skb
, DMA_TO_DEVICE
)) {
6368 return NETDEV_TX_OK
;
6371 sp
= skb_shinfo(skb
);
6372 mapping
= sp
->dma_head
;
6374 tx_buf
= &txr
->tx_buf_ring
[ring_prod
];
6377 txbd
= &txr
->tx_desc_ring
[ring_prod
];
6379 txbd
->tx_bd_haddr_hi
= (u64
) mapping
>> 32;
6380 txbd
->tx_bd_haddr_lo
= (u64
) mapping
& 0xffffffff;
6381 txbd
->tx_bd_mss_nbytes
= len
| (mss
<< 16);
6382 txbd
->tx_bd_vlan_tag_flags
= vlan_tag_flags
| TX_BD_FLAGS_START
;
6384 last_frag
= skb_shinfo(skb
)->nr_frags
;
6385 tx_buf
->nr_frags
= last_frag
;
6386 tx_buf
->is_gso
= skb_is_gso(skb
);
6388 for (i
= 0; i
< last_frag
; i
++) {
6389 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6391 prod
= NEXT_TX_BD(prod
);
6392 ring_prod
= TX_RING_IDX(prod
);
6393 txbd
= &txr
->tx_desc_ring
[ring_prod
];
6396 mapping
= sp
->dma_maps
[i
];
6398 txbd
->tx_bd_haddr_hi
= (u64
) mapping
>> 32;
6399 txbd
->tx_bd_haddr_lo
= (u64
) mapping
& 0xffffffff;
6400 txbd
->tx_bd_mss_nbytes
= len
| (mss
<< 16);
6401 txbd
->tx_bd_vlan_tag_flags
= vlan_tag_flags
;
6404 txbd
->tx_bd_vlan_tag_flags
|= TX_BD_FLAGS_END
;
6406 prod
= NEXT_TX_BD(prod
);
6407 txr
->tx_prod_bseq
+= skb
->len
;
6409 REG_WR16(bp
, txr
->tx_bidx_addr
, prod
);
6410 REG_WR(bp
, txr
->tx_bseq_addr
, txr
->tx_prod_bseq
);
6414 txr
->tx_prod
= prod
;
6416 if (unlikely(bnx2_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
)) {
6417 netif_tx_stop_queue(txq
);
6418 if (bnx2_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
6419 netif_tx_wake_queue(txq
);
6422 return NETDEV_TX_OK
;
6425 /* Called with rtnl_lock */
6427 bnx2_close(struct net_device
*dev
)
6429 struct bnx2
*bp
= netdev_priv(dev
);
6431 cancel_work_sync(&bp
->reset_task
);
6433 bnx2_disable_int_sync(bp
);
6434 bnx2_napi_disable(bp
);
6435 del_timer_sync(&bp
->timer
);
6436 bnx2_shutdown_chip(bp
);
6441 netif_carrier_off(bp
->dev
);
6442 bnx2_set_power_state(bp
, PCI_D3hot
);
6446 #define GET_NET_STATS64(ctr) \
6447 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6448 (unsigned long) (ctr##_lo)
6450 #define GET_NET_STATS32(ctr) \
6453 #if (BITS_PER_LONG == 64)
6454 #define GET_NET_STATS GET_NET_STATS64
6456 #define GET_NET_STATS GET_NET_STATS32
6459 static struct net_device_stats
*
6460 bnx2_get_stats(struct net_device
*dev
)
6462 struct bnx2
*bp
= netdev_priv(dev
);
6463 struct statistics_block
*stats_blk
= bp
->stats_blk
;
6464 struct net_device_stats
*net_stats
= &dev
->stats
;
6466 if (bp
->stats_blk
== NULL
) {
6469 net_stats
->rx_packets
=
6470 GET_NET_STATS(stats_blk
->stat_IfHCInUcastPkts
) +
6471 GET_NET_STATS(stats_blk
->stat_IfHCInMulticastPkts
) +
6472 GET_NET_STATS(stats_blk
->stat_IfHCInBroadcastPkts
);
6474 net_stats
->tx_packets
=
6475 GET_NET_STATS(stats_blk
->stat_IfHCOutUcastPkts
) +
6476 GET_NET_STATS(stats_blk
->stat_IfHCOutMulticastPkts
) +
6477 GET_NET_STATS(stats_blk
->stat_IfHCOutBroadcastPkts
);
6479 net_stats
->rx_bytes
=
6480 GET_NET_STATS(stats_blk
->stat_IfHCInOctets
);
6482 net_stats
->tx_bytes
=
6483 GET_NET_STATS(stats_blk
->stat_IfHCOutOctets
);
6485 net_stats
->multicast
=
6486 GET_NET_STATS(stats_blk
->stat_IfHCOutMulticastPkts
);
6488 net_stats
->collisions
=
6489 (unsigned long) stats_blk
->stat_EtherStatsCollisions
;
6491 net_stats
->rx_length_errors
=
6492 (unsigned long) (stats_blk
->stat_EtherStatsUndersizePkts
+
6493 stats_blk
->stat_EtherStatsOverrsizePkts
);
6495 net_stats
->rx_over_errors
=
6496 (unsigned long) (stats_blk
->stat_IfInFTQDiscards
+
6497 stats_blk
->stat_IfInMBUFDiscards
);
6499 net_stats
->rx_frame_errors
=
6500 (unsigned long) stats_blk
->stat_Dot3StatsAlignmentErrors
;
6502 net_stats
->rx_crc_errors
=
6503 (unsigned long) stats_blk
->stat_Dot3StatsFCSErrors
;
6505 net_stats
->rx_errors
= net_stats
->rx_length_errors
+
6506 net_stats
->rx_over_errors
+ net_stats
->rx_frame_errors
+
6507 net_stats
->rx_crc_errors
;
6509 net_stats
->tx_aborted_errors
=
6510 (unsigned long) (stats_blk
->stat_Dot3StatsExcessiveCollisions
+
6511 stats_blk
->stat_Dot3StatsLateCollisions
);
6513 if ((CHIP_NUM(bp
) == CHIP_NUM_5706
) ||
6514 (CHIP_ID(bp
) == CHIP_ID_5708_A0
))
6515 net_stats
->tx_carrier_errors
= 0;
6517 net_stats
->tx_carrier_errors
=
6519 stats_blk
->stat_Dot3StatsCarrierSenseErrors
;
6522 net_stats
->tx_errors
=
6524 stats_blk
->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6526 net_stats
->tx_aborted_errors
+
6527 net_stats
->tx_carrier_errors
;
6529 net_stats
->rx_missed_errors
=
6530 (unsigned long) (stats_blk
->stat_IfInFTQDiscards
+
6531 stats_blk
->stat_IfInMBUFDiscards
+ stats_blk
->stat_FwRxDrop
);
6536 /* All ethtool functions called with rtnl_lock */
6539 bnx2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6541 struct bnx2
*bp
= netdev_priv(dev
);
6542 int support_serdes
= 0, support_copper
= 0;
6544 cmd
->supported
= SUPPORTED_Autoneg
;
6545 if (bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
) {
6548 } else if (bp
->phy_port
== PORT_FIBRE
)
6553 if (support_serdes
) {
6554 cmd
->supported
|= SUPPORTED_1000baseT_Full
|
6556 if (bp
->phy_flags
& BNX2_PHY_FLAG_2_5G_CAPABLE
)
6557 cmd
->supported
|= SUPPORTED_2500baseX_Full
;
6560 if (support_copper
) {
6561 cmd
->supported
|= SUPPORTED_10baseT_Half
|
6562 SUPPORTED_10baseT_Full
|
6563 SUPPORTED_100baseT_Half
|
6564 SUPPORTED_100baseT_Full
|
6565 SUPPORTED_1000baseT_Full
|
6570 spin_lock_bh(&bp
->phy_lock
);
6571 cmd
->port
= bp
->phy_port
;
6572 cmd
->advertising
= bp
->advertising
;
6574 if (bp
->autoneg
& AUTONEG_SPEED
) {
6575 cmd
->autoneg
= AUTONEG_ENABLE
;
6578 cmd
->autoneg
= AUTONEG_DISABLE
;
6581 if (netif_carrier_ok(dev
)) {
6582 cmd
->speed
= bp
->line_speed
;
6583 cmd
->duplex
= bp
->duplex
;
6589 spin_unlock_bh(&bp
->phy_lock
);
6591 cmd
->transceiver
= XCVR_INTERNAL
;
6592 cmd
->phy_address
= bp
->phy_addr
;
6598 bnx2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6600 struct bnx2
*bp
= netdev_priv(dev
);
6601 u8 autoneg
= bp
->autoneg
;
6602 u8 req_duplex
= bp
->req_duplex
;
6603 u16 req_line_speed
= bp
->req_line_speed
;
6604 u32 advertising
= bp
->advertising
;
6607 spin_lock_bh(&bp
->phy_lock
);
6609 if (cmd
->port
!= PORT_TP
&& cmd
->port
!= PORT_FIBRE
)
6610 goto err_out_unlock
;
6612 if (cmd
->port
!= bp
->phy_port
&&
6613 !(bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
))
6614 goto err_out_unlock
;
6616 /* If device is down, we can store the settings only if the user
6617 * is setting the currently active port.
6619 if (!netif_running(dev
) && cmd
->port
!= bp
->phy_port
)
6620 goto err_out_unlock
;
6622 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
6623 autoneg
|= AUTONEG_SPEED
;
6625 cmd
->advertising
&= ETHTOOL_ALL_COPPER_SPEED
;
6627 /* allow advertising 1 speed */
6628 if ((cmd
->advertising
== ADVERTISED_10baseT_Half
) ||
6629 (cmd
->advertising
== ADVERTISED_10baseT_Full
) ||
6630 (cmd
->advertising
== ADVERTISED_100baseT_Half
) ||
6631 (cmd
->advertising
== ADVERTISED_100baseT_Full
)) {
6633 if (cmd
->port
== PORT_FIBRE
)
6634 goto err_out_unlock
;
6636 advertising
= cmd
->advertising
;
6638 } else if (cmd
->advertising
== ADVERTISED_2500baseX_Full
) {
6639 if (!(bp
->phy_flags
& BNX2_PHY_FLAG_2_5G_CAPABLE
) ||
6640 (cmd
->port
== PORT_TP
))
6641 goto err_out_unlock
;
6642 } else if (cmd
->advertising
== ADVERTISED_1000baseT_Full
)
6643 advertising
= cmd
->advertising
;
6644 else if (cmd
->advertising
== ADVERTISED_1000baseT_Half
)
6645 goto err_out_unlock
;
6647 if (cmd
->port
== PORT_FIBRE
)
6648 advertising
= ETHTOOL_ALL_FIBRE_SPEED
;
6650 advertising
= ETHTOOL_ALL_COPPER_SPEED
;
6652 advertising
|= ADVERTISED_Autoneg
;
6655 if (cmd
->port
== PORT_FIBRE
) {
6656 if ((cmd
->speed
!= SPEED_1000
&&
6657 cmd
->speed
!= SPEED_2500
) ||
6658 (cmd
->duplex
!= DUPLEX_FULL
))
6659 goto err_out_unlock
;
6661 if (cmd
->speed
== SPEED_2500
&&
6662 !(bp
->phy_flags
& BNX2_PHY_FLAG_2_5G_CAPABLE
))
6663 goto err_out_unlock
;
6665 else if (cmd
->speed
== SPEED_1000
|| cmd
->speed
== SPEED_2500
)
6666 goto err_out_unlock
;
6668 autoneg
&= ~AUTONEG_SPEED
;
6669 req_line_speed
= cmd
->speed
;
6670 req_duplex
= cmd
->duplex
;
6674 bp
->autoneg
= autoneg
;
6675 bp
->advertising
= advertising
;
6676 bp
->req_line_speed
= req_line_speed
;
6677 bp
->req_duplex
= req_duplex
;
6680 /* If device is down, the new settings will be picked up when it is
6683 if (netif_running(dev
))
6684 err
= bnx2_setup_phy(bp
, cmd
->port
);
6687 spin_unlock_bh(&bp
->phy_lock
);
6693 bnx2_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
6695 struct bnx2
*bp
= netdev_priv(dev
);
6697 strcpy(info
->driver
, DRV_MODULE_NAME
);
6698 strcpy(info
->version
, DRV_MODULE_VERSION
);
6699 strcpy(info
->bus_info
, pci_name(bp
->pdev
));
6700 strcpy(info
->fw_version
, bp
->fw_version
);
6703 #define BNX2_REGDUMP_LEN (32 * 1024)
6706 bnx2_get_regs_len(struct net_device
*dev
)
6708 return BNX2_REGDUMP_LEN
;
6712 bnx2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *_p
)
6714 u32
*p
= _p
, i
, offset
;
6716 struct bnx2
*bp
= netdev_priv(dev
);
6717 u32 reg_boundaries
[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6718 0x0800, 0x0880, 0x0c00, 0x0c10,
6719 0x0c30, 0x0d08, 0x1000, 0x101c,
6720 0x1040, 0x1048, 0x1080, 0x10a4,
6721 0x1400, 0x1490, 0x1498, 0x14f0,
6722 0x1500, 0x155c, 0x1580, 0x15dc,
6723 0x1600, 0x1658, 0x1680, 0x16d8,
6724 0x1800, 0x1820, 0x1840, 0x1854,
6725 0x1880, 0x1894, 0x1900, 0x1984,
6726 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6727 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6728 0x2000, 0x2030, 0x23c0, 0x2400,
6729 0x2800, 0x2820, 0x2830, 0x2850,
6730 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6731 0x3c00, 0x3c94, 0x4000, 0x4010,
6732 0x4080, 0x4090, 0x43c0, 0x4458,
6733 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6734 0x4fc0, 0x5010, 0x53c0, 0x5444,
6735 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6736 0x5fc0, 0x6000, 0x6400, 0x6428,
6737 0x6800, 0x6848, 0x684c, 0x6860,
6738 0x6888, 0x6910, 0x8000 };
6742 memset(p
, 0, BNX2_REGDUMP_LEN
);
6744 if (!netif_running(bp
->dev
))
6748 offset
= reg_boundaries
[0];
6750 while (offset
< BNX2_REGDUMP_LEN
) {
6751 *p
++ = REG_RD(bp
, offset
);
6753 if (offset
== reg_boundaries
[i
+ 1]) {
6754 offset
= reg_boundaries
[i
+ 2];
6755 p
= (u32
*) (orig_p
+ offset
);
6762 bnx2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
6764 struct bnx2
*bp
= netdev_priv(dev
);
6766 if (bp
->flags
& BNX2_FLAG_NO_WOL
) {
6771 wol
->supported
= WAKE_MAGIC
;
6773 wol
->wolopts
= WAKE_MAGIC
;
6777 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
6781 bnx2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
6783 struct bnx2
*bp
= netdev_priv(dev
);
6785 if (wol
->wolopts
& ~WAKE_MAGIC
)
6788 if (wol
->wolopts
& WAKE_MAGIC
) {
6789 if (bp
->flags
& BNX2_FLAG_NO_WOL
)
6801 bnx2_nway_reset(struct net_device
*dev
)
6803 struct bnx2
*bp
= netdev_priv(dev
);
6806 if (!netif_running(dev
))
6809 if (!(bp
->autoneg
& AUTONEG_SPEED
)) {
6813 spin_lock_bh(&bp
->phy_lock
);
6815 if (bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
) {
6818 rc
= bnx2_setup_remote_phy(bp
, bp
->phy_port
);
6819 spin_unlock_bh(&bp
->phy_lock
);
6823 /* Force a link down visible on the other side */
6824 if (bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) {
6825 bnx2_write_phy(bp
, bp
->mii_bmcr
, BMCR_LOOPBACK
);
6826 spin_unlock_bh(&bp
->phy_lock
);
6830 spin_lock_bh(&bp
->phy_lock
);
6832 bp
->current_interval
= BNX2_SERDES_AN_TIMEOUT
;
6833 bp
->serdes_an_pending
= 1;
6834 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
6837 bnx2_read_phy(bp
, bp
->mii_bmcr
, &bmcr
);
6838 bmcr
&= ~BMCR_LOOPBACK
;
6839 bnx2_write_phy(bp
, bp
->mii_bmcr
, bmcr
| BMCR_ANRESTART
| BMCR_ANENABLE
);
6841 spin_unlock_bh(&bp
->phy_lock
);
6847 bnx2_get_link(struct net_device
*dev
)
6849 struct bnx2
*bp
= netdev_priv(dev
);
6855 bnx2_get_eeprom_len(struct net_device
*dev
)
6857 struct bnx2
*bp
= netdev_priv(dev
);
6859 if (bp
->flash_info
== NULL
)
6862 return (int) bp
->flash_size
;
6866 bnx2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
6869 struct bnx2
*bp
= netdev_priv(dev
);
6872 if (!netif_running(dev
))
6875 /* parameters already validated in ethtool_get_eeprom */
6877 rc
= bnx2_nvram_read(bp
, eeprom
->offset
, eebuf
, eeprom
->len
);
6883 bnx2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
6886 struct bnx2
*bp
= netdev_priv(dev
);
6889 if (!netif_running(dev
))
6892 /* parameters already validated in ethtool_set_eeprom */
6894 rc
= bnx2_nvram_write(bp
, eeprom
->offset
, eebuf
, eeprom
->len
);
6900 bnx2_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*coal
)
6902 struct bnx2
*bp
= netdev_priv(dev
);
6904 memset(coal
, 0, sizeof(struct ethtool_coalesce
));
6906 coal
->rx_coalesce_usecs
= bp
->rx_ticks
;
6907 coal
->rx_max_coalesced_frames
= bp
->rx_quick_cons_trip
;
6908 coal
->rx_coalesce_usecs_irq
= bp
->rx_ticks_int
;
6909 coal
->rx_max_coalesced_frames_irq
= bp
->rx_quick_cons_trip_int
;
6911 coal
->tx_coalesce_usecs
= bp
->tx_ticks
;
6912 coal
->tx_max_coalesced_frames
= bp
->tx_quick_cons_trip
;
6913 coal
->tx_coalesce_usecs_irq
= bp
->tx_ticks_int
;
6914 coal
->tx_max_coalesced_frames_irq
= bp
->tx_quick_cons_trip_int
;
6916 coal
->stats_block_coalesce_usecs
= bp
->stats_ticks
;
6922 bnx2_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*coal
)
6924 struct bnx2
*bp
= netdev_priv(dev
);
6926 bp
->rx_ticks
= (u16
) coal
->rx_coalesce_usecs
;
6927 if (bp
->rx_ticks
> 0x3ff) bp
->rx_ticks
= 0x3ff;
6929 bp
->rx_quick_cons_trip
= (u16
) coal
->rx_max_coalesced_frames
;
6930 if (bp
->rx_quick_cons_trip
> 0xff) bp
->rx_quick_cons_trip
= 0xff;
6932 bp
->rx_ticks_int
= (u16
) coal
->rx_coalesce_usecs_irq
;
6933 if (bp
->rx_ticks_int
> 0x3ff) bp
->rx_ticks_int
= 0x3ff;
6935 bp
->rx_quick_cons_trip_int
= (u16
) coal
->rx_max_coalesced_frames_irq
;
6936 if (bp
->rx_quick_cons_trip_int
> 0xff)
6937 bp
->rx_quick_cons_trip_int
= 0xff;
6939 bp
->tx_ticks
= (u16
) coal
->tx_coalesce_usecs
;
6940 if (bp
->tx_ticks
> 0x3ff) bp
->tx_ticks
= 0x3ff;
6942 bp
->tx_quick_cons_trip
= (u16
) coal
->tx_max_coalesced_frames
;
6943 if (bp
->tx_quick_cons_trip
> 0xff) bp
->tx_quick_cons_trip
= 0xff;
6945 bp
->tx_ticks_int
= (u16
) coal
->tx_coalesce_usecs_irq
;
6946 if (bp
->tx_ticks_int
> 0x3ff) bp
->tx_ticks_int
= 0x3ff;
6948 bp
->tx_quick_cons_trip_int
= (u16
) coal
->tx_max_coalesced_frames_irq
;
6949 if (bp
->tx_quick_cons_trip_int
> 0xff) bp
->tx_quick_cons_trip_int
=
6952 bp
->stats_ticks
= coal
->stats_block_coalesce_usecs
;
6953 if (bp
->flags
& BNX2_FLAG_BROKEN_STATS
) {
6954 if (bp
->stats_ticks
!= 0 && bp
->stats_ticks
!= USEC_PER_SEC
)
6955 bp
->stats_ticks
= USEC_PER_SEC
;
6957 if (bp
->stats_ticks
> BNX2_HC_STATS_TICKS_HC_STAT_TICKS
)
6958 bp
->stats_ticks
= BNX2_HC_STATS_TICKS_HC_STAT_TICKS
;
6959 bp
->stats_ticks
&= BNX2_HC_STATS_TICKS_HC_STAT_TICKS
;
6961 if (netif_running(bp
->dev
)) {
6962 bnx2_netif_stop(bp
);
6963 bnx2_init_nic(bp
, 0);
6964 bnx2_netif_start(bp
);
6971 bnx2_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
6973 struct bnx2
*bp
= netdev_priv(dev
);
6975 ering
->rx_max_pending
= MAX_TOTAL_RX_DESC_CNT
;
6976 ering
->rx_mini_max_pending
= 0;
6977 ering
->rx_jumbo_max_pending
= MAX_TOTAL_RX_PG_DESC_CNT
;
6979 ering
->rx_pending
= bp
->rx_ring_size
;
6980 ering
->rx_mini_pending
= 0;
6981 ering
->rx_jumbo_pending
= bp
->rx_pg_ring_size
;
6983 ering
->tx_max_pending
= MAX_TX_DESC_CNT
;
6984 ering
->tx_pending
= bp
->tx_ring_size
;
6988 bnx2_change_ring_size(struct bnx2
*bp
, u32 rx
, u32 tx
)
6990 if (netif_running(bp
->dev
)) {
6991 bnx2_netif_stop(bp
);
6992 bnx2_reset_chip(bp
, BNX2_DRV_MSG_CODE_RESET
);
6997 bnx2_set_rx_ring_size(bp
, rx
);
6998 bp
->tx_ring_size
= tx
;
7000 if (netif_running(bp
->dev
)) {
7003 rc
= bnx2_alloc_mem(bp
);
7005 rc
= bnx2_init_nic(bp
, 0);
7008 bnx2_napi_enable(bp
);
7012 bnx2_netif_start(bp
);
7018 bnx2_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
7020 struct bnx2
*bp
= netdev_priv(dev
);
7023 if ((ering
->rx_pending
> MAX_TOTAL_RX_DESC_CNT
) ||
7024 (ering
->tx_pending
> MAX_TX_DESC_CNT
) ||
7025 (ering
->tx_pending
<= MAX_SKB_FRAGS
)) {
7029 rc
= bnx2_change_ring_size(bp
, ering
->rx_pending
, ering
->tx_pending
);
7034 bnx2_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
7036 struct bnx2
*bp
= netdev_priv(dev
);
7038 epause
->autoneg
= ((bp
->autoneg
& AUTONEG_FLOW_CTRL
) != 0);
7039 epause
->rx_pause
= ((bp
->flow_ctrl
& FLOW_CTRL_RX
) != 0);
7040 epause
->tx_pause
= ((bp
->flow_ctrl
& FLOW_CTRL_TX
) != 0);
7044 bnx2_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
7046 struct bnx2
*bp
= netdev_priv(dev
);
7048 bp
->req_flow_ctrl
= 0;
7049 if (epause
->rx_pause
)
7050 bp
->req_flow_ctrl
|= FLOW_CTRL_RX
;
7051 if (epause
->tx_pause
)
7052 bp
->req_flow_ctrl
|= FLOW_CTRL_TX
;
7054 if (epause
->autoneg
) {
7055 bp
->autoneg
|= AUTONEG_FLOW_CTRL
;
7058 bp
->autoneg
&= ~AUTONEG_FLOW_CTRL
;
7061 if (netif_running(dev
)) {
7062 spin_lock_bh(&bp
->phy_lock
);
7063 bnx2_setup_phy(bp
, bp
->phy_port
);
7064 spin_unlock_bh(&bp
->phy_lock
);
7071 bnx2_get_rx_csum(struct net_device
*dev
)
7073 struct bnx2
*bp
= netdev_priv(dev
);
7079 bnx2_set_rx_csum(struct net_device
*dev
, u32 data
)
7081 struct bnx2
*bp
= netdev_priv(dev
);
7088 bnx2_set_tso(struct net_device
*dev
, u32 data
)
7090 struct bnx2
*bp
= netdev_priv(dev
);
7093 dev
->features
|= NETIF_F_TSO
| NETIF_F_TSO_ECN
;
7094 if (CHIP_NUM(bp
) == CHIP_NUM_5709
)
7095 dev
->features
|= NETIF_F_TSO6
;
7097 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_TSO6
|
7103 char string
[ETH_GSTRING_LEN
];
7104 } bnx2_stats_str_arr
[] = {
7106 { "rx_error_bytes" },
7108 { "tx_error_bytes" },
7109 { "rx_ucast_packets" },
7110 { "rx_mcast_packets" },
7111 { "rx_bcast_packets" },
7112 { "tx_ucast_packets" },
7113 { "tx_mcast_packets" },
7114 { "tx_bcast_packets" },
7115 { "tx_mac_errors" },
7116 { "tx_carrier_errors" },
7117 { "rx_crc_errors" },
7118 { "rx_align_errors" },
7119 { "tx_single_collisions" },
7120 { "tx_multi_collisions" },
7122 { "tx_excess_collisions" },
7123 { "tx_late_collisions" },
7124 { "tx_total_collisions" },
7127 { "rx_undersize_packets" },
7128 { "rx_oversize_packets" },
7129 { "rx_64_byte_packets" },
7130 { "rx_65_to_127_byte_packets" },
7131 { "rx_128_to_255_byte_packets" },
7132 { "rx_256_to_511_byte_packets" },
7133 { "rx_512_to_1023_byte_packets" },
7134 { "rx_1024_to_1522_byte_packets" },
7135 { "rx_1523_to_9022_byte_packets" },
7136 { "tx_64_byte_packets" },
7137 { "tx_65_to_127_byte_packets" },
7138 { "tx_128_to_255_byte_packets" },
7139 { "tx_256_to_511_byte_packets" },
7140 { "tx_512_to_1023_byte_packets" },
7141 { "tx_1024_to_1522_byte_packets" },
7142 { "tx_1523_to_9022_byte_packets" },
7143 { "rx_xon_frames" },
7144 { "rx_xoff_frames" },
7145 { "tx_xon_frames" },
7146 { "tx_xoff_frames" },
7147 { "rx_mac_ctrl_frames" },
7148 { "rx_filtered_packets" },
7149 { "rx_ftq_discards" },
7151 { "rx_fw_discards" },
7154 #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7155 sizeof(bnx2_stats_str_arr[0]))
7157 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7159 static const unsigned long bnx2_stats_offset_arr
[BNX2_NUM_STATS
] = {
7160 STATS_OFFSET32(stat_IfHCInOctets_hi
),
7161 STATS_OFFSET32(stat_IfHCInBadOctets_hi
),
7162 STATS_OFFSET32(stat_IfHCOutOctets_hi
),
7163 STATS_OFFSET32(stat_IfHCOutBadOctets_hi
),
7164 STATS_OFFSET32(stat_IfHCInUcastPkts_hi
),
7165 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi
),
7166 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi
),
7167 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi
),
7168 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi
),
7169 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi
),
7170 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors
),
7171 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors
),
7172 STATS_OFFSET32(stat_Dot3StatsFCSErrors
),
7173 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors
),
7174 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames
),
7175 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames
),
7176 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions
),
7177 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions
),
7178 STATS_OFFSET32(stat_Dot3StatsLateCollisions
),
7179 STATS_OFFSET32(stat_EtherStatsCollisions
),
7180 STATS_OFFSET32(stat_EtherStatsFragments
),
7181 STATS_OFFSET32(stat_EtherStatsJabbers
),
7182 STATS_OFFSET32(stat_EtherStatsUndersizePkts
),
7183 STATS_OFFSET32(stat_EtherStatsOverrsizePkts
),
7184 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets
),
7185 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets
),
7186 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets
),
7187 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets
),
7188 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets
),
7189 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets
),
7190 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets
),
7191 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets
),
7192 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets
),
7193 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets
),
7194 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets
),
7195 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets
),
7196 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets
),
7197 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets
),
7198 STATS_OFFSET32(stat_XonPauseFramesReceived
),
7199 STATS_OFFSET32(stat_XoffPauseFramesReceived
),
7200 STATS_OFFSET32(stat_OutXonSent
),
7201 STATS_OFFSET32(stat_OutXoffSent
),
7202 STATS_OFFSET32(stat_MacControlFramesReceived
),
7203 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards
),
7204 STATS_OFFSET32(stat_IfInFTQDiscards
),
7205 STATS_OFFSET32(stat_IfInMBUFDiscards
),
7206 STATS_OFFSET32(stat_FwRxDrop
),
7209 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7210 * skipped because of errata.
7212 static u8 bnx2_5706_stats_len_arr
[BNX2_NUM_STATS
] = {
7213 8,0,8,8,8,8,8,8,8,8,
7214 4,0,4,4,4,4,4,4,4,4,
7215 4,4,4,4,4,4,4,4,4,4,
7216 4,4,4,4,4,4,4,4,4,4,
7220 static u8 bnx2_5708_stats_len_arr
[BNX2_NUM_STATS
] = {
7221 8,0,8,8,8,8,8,8,8,8,
7222 4,4,4,4,4,4,4,4,4,4,
7223 4,4,4,4,4,4,4,4,4,4,
7224 4,4,4,4,4,4,4,4,4,4,
7228 #define BNX2_NUM_TESTS 6
7231 char string
[ETH_GSTRING_LEN
];
7232 } bnx2_tests_str_arr
[BNX2_NUM_TESTS
] = {
7233 { "register_test (offline)" },
7234 { "memory_test (offline)" },
7235 { "loopback_test (offline)" },
7236 { "nvram_test (online)" },
7237 { "interrupt_test (online)" },
7238 { "link_test (online)" },
7242 bnx2_get_sset_count(struct net_device
*dev
, int sset
)
7246 return BNX2_NUM_TESTS
;
7248 return BNX2_NUM_STATS
;
7255 bnx2_self_test(struct net_device
*dev
, struct ethtool_test
*etest
, u64
*buf
)
7257 struct bnx2
*bp
= netdev_priv(dev
);
7259 bnx2_set_power_state(bp
, PCI_D0
);
7261 memset(buf
, 0, sizeof(u64
) * BNX2_NUM_TESTS
);
7262 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
7265 bnx2_netif_stop(bp
);
7266 bnx2_reset_chip(bp
, BNX2_DRV_MSG_CODE_DIAG
);
7269 if (bnx2_test_registers(bp
) != 0) {
7271 etest
->flags
|= ETH_TEST_FL_FAILED
;
7273 if (bnx2_test_memory(bp
) != 0) {
7275 etest
->flags
|= ETH_TEST_FL_FAILED
;
7277 if ((buf
[2] = bnx2_test_loopback(bp
)) != 0)
7278 etest
->flags
|= ETH_TEST_FL_FAILED
;
7280 if (!netif_running(bp
->dev
))
7281 bnx2_shutdown_chip(bp
);
7283 bnx2_init_nic(bp
, 1);
7284 bnx2_netif_start(bp
);
7287 /* wait for link up */
7288 for (i
= 0; i
< 7; i
++) {
7291 msleep_interruptible(1000);
7295 if (bnx2_test_nvram(bp
) != 0) {
7297 etest
->flags
|= ETH_TEST_FL_FAILED
;
7299 if (bnx2_test_intr(bp
) != 0) {
7301 etest
->flags
|= ETH_TEST_FL_FAILED
;
7304 if (bnx2_test_link(bp
) != 0) {
7306 etest
->flags
|= ETH_TEST_FL_FAILED
;
7309 if (!netif_running(bp
->dev
))
7310 bnx2_set_power_state(bp
, PCI_D3hot
);
7314 bnx2_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
7316 switch (stringset
) {
7318 memcpy(buf
, bnx2_stats_str_arr
,
7319 sizeof(bnx2_stats_str_arr
));
7322 memcpy(buf
, bnx2_tests_str_arr
,
7323 sizeof(bnx2_tests_str_arr
));
7329 bnx2_get_ethtool_stats(struct net_device
*dev
,
7330 struct ethtool_stats
*stats
, u64
*buf
)
7332 struct bnx2
*bp
= netdev_priv(dev
);
7334 u32
*hw_stats
= (u32
*) bp
->stats_blk
;
7335 u8
*stats_len_arr
= NULL
;
7337 if (hw_stats
== NULL
) {
7338 memset(buf
, 0, sizeof(u64
) * BNX2_NUM_STATS
);
7342 if ((CHIP_ID(bp
) == CHIP_ID_5706_A0
) ||
7343 (CHIP_ID(bp
) == CHIP_ID_5706_A1
) ||
7344 (CHIP_ID(bp
) == CHIP_ID_5706_A2
) ||
7345 (CHIP_ID(bp
) == CHIP_ID_5708_A0
))
7346 stats_len_arr
= bnx2_5706_stats_len_arr
;
7348 stats_len_arr
= bnx2_5708_stats_len_arr
;
7350 for (i
= 0; i
< BNX2_NUM_STATS
; i
++) {
7351 if (stats_len_arr
[i
] == 0) {
7352 /* skip this counter */
7356 if (stats_len_arr
[i
] == 4) {
7357 /* 4-byte counter */
7359 *(hw_stats
+ bnx2_stats_offset_arr
[i
]);
7362 /* 8-byte counter */
7363 buf
[i
] = (((u64
) *(hw_stats
+
7364 bnx2_stats_offset_arr
[i
])) << 32) +
7365 *(hw_stats
+ bnx2_stats_offset_arr
[i
] + 1);
7370 bnx2_phys_id(struct net_device
*dev
, u32 data
)
7372 struct bnx2
*bp
= netdev_priv(dev
);
7376 bnx2_set_power_state(bp
, PCI_D0
);
7381 save
= REG_RD(bp
, BNX2_MISC_CFG
);
7382 REG_WR(bp
, BNX2_MISC_CFG
, BNX2_MISC_CFG_LEDMODE_MAC
);
7384 for (i
= 0; i
< (data
* 2); i
++) {
7386 REG_WR(bp
, BNX2_EMAC_LED
, BNX2_EMAC_LED_OVERRIDE
);
7389 REG_WR(bp
, BNX2_EMAC_LED
, BNX2_EMAC_LED_OVERRIDE
|
7390 BNX2_EMAC_LED_1000MB_OVERRIDE
|
7391 BNX2_EMAC_LED_100MB_OVERRIDE
|
7392 BNX2_EMAC_LED_10MB_OVERRIDE
|
7393 BNX2_EMAC_LED_TRAFFIC_OVERRIDE
|
7394 BNX2_EMAC_LED_TRAFFIC
);
7396 msleep_interruptible(500);
7397 if (signal_pending(current
))
7400 REG_WR(bp
, BNX2_EMAC_LED
, 0);
7401 REG_WR(bp
, BNX2_MISC_CFG
, save
);
7403 if (!netif_running(dev
))
7404 bnx2_set_power_state(bp
, PCI_D3hot
);
7410 bnx2_set_tx_csum(struct net_device
*dev
, u32 data
)
7412 struct bnx2
*bp
= netdev_priv(dev
);
7414 if (CHIP_NUM(bp
) == CHIP_NUM_5709
)
7415 return (ethtool_op_set_tx_ipv6_csum(dev
, data
));
7417 return (ethtool_op_set_tx_csum(dev
, data
));
7420 static const struct ethtool_ops bnx2_ethtool_ops
= {
7421 .get_settings
= bnx2_get_settings
,
7422 .set_settings
= bnx2_set_settings
,
7423 .get_drvinfo
= bnx2_get_drvinfo
,
7424 .get_regs_len
= bnx2_get_regs_len
,
7425 .get_regs
= bnx2_get_regs
,
7426 .get_wol
= bnx2_get_wol
,
7427 .set_wol
= bnx2_set_wol
,
7428 .nway_reset
= bnx2_nway_reset
,
7429 .get_link
= bnx2_get_link
,
7430 .get_eeprom_len
= bnx2_get_eeprom_len
,
7431 .get_eeprom
= bnx2_get_eeprom
,
7432 .set_eeprom
= bnx2_set_eeprom
,
7433 .get_coalesce
= bnx2_get_coalesce
,
7434 .set_coalesce
= bnx2_set_coalesce
,
7435 .get_ringparam
= bnx2_get_ringparam
,
7436 .set_ringparam
= bnx2_set_ringparam
,
7437 .get_pauseparam
= bnx2_get_pauseparam
,
7438 .set_pauseparam
= bnx2_set_pauseparam
,
7439 .get_rx_csum
= bnx2_get_rx_csum
,
7440 .set_rx_csum
= bnx2_set_rx_csum
,
7441 .set_tx_csum
= bnx2_set_tx_csum
,
7442 .set_sg
= ethtool_op_set_sg
,
7443 .set_tso
= bnx2_set_tso
,
7444 .self_test
= bnx2_self_test
,
7445 .get_strings
= bnx2_get_strings
,
7446 .phys_id
= bnx2_phys_id
,
7447 .get_ethtool_stats
= bnx2_get_ethtool_stats
,
7448 .get_sset_count
= bnx2_get_sset_count
,
7451 /* Called with rtnl_lock */
7453 bnx2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7455 struct mii_ioctl_data
*data
= if_mii(ifr
);
7456 struct bnx2
*bp
= netdev_priv(dev
);
7461 data
->phy_id
= bp
->phy_addr
;
7467 if (bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
)
7470 if (!netif_running(dev
))
7473 spin_lock_bh(&bp
->phy_lock
);
7474 err
= bnx2_read_phy(bp
, data
->reg_num
& 0x1f, &mii_regval
);
7475 spin_unlock_bh(&bp
->phy_lock
);
7477 data
->val_out
= mii_regval
;
7483 if (!capable(CAP_NET_ADMIN
))
7486 if (bp
->phy_flags
& BNX2_PHY_FLAG_REMOTE_PHY_CAP
)
7489 if (!netif_running(dev
))
7492 spin_lock_bh(&bp
->phy_lock
);
7493 err
= bnx2_write_phy(bp
, data
->reg_num
& 0x1f, data
->val_in
);
7494 spin_unlock_bh(&bp
->phy_lock
);
7505 /* Called with rtnl_lock */
7507 bnx2_change_mac_addr(struct net_device
*dev
, void *p
)
7509 struct sockaddr
*addr
= p
;
7510 struct bnx2
*bp
= netdev_priv(dev
);
7512 if (!is_valid_ether_addr(addr
->sa_data
))
7515 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
7516 if (netif_running(dev
))
7517 bnx2_set_mac_addr(bp
, bp
->dev
->dev_addr
, 0);
7522 /* Called with rtnl_lock */
7524 bnx2_change_mtu(struct net_device
*dev
, int new_mtu
)
7526 struct bnx2
*bp
= netdev_priv(dev
);
7528 if (((new_mtu
+ ETH_HLEN
) > MAX_ETHERNET_JUMBO_PACKET_SIZE
) ||
7529 ((new_mtu
+ ETH_HLEN
) < MIN_ETHERNET_PACKET_SIZE
))
7533 return (bnx2_change_ring_size(bp
, bp
->rx_ring_size
, bp
->tx_ring_size
));
7536 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7538 poll_bnx2(struct net_device
*dev
)
7540 struct bnx2
*bp
= netdev_priv(dev
);
7543 for (i
= 0; i
< bp
->irq_nvecs
; i
++) {
7544 disable_irq(bp
->irq_tbl
[i
].vector
);
7545 bnx2_interrupt(bp
->irq_tbl
[i
].vector
, &bp
->bnx2_napi
[i
]);
7546 enable_irq(bp
->irq_tbl
[i
].vector
);
7551 static void __devinit
7552 bnx2_get_5709_media(struct bnx2
*bp
)
7554 u32 val
= REG_RD(bp
, BNX2_MISC_DUAL_MEDIA_CTRL
);
7555 u32 bond_id
= val
& BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID
;
7558 if (bond_id
== BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C
)
7560 else if (bond_id
== BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S
) {
7561 bp
->phy_flags
|= BNX2_PHY_FLAG_SERDES
;
7565 if (val
& BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE
)
7566 strap
= (val
& BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL
) >> 21;
7568 strap
= (val
& BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP
) >> 8;
7570 if (PCI_FUNC(bp
->pdev
->devfn
) == 0) {
7575 bp
->phy_flags
|= BNX2_PHY_FLAG_SERDES
;
7583 bp
->phy_flags
|= BNX2_PHY_FLAG_SERDES
;
7589 static void __devinit
7590 bnx2_get_pci_speed(struct bnx2
*bp
)
7594 reg
= REG_RD(bp
, BNX2_PCICFG_MISC_STATUS
);
7595 if (reg
& BNX2_PCICFG_MISC_STATUS_PCIX_DET
) {
7598 bp
->flags
|= BNX2_FLAG_PCIX
;
7600 clkreg
= REG_RD(bp
, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS
);
7602 clkreg
&= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET
;
7604 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ
:
7605 bp
->bus_speed_mhz
= 133;
7608 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ
:
7609 bp
->bus_speed_mhz
= 100;
7612 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ
:
7613 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ
:
7614 bp
->bus_speed_mhz
= 66;
7617 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ
:
7618 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ
:
7619 bp
->bus_speed_mhz
= 50;
7622 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW
:
7623 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ
:
7624 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ
:
7625 bp
->bus_speed_mhz
= 33;
7630 if (reg
& BNX2_PCICFG_MISC_STATUS_M66EN
)
7631 bp
->bus_speed_mhz
= 66;
7633 bp
->bus_speed_mhz
= 33;
7636 if (reg
& BNX2_PCICFG_MISC_STATUS_32BIT_DET
)
7637 bp
->flags
|= BNX2_FLAG_PCI_32BIT
;
7641 static int __devinit
7642 bnx2_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
7645 unsigned long mem_len
;
7648 u64 dma_mask
, persist_dma_mask
;
7650 SET_NETDEV_DEV(dev
, &pdev
->dev
);
7651 bp
= netdev_priv(dev
);
7656 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7657 rc
= pci_enable_device(pdev
);
7659 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting.\n");
7663 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
7665 "Cannot find PCI device base address, aborting.\n");
7667 goto err_out_disable
;
7670 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
7672 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting.\n");
7673 goto err_out_disable
;
7676 pci_set_master(pdev
);
7677 pci_save_state(pdev
);
7679 bp
->pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
7680 if (bp
->pm_cap
== 0) {
7682 "Cannot find power management capability, aborting.\n");
7684 goto err_out_release
;
7690 spin_lock_init(&bp
->phy_lock
);
7691 spin_lock_init(&bp
->indirect_lock
);
7693 mutex_init(&bp
->cnic_lock
);
7695 INIT_WORK(&bp
->reset_task
, bnx2_reset_task
);
7697 dev
->base_addr
= dev
->mem_start
= pci_resource_start(pdev
, 0);
7698 mem_len
= MB_GET_CID_ADDR(TX_TSS_CID
+ TX_MAX_TSS_RINGS
+ 1);
7699 dev
->mem_end
= dev
->mem_start
+ mem_len
;
7700 dev
->irq
= pdev
->irq
;
7702 bp
->regview
= ioremap_nocache(dev
->base_addr
, mem_len
);
7705 dev_err(&pdev
->dev
, "Cannot map register space, aborting.\n");
7707 goto err_out_release
;
7710 /* Configure byte swap and enable write to the reg_window registers.
7711 * Rely on CPU to do target byte swapping on big endian systems
7712 * The chip's target access swapping will not swap all accesses
7714 pci_write_config_dword(bp
->pdev
, BNX2_PCICFG_MISC_CONFIG
,
7715 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA
|
7716 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP
);
7718 bnx2_set_power_state(bp
, PCI_D0
);
7720 bp
->chip_id
= REG_RD(bp
, BNX2_MISC_ID
);
7722 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
7723 if (pci_find_capability(pdev
, PCI_CAP_ID_EXP
) == 0) {
7725 "Cannot find PCIE capability, aborting.\n");
7729 bp
->flags
|= BNX2_FLAG_PCIE
;
7730 if (CHIP_REV(bp
) == CHIP_REV_Ax
)
7731 bp
->flags
|= BNX2_FLAG_JUMBO_BROKEN
;
7733 bp
->pcix_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PCIX
);
7734 if (bp
->pcix_cap
== 0) {
7736 "Cannot find PCIX capability, aborting.\n");
7740 bp
->flags
|= BNX2_FLAG_BROKEN_STATS
;
7743 if (CHIP_NUM(bp
) == CHIP_NUM_5709
&& CHIP_REV(bp
) != CHIP_REV_Ax
) {
7744 if (pci_find_capability(pdev
, PCI_CAP_ID_MSIX
))
7745 bp
->flags
|= BNX2_FLAG_MSIX_CAP
;
7748 if (CHIP_ID(bp
) != CHIP_ID_5706_A0
&& CHIP_ID(bp
) != CHIP_ID_5706_A1
) {
7749 if (pci_find_capability(pdev
, PCI_CAP_ID_MSI
))
7750 bp
->flags
|= BNX2_FLAG_MSI_CAP
;
7753 /* 5708 cannot support DMA addresses > 40-bit. */
7754 if (CHIP_NUM(bp
) == CHIP_NUM_5708
)
7755 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
7757 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
7759 /* Configure DMA attributes. */
7760 if (pci_set_dma_mask(pdev
, dma_mask
) == 0) {
7761 dev
->features
|= NETIF_F_HIGHDMA
;
7762 rc
= pci_set_consistent_dma_mask(pdev
, persist_dma_mask
);
7765 "pci_set_consistent_dma_mask failed, aborting.\n");
7768 } else if ((rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32))) != 0) {
7769 dev_err(&pdev
->dev
, "System does not support DMA, aborting.\n");
7773 if (!(bp
->flags
& BNX2_FLAG_PCIE
))
7774 bnx2_get_pci_speed(bp
);
7776 /* 5706A0 may falsely detect SERR and PERR. */
7777 if (CHIP_ID(bp
) == CHIP_ID_5706_A0
) {
7778 reg
= REG_RD(bp
, PCI_COMMAND
);
7779 reg
&= ~(PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
);
7780 REG_WR(bp
, PCI_COMMAND
, reg
);
7782 else if ((CHIP_ID(bp
) == CHIP_ID_5706_A1
) &&
7783 !(bp
->flags
& BNX2_FLAG_PCIX
)) {
7786 "5706 A1 can only be used in a PCIX bus, aborting.\n");
7790 bnx2_init_nvram(bp
);
7792 reg
= bnx2_reg_rd_ind(bp
, BNX2_SHM_HDR_SIGNATURE
);
7794 if ((reg
& BNX2_SHM_HDR_SIGNATURE_SIG_MASK
) ==
7795 BNX2_SHM_HDR_SIGNATURE_SIG
) {
7796 u32 off
= PCI_FUNC(pdev
->devfn
) << 2;
7798 bp
->shmem_base
= bnx2_reg_rd_ind(bp
, BNX2_SHM_HDR_ADDR_0
+ off
);
7800 bp
->shmem_base
= HOST_VIEW_SHMEM_BASE
;
7802 /* Get the permanent MAC address. First we need to make sure the
7803 * firmware is actually running.
7805 reg
= bnx2_shmem_rd(bp
, BNX2_DEV_INFO_SIGNATURE
);
7807 if ((reg
& BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK
) !=
7808 BNX2_DEV_INFO_SIGNATURE_MAGIC
) {
7809 dev_err(&pdev
->dev
, "Firmware not running, aborting.\n");
7814 reg
= bnx2_shmem_rd(bp
, BNX2_DEV_INFO_BC_REV
);
7815 for (i
= 0, j
= 0; i
< 3; i
++) {
7818 num
= (u8
) (reg
>> (24 - (i
* 8)));
7819 for (k
= 100, skip0
= 1; k
>= 1; num
%= k
, k
/= 10) {
7820 if (num
>= k
|| !skip0
|| k
== 1) {
7821 bp
->fw_version
[j
++] = (num
/ k
) + '0';
7826 bp
->fw_version
[j
++] = '.';
7828 reg
= bnx2_shmem_rd(bp
, BNX2_PORT_FEATURE
);
7829 if (reg
& BNX2_PORT_FEATURE_WOL_ENABLED
)
7832 if (reg
& BNX2_PORT_FEATURE_ASF_ENABLED
) {
7833 bp
->flags
|= BNX2_FLAG_ASF_ENABLE
;
7835 for (i
= 0; i
< 30; i
++) {
7836 reg
= bnx2_shmem_rd(bp
, BNX2_BC_STATE_CONDITION
);
7837 if (reg
& BNX2_CONDITION_MFW_RUN_MASK
)
7842 reg
= bnx2_shmem_rd(bp
, BNX2_BC_STATE_CONDITION
);
7843 reg
&= BNX2_CONDITION_MFW_RUN_MASK
;
7844 if (reg
!= BNX2_CONDITION_MFW_RUN_UNKNOWN
&&
7845 reg
!= BNX2_CONDITION_MFW_RUN_NONE
) {
7846 u32 addr
= bnx2_shmem_rd(bp
, BNX2_MFW_VER_PTR
);
7848 bp
->fw_version
[j
++] = ' ';
7849 for (i
= 0; i
< 3; i
++) {
7850 reg
= bnx2_reg_rd_ind(bp
, addr
+ i
* 4);
7852 memcpy(&bp
->fw_version
[j
], ®
, 4);
7857 reg
= bnx2_shmem_rd(bp
, BNX2_PORT_HW_CFG_MAC_UPPER
);
7858 bp
->mac_addr
[0] = (u8
) (reg
>> 8);
7859 bp
->mac_addr
[1] = (u8
) reg
;
7861 reg
= bnx2_shmem_rd(bp
, BNX2_PORT_HW_CFG_MAC_LOWER
);
7862 bp
->mac_addr
[2] = (u8
) (reg
>> 24);
7863 bp
->mac_addr
[3] = (u8
) (reg
>> 16);
7864 bp
->mac_addr
[4] = (u8
) (reg
>> 8);
7865 bp
->mac_addr
[5] = (u8
) reg
;
7867 bp
->tx_ring_size
= MAX_TX_DESC_CNT
;
7868 bnx2_set_rx_ring_size(bp
, 255);
7872 bp
->tx_quick_cons_trip_int
= 2;
7873 bp
->tx_quick_cons_trip
= 20;
7874 bp
->tx_ticks_int
= 18;
7877 bp
->rx_quick_cons_trip_int
= 2;
7878 bp
->rx_quick_cons_trip
= 12;
7879 bp
->rx_ticks_int
= 18;
7882 bp
->stats_ticks
= USEC_PER_SEC
& BNX2_HC_STATS_TICKS_HC_STAT_TICKS
;
7884 bp
->current_interval
= BNX2_TIMER_INTERVAL
;
7888 /* Disable WOL support if we are running on a SERDES chip. */
7889 if (CHIP_NUM(bp
) == CHIP_NUM_5709
)
7890 bnx2_get_5709_media(bp
);
7891 else if (CHIP_BOND_ID(bp
) & CHIP_BOND_ID_SERDES_BIT
)
7892 bp
->phy_flags
|= BNX2_PHY_FLAG_SERDES
;
7894 bp
->phy_port
= PORT_TP
;
7895 if (bp
->phy_flags
& BNX2_PHY_FLAG_SERDES
) {
7896 bp
->phy_port
= PORT_FIBRE
;
7897 reg
= bnx2_shmem_rd(bp
, BNX2_SHARED_HW_CFG_CONFIG
);
7898 if (!(reg
& BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX
)) {
7899 bp
->flags
|= BNX2_FLAG_NO_WOL
;
7902 if (CHIP_NUM(bp
) == CHIP_NUM_5706
) {
7903 /* Don't do parallel detect on this board because of
7904 * some board problems. The link will not go down
7905 * if we do parallel detect.
7907 if (pdev
->subsystem_vendor
== PCI_VENDOR_ID_HP
&&
7908 pdev
->subsystem_device
== 0x310c)
7909 bp
->phy_flags
|= BNX2_PHY_FLAG_NO_PARALLEL
;
7912 if (reg
& BNX2_SHARED_HW_CFG_PHY_2_5G
)
7913 bp
->phy_flags
|= BNX2_PHY_FLAG_2_5G_CAPABLE
;
7915 } else if (CHIP_NUM(bp
) == CHIP_NUM_5706
||
7916 CHIP_NUM(bp
) == CHIP_NUM_5708
)
7917 bp
->phy_flags
|= BNX2_PHY_FLAG_CRC_FIX
;
7918 else if (CHIP_NUM(bp
) == CHIP_NUM_5709
&&
7919 (CHIP_REV(bp
) == CHIP_REV_Ax
||
7920 CHIP_REV(bp
) == CHIP_REV_Bx
))
7921 bp
->phy_flags
|= BNX2_PHY_FLAG_DIS_EARLY_DAC
;
7923 bnx2_init_fw_cap(bp
);
7925 if ((CHIP_ID(bp
) == CHIP_ID_5708_A0
) ||
7926 (CHIP_ID(bp
) == CHIP_ID_5708_B0
) ||
7927 (CHIP_ID(bp
) == CHIP_ID_5708_B1
) ||
7928 !(REG_RD(bp
, BNX2_PCI_CONFIG_3
) & BNX2_PCI_CONFIG_3_VAUX_PRESET
)) {
7929 bp
->flags
|= BNX2_FLAG_NO_WOL
;
7933 if (CHIP_ID(bp
) == CHIP_ID_5706_A0
) {
7934 bp
->tx_quick_cons_trip_int
=
7935 bp
->tx_quick_cons_trip
;
7936 bp
->tx_ticks_int
= bp
->tx_ticks
;
7937 bp
->rx_quick_cons_trip_int
=
7938 bp
->rx_quick_cons_trip
;
7939 bp
->rx_ticks_int
= bp
->rx_ticks
;
7940 bp
->comp_prod_trip_int
= bp
->comp_prod_trip
;
7941 bp
->com_ticks_int
= bp
->com_ticks
;
7942 bp
->cmd_ticks_int
= bp
->cmd_ticks
;
7945 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7947 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7948 * with byte enables disabled on the unused 32-bit word. This is legal
7949 * but causes problems on the AMD 8132 which will eventually stop
7950 * responding after a while.
7952 * AMD believes this incompatibility is unique to the 5706, and
7953 * prefers to locally disable MSI rather than globally disabling it.
7955 if (CHIP_NUM(bp
) == CHIP_NUM_5706
&& disable_msi
== 0) {
7956 struct pci_dev
*amd_8132
= NULL
;
7958 while ((amd_8132
= pci_get_device(PCI_VENDOR_ID_AMD
,
7959 PCI_DEVICE_ID_AMD_8132_BRIDGE
,
7962 if (amd_8132
->revision
>= 0x10 &&
7963 amd_8132
->revision
<= 0x13) {
7965 pci_dev_put(amd_8132
);
7971 bnx2_set_default_link(bp
);
7972 bp
->req_flow_ctrl
= FLOW_CTRL_RX
| FLOW_CTRL_TX
;
7974 init_timer(&bp
->timer
);
7975 bp
->timer
.expires
= RUN_AT(BNX2_TIMER_INTERVAL
);
7976 bp
->timer
.data
= (unsigned long) bp
;
7977 bp
->timer
.function
= bnx2_timer
;
7983 iounmap(bp
->regview
);
7988 pci_release_regions(pdev
);
7991 pci_disable_device(pdev
);
7992 pci_set_drvdata(pdev
, NULL
);
7998 static char * __devinit
7999 bnx2_bus_string(struct bnx2
*bp
, char *str
)
8003 if (bp
->flags
& BNX2_FLAG_PCIE
) {
8004 s
+= sprintf(s
, "PCI Express");
8006 s
+= sprintf(s
, "PCI");
8007 if (bp
->flags
& BNX2_FLAG_PCIX
)
8008 s
+= sprintf(s
, "-X");
8009 if (bp
->flags
& BNX2_FLAG_PCI_32BIT
)
8010 s
+= sprintf(s
, " 32-bit");
8012 s
+= sprintf(s
, " 64-bit");
8013 s
+= sprintf(s
, " %dMHz", bp
->bus_speed_mhz
);
8018 static void __devinit
8019 bnx2_init_napi(struct bnx2
*bp
)
8023 for (i
= 0; i
< BNX2_MAX_MSIX_VEC
; i
++) {
8024 struct bnx2_napi
*bnapi
= &bp
->bnx2_napi
[i
];
8025 int (*poll
)(struct napi_struct
*, int);
8030 poll
= bnx2_poll_msix
;
8032 netif_napi_add(bp
->dev
, &bp
->bnx2_napi
[i
].napi
, poll
, 64);
8037 static const struct net_device_ops bnx2_netdev_ops
= {
8038 .ndo_open
= bnx2_open
,
8039 .ndo_start_xmit
= bnx2_start_xmit
,
8040 .ndo_stop
= bnx2_close
,
8041 .ndo_get_stats
= bnx2_get_stats
,
8042 .ndo_set_rx_mode
= bnx2_set_rx_mode
,
8043 .ndo_do_ioctl
= bnx2_ioctl
,
8044 .ndo_validate_addr
= eth_validate_addr
,
8045 .ndo_set_mac_address
= bnx2_change_mac_addr
,
8046 .ndo_change_mtu
= bnx2_change_mtu
,
8047 .ndo_tx_timeout
= bnx2_tx_timeout
,
8049 .ndo_vlan_rx_register
= bnx2_vlan_rx_register
,
8051 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
8052 .ndo_poll_controller
= poll_bnx2
,
8056 static void inline vlan_features_add(struct net_device
*dev
, unsigned long flags
)
8059 dev
->vlan_features
|= flags
;
8063 static int __devinit
8064 bnx2_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
8066 static int version_printed
= 0;
8067 struct net_device
*dev
= NULL
;
8072 if (version_printed
++ == 0)
8073 printk(KERN_INFO
"%s", version
);
8075 /* dev zeroed in init_etherdev */
8076 dev
= alloc_etherdev_mq(sizeof(*bp
), TX_MAX_RINGS
);
8081 rc
= bnx2_init_board(pdev
, dev
);
8087 dev
->netdev_ops
= &bnx2_netdev_ops
;
8088 dev
->watchdog_timeo
= TX_TIMEOUT
;
8089 dev
->ethtool_ops
= &bnx2_ethtool_ops
;
8091 bp
= netdev_priv(dev
);
8094 pci_set_drvdata(pdev
, dev
);
8096 rc
= bnx2_request_firmware(bp
);
8100 memcpy(dev
->dev_addr
, bp
->mac_addr
, 6);
8101 memcpy(dev
->perm_addr
, bp
->mac_addr
, 6);
8103 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
8104 vlan_features_add(dev
, NETIF_F_IP_CSUM
| NETIF_F_SG
);
8105 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
8106 dev
->features
|= NETIF_F_IPV6_CSUM
;
8107 vlan_features_add(dev
, NETIF_F_IPV6_CSUM
);
8110 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
8112 dev
->features
|= NETIF_F_TSO
| NETIF_F_TSO_ECN
;
8113 vlan_features_add(dev
, NETIF_F_TSO
| NETIF_F_TSO_ECN
);
8114 if (CHIP_NUM(bp
) == CHIP_NUM_5709
) {
8115 dev
->features
|= NETIF_F_TSO6
;
8116 vlan_features_add(dev
, NETIF_F_TSO6
);
8118 if ((rc
= register_netdev(dev
))) {
8119 dev_err(&pdev
->dev
, "Cannot register net device\n");
8123 printk(KERN_INFO
"%s: %s (%c%d) %s found at mem %lx, "
8124 "IRQ %d, node addr %pM\n",
8126 board_info
[ent
->driver_data
].name
,
8127 ((CHIP_ID(bp
) & 0xf000) >> 12) + 'A',
8128 ((CHIP_ID(bp
) & 0x0ff0) >> 4),
8129 bnx2_bus_string(bp
, str
),
8131 bp
->pdev
->irq
, dev
->dev_addr
);
8136 if (bp
->mips_firmware
)
8137 release_firmware(bp
->mips_firmware
);
8138 if (bp
->rv2p_firmware
)
8139 release_firmware(bp
->rv2p_firmware
);
8142 iounmap(bp
->regview
);
8143 pci_release_regions(pdev
);
8144 pci_disable_device(pdev
);
8145 pci_set_drvdata(pdev
, NULL
);
8150 static void __devexit
8151 bnx2_remove_one(struct pci_dev
*pdev
)
8153 struct net_device
*dev
= pci_get_drvdata(pdev
);
8154 struct bnx2
*bp
= netdev_priv(dev
);
8156 flush_scheduled_work();
8158 unregister_netdev(dev
);
8160 if (bp
->mips_firmware
)
8161 release_firmware(bp
->mips_firmware
);
8162 if (bp
->rv2p_firmware
)
8163 release_firmware(bp
->rv2p_firmware
);
8166 iounmap(bp
->regview
);
8169 pci_release_regions(pdev
);
8170 pci_disable_device(pdev
);
8171 pci_set_drvdata(pdev
, NULL
);
8175 bnx2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
8177 struct net_device
*dev
= pci_get_drvdata(pdev
);
8178 struct bnx2
*bp
= netdev_priv(dev
);
8180 /* PCI register 4 needs to be saved whether netif_running() or not.
8181 * MSI address and data need to be saved if using MSI and
8184 pci_save_state(pdev
);
8185 if (!netif_running(dev
))
8188 flush_scheduled_work();
8189 bnx2_netif_stop(bp
);
8190 netif_device_detach(dev
);
8191 del_timer_sync(&bp
->timer
);
8192 bnx2_shutdown_chip(bp
);
8194 bnx2_set_power_state(bp
, pci_choose_state(pdev
, state
));
8199 bnx2_resume(struct pci_dev
*pdev
)
8201 struct net_device
*dev
= pci_get_drvdata(pdev
);
8202 struct bnx2
*bp
= netdev_priv(dev
);
8204 pci_restore_state(pdev
);
8205 if (!netif_running(dev
))
8208 bnx2_set_power_state(bp
, PCI_D0
);
8209 netif_device_attach(dev
);
8210 bnx2_init_nic(bp
, 1);
8211 bnx2_netif_start(bp
);
8216 * bnx2_io_error_detected - called when PCI error is detected
8217 * @pdev: Pointer to PCI device
8218 * @state: The current pci connection state
8220 * This function is called after a PCI bus error affecting
8221 * this device has been detected.
8223 static pci_ers_result_t
bnx2_io_error_detected(struct pci_dev
*pdev
,
8224 pci_channel_state_t state
)
8226 struct net_device
*dev
= pci_get_drvdata(pdev
);
8227 struct bnx2
*bp
= netdev_priv(dev
);
8230 netif_device_detach(dev
);
8232 if (state
== pci_channel_io_perm_failure
) {
8234 return PCI_ERS_RESULT_DISCONNECT
;
8237 if (netif_running(dev
)) {
8238 bnx2_netif_stop(bp
);
8239 del_timer_sync(&bp
->timer
);
8240 bnx2_reset_nic(bp
, BNX2_DRV_MSG_CODE_RESET
);
8243 pci_disable_device(pdev
);
8246 /* Request a slot slot reset. */
8247 return PCI_ERS_RESULT_NEED_RESET
;
8251 * bnx2_io_slot_reset - called after the pci bus has been reset.
8252 * @pdev: Pointer to PCI device
8254 * Restart the card from scratch, as if from a cold-boot.
8256 static pci_ers_result_t
bnx2_io_slot_reset(struct pci_dev
*pdev
)
8258 struct net_device
*dev
= pci_get_drvdata(pdev
);
8259 struct bnx2
*bp
= netdev_priv(dev
);
8262 if (pci_enable_device(pdev
)) {
8264 "Cannot re-enable PCI device after reset.\n");
8266 return PCI_ERS_RESULT_DISCONNECT
;
8268 pci_set_master(pdev
);
8269 pci_restore_state(pdev
);
8271 if (netif_running(dev
)) {
8272 bnx2_set_power_state(bp
, PCI_D0
);
8273 bnx2_init_nic(bp
, 1);
8277 return PCI_ERS_RESULT_RECOVERED
;
8281 * bnx2_io_resume - called when traffic can start flowing again.
8282 * @pdev: Pointer to PCI device
8284 * This callback is called when the error recovery driver tells us that
8285 * its OK to resume normal operation.
8287 static void bnx2_io_resume(struct pci_dev
*pdev
)
8289 struct net_device
*dev
= pci_get_drvdata(pdev
);
8290 struct bnx2
*bp
= netdev_priv(dev
);
8293 if (netif_running(dev
))
8294 bnx2_netif_start(bp
);
8296 netif_device_attach(dev
);
8300 static struct pci_error_handlers bnx2_err_handler
= {
8301 .error_detected
= bnx2_io_error_detected
,
8302 .slot_reset
= bnx2_io_slot_reset
,
8303 .resume
= bnx2_io_resume
,
8306 static struct pci_driver bnx2_pci_driver
= {
8307 .name
= DRV_MODULE_NAME
,
8308 .id_table
= bnx2_pci_tbl
,
8309 .probe
= bnx2_init_one
,
8310 .remove
= __devexit_p(bnx2_remove_one
),
8311 .suspend
= bnx2_suspend
,
8312 .resume
= bnx2_resume
,
8313 .err_handler
= &bnx2_err_handler
,
8316 static int __init
bnx2_init(void)
8318 return pci_register_driver(&bnx2_pci_driver
);
8321 static void __exit
bnx2_cleanup(void)
8323 pci_unregister_driver(&bnx2_pci_driver
);
8326 module_init(bnx2_init
);
8327 module_exit(bnx2_cleanup
);