2 * Copyright (C) 2005 - 2009 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
20 static void be_mcc_notify(struct be_ctrl_info
*ctrl
)
22 struct be_queue_info
*mccq
= &ctrl
->mcc_obj
.q
;
25 val
|= mccq
->id
& DB_MCCQ_RING_ID_MASK
;
26 val
|= 1 << DB_MCCQ_NUM_POSTED_SHIFT
;
27 iowrite32(val
, ctrl
->db
+ DB_MCCQ_OFFSET
);
30 /* To check if valid bit is set, check the entire word as we don't know
31 * the endianness of the data (old entry is host endian while a new entry is
33 static inline bool be_mcc_compl_is_new(struct be_mcc_cq_entry
*compl)
35 if (compl->flags
!= 0) {
36 compl->flags
= le32_to_cpu(compl->flags
);
37 BUG_ON((compl->flags
& CQE_FLAGS_VALID_MASK
) == 0);
44 /* Need to reset the entire word that houses the valid bit */
45 static inline void be_mcc_compl_use(struct be_mcc_cq_entry
*compl)
50 static int be_mcc_compl_process(struct be_ctrl_info
*ctrl
,
51 struct be_mcc_cq_entry
*compl)
53 u16 compl_status
, extd_status
;
55 /* Just swap the status to host endian; mcc tag is opaquely copied
57 be_dws_le_to_cpu(compl, 4);
59 compl_status
= (compl->status
>> CQE_STATUS_COMPL_SHIFT
) &
60 CQE_STATUS_COMPL_MASK
;
61 if (compl_status
!= MCC_STATUS_SUCCESS
) {
62 extd_status
= (compl->status
>> CQE_STATUS_EXTD_SHIFT
) &
64 printk(KERN_WARNING DRV_NAME
65 " error in cmd completion: status(compl/extd)=%d/%d\n",
66 compl_status
, extd_status
);
73 static struct be_mcc_cq_entry
*be_mcc_compl_get(struct be_ctrl_info
*ctrl
)
75 struct be_queue_info
*mcc_cq
= &ctrl
->mcc_obj
.cq
;
76 struct be_mcc_cq_entry
*compl = queue_tail_node(mcc_cq
);
78 if (be_mcc_compl_is_new(compl)) {
79 queue_tail_inc(mcc_cq
);
85 void be_process_mcc(struct be_ctrl_info
*ctrl
)
87 struct be_mcc_cq_entry
*compl;
90 spin_lock_bh(&ctrl
->mcc_cq_lock
);
91 while ((compl = be_mcc_compl_get(ctrl
))) {
92 if (!(compl->flags
& CQE_FLAGS_ASYNC_MASK
)) {
93 be_mcc_compl_process(ctrl
, compl);
94 atomic_dec(&ctrl
->mcc_obj
.q
.used
);
96 be_mcc_compl_use(compl);
100 be_cq_notify(ctrl
, ctrl
->mcc_obj
.cq
.id
, true, num
);
101 spin_unlock_bh(&ctrl
->mcc_cq_lock
);
104 /* Wait till no more pending mcc requests are present */
105 static void be_mcc_wait_compl(struct be_ctrl_info
*ctrl
)
107 #define mcc_timeout 50000 /* 5s timeout */
109 for (i
= 0; i
< mcc_timeout
; i
++) {
110 be_process_mcc(ctrl
);
111 if (atomic_read(&ctrl
->mcc_obj
.q
.used
) == 0)
115 if (i
== mcc_timeout
)
116 printk(KERN_WARNING DRV_NAME
"mcc poll timed out\n");
119 /* Notify MCC requests and wait for completion */
120 static void be_mcc_notify_wait(struct be_ctrl_info
*ctrl
)
123 be_mcc_wait_compl(ctrl
);
126 static int be_mbox_db_ready_wait(void __iomem
*db
)
128 int cnt
= 0, wait
= 5;
132 ready
= ioread32(db
) & MPU_MAILBOX_DB_RDY_MASK
;
137 printk(KERN_WARNING DRV_NAME
138 ": mbox_db poll timed out\n");
152 * Insert the mailbox address into the doorbell in two steps
153 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
155 static int be_mbox_db_ring(struct be_ctrl_info
*ctrl
)
159 void __iomem
*db
= ctrl
->db
+ MPU_MAILBOX_DB_OFFSET
;
160 struct be_dma_mem
*mbox_mem
= &ctrl
->mbox_mem
;
161 struct be_mcc_mailbox
*mbox
= mbox_mem
->va
;
162 struct be_mcc_cq_entry
*cqe
= &mbox
->cqe
;
164 memset(cqe
, 0, sizeof(*cqe
));
166 val
&= ~MPU_MAILBOX_DB_RDY_MASK
;
167 val
|= MPU_MAILBOX_DB_HI_MASK
;
168 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
169 val
|= (upper_32_bits(mbox_mem
->dma
) >> 2) << 2;
172 /* wait for ready to be set */
173 status
= be_mbox_db_ready_wait(db
);
178 val
&= ~MPU_MAILBOX_DB_RDY_MASK
;
179 val
&= ~MPU_MAILBOX_DB_HI_MASK
;
180 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
181 val
|= (u32
)(mbox_mem
->dma
>> 4) << 2;
184 status
= be_mbox_db_ready_wait(db
);
188 /* A cq entry has been made now */
189 if (be_mcc_compl_is_new(cqe
)) {
190 status
= be_mcc_compl_process(ctrl
, &mbox
->cqe
);
191 be_mcc_compl_use(cqe
);
195 printk(KERN_WARNING DRV_NAME
"invalid mailbox completion\n");
201 static int be_POST_stage_get(struct be_ctrl_info
*ctrl
, u16
*stage
)
203 u32 sem
= ioread32(ctrl
->csr
+ MPU_EP_SEMAPHORE_OFFSET
);
205 *stage
= sem
& EP_SEMAPHORE_POST_STAGE_MASK
;
206 if ((sem
>> EP_SEMAPHORE_POST_ERR_SHIFT
) & EP_SEMAPHORE_POST_ERR_MASK
)
212 static int be_POST_stage_poll(struct be_ctrl_info
*ctrl
, u16 poll_stage
)
214 u16 stage
, cnt
, error
;
215 for (cnt
= 0; cnt
< 5000; cnt
++) {
216 error
= be_POST_stage_get(ctrl
, &stage
);
220 if (stage
== poll_stage
)
224 if (stage
!= poll_stage
)
230 int be_cmd_POST(struct be_ctrl_info
*ctrl
)
234 error
= be_POST_stage_get(ctrl
, &stage
);
238 if (stage
== POST_STAGE_ARMFW_RDY
)
241 if (stage
!= POST_STAGE_AWAITING_HOST_RDY
)
244 /* On awaiting host rdy, reset and again poll on awaiting host rdy */
245 iowrite32(POST_STAGE_BE_RESET
, ctrl
->csr
+ MPU_EP_SEMAPHORE_OFFSET
);
246 error
= be_POST_stage_poll(ctrl
, POST_STAGE_AWAITING_HOST_RDY
);
250 /* Now kickoff POST and poll on armfw ready */
251 iowrite32(POST_STAGE_HOST_RDY
, ctrl
->csr
+ MPU_EP_SEMAPHORE_OFFSET
);
252 error
= be_POST_stage_poll(ctrl
, POST_STAGE_ARMFW_RDY
);
258 printk(KERN_WARNING DRV_NAME
": ERROR, stage=%d\n", stage
);
262 static inline void *embedded_payload(struct be_mcc_wrb
*wrb
)
264 return wrb
->payload
.embedded_payload
;
267 static inline struct be_sge
*nonembedded_sgl(struct be_mcc_wrb
*wrb
)
269 return &wrb
->payload
.sgl
[0];
272 /* Don't touch the hdr after it's prepared */
273 static void be_wrb_hdr_prepare(struct be_mcc_wrb
*wrb
, int payload_len
,
274 bool embedded
, u8 sge_cnt
)
277 wrb
->embedded
|= MCC_WRB_EMBEDDED_MASK
;
279 wrb
->embedded
|= (sge_cnt
& MCC_WRB_SGE_CNT_MASK
) <<
280 MCC_WRB_SGE_CNT_SHIFT
;
281 wrb
->payload_length
= payload_len
;
282 be_dws_cpu_to_le(wrb
, 20);
285 /* Don't touch the hdr after it's prepared */
286 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr
*req_hdr
,
287 u8 subsystem
, u8 opcode
, int cmd_len
)
289 req_hdr
->opcode
= opcode
;
290 req_hdr
->subsystem
= subsystem
;
291 req_hdr
->request_length
= cpu_to_le32(cmd_len
- sizeof(*req_hdr
));
294 static void be_cmd_page_addrs_prepare(struct phys_addr
*pages
, u32 max_pages
,
295 struct be_dma_mem
*mem
)
297 int i
, buf_pages
= min(PAGES_4K_SPANNED(mem
->va
, mem
->size
), max_pages
);
298 u64 dma
= (u64
)mem
->dma
;
300 for (i
= 0; i
< buf_pages
; i
++) {
301 pages
[i
].lo
= cpu_to_le32(dma
& 0xFFFFFFFF);
302 pages
[i
].hi
= cpu_to_le32(upper_32_bits(dma
));
307 /* Converts interrupt delay in microseconds to multiplier value */
308 static u32
eq_delay_to_mult(u32 usec_delay
)
310 #define MAX_INTR_RATE 651042
311 const u32 round
= 10;
317 u32 interrupt_rate
= 1000000 / usec_delay
;
318 /* Max delay, corresponding to the lowest interrupt rate */
319 if (interrupt_rate
== 0)
322 multiplier
= (MAX_INTR_RATE
- interrupt_rate
) * round
;
323 multiplier
/= interrupt_rate
;
324 /* Round the multiplier to the closest value.*/
325 multiplier
= (multiplier
+ round
/2) / round
;
326 multiplier
= min(multiplier
, (u32
)1023);
332 static inline struct be_mcc_wrb
*wrb_from_mbox(struct be_dma_mem
*mbox_mem
)
334 return &((struct be_mcc_mailbox
*)(mbox_mem
->va
))->wrb
;
337 static inline struct be_mcc_wrb
*wrb_from_mcc(struct be_queue_info
*mccq
)
339 struct be_mcc_wrb
*wrb
= NULL
;
340 if (atomic_read(&mccq
->used
) < mccq
->len
) {
341 wrb
= queue_head_node(mccq
);
342 queue_head_inc(mccq
);
343 atomic_inc(&mccq
->used
);
344 memset(wrb
, 0, sizeof(*wrb
));
349 int be_cmd_eq_create(struct be_ctrl_info
*ctrl
,
350 struct be_queue_info
*eq
, int eq_delay
)
352 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
353 struct be_cmd_req_eq_create
*req
= embedded_payload(wrb
);
354 struct be_cmd_resp_eq_create
*resp
= embedded_payload(wrb
);
355 struct be_dma_mem
*q_mem
= &eq
->dma_mem
;
358 spin_lock(&ctrl
->mbox_lock
);
359 memset(wrb
, 0, sizeof(*wrb
));
361 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
363 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
364 OPCODE_COMMON_EQ_CREATE
, sizeof(*req
));
366 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
368 AMAP_SET_BITS(struct amap_eq_context
, func
, req
->context
,
370 AMAP_SET_BITS(struct amap_eq_context
, valid
, req
->context
, 1);
372 AMAP_SET_BITS(struct amap_eq_context
, size
, req
->context
, 0);
373 AMAP_SET_BITS(struct amap_eq_context
, count
, req
->context
,
374 __ilog2_u32(eq
->len
/256));
375 AMAP_SET_BITS(struct amap_eq_context
, delaymult
, req
->context
,
376 eq_delay_to_mult(eq_delay
));
377 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
379 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
381 status
= be_mbox_db_ring(ctrl
);
383 eq
->id
= le16_to_cpu(resp
->eq_id
);
386 spin_unlock(&ctrl
->mbox_lock
);
390 int be_cmd_mac_addr_query(struct be_ctrl_info
*ctrl
, u8
*mac_addr
,
391 u8 type
, bool permanent
, u32 if_handle
)
393 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
394 struct be_cmd_req_mac_query
*req
= embedded_payload(wrb
);
395 struct be_cmd_resp_mac_query
*resp
= embedded_payload(wrb
);
398 spin_lock(&ctrl
->mbox_lock
);
399 memset(wrb
, 0, sizeof(*wrb
));
401 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
403 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
404 OPCODE_COMMON_NTWK_MAC_QUERY
, sizeof(*req
));
410 req
->if_id
= cpu_to_le16((u16
)if_handle
);
414 status
= be_mbox_db_ring(ctrl
);
416 memcpy(mac_addr
, resp
->mac
.addr
, ETH_ALEN
);
418 spin_unlock(&ctrl
->mbox_lock
);
422 int be_cmd_pmac_add(struct be_ctrl_info
*ctrl
, u8
*mac_addr
,
423 u32 if_id
, u32
*pmac_id
)
425 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
426 struct be_cmd_req_pmac_add
*req
= embedded_payload(wrb
);
429 spin_lock(&ctrl
->mbox_lock
);
430 memset(wrb
, 0, sizeof(*wrb
));
432 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
434 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
435 OPCODE_COMMON_NTWK_PMAC_ADD
, sizeof(*req
));
437 req
->if_id
= cpu_to_le32(if_id
);
438 memcpy(req
->mac_address
, mac_addr
, ETH_ALEN
);
440 status
= be_mbox_db_ring(ctrl
);
442 struct be_cmd_resp_pmac_add
*resp
= embedded_payload(wrb
);
443 *pmac_id
= le32_to_cpu(resp
->pmac_id
);
446 spin_unlock(&ctrl
->mbox_lock
);
450 int be_cmd_pmac_del(struct be_ctrl_info
*ctrl
, u32 if_id
, u32 pmac_id
)
452 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
453 struct be_cmd_req_pmac_del
*req
= embedded_payload(wrb
);
456 spin_lock(&ctrl
->mbox_lock
);
457 memset(wrb
, 0, sizeof(*wrb
));
459 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
461 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
462 OPCODE_COMMON_NTWK_PMAC_DEL
, sizeof(*req
));
464 req
->if_id
= cpu_to_le32(if_id
);
465 req
->pmac_id
= cpu_to_le32(pmac_id
);
467 status
= be_mbox_db_ring(ctrl
);
468 spin_unlock(&ctrl
->mbox_lock
);
473 int be_cmd_cq_create(struct be_ctrl_info
*ctrl
,
474 struct be_queue_info
*cq
, struct be_queue_info
*eq
,
475 bool sol_evts
, bool no_delay
, int coalesce_wm
)
477 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
478 struct be_cmd_req_cq_create
*req
= embedded_payload(wrb
);
479 struct be_cmd_resp_cq_create
*resp
= embedded_payload(wrb
);
480 struct be_dma_mem
*q_mem
= &cq
->dma_mem
;
481 void *ctxt
= &req
->context
;
484 spin_lock(&ctrl
->mbox_lock
);
485 memset(wrb
, 0, sizeof(*wrb
));
487 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
489 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
490 OPCODE_COMMON_CQ_CREATE
, sizeof(*req
));
492 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
494 AMAP_SET_BITS(struct amap_cq_context
, coalescwm
, ctxt
, coalesce_wm
);
495 AMAP_SET_BITS(struct amap_cq_context
, nodelay
, ctxt
, no_delay
);
496 AMAP_SET_BITS(struct amap_cq_context
, count
, ctxt
,
497 __ilog2_u32(cq
->len
/256));
498 AMAP_SET_BITS(struct amap_cq_context
, valid
, ctxt
, 1);
499 AMAP_SET_BITS(struct amap_cq_context
, solevent
, ctxt
, sol_evts
);
500 AMAP_SET_BITS(struct amap_cq_context
, eventable
, ctxt
, 1);
501 AMAP_SET_BITS(struct amap_cq_context
, eqid
, ctxt
, eq
->id
);
502 AMAP_SET_BITS(struct amap_cq_context
, armed
, ctxt
, 1);
503 AMAP_SET_BITS(struct amap_cq_context
, func
, ctxt
, ctrl
->pci_func
);
504 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
506 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
508 status
= be_mbox_db_ring(ctrl
);
510 cq
->id
= le16_to_cpu(resp
->cq_id
);
513 spin_unlock(&ctrl
->mbox_lock
);
518 static u32
be_encoded_q_len(int q_len
)
520 u32 len_encoded
= fls(q_len
); /* log2(len) + 1 */
521 if (len_encoded
== 16)
526 int be_cmd_mccq_create(struct be_ctrl_info
*ctrl
,
527 struct be_queue_info
*mccq
,
528 struct be_queue_info
*cq
)
530 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
531 struct be_cmd_req_mcc_create
*req
= embedded_payload(wrb
);
532 struct be_dma_mem
*q_mem
= &mccq
->dma_mem
;
533 void *ctxt
= &req
->context
;
536 spin_lock(&ctrl
->mbox_lock
);
537 memset(wrb
, 0, sizeof(*wrb
));
539 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
541 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
542 OPCODE_COMMON_MCC_CREATE
, sizeof(*req
));
544 req
->num_pages
= PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
);
546 AMAP_SET_BITS(struct amap_mcc_context
, fid
, ctxt
, ctrl
->pci_func
);
547 AMAP_SET_BITS(struct amap_mcc_context
, valid
, ctxt
, 1);
548 AMAP_SET_BITS(struct amap_mcc_context
, ring_size
, ctxt
,
549 be_encoded_q_len(mccq
->len
));
550 AMAP_SET_BITS(struct amap_mcc_context
, cq_id
, ctxt
, cq
->id
);
552 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
554 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
556 status
= be_mbox_db_ring(ctrl
);
558 struct be_cmd_resp_mcc_create
*resp
= embedded_payload(wrb
);
559 mccq
->id
= le16_to_cpu(resp
->id
);
560 mccq
->created
= true;
562 spin_unlock(&ctrl
->mbox_lock
);
567 int be_cmd_txq_create(struct be_ctrl_info
*ctrl
,
568 struct be_queue_info
*txq
,
569 struct be_queue_info
*cq
)
571 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
572 struct be_cmd_req_eth_tx_create
*req
= embedded_payload(wrb
);
573 struct be_dma_mem
*q_mem
= &txq
->dma_mem
;
574 void *ctxt
= &req
->context
;
578 spin_lock(&ctrl
->mbox_lock
);
579 memset(wrb
, 0, sizeof(*wrb
));
581 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
583 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
, OPCODE_ETH_TX_CREATE
,
586 req
->num_pages
= PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
);
587 req
->ulp_num
= BE_ULP1_NUM
;
588 req
->type
= BE_ETH_TX_RING_TYPE_STANDARD
;
590 len_encoded
= fls(txq
->len
); /* log2(len) + 1 */
591 if (len_encoded
== 16)
593 AMAP_SET_BITS(struct amap_tx_context
, tx_ring_size
, ctxt
, len_encoded
);
594 AMAP_SET_BITS(struct amap_tx_context
, pci_func_id
, ctxt
,
596 AMAP_SET_BITS(struct amap_tx_context
, ctx_valid
, ctxt
, 1);
597 AMAP_SET_BITS(struct amap_tx_context
, cq_id_send
, ctxt
, cq
->id
);
599 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
601 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
603 status
= be_mbox_db_ring(ctrl
);
605 struct be_cmd_resp_eth_tx_create
*resp
= embedded_payload(wrb
);
606 txq
->id
= le16_to_cpu(resp
->cid
);
609 spin_unlock(&ctrl
->mbox_lock
);
614 int be_cmd_rxq_create(struct be_ctrl_info
*ctrl
,
615 struct be_queue_info
*rxq
, u16 cq_id
, u16 frag_size
,
616 u16 max_frame_size
, u32 if_id
, u32 rss
)
618 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
619 struct be_cmd_req_eth_rx_create
*req
= embedded_payload(wrb
);
620 struct be_dma_mem
*q_mem
= &rxq
->dma_mem
;
623 spin_lock(&ctrl
->mbox_lock
);
624 memset(wrb
, 0, sizeof(*wrb
));
626 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
628 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
, OPCODE_ETH_RX_CREATE
,
631 req
->cq_id
= cpu_to_le16(cq_id
);
632 req
->frag_size
= fls(frag_size
) - 1;
634 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
635 req
->interface_id
= cpu_to_le32(if_id
);
636 req
->max_frame_size
= cpu_to_le16(max_frame_size
);
637 req
->rss_queue
= cpu_to_le32(rss
);
639 status
= be_mbox_db_ring(ctrl
);
641 struct be_cmd_resp_eth_rx_create
*resp
= embedded_payload(wrb
);
642 rxq
->id
= le16_to_cpu(resp
->id
);
645 spin_unlock(&ctrl
->mbox_lock
);
650 /* Generic destroyer function for all types of queues */
651 int be_cmd_q_destroy(struct be_ctrl_info
*ctrl
, struct be_queue_info
*q
,
654 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
655 struct be_cmd_req_q_destroy
*req
= embedded_payload(wrb
);
656 u8 subsys
= 0, opcode
= 0;
659 spin_lock(&ctrl
->mbox_lock
);
661 memset(wrb
, 0, sizeof(*wrb
));
662 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
664 switch (queue_type
) {
666 subsys
= CMD_SUBSYSTEM_COMMON
;
667 opcode
= OPCODE_COMMON_EQ_DESTROY
;
670 subsys
= CMD_SUBSYSTEM_COMMON
;
671 opcode
= OPCODE_COMMON_CQ_DESTROY
;
674 subsys
= CMD_SUBSYSTEM_ETH
;
675 opcode
= OPCODE_ETH_TX_DESTROY
;
678 subsys
= CMD_SUBSYSTEM_ETH
;
679 opcode
= OPCODE_ETH_RX_DESTROY
;
682 subsys
= CMD_SUBSYSTEM_COMMON
;
683 opcode
= OPCODE_COMMON_MCC_DESTROY
;
686 printk(KERN_WARNING DRV_NAME
":bad Q type in Q destroy cmd\n");
690 be_cmd_hdr_prepare(&req
->hdr
, subsys
, opcode
, sizeof(*req
));
691 req
->id
= cpu_to_le16(q
->id
);
693 status
= be_mbox_db_ring(ctrl
);
695 spin_unlock(&ctrl
->mbox_lock
);
700 /* Create an rx filtering policy configuration on an i/f */
701 int be_cmd_if_create(struct be_ctrl_info
*ctrl
, u32 flags
, u8
*mac
,
702 bool pmac_invalid
, u32
*if_handle
, u32
*pmac_id
)
704 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
705 struct be_cmd_req_if_create
*req
= embedded_payload(wrb
);
708 spin_lock(&ctrl
->mbox_lock
);
709 memset(wrb
, 0, sizeof(*wrb
));
711 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
713 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
714 OPCODE_COMMON_NTWK_INTERFACE_CREATE
, sizeof(*req
));
716 req
->capability_flags
= cpu_to_le32(flags
);
717 req
->enable_flags
= cpu_to_le32(flags
);
719 memcpy(req
->mac_addr
, mac
, ETH_ALEN
);
721 status
= be_mbox_db_ring(ctrl
);
723 struct be_cmd_resp_if_create
*resp
= embedded_payload(wrb
);
724 *if_handle
= le32_to_cpu(resp
->interface_id
);
726 *pmac_id
= le32_to_cpu(resp
->pmac_id
);
729 spin_unlock(&ctrl
->mbox_lock
);
733 int be_cmd_if_destroy(struct be_ctrl_info
*ctrl
, u32 interface_id
)
735 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
736 struct be_cmd_req_if_destroy
*req
= embedded_payload(wrb
);
739 spin_lock(&ctrl
->mbox_lock
);
740 memset(wrb
, 0, sizeof(*wrb
));
742 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
744 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
745 OPCODE_COMMON_NTWK_INTERFACE_DESTROY
, sizeof(*req
));
747 req
->interface_id
= cpu_to_le32(interface_id
);
748 status
= be_mbox_db_ring(ctrl
);
750 spin_unlock(&ctrl
->mbox_lock
);
755 /* Get stats is a non embedded command: the request is not embedded inside
756 * WRB but is a separate dma memory block
758 int be_cmd_get_stats(struct be_ctrl_info
*ctrl
, struct be_dma_mem
*nonemb_cmd
)
760 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
761 struct be_cmd_req_get_stats
*req
= nonemb_cmd
->va
;
762 struct be_sge
*sge
= nonembedded_sgl(wrb
);
765 spin_lock(&ctrl
->mbox_lock
);
766 memset(wrb
, 0, sizeof(*wrb
));
768 memset(req
, 0, sizeof(*req
));
770 be_wrb_hdr_prepare(wrb
, sizeof(*req
), false, 1);
772 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
773 OPCODE_ETH_GET_STATISTICS
, sizeof(*req
));
774 sge
->pa_hi
= cpu_to_le32(upper_32_bits(nonemb_cmd
->dma
));
775 sge
->pa_lo
= cpu_to_le32(nonemb_cmd
->dma
& 0xFFFFFFFF);
776 sge
->len
= cpu_to_le32(nonemb_cmd
->size
);
778 status
= be_mbox_db_ring(ctrl
);
780 struct be_cmd_resp_get_stats
*resp
= nonemb_cmd
->va
;
781 be_dws_le_to_cpu(&resp
->hw_stats
, sizeof(resp
->hw_stats
));
784 spin_unlock(&ctrl
->mbox_lock
);
788 int be_cmd_link_status_query(struct be_ctrl_info
*ctrl
,
789 struct be_link_info
*link
)
791 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
792 struct be_cmd_req_link_status
*req
= embedded_payload(wrb
);
795 spin_lock(&ctrl
->mbox_lock
);
796 memset(wrb
, 0, sizeof(*wrb
));
798 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
800 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
801 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY
, sizeof(*req
));
803 status
= be_mbox_db_ring(ctrl
);
805 struct be_cmd_resp_link_status
*resp
= embedded_payload(wrb
);
806 link
->speed
= resp
->mac_speed
;
807 link
->duplex
= resp
->mac_duplex
;
808 link
->fault
= resp
->mac_fault
;
810 link
->speed
= PHY_LINK_SPEED_ZERO
;
813 spin_unlock(&ctrl
->mbox_lock
);
817 int be_cmd_get_fw_ver(struct be_ctrl_info
*ctrl
, char *fw_ver
)
819 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
820 struct be_cmd_req_get_fw_version
*req
= embedded_payload(wrb
);
823 spin_lock(&ctrl
->mbox_lock
);
824 memset(wrb
, 0, sizeof(*wrb
));
826 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
828 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
829 OPCODE_COMMON_GET_FW_VERSION
, sizeof(*req
));
831 status
= be_mbox_db_ring(ctrl
);
833 struct be_cmd_resp_get_fw_version
*resp
= embedded_payload(wrb
);
834 strncpy(fw_ver
, resp
->firmware_version_string
, FW_VER_LEN
);
837 spin_unlock(&ctrl
->mbox_lock
);
841 /* set the EQ delay interval of an EQ to specified value */
842 int be_cmd_modify_eqd(struct be_ctrl_info
*ctrl
, u32 eq_id
, u32 eqd
)
844 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
845 struct be_cmd_req_modify_eq_delay
*req
= embedded_payload(wrb
);
848 spin_lock(&ctrl
->mbox_lock
);
849 memset(wrb
, 0, sizeof(*wrb
));
851 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
853 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
854 OPCODE_COMMON_MODIFY_EQ_DELAY
, sizeof(*req
));
856 req
->num_eq
= cpu_to_le32(1);
857 req
->delay
[0].eq_id
= cpu_to_le32(eq_id
);
858 req
->delay
[0].phase
= 0;
859 req
->delay
[0].delay_multiplier
= cpu_to_le32(eqd
);
861 status
= be_mbox_db_ring(ctrl
);
863 spin_unlock(&ctrl
->mbox_lock
);
867 int be_cmd_vlan_config(struct be_ctrl_info
*ctrl
, u32 if_id
, u16
*vtag_array
,
868 u32 num
, bool untagged
, bool promiscuous
)
870 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
871 struct be_cmd_req_vlan_config
*req
= embedded_payload(wrb
);
874 spin_lock(&ctrl
->mbox_lock
);
875 memset(wrb
, 0, sizeof(*wrb
));
877 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
879 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
880 OPCODE_COMMON_NTWK_VLAN_CONFIG
, sizeof(*req
));
882 req
->interface_id
= if_id
;
883 req
->promiscuous
= promiscuous
;
884 req
->untagged
= untagged
;
887 memcpy(req
->normal_vlan
, vtag_array
,
888 req
->num_vlan
* sizeof(vtag_array
[0]));
891 status
= be_mbox_db_ring(ctrl
);
893 spin_unlock(&ctrl
->mbox_lock
);
897 /* Use MCC for this command as it may be called in BH context */
898 int be_cmd_promiscuous_config(struct be_ctrl_info
*ctrl
, u8 port_num
, bool en
)
900 struct be_mcc_wrb
*wrb
;
901 struct be_cmd_req_promiscuous_config
*req
;
903 spin_lock_bh(&ctrl
->mcc_lock
);
905 wrb
= wrb_from_mcc(&ctrl
->mcc_obj
.q
);
908 req
= embedded_payload(wrb
);
910 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
912 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
913 OPCODE_ETH_PROMISCUOUS
, sizeof(*req
));
916 req
->port1_promiscuous
= en
;
918 req
->port0_promiscuous
= en
;
920 be_mcc_notify_wait(ctrl
);
922 spin_unlock_bh(&ctrl
->mcc_lock
);
927 * Use MCC for this command as it may be called in BH context
928 * (mc == NULL) => multicast promiscous
930 int be_cmd_multicast_set(struct be_ctrl_info
*ctrl
, u32 if_id
,
931 struct dev_mc_list
*mc_list
, u32 mc_count
)
933 #define BE_MAX_MC 32 /* set mcast promisc if > 32 */
934 struct be_mcc_wrb
*wrb
;
935 struct be_cmd_req_mcast_mac_config
*req
;
937 spin_lock_bh(&ctrl
->mcc_lock
);
939 wrb
= wrb_from_mcc(&ctrl
->mcc_obj
.q
);
942 req
= embedded_payload(wrb
);
944 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
946 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
947 OPCODE_COMMON_NTWK_MULTICAST_SET
, sizeof(*req
));
949 req
->interface_id
= if_id
;
950 if (mc_list
&& mc_count
<= BE_MAX_MC
) {
952 struct dev_mc_list
*mc
;
954 req
->num_mac
= cpu_to_le16(mc_count
);
956 for (mc
= mc_list
, i
= 0; mc
; mc
= mc
->next
, i
++)
957 memcpy(req
->mac
[i
].byte
, mc
->dmi_addr
, ETH_ALEN
);
959 req
->promiscuous
= 1;
962 be_mcc_notify_wait(ctrl
);
964 spin_unlock_bh(&ctrl
->mcc_lock
);
969 int be_cmd_set_flow_control(struct be_ctrl_info
*ctrl
, u32 tx_fc
, u32 rx_fc
)
971 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
972 struct be_cmd_req_set_flow_control
*req
= embedded_payload(wrb
);
975 spin_lock(&ctrl
->mbox_lock
);
977 memset(wrb
, 0, sizeof(*wrb
));
979 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
981 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
982 OPCODE_COMMON_SET_FLOW_CONTROL
, sizeof(*req
));
984 req
->tx_flow_control
= cpu_to_le16((u16
)tx_fc
);
985 req
->rx_flow_control
= cpu_to_le16((u16
)rx_fc
);
987 status
= be_mbox_db_ring(ctrl
);
989 spin_unlock(&ctrl
->mbox_lock
);
993 int be_cmd_get_flow_control(struct be_ctrl_info
*ctrl
, u32
*tx_fc
, u32
*rx_fc
)
995 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
996 struct be_cmd_req_get_flow_control
*req
= embedded_payload(wrb
);
999 spin_lock(&ctrl
->mbox_lock
);
1001 memset(wrb
, 0, sizeof(*wrb
));
1003 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
1005 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1006 OPCODE_COMMON_GET_FLOW_CONTROL
, sizeof(*req
));
1008 status
= be_mbox_db_ring(ctrl
);
1010 struct be_cmd_resp_get_flow_control
*resp
=
1011 embedded_payload(wrb
);
1012 *tx_fc
= le16_to_cpu(resp
->tx_flow_control
);
1013 *rx_fc
= le16_to_cpu(resp
->rx_flow_control
);
1016 spin_unlock(&ctrl
->mbox_lock
);
1020 int be_cmd_query_fw_cfg(struct be_ctrl_info
*ctrl
, u32
*port_num
)
1022 struct be_mcc_wrb
*wrb
= wrb_from_mbox(&ctrl
->mbox_mem
);
1023 struct be_cmd_req_query_fw_cfg
*req
= embedded_payload(wrb
);
1026 spin_lock(&ctrl
->mbox_lock
);
1028 memset(wrb
, 0, sizeof(*wrb
));
1030 be_wrb_hdr_prepare(wrb
, sizeof(*req
), true, 0);
1032 be_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1033 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG
, sizeof(*req
));
1035 status
= be_mbox_db_ring(ctrl
);
1037 struct be_cmd_resp_query_fw_cfg
*resp
= embedded_payload(wrb
);
1038 *port_num
= le32_to_cpu(resp
->phys_port
);
1041 spin_unlock(&ctrl
->mbox_lock
);