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x86, bts: DS and BTS initialization
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / atlx / atl1.c
1 /*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called COPYING.
25 *
26 * Contact Information:
27 * Xiong Huang <xiong.huang@atheros.com>
28 * Jie Yang <jie.yang@atheros.com>
29 * Chris Snook <csnook@redhat.com>
30 * Jay Cliburn <jcliburn@gmail.com>
31 *
32 * This version is adapted from the Attansic reference driver.
33 *
34 * TODO:
35 * Add more ethtool functions.
36 * Fix abstruse irq enable/disable condition described here:
37 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
38 *
39 * NEEDS TESTING:
40 * VLAN
41 * multicast
42 * promiscuous mode
43 * interrupt coalescing
44 * SMP torture testing
45 */
46
47 #include <asm/atomic.h>
48 #include <asm/byteorder.h>
49
50 #include <linux/compiler.h>
51 #include <linux/crc32.h>
52 #include <linux/delay.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/etherdevice.h>
55 #include <linux/hardirq.h>
56 #include <linux/if_ether.h>
57 #include <linux/if_vlan.h>
58 #include <linux/in.h>
59 #include <linux/interrupt.h>
60 #include <linux/ip.h>
61 #include <linux/irqflags.h>
62 #include <linux/irqreturn.h>
63 #include <linux/jiffies.h>
64 #include <linux/mii.h>
65 #include <linux/module.h>
66 #include <linux/moduleparam.h>
67 #include <linux/net.h>
68 #include <linux/netdevice.h>
69 #include <linux/pci.h>
70 #include <linux/pci_ids.h>
71 #include <linux/pm.h>
72 #include <linux/skbuff.h>
73 #include <linux/slab.h>
74 #include <linux/spinlock.h>
75 #include <linux/string.h>
76 #include <linux/tcp.h>
77 #include <linux/timer.h>
78 #include <linux/types.h>
79 #include <linux/workqueue.h>
80
81 #include <net/checksum.h>
82
83 #include "atl1.h"
84
85 /* Temporary hack for merging atl1 and atl2 */
86 #include "atlx.c"
87
88 /*
89 * This is the only thing that needs to be changed to adjust the
90 * maximum number of ports that the driver can manage.
91 */
92 #define ATL1_MAX_NIC 4
93
94 #define OPTION_UNSET -1
95 #define OPTION_DISABLED 0
96 #define OPTION_ENABLED 1
97
98 #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
99
100 /*
101 * Interrupt Moderate Timer in units of 2 us
102 *
103 * Valid Range: 10-65535
104 *
105 * Default Value: 100 (200us)
106 */
107 static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
108 static int num_int_mod_timer;
109 module_param_array_named(int_mod_timer, int_mod_timer, int,
110 &num_int_mod_timer, 0);
111 MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
112
113 #define DEFAULT_INT_MOD_CNT 100 /* 200us */
114 #define MAX_INT_MOD_CNT 65000
115 #define MIN_INT_MOD_CNT 50
116
117 struct atl1_option {
118 enum { enable_option, range_option, list_option } type;
119 char *name;
120 char *err;
121 int def;
122 union {
123 struct { /* range_option info */
124 int min;
125 int max;
126 } r;
127 struct { /* list_option info */
128 int nr;
129 struct atl1_opt_list {
130 int i;
131 char *str;
132 } *p;
133 } l;
134 } arg;
135 };
136
137 static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
138 struct pci_dev *pdev)
139 {
140 if (*value == OPTION_UNSET) {
141 *value = opt->def;
142 return 0;
143 }
144
145 switch (opt->type) {
146 case enable_option:
147 switch (*value) {
148 case OPTION_ENABLED:
149 dev_info(&pdev->dev, "%s enabled\n", opt->name);
150 return 0;
151 case OPTION_DISABLED:
152 dev_info(&pdev->dev, "%s disabled\n", opt->name);
153 return 0;
154 }
155 break;
156 case range_option:
157 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
158 dev_info(&pdev->dev, "%s set to %i\n", opt->name,
159 *value);
160 return 0;
161 }
162 break;
163 case list_option:{
164 int i;
165 struct atl1_opt_list *ent;
166
167 for (i = 0; i < opt->arg.l.nr; i++) {
168 ent = &opt->arg.l.p[i];
169 if (*value == ent->i) {
170 if (ent->str[0] != '\0')
171 dev_info(&pdev->dev, "%s\n",
172 ent->str);
173 return 0;
174 }
175 }
176 }
177 break;
178
179 default:
180 break;
181 }
182
183 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
184 opt->name, *value, opt->err);
185 *value = opt->def;
186 return -1;
187 }
188
189 /*
190 * atl1_check_options - Range Checking for Command Line Parameters
191 * @adapter: board private structure
192 *
193 * This routine checks all command line parameters for valid user
194 * input. If an invalid value is given, or if no user specified
195 * value exists, a default value is used. The final value is stored
196 * in a variable in the adapter structure.
197 */
198 void __devinit atl1_check_options(struct atl1_adapter *adapter)
199 {
200 struct pci_dev *pdev = adapter->pdev;
201 int bd = adapter->bd_number;
202 if (bd >= ATL1_MAX_NIC) {
203 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
204 dev_notice(&pdev->dev, "using defaults for all values\n");
205 }
206 { /* Interrupt Moderate Timer */
207 struct atl1_option opt = {
208 .type = range_option,
209 .name = "Interrupt Moderator Timer",
210 .err = "using default of "
211 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
212 .def = DEFAULT_INT_MOD_CNT,
213 .arg = {.r = {.min = MIN_INT_MOD_CNT,
214 .max = MAX_INT_MOD_CNT} }
215 };
216 int val;
217 if (num_int_mod_timer > bd) {
218 val = int_mod_timer[bd];
219 atl1_validate_option(&val, &opt, pdev);
220 adapter->imt = (u16) val;
221 } else
222 adapter->imt = (u16) (opt.def);
223 }
224 }
225
226 /*
227 * atl1_pci_tbl - PCI Device ID Table
228 */
229 static const struct pci_device_id atl1_pci_tbl[] = {
230 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
231 /* required last entry */
232 {0,}
233 };
234 MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
235
236 static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
237 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
238
239 static int debug = -1;
240 module_param(debug, int, 0);
241 MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
242
243 /*
244 * Reset the transmit and receive units; mask and clear all interrupts.
245 * hw - Struct containing variables accessed by shared code
246 * return : 0 or idle status (if error)
247 */
248 static s32 atl1_reset_hw(struct atl1_hw *hw)
249 {
250 struct pci_dev *pdev = hw->back->pdev;
251 struct atl1_adapter *adapter = hw->back;
252 u32 icr;
253 int i;
254
255 /*
256 * Clear Interrupt mask to stop board from generating
257 * interrupts & Clear any pending interrupt events
258 */
259 /*
260 * iowrite32(0, hw->hw_addr + REG_IMR);
261 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
262 */
263
264 /*
265 * Issue Soft Reset to the MAC. This will reset the chip's
266 * transmit, receive, DMA. It will not effect
267 * the current PCI configuration. The global reset bit is self-
268 * clearing, and should clear within a microsecond.
269 */
270 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
271 ioread32(hw->hw_addr + REG_MASTER_CTRL);
272
273 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
274 ioread16(hw->hw_addr + REG_PHY_ENABLE);
275
276 /* delay about 1ms */
277 msleep(1);
278
279 /* Wait at least 10ms for All module to be Idle */
280 for (i = 0; i < 10; i++) {
281 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
282 if (!icr)
283 break;
284 /* delay 1 ms */
285 msleep(1);
286 /* FIXME: still the right way to do this? */
287 cpu_relax();
288 }
289
290 if (icr) {
291 if (netif_msg_hw(adapter))
292 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
293 return icr;
294 }
295
296 return 0;
297 }
298
299 /* function about EEPROM
300 *
301 * check_eeprom_exist
302 * return 0 if eeprom exist
303 */
304 static int atl1_check_eeprom_exist(struct atl1_hw *hw)
305 {
306 u32 value;
307 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
308 if (value & SPI_FLASH_CTRL_EN_VPD) {
309 value &= ~SPI_FLASH_CTRL_EN_VPD;
310 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
311 }
312
313 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
314 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
315 }
316
317 static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
318 {
319 int i;
320 u32 control;
321
322 if (offset & 3)
323 /* address do not align */
324 return false;
325
326 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
327 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
328 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
329 ioread32(hw->hw_addr + REG_VPD_CAP);
330
331 for (i = 0; i < 10; i++) {
332 msleep(2);
333 control = ioread32(hw->hw_addr + REG_VPD_CAP);
334 if (control & VPD_CAP_VPD_FLAG)
335 break;
336 }
337 if (control & VPD_CAP_VPD_FLAG) {
338 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
339 return true;
340 }
341 /* timeout */
342 return false;
343 }
344
345 /*
346 * Reads the value from a PHY register
347 * hw - Struct containing variables accessed by shared code
348 * reg_addr - address of the PHY register to read
349 */
350 s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
351 {
352 u32 val;
353 int i;
354
355 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
356 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
357 MDIO_CLK_SEL_SHIFT;
358 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
359 ioread32(hw->hw_addr + REG_MDIO_CTRL);
360
361 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
362 udelay(2);
363 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
364 if (!(val & (MDIO_START | MDIO_BUSY)))
365 break;
366 }
367 if (!(val & (MDIO_START | MDIO_BUSY))) {
368 *phy_data = (u16) val;
369 return 0;
370 }
371 return ATLX_ERR_PHY;
372 }
373
374 #define CUSTOM_SPI_CS_SETUP 2
375 #define CUSTOM_SPI_CLK_HI 2
376 #define CUSTOM_SPI_CLK_LO 2
377 #define CUSTOM_SPI_CS_HOLD 2
378 #define CUSTOM_SPI_CS_HI 3
379
380 static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
381 {
382 int i;
383 u32 value;
384
385 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
386 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
387
388 value = SPI_FLASH_CTRL_WAIT_READY |
389 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
390 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
391 SPI_FLASH_CTRL_CLK_HI_MASK) <<
392 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
393 SPI_FLASH_CTRL_CLK_LO_MASK) <<
394 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
395 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
396 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
397 SPI_FLASH_CTRL_CS_HI_MASK) <<
398 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
399 SPI_FLASH_CTRL_INS_SHIFT;
400
401 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
402
403 value |= SPI_FLASH_CTRL_START;
404 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
405 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
406
407 for (i = 0; i < 10; i++) {
408 msleep(1);
409 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
410 if (!(value & SPI_FLASH_CTRL_START))
411 break;
412 }
413
414 if (value & SPI_FLASH_CTRL_START)
415 return false;
416
417 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
418
419 return true;
420 }
421
422 /*
423 * get_permanent_address
424 * return 0 if get valid mac address,
425 */
426 static int atl1_get_permanent_address(struct atl1_hw *hw)
427 {
428 u32 addr[2];
429 u32 i, control;
430 u16 reg;
431 u8 eth_addr[ETH_ALEN];
432 bool key_valid;
433
434 if (is_valid_ether_addr(hw->perm_mac_addr))
435 return 0;
436
437 /* init */
438 addr[0] = addr[1] = 0;
439
440 if (!atl1_check_eeprom_exist(hw)) {
441 reg = 0;
442 key_valid = false;
443 /* Read out all EEPROM content */
444 i = 0;
445 while (1) {
446 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
447 if (key_valid) {
448 if (reg == REG_MAC_STA_ADDR)
449 addr[0] = control;
450 else if (reg == (REG_MAC_STA_ADDR + 4))
451 addr[1] = control;
452 key_valid = false;
453 } else if ((control & 0xff) == 0x5A) {
454 key_valid = true;
455 reg = (u16) (control >> 16);
456 } else
457 break;
458 } else
459 /* read error */
460 break;
461 i += 4;
462 }
463
464 *(u32 *) &eth_addr[2] = swab32(addr[0]);
465 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
466 if (is_valid_ether_addr(eth_addr)) {
467 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
468 return 0;
469 }
470 }
471
472 /* see if SPI FLAGS exist ? */
473 addr[0] = addr[1] = 0;
474 reg = 0;
475 key_valid = false;
476 i = 0;
477 while (1) {
478 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
479 if (key_valid) {
480 if (reg == REG_MAC_STA_ADDR)
481 addr[0] = control;
482 else if (reg == (REG_MAC_STA_ADDR + 4))
483 addr[1] = control;
484 key_valid = false;
485 } else if ((control & 0xff) == 0x5A) {
486 key_valid = true;
487 reg = (u16) (control >> 16);
488 } else
489 /* data end */
490 break;
491 } else
492 /* read error */
493 break;
494 i += 4;
495 }
496
497 *(u32 *) &eth_addr[2] = swab32(addr[0]);
498 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
499 if (is_valid_ether_addr(eth_addr)) {
500 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
501 return 0;
502 }
503
504 /*
505 * On some motherboards, the MAC address is written by the
506 * BIOS directly to the MAC register during POST, and is
507 * not stored in eeprom. If all else thus far has failed
508 * to fetch the permanent MAC address, try reading it directly.
509 */
510 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
511 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
512 *(u32 *) &eth_addr[2] = swab32(addr[0]);
513 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
514 if (is_valid_ether_addr(eth_addr)) {
515 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
516 return 0;
517 }
518
519 return 1;
520 }
521
522 /*
523 * Reads the adapter's MAC address from the EEPROM
524 * hw - Struct containing variables accessed by shared code
525 */
526 s32 atl1_read_mac_addr(struct atl1_hw *hw)
527 {
528 u16 i;
529
530 if (atl1_get_permanent_address(hw))
531 random_ether_addr(hw->perm_mac_addr);
532
533 for (i = 0; i < ETH_ALEN; i++)
534 hw->mac_addr[i] = hw->perm_mac_addr[i];
535 return 0;
536 }
537
538 /*
539 * Hashes an address to determine its location in the multicast table
540 * hw - Struct containing variables accessed by shared code
541 * mc_addr - the multicast address to hash
542 *
543 * atl1_hash_mc_addr
544 * purpose
545 * set hash value for a multicast address
546 * hash calcu processing :
547 * 1. calcu 32bit CRC for multicast address
548 * 2. reverse crc with MSB to LSB
549 */
550 u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
551 {
552 u32 crc32, value = 0;
553 int i;
554
555 crc32 = ether_crc_le(6, mc_addr);
556 for (i = 0; i < 32; i++)
557 value |= (((crc32 >> i) & 1) << (31 - i));
558
559 return value;
560 }
561
562 /*
563 * Sets the bit in the multicast table corresponding to the hash value.
564 * hw - Struct containing variables accessed by shared code
565 * hash_value - Multicast address hash value
566 */
567 void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
568 {
569 u32 hash_bit, hash_reg;
570 u32 mta;
571
572 /*
573 * The HASH Table is a register array of 2 32-bit registers.
574 * It is treated like an array of 64 bits. We want to set
575 * bit BitArray[hash_value]. So we figure out what register
576 * the bit is in, read it, OR in the new bit, then write
577 * back the new value. The register is determined by the
578 * upper 7 bits of the hash value and the bit within that
579 * register are determined by the lower 5 bits of the value.
580 */
581 hash_reg = (hash_value >> 31) & 0x1;
582 hash_bit = (hash_value >> 26) & 0x1F;
583 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
584 mta |= (1 << hash_bit);
585 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
586 }
587
588 /*
589 * Writes a value to a PHY register
590 * hw - Struct containing variables accessed by shared code
591 * reg_addr - address of the PHY register to write
592 * data - data to write to the PHY
593 */
594 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
595 {
596 int i;
597 u32 val;
598
599 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
600 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
601 MDIO_SUP_PREAMBLE |
602 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
603 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
604 ioread32(hw->hw_addr + REG_MDIO_CTRL);
605
606 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
607 udelay(2);
608 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
609 if (!(val & (MDIO_START | MDIO_BUSY)))
610 break;
611 }
612
613 if (!(val & (MDIO_START | MDIO_BUSY)))
614 return 0;
615
616 return ATLX_ERR_PHY;
617 }
618
619 /*
620 * Make L001's PHY out of Power Saving State (bug)
621 * hw - Struct containing variables accessed by shared code
622 * when power on, L001's PHY always on Power saving State
623 * (Gigabit Link forbidden)
624 */
625 static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
626 {
627 s32 ret;
628 ret = atl1_write_phy_reg(hw, 29, 0x0029);
629 if (ret)
630 return ret;
631 return atl1_write_phy_reg(hw, 30, 0);
632 }
633
634 /*
635 * Resets the PHY and make all config validate
636 * hw - Struct containing variables accessed by shared code
637 *
638 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
639 */
640 static s32 atl1_phy_reset(struct atl1_hw *hw)
641 {
642 struct pci_dev *pdev = hw->back->pdev;
643 struct atl1_adapter *adapter = hw->back;
644 s32 ret_val;
645 u16 phy_data;
646
647 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
648 hw->media_type == MEDIA_TYPE_1000M_FULL)
649 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
650 else {
651 switch (hw->media_type) {
652 case MEDIA_TYPE_100M_FULL:
653 phy_data =
654 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
655 MII_CR_RESET;
656 break;
657 case MEDIA_TYPE_100M_HALF:
658 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
659 break;
660 case MEDIA_TYPE_10M_FULL:
661 phy_data =
662 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
663 break;
664 default:
665 /* MEDIA_TYPE_10M_HALF: */
666 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
667 break;
668 }
669 }
670
671 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
672 if (ret_val) {
673 u32 val;
674 int i;
675 /* pcie serdes link may be down! */
676 if (netif_msg_hw(adapter))
677 dev_dbg(&pdev->dev, "pcie phy link down\n");
678
679 for (i = 0; i < 25; i++) {
680 msleep(1);
681 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
682 if (!(val & (MDIO_START | MDIO_BUSY)))
683 break;
684 }
685
686 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
687 if (netif_msg_hw(adapter))
688 dev_warn(&pdev->dev,
689 "pcie link down at least 25ms\n");
690 return ret_val;
691 }
692 }
693 return 0;
694 }
695
696 /*
697 * Configures PHY autoneg and flow control advertisement settings
698 * hw - Struct containing variables accessed by shared code
699 */
700 static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
701 {
702 s32 ret_val;
703 s16 mii_autoneg_adv_reg;
704 s16 mii_1000t_ctrl_reg;
705
706 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
707 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
708
709 /* Read the MII 1000Base-T Control Register (Address 9). */
710 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
711
712 /*
713 * First we clear all the 10/100 mb speed bits in the Auto-Neg
714 * Advertisement Register (Address 4) and the 1000 mb speed bits in
715 * the 1000Base-T Control Register (Address 9).
716 */
717 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
718 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
719
720 /*
721 * Need to parse media_type and set up
722 * the appropriate PHY registers.
723 */
724 switch (hw->media_type) {
725 case MEDIA_TYPE_AUTO_SENSOR:
726 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
727 MII_AR_10T_FD_CAPS |
728 MII_AR_100TX_HD_CAPS |
729 MII_AR_100TX_FD_CAPS);
730 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
731 break;
732
733 case MEDIA_TYPE_1000M_FULL:
734 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
735 break;
736
737 case MEDIA_TYPE_100M_FULL:
738 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
739 break;
740
741 case MEDIA_TYPE_100M_HALF:
742 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
743 break;
744
745 case MEDIA_TYPE_10M_FULL:
746 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
747 break;
748
749 default:
750 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
751 break;
752 }
753
754 /* flow control fixed to enable all */
755 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
756
757 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
758 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
759
760 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
761 if (ret_val)
762 return ret_val;
763
764 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
765 if (ret_val)
766 return ret_val;
767
768 return 0;
769 }
770
771 /*
772 * Configures link settings.
773 * hw - Struct containing variables accessed by shared code
774 * Assumes the hardware has previously been reset and the
775 * transmitter and receiver are not enabled.
776 */
777 static s32 atl1_setup_link(struct atl1_hw *hw)
778 {
779 struct pci_dev *pdev = hw->back->pdev;
780 struct atl1_adapter *adapter = hw->back;
781 s32 ret_val;
782
783 /*
784 * Options:
785 * PHY will advertise value(s) parsed from
786 * autoneg_advertised and fc
787 * no matter what autoneg is , We will not wait link result.
788 */
789 ret_val = atl1_phy_setup_autoneg_adv(hw);
790 if (ret_val) {
791 if (netif_msg_link(adapter))
792 dev_dbg(&pdev->dev,
793 "error setting up autonegotiation\n");
794 return ret_val;
795 }
796 /* SW.Reset , En-Auto-Neg if needed */
797 ret_val = atl1_phy_reset(hw);
798 if (ret_val) {
799 if (netif_msg_link(adapter))
800 dev_dbg(&pdev->dev, "error resetting phy\n");
801 return ret_val;
802 }
803 hw->phy_configured = true;
804 return ret_val;
805 }
806
807 static void atl1_init_flash_opcode(struct atl1_hw *hw)
808 {
809 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
810 /* Atmel */
811 hw->flash_vendor = 0;
812
813 /* Init OP table */
814 iowrite8(flash_table[hw->flash_vendor].cmd_program,
815 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
816 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
817 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
818 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
819 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
820 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
821 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
822 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
823 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
824 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
825 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
826 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
827 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
828 iowrite8(flash_table[hw->flash_vendor].cmd_read,
829 hw->hw_addr + REG_SPI_FLASH_OP_READ);
830 }
831
832 /*
833 * Performs basic configuration of the adapter.
834 * hw - Struct containing variables accessed by shared code
835 * Assumes that the controller has previously been reset and is in a
836 * post-reset uninitialized state. Initializes multicast table,
837 * and Calls routines to setup link
838 * Leaves the transmit and receive units disabled and uninitialized.
839 */
840 static s32 atl1_init_hw(struct atl1_hw *hw)
841 {
842 u32 ret_val = 0;
843
844 /* Zero out the Multicast HASH table */
845 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
846 /* clear the old settings from the multicast hash table */
847 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
848
849 atl1_init_flash_opcode(hw);
850
851 if (!hw->phy_configured) {
852 /* enable GPHY LinkChange Interrrupt */
853 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
854 if (ret_val)
855 return ret_val;
856 /* make PHY out of power-saving state */
857 ret_val = atl1_phy_leave_power_saving(hw);
858 if (ret_val)
859 return ret_val;
860 /* Call a subroutine to configure the link */
861 ret_val = atl1_setup_link(hw);
862 }
863 return ret_val;
864 }
865
866 /*
867 * Detects the current speed and duplex settings of the hardware.
868 * hw - Struct containing variables accessed by shared code
869 * speed - Speed of the connection
870 * duplex - Duplex setting of the connection
871 */
872 static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
873 {
874 struct pci_dev *pdev = hw->back->pdev;
875 struct atl1_adapter *adapter = hw->back;
876 s32 ret_val;
877 u16 phy_data;
878
879 /* ; --- Read PHY Specific Status Register (17) */
880 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
881 if (ret_val)
882 return ret_val;
883
884 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
885 return ATLX_ERR_PHY_RES;
886
887 switch (phy_data & MII_ATLX_PSSR_SPEED) {
888 case MII_ATLX_PSSR_1000MBS:
889 *speed = SPEED_1000;
890 break;
891 case MII_ATLX_PSSR_100MBS:
892 *speed = SPEED_100;
893 break;
894 case MII_ATLX_PSSR_10MBS:
895 *speed = SPEED_10;
896 break;
897 default:
898 if (netif_msg_hw(adapter))
899 dev_dbg(&pdev->dev, "error getting speed\n");
900 return ATLX_ERR_PHY_SPEED;
901 break;
902 }
903 if (phy_data & MII_ATLX_PSSR_DPLX)
904 *duplex = FULL_DUPLEX;
905 else
906 *duplex = HALF_DUPLEX;
907
908 return 0;
909 }
910
911 void atl1_set_mac_addr(struct atl1_hw *hw)
912 {
913 u32 value;
914 /*
915 * 00-0B-6A-F6-00-DC
916 * 0: 6AF600DC 1: 000B
917 * low dword
918 */
919 value = (((u32) hw->mac_addr[2]) << 24) |
920 (((u32) hw->mac_addr[3]) << 16) |
921 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
922 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
923 /* high dword */
924 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
925 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
926 }
927
928 /*
929 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
930 * @adapter: board private structure to initialize
931 *
932 * atl1_sw_init initializes the Adapter private data structure.
933 * Fields are initialized based on PCI device information and
934 * OS network device settings (MTU size).
935 */
936 static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
937 {
938 struct atl1_hw *hw = &adapter->hw;
939 struct net_device *netdev = adapter->netdev;
940
941 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
942 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
943
944 adapter->wol = 0;
945 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
946 adapter->ict = 50000; /* 100ms */
947 adapter->link_speed = SPEED_0; /* hardware init */
948 adapter->link_duplex = FULL_DUPLEX;
949
950 hw->phy_configured = false;
951 hw->preamble_len = 7;
952 hw->ipgt = 0x60;
953 hw->min_ifg = 0x50;
954 hw->ipgr1 = 0x40;
955 hw->ipgr2 = 0x60;
956 hw->max_retry = 0xf;
957 hw->lcol = 0x37;
958 hw->jam_ipg = 7;
959 hw->rfd_burst = 8;
960 hw->rrd_burst = 8;
961 hw->rfd_fetch_gap = 1;
962 hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
963 hw->rx_jumbo_lkah = 1;
964 hw->rrd_ret_timer = 16;
965 hw->tpd_burst = 4;
966 hw->tpd_fetch_th = 16;
967 hw->txf_burst = 0x100;
968 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
969 hw->tpd_fetch_gap = 1;
970 hw->rcb_value = atl1_rcb_64;
971 hw->dma_ord = atl1_dma_ord_enh;
972 hw->dmar_block = atl1_dma_req_256;
973 hw->dmaw_block = atl1_dma_req_256;
974 hw->cmb_rrd = 4;
975 hw->cmb_tpd = 4;
976 hw->cmb_rx_timer = 1; /* about 2us */
977 hw->cmb_tx_timer = 1; /* about 2us */
978 hw->smb_timer = 100000; /* about 200ms */
979
980 spin_lock_init(&adapter->lock);
981 spin_lock_init(&adapter->mb_lock);
982
983 return 0;
984 }
985
986 static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
987 {
988 struct atl1_adapter *adapter = netdev_priv(netdev);
989 u16 result;
990
991 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
992
993 return result;
994 }
995
996 static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
997 int val)
998 {
999 struct atl1_adapter *adapter = netdev_priv(netdev);
1000
1001 atl1_write_phy_reg(&adapter->hw, reg_num, val);
1002 }
1003
1004 /*
1005 * atl1_mii_ioctl -
1006 * @netdev:
1007 * @ifreq:
1008 * @cmd:
1009 */
1010 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1011 {
1012 struct atl1_adapter *adapter = netdev_priv(netdev);
1013 unsigned long flags;
1014 int retval;
1015
1016 if (!netif_running(netdev))
1017 return -EINVAL;
1018
1019 spin_lock_irqsave(&adapter->lock, flags);
1020 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
1021 spin_unlock_irqrestore(&adapter->lock, flags);
1022
1023 return retval;
1024 }
1025
1026 /*
1027 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
1028 * @adapter: board private structure
1029 *
1030 * Return 0 on success, negative on failure
1031 */
1032 static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
1033 {
1034 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1035 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1036 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1037 struct atl1_ring_header *ring_header = &adapter->ring_header;
1038 struct pci_dev *pdev = adapter->pdev;
1039 int size;
1040 u8 offset = 0;
1041
1042 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
1043 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
1044 if (unlikely(!tpd_ring->buffer_info)) {
1045 if (netif_msg_drv(adapter))
1046 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n",
1047 size);
1048 goto err_nomem;
1049 }
1050 rfd_ring->buffer_info =
1051 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
1052
1053 /*
1054 * real ring DMA buffer
1055 * each ring/block may need up to 8 bytes for alignment, hence the
1056 * additional 40 bytes tacked onto the end.
1057 */
1058 ring_header->size = size =
1059 sizeof(struct tx_packet_desc) * tpd_ring->count
1060 + sizeof(struct rx_free_desc) * rfd_ring->count
1061 + sizeof(struct rx_return_desc) * rrd_ring->count
1062 + sizeof(struct coals_msg_block)
1063 + sizeof(struct stats_msg_block)
1064 + 40;
1065
1066 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
1067 &ring_header->dma);
1068 if (unlikely(!ring_header->desc)) {
1069 if (netif_msg_drv(adapter))
1070 dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
1071 goto err_nomem;
1072 }
1073
1074 memset(ring_header->desc, 0, ring_header->size);
1075
1076 /* init TPD ring */
1077 tpd_ring->dma = ring_header->dma;
1078 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
1079 tpd_ring->dma += offset;
1080 tpd_ring->desc = (u8 *) ring_header->desc + offset;
1081 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
1082
1083 /* init RFD ring */
1084 rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
1085 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
1086 rfd_ring->dma += offset;
1087 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
1088 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
1089
1090
1091 /* init RRD ring */
1092 rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
1093 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
1094 rrd_ring->dma += offset;
1095 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
1096 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
1097
1098
1099 /* init CMB */
1100 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
1101 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
1102 adapter->cmb.dma += offset;
1103 adapter->cmb.cmb = (struct coals_msg_block *)
1104 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
1105
1106 /* init SMB */
1107 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
1108 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
1109 adapter->smb.dma += offset;
1110 adapter->smb.smb = (struct stats_msg_block *)
1111 ((u8 *) adapter->cmb.cmb +
1112 (sizeof(struct coals_msg_block) + offset));
1113
1114 return 0;
1115
1116 err_nomem:
1117 kfree(tpd_ring->buffer_info);
1118 return -ENOMEM;
1119 }
1120
1121 static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
1122 {
1123 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1124 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1125 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1126
1127 atomic_set(&tpd_ring->next_to_use, 0);
1128 atomic_set(&tpd_ring->next_to_clean, 0);
1129
1130 rfd_ring->next_to_clean = 0;
1131 atomic_set(&rfd_ring->next_to_use, 0);
1132
1133 rrd_ring->next_to_use = 0;
1134 atomic_set(&rrd_ring->next_to_clean, 0);
1135 }
1136
1137 /*
1138 * atl1_clean_rx_ring - Free RFD Buffers
1139 * @adapter: board private structure
1140 */
1141 static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
1142 {
1143 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1144 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1145 struct atl1_buffer *buffer_info;
1146 struct pci_dev *pdev = adapter->pdev;
1147 unsigned long size;
1148 unsigned int i;
1149
1150 /* Free all the Rx ring sk_buffs */
1151 for (i = 0; i < rfd_ring->count; i++) {
1152 buffer_info = &rfd_ring->buffer_info[i];
1153 if (buffer_info->dma) {
1154 pci_unmap_page(pdev, buffer_info->dma,
1155 buffer_info->length, PCI_DMA_FROMDEVICE);
1156 buffer_info->dma = 0;
1157 }
1158 if (buffer_info->skb) {
1159 dev_kfree_skb(buffer_info->skb);
1160 buffer_info->skb = NULL;
1161 }
1162 }
1163
1164 size = sizeof(struct atl1_buffer) * rfd_ring->count;
1165 memset(rfd_ring->buffer_info, 0, size);
1166
1167 /* Zero out the descriptor ring */
1168 memset(rfd_ring->desc, 0, rfd_ring->size);
1169
1170 rfd_ring->next_to_clean = 0;
1171 atomic_set(&rfd_ring->next_to_use, 0);
1172
1173 rrd_ring->next_to_use = 0;
1174 atomic_set(&rrd_ring->next_to_clean, 0);
1175 }
1176
1177 /*
1178 * atl1_clean_tx_ring - Free Tx Buffers
1179 * @adapter: board private structure
1180 */
1181 static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
1182 {
1183 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1184 struct atl1_buffer *buffer_info;
1185 struct pci_dev *pdev = adapter->pdev;
1186 unsigned long size;
1187 unsigned int i;
1188
1189 /* Free all the Tx ring sk_buffs */
1190 for (i = 0; i < tpd_ring->count; i++) {
1191 buffer_info = &tpd_ring->buffer_info[i];
1192 if (buffer_info->dma) {
1193 pci_unmap_page(pdev, buffer_info->dma,
1194 buffer_info->length, PCI_DMA_TODEVICE);
1195 buffer_info->dma = 0;
1196 }
1197 }
1198
1199 for (i = 0; i < tpd_ring->count; i++) {
1200 buffer_info = &tpd_ring->buffer_info[i];
1201 if (buffer_info->skb) {
1202 dev_kfree_skb_any(buffer_info->skb);
1203 buffer_info->skb = NULL;
1204 }
1205 }
1206
1207 size = sizeof(struct atl1_buffer) * tpd_ring->count;
1208 memset(tpd_ring->buffer_info, 0, size);
1209
1210 /* Zero out the descriptor ring */
1211 memset(tpd_ring->desc, 0, tpd_ring->size);
1212
1213 atomic_set(&tpd_ring->next_to_use, 0);
1214 atomic_set(&tpd_ring->next_to_clean, 0);
1215 }
1216
1217 /*
1218 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1219 * @adapter: board private structure
1220 *
1221 * Free all transmit software resources
1222 */
1223 static void atl1_free_ring_resources(struct atl1_adapter *adapter)
1224 {
1225 struct pci_dev *pdev = adapter->pdev;
1226 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1227 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1228 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1229 struct atl1_ring_header *ring_header = &adapter->ring_header;
1230
1231 atl1_clean_tx_ring(adapter);
1232 atl1_clean_rx_ring(adapter);
1233
1234 kfree(tpd_ring->buffer_info);
1235 pci_free_consistent(pdev, ring_header->size, ring_header->desc,
1236 ring_header->dma);
1237
1238 tpd_ring->buffer_info = NULL;
1239 tpd_ring->desc = NULL;
1240 tpd_ring->dma = 0;
1241
1242 rfd_ring->buffer_info = NULL;
1243 rfd_ring->desc = NULL;
1244 rfd_ring->dma = 0;
1245
1246 rrd_ring->desc = NULL;
1247 rrd_ring->dma = 0;
1248 }
1249
1250 static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
1251 {
1252 u32 value;
1253 struct atl1_hw *hw = &adapter->hw;
1254 struct net_device *netdev = adapter->netdev;
1255 /* Config MAC CTRL Register */
1256 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1257 /* duplex */
1258 if (FULL_DUPLEX == adapter->link_duplex)
1259 value |= MAC_CTRL_DUPLX;
1260 /* speed */
1261 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
1262 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1263 MAC_CTRL_SPEED_SHIFT);
1264 /* flow control */
1265 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1266 /* PAD & CRC */
1267 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1268 /* preamble length */
1269 value |= (((u32) adapter->hw.preamble_len
1270 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1271 /* vlan */
1272 if (adapter->vlgrp)
1273 value |= MAC_CTRL_RMV_VLAN;
1274 /* rx checksum
1275 if (adapter->rx_csum)
1276 value |= MAC_CTRL_RX_CHKSUM_EN;
1277 */
1278 /* filter mode */
1279 value |= MAC_CTRL_BC_EN;
1280 if (netdev->flags & IFF_PROMISC)
1281 value |= MAC_CTRL_PROMIS_EN;
1282 else if (netdev->flags & IFF_ALLMULTI)
1283 value |= MAC_CTRL_MC_ALL_EN;
1284 /* value |= MAC_CTRL_LOOPBACK; */
1285 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1286 }
1287
1288 static u32 atl1_check_link(struct atl1_adapter *adapter)
1289 {
1290 struct atl1_hw *hw = &adapter->hw;
1291 struct net_device *netdev = adapter->netdev;
1292 u32 ret_val;
1293 u16 speed, duplex, phy_data;
1294 int reconfig = 0;
1295
1296 /* MII_BMSR must read twice */
1297 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1298 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1299 if (!(phy_data & BMSR_LSTATUS)) {
1300 /* link down */
1301 if (netif_carrier_ok(netdev)) {
1302 /* old link state: Up */
1303 if (netif_msg_link(adapter))
1304 dev_info(&adapter->pdev->dev, "link is down\n");
1305 adapter->link_speed = SPEED_0;
1306 netif_carrier_off(netdev);
1307 }
1308 return 0;
1309 }
1310
1311 /* Link Up */
1312 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
1313 if (ret_val)
1314 return ret_val;
1315
1316 switch (hw->media_type) {
1317 case MEDIA_TYPE_1000M_FULL:
1318 if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
1319 reconfig = 1;
1320 break;
1321 case MEDIA_TYPE_100M_FULL:
1322 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1323 reconfig = 1;
1324 break;
1325 case MEDIA_TYPE_100M_HALF:
1326 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1327 reconfig = 1;
1328 break;
1329 case MEDIA_TYPE_10M_FULL:
1330 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1331 reconfig = 1;
1332 break;
1333 case MEDIA_TYPE_10M_HALF:
1334 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1335 reconfig = 1;
1336 break;
1337 }
1338
1339 /* link result is our setting */
1340 if (!reconfig) {
1341 if (adapter->link_speed != speed
1342 || adapter->link_duplex != duplex) {
1343 adapter->link_speed = speed;
1344 adapter->link_duplex = duplex;
1345 atl1_setup_mac_ctrl(adapter);
1346 if (netif_msg_link(adapter))
1347 dev_info(&adapter->pdev->dev,
1348 "%s link is up %d Mbps %s\n",
1349 netdev->name, adapter->link_speed,
1350 adapter->link_duplex == FULL_DUPLEX ?
1351 "full duplex" : "half duplex");
1352 }
1353 if (!netif_carrier_ok(netdev)) {
1354 /* Link down -> Up */
1355 netif_carrier_on(netdev);
1356 }
1357 return 0;
1358 }
1359
1360 /* change original link status */
1361 if (netif_carrier_ok(netdev)) {
1362 adapter->link_speed = SPEED_0;
1363 netif_carrier_off(netdev);
1364 netif_stop_queue(netdev);
1365 }
1366
1367 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
1368 hw->media_type != MEDIA_TYPE_1000M_FULL) {
1369 switch (hw->media_type) {
1370 case MEDIA_TYPE_100M_FULL:
1371 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
1372 MII_CR_RESET;
1373 break;
1374 case MEDIA_TYPE_100M_HALF:
1375 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
1376 break;
1377 case MEDIA_TYPE_10M_FULL:
1378 phy_data =
1379 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
1380 break;
1381 default:
1382 /* MEDIA_TYPE_10M_HALF: */
1383 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
1384 break;
1385 }
1386 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
1387 return 0;
1388 }
1389
1390 /* auto-neg, insert timer to re-config phy */
1391 if (!adapter->phy_timer_pending) {
1392 adapter->phy_timer_pending = true;
1393 mod_timer(&adapter->phy_config_timer, jiffies + 3 * HZ);
1394 }
1395
1396 return 0;
1397 }
1398
1399 static void set_flow_ctrl_old(struct atl1_adapter *adapter)
1400 {
1401 u32 hi, lo, value;
1402
1403 /* RFD Flow Control */
1404 value = adapter->rfd_ring.count;
1405 hi = value / 16;
1406 if (hi < 2)
1407 hi = 2;
1408 lo = value * 7 / 8;
1409
1410 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1411 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1412 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1413
1414 /* RRD Flow Control */
1415 value = adapter->rrd_ring.count;
1416 lo = value / 16;
1417 hi = value * 7 / 8;
1418 if (lo < 2)
1419 lo = 2;
1420 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1421 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1422 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1423 }
1424
1425 static void set_flow_ctrl_new(struct atl1_hw *hw)
1426 {
1427 u32 hi, lo, value;
1428
1429 /* RXF Flow Control */
1430 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1431 lo = value / 16;
1432 if (lo < 192)
1433 lo = 192;
1434 hi = value * 7 / 8;
1435 if (hi < lo)
1436 hi = lo + 16;
1437 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1438 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1439 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1440
1441 /* RRD Flow Control */
1442 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1443 lo = value / 8;
1444 hi = value * 7 / 8;
1445 if (lo < 2)
1446 lo = 2;
1447 if (hi < lo)
1448 hi = lo + 3;
1449 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1450 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1451 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1452 }
1453
1454 /*
1455 * atl1_configure - Configure Transmit&Receive Unit after Reset
1456 * @adapter: board private structure
1457 *
1458 * Configure the Tx /Rx unit of the MAC after a reset.
1459 */
1460 static u32 atl1_configure(struct atl1_adapter *adapter)
1461 {
1462 struct atl1_hw *hw = &adapter->hw;
1463 u32 value;
1464
1465 /* clear interrupt status */
1466 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1467
1468 /* set MAC Address */
1469 value = (((u32) hw->mac_addr[2]) << 24) |
1470 (((u32) hw->mac_addr[3]) << 16) |
1471 (((u32) hw->mac_addr[4]) << 8) |
1472 (((u32) hw->mac_addr[5]));
1473 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1474 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1475 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1476
1477 /* tx / rx ring */
1478
1479 /* HI base address */
1480 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
1481 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1482 /* LO base address */
1483 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
1484 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1485 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
1486 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1487 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
1488 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1489 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
1490 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1491 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
1492 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
1493
1494 /* element count */
1495 value = adapter->rrd_ring.count;
1496 value <<= 16;
1497 value += adapter->rfd_ring.count;
1498 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1499 iowrite32(adapter->tpd_ring.count, hw->hw_addr +
1500 REG_DESC_TPD_RING_SIZE);
1501
1502 /* Load Ptr */
1503 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
1504
1505 /* config Mailbox */
1506 value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1507 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
1508 ((atomic_read(&adapter->rrd_ring.next_to_clean)
1509 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
1510 ((atomic_read(&adapter->rfd_ring.next_to_use)
1511 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
1512 iowrite32(value, hw->hw_addr + REG_MAILBOX);
1513
1514 /* config IPG/IFG */
1515 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1516 << MAC_IPG_IFG_IPGT_SHIFT) |
1517 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1518 << MAC_IPG_IFG_MIFG_SHIFT) |
1519 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1520 << MAC_IPG_IFG_IPGR1_SHIFT) |
1521 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1522 << MAC_IPG_IFG_IPGR2_SHIFT);
1523 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
1524
1525 /* config Half-Duplex Control */
1526 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1527 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1528 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
1529 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
1530 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
1531 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1532 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
1533 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
1534
1535 /* set Interrupt Moderator Timer */
1536 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1537 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
1538
1539 /* set Interrupt Clear Timer */
1540 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
1541
1542 /* set max frame size hw will accept */
1543 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
1544
1545 /* jumbo size & rrd retirement timer */
1546 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1547 << RXQ_JMBOSZ_TH_SHIFT) |
1548 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1549 << RXQ_JMBO_LKAH_SHIFT) |
1550 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1551 << RXQ_RRD_TIMER_SHIFT);
1552 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
1553
1554 /* Flow Control */
1555 switch (hw->dev_rev) {
1556 case 0x8001:
1557 case 0x9001:
1558 case 0x9002:
1559 case 0x9003:
1560 set_flow_ctrl_old(adapter);
1561 break;
1562 default:
1563 set_flow_ctrl_new(hw);
1564 break;
1565 }
1566
1567 /* config TXQ */
1568 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1569 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
1570 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1571 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
1572 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1573 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
1574 TXQ_CTRL_EN;
1575 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
1576
1577 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1578 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1579 << TX_JUMBO_TASK_TH_SHIFT) |
1580 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1581 << TX_TPD_MIN_IPG_SHIFT);
1582 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
1583
1584 /* config RXQ */
1585 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1586 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
1587 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1588 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
1589 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1590 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
1591 RXQ_CTRL_EN;
1592 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
1593
1594 /* config DMA Engine */
1595 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1596 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
1597 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1598 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
1599 DMA_CTRL_DMAW_EN;
1600 value |= (u32) hw->dma_ord;
1601 if (atl1_rcb_128 == hw->rcb_value)
1602 value |= DMA_CTRL_RCB_VALUE;
1603 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
1604
1605 /* config CMB / SMB */
1606 value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1607 hw->cmb_tpd : adapter->tpd_ring.count;
1608 value <<= 16;
1609 value |= hw->cmb_rrd;
1610 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1611 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1612 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1613 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
1614
1615 /* --- enable CMB / SMB */
1616 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1617 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
1618
1619 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1620 if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1621 value = 1; /* config failed */
1622 else
1623 value = 0;
1624
1625 /* clear all interrupt status */
1626 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1627 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1628 return value;
1629 }
1630
1631 /*
1632 * atl1_pcie_patch - Patch for PCIE module
1633 */
1634 static void atl1_pcie_patch(struct atl1_adapter *adapter)
1635 {
1636 u32 value;
1637
1638 /* much vendor magic here */
1639 value = 0x6500;
1640 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1641 /* pcie flow control mode change */
1642 value = ioread32(adapter->hw.hw_addr + 0x1008);
1643 value |= 0x8000;
1644 iowrite32(value, adapter->hw.hw_addr + 0x1008);
1645 }
1646
1647 /*
1648 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
1649 * on PCI Command register is disable.
1650 * The function enable this bit.
1651 * Brackett, 2006/03/15
1652 */
1653 static void atl1_via_workaround(struct atl1_adapter *adapter)
1654 {
1655 unsigned long value;
1656
1657 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1658 if (value & PCI_COMMAND_INTX_DISABLE)
1659 value &= ~PCI_COMMAND_INTX_DISABLE;
1660 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
1661 }
1662
1663 static void atl1_inc_smb(struct atl1_adapter *adapter)
1664 {
1665 struct stats_msg_block *smb = adapter->smb.smb;
1666
1667 /* Fill out the OS statistics structure */
1668 adapter->soft_stats.rx_packets += smb->rx_ok;
1669 adapter->soft_stats.tx_packets += smb->tx_ok;
1670 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
1671 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
1672 adapter->soft_stats.multicast += smb->rx_mcast;
1673 adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
1674 smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
1675
1676 /* Rx Errors */
1677 adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
1678 smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
1679 smb->rx_rrd_ov + smb->rx_align_err);
1680 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
1681 adapter->soft_stats.rx_length_errors += smb->rx_len_err;
1682 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
1683 adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
1684 adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
1685 smb->rx_rxf_ov);
1686
1687 adapter->soft_stats.rx_pause += smb->rx_pause;
1688 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
1689 adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
1690
1691 /* Tx Errors */
1692 adapter->soft_stats.tx_errors += (smb->tx_late_col +
1693 smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
1694 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
1695 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
1696 adapter->soft_stats.tx_window_errors += smb->tx_late_col;
1697
1698 adapter->soft_stats.excecol += smb->tx_abort_col;
1699 adapter->soft_stats.deffer += smb->tx_defer;
1700 adapter->soft_stats.scc += smb->tx_1_col;
1701 adapter->soft_stats.mcc += smb->tx_2_col;
1702 adapter->soft_stats.latecol += smb->tx_late_col;
1703 adapter->soft_stats.tx_underun += smb->tx_underrun;
1704 adapter->soft_stats.tx_trunc += smb->tx_trunc;
1705 adapter->soft_stats.tx_pause += smb->tx_pause;
1706
1707 adapter->net_stats.rx_packets = adapter->soft_stats.rx_packets;
1708 adapter->net_stats.tx_packets = adapter->soft_stats.tx_packets;
1709 adapter->net_stats.rx_bytes = adapter->soft_stats.rx_bytes;
1710 adapter->net_stats.tx_bytes = adapter->soft_stats.tx_bytes;
1711 adapter->net_stats.multicast = adapter->soft_stats.multicast;
1712 adapter->net_stats.collisions = adapter->soft_stats.collisions;
1713 adapter->net_stats.rx_errors = adapter->soft_stats.rx_errors;
1714 adapter->net_stats.rx_over_errors =
1715 adapter->soft_stats.rx_missed_errors;
1716 adapter->net_stats.rx_length_errors =
1717 adapter->soft_stats.rx_length_errors;
1718 adapter->net_stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
1719 adapter->net_stats.rx_frame_errors =
1720 adapter->soft_stats.rx_frame_errors;
1721 adapter->net_stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
1722 adapter->net_stats.rx_missed_errors =
1723 adapter->soft_stats.rx_missed_errors;
1724 adapter->net_stats.tx_errors = adapter->soft_stats.tx_errors;
1725 adapter->net_stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
1726 adapter->net_stats.tx_aborted_errors =
1727 adapter->soft_stats.tx_aborted_errors;
1728 adapter->net_stats.tx_window_errors =
1729 adapter->soft_stats.tx_window_errors;
1730 adapter->net_stats.tx_carrier_errors =
1731 adapter->soft_stats.tx_carrier_errors;
1732 }
1733
1734 static void atl1_update_mailbox(struct atl1_adapter *adapter)
1735 {
1736 unsigned long flags;
1737 u32 tpd_next_to_use;
1738 u32 rfd_next_to_use;
1739 u32 rrd_next_to_clean;
1740 u32 value;
1741
1742 spin_lock_irqsave(&adapter->mb_lock, flags);
1743
1744 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1745 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1746 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
1747
1748 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1749 MB_RFD_PROD_INDX_SHIFT) |
1750 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1751 MB_RRD_CONS_INDX_SHIFT) |
1752 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1753 MB_TPD_PROD_INDX_SHIFT);
1754 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1755
1756 spin_unlock_irqrestore(&adapter->mb_lock, flags);
1757 }
1758
1759 static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
1760 struct rx_return_desc *rrd, u16 offset)
1761 {
1762 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1763
1764 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
1765 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
1766 if (++rfd_ring->next_to_clean == rfd_ring->count) {
1767 rfd_ring->next_to_clean = 0;
1768 }
1769 }
1770 }
1771
1772 static void atl1_update_rfd_index(struct atl1_adapter *adapter,
1773 struct rx_return_desc *rrd)
1774 {
1775 u16 num_buf;
1776
1777 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
1778 adapter->rx_buffer_len;
1779 if (rrd->num_buf == num_buf)
1780 /* clean alloc flag for bad rrd */
1781 atl1_clean_alloc_flag(adapter, rrd, num_buf);
1782 }
1783
1784 static void atl1_rx_checksum(struct atl1_adapter *adapter,
1785 struct rx_return_desc *rrd, struct sk_buff *skb)
1786 {
1787 struct pci_dev *pdev = adapter->pdev;
1788
1789 /*
1790 * The L1 hardware contains a bug that erroneously sets the
1791 * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a
1792 * fragmented IP packet is received, even though the packet
1793 * is perfectly valid and its checksum is correct. There's
1794 * no way to distinguish between one of these good packets
1795 * and a packet that actually contains a TCP/UDP checksum
1796 * error, so all we can do is allow it to be handed up to
1797 * the higher layers and let it be sorted out there.
1798 */
1799
1800 skb->ip_summed = CHECKSUM_NONE;
1801
1802 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1803 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
1804 ERR_FLAG_CODE | ERR_FLAG_OV)) {
1805 adapter->hw_csum_err++;
1806 if (netif_msg_rx_err(adapter))
1807 dev_printk(KERN_DEBUG, &pdev->dev,
1808 "rx checksum error\n");
1809 return;
1810 }
1811 }
1812
1813 /* not IPv4 */
1814 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
1815 /* checksum is invalid, but it's not an IPv4 pkt, so ok */
1816 return;
1817
1818 /* IPv4 packet */
1819 if (likely(!(rrd->err_flg &
1820 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
1821 skb->ip_summed = CHECKSUM_UNNECESSARY;
1822 adapter->hw_csum_good++;
1823 return;
1824 }
1825
1826 return;
1827 }
1828
1829 /*
1830 * atl1_alloc_rx_buffers - Replace used receive buffers
1831 * @adapter: address of board private structure
1832 */
1833 static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
1834 {
1835 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1836 struct pci_dev *pdev = adapter->pdev;
1837 struct page *page;
1838 unsigned long offset;
1839 struct atl1_buffer *buffer_info, *next_info;
1840 struct sk_buff *skb;
1841 u16 num_alloc = 0;
1842 u16 rfd_next_to_use, next_next;
1843 struct rx_free_desc *rfd_desc;
1844
1845 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
1846 if (++next_next == rfd_ring->count)
1847 next_next = 0;
1848 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1849 next_info = &rfd_ring->buffer_info[next_next];
1850
1851 while (!buffer_info->alloced && !next_info->alloced) {
1852 if (buffer_info->skb) {
1853 buffer_info->alloced = 1;
1854 goto next;
1855 }
1856
1857 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
1858
1859 skb = netdev_alloc_skb(adapter->netdev,
1860 adapter->rx_buffer_len + NET_IP_ALIGN);
1861 if (unlikely(!skb)) {
1862 /* Better luck next round */
1863 adapter->net_stats.rx_dropped++;
1864 break;
1865 }
1866
1867 /*
1868 * Make buffer alignment 2 beyond a 16 byte boundary
1869 * this will result in a 16 byte aligned IP header after
1870 * the 14 byte MAC header is removed
1871 */
1872 skb_reserve(skb, NET_IP_ALIGN);
1873
1874 buffer_info->alloced = 1;
1875 buffer_info->skb = skb;
1876 buffer_info->length = (u16) adapter->rx_buffer_len;
1877 page = virt_to_page(skb->data);
1878 offset = (unsigned long)skb->data & ~PAGE_MASK;
1879 buffer_info->dma = pci_map_page(pdev, page, offset,
1880 adapter->rx_buffer_len,
1881 PCI_DMA_FROMDEVICE);
1882 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1883 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
1884 rfd_desc->coalese = 0;
1885
1886 next:
1887 rfd_next_to_use = next_next;
1888 if (unlikely(++next_next == rfd_ring->count))
1889 next_next = 0;
1890
1891 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1892 next_info = &rfd_ring->buffer_info[next_next];
1893 num_alloc++;
1894 }
1895
1896 if (num_alloc) {
1897 /*
1898 * Force memory writes to complete before letting h/w
1899 * know there are new descriptors to fetch. (Only
1900 * applicable for weak-ordered memory model archs,
1901 * such as IA-64).
1902 */
1903 wmb();
1904 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
1905 }
1906 return num_alloc;
1907 }
1908
1909 static void atl1_intr_rx(struct atl1_adapter *adapter)
1910 {
1911 int i, count;
1912 u16 length;
1913 u16 rrd_next_to_clean;
1914 u32 value;
1915 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1916 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1917 struct atl1_buffer *buffer_info;
1918 struct rx_return_desc *rrd;
1919 struct sk_buff *skb;
1920
1921 count = 0;
1922
1923 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
1924
1925 while (1) {
1926 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
1927 i = 1;
1928 if (likely(rrd->xsz.valid)) { /* packet valid */
1929 chk_rrd:
1930 /* check rrd status */
1931 if (likely(rrd->num_buf == 1))
1932 goto rrd_ok;
1933 else if (netif_msg_rx_err(adapter)) {
1934 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1935 "unexpected RRD buffer count\n");
1936 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1937 "rx_buf_len = %d\n",
1938 adapter->rx_buffer_len);
1939 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1940 "RRD num_buf = %d\n",
1941 rrd->num_buf);
1942 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1943 "RRD pkt_len = %d\n",
1944 rrd->xsz.xsum_sz.pkt_size);
1945 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1946 "RRD pkt_flg = 0x%08X\n",
1947 rrd->pkt_flg);
1948 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1949 "RRD err_flg = 0x%08X\n",
1950 rrd->err_flg);
1951 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1952 "RRD vlan_tag = 0x%08X\n",
1953 rrd->vlan_tag);
1954 }
1955
1956 /* rrd seems to be bad */
1957 if (unlikely(i-- > 0)) {
1958 /* rrd may not be DMAed completely */
1959 udelay(1);
1960 goto chk_rrd;
1961 }
1962 /* bad rrd */
1963 if (netif_msg_rx_err(adapter))
1964 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1965 "bad RRD\n");
1966 /* see if update RFD index */
1967 if (rrd->num_buf > 1)
1968 atl1_update_rfd_index(adapter, rrd);
1969
1970 /* update rrd */
1971 rrd->xsz.valid = 0;
1972 if (++rrd_next_to_clean == rrd_ring->count)
1973 rrd_next_to_clean = 0;
1974 count++;
1975 continue;
1976 } else { /* current rrd still not be updated */
1977
1978 break;
1979 }
1980 rrd_ok:
1981 /* clean alloc flag for bad rrd */
1982 atl1_clean_alloc_flag(adapter, rrd, 0);
1983
1984 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
1985 if (++rfd_ring->next_to_clean == rfd_ring->count)
1986 rfd_ring->next_to_clean = 0;
1987
1988 /* update rrd next to clean */
1989 if (++rrd_next_to_clean == rrd_ring->count)
1990 rrd_next_to_clean = 0;
1991 count++;
1992
1993 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1994 if (!(rrd->err_flg &
1995 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
1996 | ERR_FLAG_LEN))) {
1997 /* packet error, don't need upstream */
1998 buffer_info->alloced = 0;
1999 rrd->xsz.valid = 0;
2000 continue;
2001 }
2002 }
2003
2004 /* Good Receive */
2005 pci_unmap_page(adapter->pdev, buffer_info->dma,
2006 buffer_info->length, PCI_DMA_FROMDEVICE);
2007 buffer_info->dma = 0;
2008 skb = buffer_info->skb;
2009 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
2010
2011 skb_put(skb, length - ETH_FCS_LEN);
2012
2013 /* Receive Checksum Offload */
2014 atl1_rx_checksum(adapter, rrd, skb);
2015 skb->protocol = eth_type_trans(skb, adapter->netdev);
2016
2017 if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) {
2018 u16 vlan_tag = (rrd->vlan_tag >> 4) |
2019 ((rrd->vlan_tag & 7) << 13) |
2020 ((rrd->vlan_tag & 8) << 9);
2021 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
2022 } else
2023 netif_rx(skb);
2024
2025 /* let protocol layer free skb */
2026 buffer_info->skb = NULL;
2027 buffer_info->alloced = 0;
2028 rrd->xsz.valid = 0;
2029
2030 adapter->netdev->last_rx = jiffies;
2031 }
2032
2033 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
2034
2035 atl1_alloc_rx_buffers(adapter);
2036
2037 /* update mailbox ? */
2038 if (count) {
2039 u32 tpd_next_to_use;
2040 u32 rfd_next_to_use;
2041
2042 spin_lock(&adapter->mb_lock);
2043
2044 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
2045 rfd_next_to_use =
2046 atomic_read(&adapter->rfd_ring.next_to_use);
2047 rrd_next_to_clean =
2048 atomic_read(&adapter->rrd_ring.next_to_clean);
2049 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
2050 MB_RFD_PROD_INDX_SHIFT) |
2051 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
2052 MB_RRD_CONS_INDX_SHIFT) |
2053 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
2054 MB_TPD_PROD_INDX_SHIFT);
2055 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2056 spin_unlock(&adapter->mb_lock);
2057 }
2058 }
2059
2060 static void atl1_intr_tx(struct atl1_adapter *adapter)
2061 {
2062 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2063 struct atl1_buffer *buffer_info;
2064 u16 sw_tpd_next_to_clean;
2065 u16 cmb_tpd_next_to_clean;
2066
2067 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2068 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
2069
2070 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
2071 struct tx_packet_desc *tpd;
2072
2073 tpd = ATL1_TPD_DESC(tpd_ring, sw_tpd_next_to_clean);
2074 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
2075 if (buffer_info->dma) {
2076 pci_unmap_page(adapter->pdev, buffer_info->dma,
2077 buffer_info->length, PCI_DMA_TODEVICE);
2078 buffer_info->dma = 0;
2079 }
2080
2081 if (buffer_info->skb) {
2082 dev_kfree_skb_irq(buffer_info->skb);
2083 buffer_info->skb = NULL;
2084 }
2085
2086 if (++sw_tpd_next_to_clean == tpd_ring->count)
2087 sw_tpd_next_to_clean = 0;
2088 }
2089 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
2090
2091 if (netif_queue_stopped(adapter->netdev)
2092 && netif_carrier_ok(adapter->netdev))
2093 netif_wake_queue(adapter->netdev);
2094 }
2095
2096 static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
2097 {
2098 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2099 u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
2100 return ((next_to_clean > next_to_use) ?
2101 next_to_clean - next_to_use - 1 :
2102 tpd_ring->count + next_to_clean - next_to_use - 1);
2103 }
2104
2105 static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
2106 struct tx_packet_desc *ptpd)
2107 {
2108 u8 hdr_len, ip_off;
2109 u32 real_len;
2110 int err;
2111
2112 if (skb_shinfo(skb)->gso_size) {
2113 if (skb_header_cloned(skb)) {
2114 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2115 if (unlikely(err))
2116 return -1;
2117 }
2118
2119 if (skb->protocol == htons(ETH_P_IP)) {
2120 struct iphdr *iph = ip_hdr(skb);
2121
2122 real_len = (((unsigned char *)iph - skb->data) +
2123 ntohs(iph->tot_len));
2124 if (real_len < skb->len)
2125 pskb_trim(skb, real_len);
2126 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2127 if (skb->len == hdr_len) {
2128 iph->check = 0;
2129 tcp_hdr(skb)->check =
2130 ~csum_tcpudp_magic(iph->saddr,
2131 iph->daddr, tcp_hdrlen(skb),
2132 IPPROTO_TCP, 0);
2133 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2134 TPD_IPHL_SHIFT;
2135 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2136 TPD_TCPHDRLEN_MASK) <<
2137 TPD_TCPHDRLEN_SHIFT;
2138 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT;
2139 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT;
2140 return 1;
2141 }
2142
2143 iph->check = 0;
2144 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2145 iph->daddr, 0, IPPROTO_TCP, 0);
2146 ip_off = (unsigned char *)iph -
2147 (unsigned char *) skb_network_header(skb);
2148 if (ip_off == 8) /* 802.3-SNAP frame */
2149 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT;
2150 else if (ip_off != 0)
2151 return -2;
2152
2153 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2154 TPD_IPHL_SHIFT;
2155 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2156 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT;
2157 ptpd->word3 |= (skb_shinfo(skb)->gso_size &
2158 TPD_MSS_MASK) << TPD_MSS_SHIFT;
2159 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
2160 return 3;
2161 }
2162 }
2163 return false;
2164 }
2165
2166 static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
2167 struct tx_packet_desc *ptpd)
2168 {
2169 u8 css, cso;
2170
2171 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2172 css = (u8) (skb->csum_start - skb_headroom(skb));
2173 cso = css + (u8) skb->csum_offset;
2174 if (unlikely(css & 0x1)) {
2175 /* L1 hardware requires an even number here */
2176 if (netif_msg_tx_err(adapter))
2177 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2178 "payload offset not an even number\n");
2179 return -1;
2180 }
2181 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) <<
2182 TPD_PLOADOFFSET_SHIFT;
2183 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) <<
2184 TPD_CCSUMOFFSET_SHIFT;
2185 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
2186 return true;
2187 }
2188 return 0;
2189 }
2190
2191 static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
2192 struct tx_packet_desc *ptpd)
2193 {
2194 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2195 struct atl1_buffer *buffer_info;
2196 u16 buf_len = skb->len;
2197 struct page *page;
2198 unsigned long offset;
2199 unsigned int nr_frags;
2200 unsigned int f;
2201 int retval;
2202 u16 next_to_use;
2203 u16 data_len;
2204 u8 hdr_len;
2205
2206 buf_len -= skb->data_len;
2207 nr_frags = skb_shinfo(skb)->nr_frags;
2208 next_to_use = atomic_read(&tpd_ring->next_to_use);
2209 buffer_info = &tpd_ring->buffer_info[next_to_use];
2210 if (unlikely(buffer_info->skb))
2211 BUG();
2212 /* put skb in last TPD */
2213 buffer_info->skb = NULL;
2214
2215 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
2216 if (retval) {
2217 /* TSO */
2218 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2219 buffer_info->length = hdr_len;
2220 page = virt_to_page(skb->data);
2221 offset = (unsigned long)skb->data & ~PAGE_MASK;
2222 buffer_info->dma = pci_map_page(adapter->pdev, page,
2223 offset, hdr_len,
2224 PCI_DMA_TODEVICE);
2225
2226 if (++next_to_use == tpd_ring->count)
2227 next_to_use = 0;
2228
2229 if (buf_len > hdr_len) {
2230 int i, nseg;
2231
2232 data_len = buf_len - hdr_len;
2233 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) /
2234 ATL1_MAX_TX_BUF_LEN;
2235 for (i = 0; i < nseg; i++) {
2236 buffer_info =
2237 &tpd_ring->buffer_info[next_to_use];
2238 buffer_info->skb = NULL;
2239 buffer_info->length =
2240 (ATL1_MAX_TX_BUF_LEN >=
2241 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len;
2242 data_len -= buffer_info->length;
2243 page = virt_to_page(skb->data +
2244 (hdr_len + i * ATL1_MAX_TX_BUF_LEN));
2245 offset = (unsigned long)(skb->data +
2246 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) &
2247 ~PAGE_MASK;
2248 buffer_info->dma = pci_map_page(adapter->pdev,
2249 page, offset, buffer_info->length,
2250 PCI_DMA_TODEVICE);
2251 if (++next_to_use == tpd_ring->count)
2252 next_to_use = 0;
2253 }
2254 }
2255 } else {
2256 /* not TSO */
2257 buffer_info->length = buf_len;
2258 page = virt_to_page(skb->data);
2259 offset = (unsigned long)skb->data & ~PAGE_MASK;
2260 buffer_info->dma = pci_map_page(adapter->pdev, page,
2261 offset, buf_len, PCI_DMA_TODEVICE);
2262 if (++next_to_use == tpd_ring->count)
2263 next_to_use = 0;
2264 }
2265
2266 for (f = 0; f < nr_frags; f++) {
2267 struct skb_frag_struct *frag;
2268 u16 i, nseg;
2269
2270 frag = &skb_shinfo(skb)->frags[f];
2271 buf_len = frag->size;
2272
2273 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) /
2274 ATL1_MAX_TX_BUF_LEN;
2275 for (i = 0; i < nseg; i++) {
2276 buffer_info = &tpd_ring->buffer_info[next_to_use];
2277 if (unlikely(buffer_info->skb))
2278 BUG();
2279 buffer_info->skb = NULL;
2280 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
2281 ATL1_MAX_TX_BUF_LEN : buf_len;
2282 buf_len -= buffer_info->length;
2283 buffer_info->dma = pci_map_page(adapter->pdev,
2284 frag->page,
2285 frag->page_offset + (i * ATL1_MAX_TX_BUF_LEN),
2286 buffer_info->length, PCI_DMA_TODEVICE);
2287
2288 if (++next_to_use == tpd_ring->count)
2289 next_to_use = 0;
2290 }
2291 }
2292
2293 /* last tpd's buffer-info */
2294 buffer_info->skb = skb;
2295 }
2296
2297 static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count,
2298 struct tx_packet_desc *ptpd)
2299 {
2300 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2301 struct atl1_buffer *buffer_info;
2302 struct tx_packet_desc *tpd;
2303 u16 j;
2304 u32 val;
2305 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use);
2306
2307 for (j = 0; j < count; j++) {
2308 buffer_info = &tpd_ring->buffer_info[next_to_use];
2309 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use);
2310 if (tpd != ptpd)
2311 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc));
2312 tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2313 tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT);
2314 tpd->word2 |= (cpu_to_le16(buffer_info->length) &
2315 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT;
2316
2317 /*
2318 * if this is the first packet in a TSO chain, set
2319 * TPD_HDRFLAG, otherwise, clear it.
2320 */
2321 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) &
2322 TPD_SEGMENT_EN_MASK;
2323 if (val) {
2324 if (!j)
2325 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
2326 else
2327 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT);
2328 }
2329
2330 if (j == (count - 1))
2331 tpd->word3 |= 1 << TPD_EOP_SHIFT;
2332
2333 if (++next_to_use == tpd_ring->count)
2334 next_to_use = 0;
2335 }
2336 /*
2337 * Force memory writes to complete before letting h/w
2338 * know there are new descriptors to fetch. (Only
2339 * applicable for weak-ordered memory model archs,
2340 * such as IA-64).
2341 */
2342 wmb();
2343
2344 atomic_set(&tpd_ring->next_to_use, next_to_use);
2345 }
2346
2347 static int atl1_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2348 {
2349 struct atl1_adapter *adapter = netdev_priv(netdev);
2350 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2351 int len = skb->len;
2352 int tso;
2353 int count = 1;
2354 int ret_val;
2355 struct tx_packet_desc *ptpd;
2356 u16 frag_size;
2357 u16 vlan_tag;
2358 unsigned int nr_frags = 0;
2359 unsigned int mss = 0;
2360 unsigned int f;
2361 unsigned int proto_hdr_len;
2362
2363 len -= skb->data_len;
2364
2365 if (unlikely(skb->len <= 0)) {
2366 dev_kfree_skb_any(skb);
2367 return NETDEV_TX_OK;
2368 }
2369
2370 nr_frags = skb_shinfo(skb)->nr_frags;
2371 for (f = 0; f < nr_frags; f++) {
2372 frag_size = skb_shinfo(skb)->frags[f].size;
2373 if (frag_size)
2374 count += (frag_size + ATL1_MAX_TX_BUF_LEN - 1) /
2375 ATL1_MAX_TX_BUF_LEN;
2376 }
2377
2378 mss = skb_shinfo(skb)->gso_size;
2379 if (mss) {
2380 if (skb->protocol == ntohs(ETH_P_IP)) {
2381 proto_hdr_len = (skb_transport_offset(skb) +
2382 tcp_hdrlen(skb));
2383 if (unlikely(proto_hdr_len > len)) {
2384 dev_kfree_skb_any(skb);
2385 return NETDEV_TX_OK;
2386 }
2387 /* need additional TPD ? */
2388 if (proto_hdr_len != len)
2389 count += (len - proto_hdr_len +
2390 ATL1_MAX_TX_BUF_LEN - 1) /
2391 ATL1_MAX_TX_BUF_LEN;
2392 }
2393 }
2394
2395 if (atl1_tpd_avail(&adapter->tpd_ring) < count) {
2396 /* not enough descriptors */
2397 netif_stop_queue(netdev);
2398 if (netif_msg_tx_queued(adapter))
2399 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2400 "tx busy\n");
2401 return NETDEV_TX_BUSY;
2402 }
2403
2404 ptpd = ATL1_TPD_DESC(tpd_ring,
2405 (u16) atomic_read(&tpd_ring->next_to_use));
2406 memset(ptpd, 0, sizeof(struct tx_packet_desc));
2407
2408 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2409 vlan_tag = vlan_tx_tag_get(skb);
2410 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
2411 ((vlan_tag >> 9) & 0x8);
2412 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
2413 ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) <<
2414 TPD_VLANTAG_SHIFT;
2415 }
2416
2417 tso = atl1_tso(adapter, skb, ptpd);
2418 if (tso < 0) {
2419 dev_kfree_skb_any(skb);
2420 return NETDEV_TX_OK;
2421 }
2422
2423 if (!tso) {
2424 ret_val = atl1_tx_csum(adapter, skb, ptpd);
2425 if (ret_val < 0) {
2426 dev_kfree_skb_any(skb);
2427 return NETDEV_TX_OK;
2428 }
2429 }
2430
2431 atl1_tx_map(adapter, skb, ptpd);
2432 atl1_tx_queue(adapter, count, ptpd);
2433 atl1_update_mailbox(adapter);
2434 mmiowb();
2435 netdev->trans_start = jiffies;
2436 return NETDEV_TX_OK;
2437 }
2438
2439 /*
2440 * atl1_intr - Interrupt Handler
2441 * @irq: interrupt number
2442 * @data: pointer to a network interface device structure
2443 * @pt_regs: CPU registers structure
2444 */
2445 static irqreturn_t atl1_intr(int irq, void *data)
2446 {
2447 struct atl1_adapter *adapter = netdev_priv(data);
2448 u32 status;
2449 int max_ints = 10;
2450
2451 status = adapter->cmb.cmb->int_stats;
2452 if (!status)
2453 return IRQ_NONE;
2454
2455 do {
2456 /* clear CMB interrupt status at once */
2457 adapter->cmb.cmb->int_stats = 0;
2458
2459 if (status & ISR_GPHY) /* clear phy status */
2460 atlx_clear_phy_int(adapter);
2461
2462 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
2463 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
2464
2465 /* check if SMB intr */
2466 if (status & ISR_SMB)
2467 atl1_inc_smb(adapter);
2468
2469 /* check if PCIE PHY Link down */
2470 if (status & ISR_PHY_LINKDOWN) {
2471 if (netif_msg_intr(adapter))
2472 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2473 "pcie phy link down %x\n", status);
2474 if (netif_running(adapter->netdev)) { /* reset MAC */
2475 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2476 schedule_work(&adapter->pcie_dma_to_rst_task);
2477 return IRQ_HANDLED;
2478 }
2479 }
2480
2481 /* check if DMA read/write error ? */
2482 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
2483 if (netif_msg_intr(adapter))
2484 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2485 "pcie DMA r/w error (status = 0x%x)\n",
2486 status);
2487 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2488 schedule_work(&adapter->pcie_dma_to_rst_task);
2489 return IRQ_HANDLED;
2490 }
2491
2492 /* link event */
2493 if (status & ISR_GPHY) {
2494 adapter->soft_stats.tx_carrier_errors++;
2495 atl1_check_for_link(adapter);
2496 }
2497
2498 /* transmit event */
2499 if (status & ISR_CMB_TX)
2500 atl1_intr_tx(adapter);
2501
2502 /* rx exception */
2503 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2504 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2505 ISR_HOST_RRD_OV | ISR_CMB_RX))) {
2506 if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2507 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2508 ISR_HOST_RRD_OV))
2509 if (netif_msg_intr(adapter))
2510 dev_printk(KERN_DEBUG,
2511 &adapter->pdev->dev,
2512 "rx exception, ISR = 0x%x\n",
2513 status);
2514 atl1_intr_rx(adapter);
2515 }
2516
2517 if (--max_ints < 0)
2518 break;
2519
2520 } while ((status = adapter->cmb.cmb->int_stats));
2521
2522 /* re-enable Interrupt */
2523 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
2524 return IRQ_HANDLED;
2525 }
2526
2527 /*
2528 * atl1_watchdog - Timer Call-back
2529 * @data: pointer to netdev cast into an unsigned long
2530 */
2531 static void atl1_watchdog(unsigned long data)
2532 {
2533 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2534
2535 /* Reset the timer */
2536 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2537 }
2538
2539 /*
2540 * atl1_phy_config - Timer Call-back
2541 * @data: pointer to netdev cast into an unsigned long
2542 */
2543 static void atl1_phy_config(unsigned long data)
2544 {
2545 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2546 struct atl1_hw *hw = &adapter->hw;
2547 unsigned long flags;
2548
2549 spin_lock_irqsave(&adapter->lock, flags);
2550 adapter->phy_timer_pending = false;
2551 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
2552 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
2553 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
2554 spin_unlock_irqrestore(&adapter->lock, flags);
2555 }
2556
2557 /*
2558 * Orphaned vendor comment left intact here:
2559 * <vendor comment>
2560 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
2561 * will assert. We do soft reset <0x1400=1> according
2562 * with the SPEC. BUT, it seemes that PCIE or DMA
2563 * state-machine will not be reset. DMAR_TO_INT will
2564 * assert again and again.
2565 * </vendor comment>
2566 */
2567
2568 static int atl1_reset(struct atl1_adapter *adapter)
2569 {
2570 int ret;
2571 ret = atl1_reset_hw(&adapter->hw);
2572 if (ret)
2573 return ret;
2574 return atl1_init_hw(&adapter->hw);
2575 }
2576
2577 static s32 atl1_up(struct atl1_adapter *adapter)
2578 {
2579 struct net_device *netdev = adapter->netdev;
2580 int err;
2581 int irq_flags = IRQF_SAMPLE_RANDOM;
2582
2583 /* hardware has been reset, we need to reload some things */
2584 atlx_set_multi(netdev);
2585 atl1_init_ring_ptrs(adapter);
2586 atlx_restore_vlan(adapter);
2587 err = atl1_alloc_rx_buffers(adapter);
2588 if (unlikely(!err))
2589 /* no RX BUFFER allocated */
2590 return -ENOMEM;
2591
2592 if (unlikely(atl1_configure(adapter))) {
2593 err = -EIO;
2594 goto err_up;
2595 }
2596
2597 err = pci_enable_msi(adapter->pdev);
2598 if (err) {
2599 if (netif_msg_ifup(adapter))
2600 dev_info(&adapter->pdev->dev,
2601 "Unable to enable MSI: %d\n", err);
2602 irq_flags |= IRQF_SHARED;
2603 }
2604
2605 err = request_irq(adapter->pdev->irq, &atl1_intr, irq_flags,
2606 netdev->name, netdev);
2607 if (unlikely(err))
2608 goto err_up;
2609
2610 mod_timer(&adapter->watchdog_timer, jiffies);
2611 atlx_irq_enable(adapter);
2612 atl1_check_link(adapter);
2613 netif_start_queue(netdev);
2614 return 0;
2615
2616 err_up:
2617 pci_disable_msi(adapter->pdev);
2618 /* free rx_buffers */
2619 atl1_clean_rx_ring(adapter);
2620 return err;
2621 }
2622
2623 static void atl1_down(struct atl1_adapter *adapter)
2624 {
2625 struct net_device *netdev = adapter->netdev;
2626
2627 netif_stop_queue(netdev);
2628 del_timer_sync(&adapter->watchdog_timer);
2629 del_timer_sync(&adapter->phy_config_timer);
2630 adapter->phy_timer_pending = false;
2631
2632 atlx_irq_disable(adapter);
2633 free_irq(adapter->pdev->irq, netdev);
2634 pci_disable_msi(adapter->pdev);
2635 atl1_reset_hw(&adapter->hw);
2636 adapter->cmb.cmb->int_stats = 0;
2637
2638 adapter->link_speed = SPEED_0;
2639 adapter->link_duplex = -1;
2640 netif_carrier_off(netdev);
2641
2642 atl1_clean_tx_ring(adapter);
2643 atl1_clean_rx_ring(adapter);
2644 }
2645
2646 static void atl1_tx_timeout_task(struct work_struct *work)
2647 {
2648 struct atl1_adapter *adapter =
2649 container_of(work, struct atl1_adapter, tx_timeout_task);
2650 struct net_device *netdev = adapter->netdev;
2651
2652 netif_device_detach(netdev);
2653 atl1_down(adapter);
2654 atl1_up(adapter);
2655 netif_device_attach(netdev);
2656 }
2657
2658 /*
2659 * atl1_change_mtu - Change the Maximum Transfer Unit
2660 * @netdev: network interface device structure
2661 * @new_mtu: new value for maximum frame size
2662 *
2663 * Returns 0 on success, negative on failure
2664 */
2665 static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
2666 {
2667 struct atl1_adapter *adapter = netdev_priv(netdev);
2668 int old_mtu = netdev->mtu;
2669 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
2670
2671 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2672 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2673 if (netif_msg_link(adapter))
2674 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
2675 return -EINVAL;
2676 }
2677
2678 adapter->hw.max_frame_size = max_frame;
2679 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
2680 adapter->rx_buffer_len = (max_frame + 7) & ~7;
2681 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
2682
2683 netdev->mtu = new_mtu;
2684 if ((old_mtu != new_mtu) && netif_running(netdev)) {
2685 atl1_down(adapter);
2686 atl1_up(adapter);
2687 }
2688
2689 return 0;
2690 }
2691
2692 /*
2693 * atl1_open - Called when a network interface is made active
2694 * @netdev: network interface device structure
2695 *
2696 * Returns 0 on success, negative value on failure
2697 *
2698 * The open entry point is called when a network interface is made
2699 * active by the system (IFF_UP). At this point all resources needed
2700 * for transmit and receive operations are allocated, the interrupt
2701 * handler is registered with the OS, the watchdog timer is started,
2702 * and the stack is notified that the interface is ready.
2703 */
2704 static int atl1_open(struct net_device *netdev)
2705 {
2706 struct atl1_adapter *adapter = netdev_priv(netdev);
2707 int err;
2708
2709 netif_carrier_off(netdev);
2710
2711 /* allocate transmit descriptors */
2712 err = atl1_setup_ring_resources(adapter);
2713 if (err)
2714 return err;
2715
2716 err = atl1_up(adapter);
2717 if (err)
2718 goto err_up;
2719
2720 return 0;
2721
2722 err_up:
2723 atl1_reset(adapter);
2724 return err;
2725 }
2726
2727 /*
2728 * atl1_close - Disables a network interface
2729 * @netdev: network interface device structure
2730 *
2731 * Returns 0, this is not allowed to fail
2732 *
2733 * The close entry point is called when an interface is de-activated
2734 * by the OS. The hardware is still under the drivers control, but
2735 * needs to be disabled. A global MAC reset is issued to stop the
2736 * hardware, and all transmit and receive resources are freed.
2737 */
2738 static int atl1_close(struct net_device *netdev)
2739 {
2740 struct atl1_adapter *adapter = netdev_priv(netdev);
2741 atl1_down(adapter);
2742 atl1_free_ring_resources(adapter);
2743 return 0;
2744 }
2745
2746 #ifdef CONFIG_PM
2747 static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
2748 {
2749 struct net_device *netdev = pci_get_drvdata(pdev);
2750 struct atl1_adapter *adapter = netdev_priv(netdev);
2751 struct atl1_hw *hw = &adapter->hw;
2752 u32 ctrl = 0;
2753 u32 wufc = adapter->wol;
2754 u32 val;
2755 int retval;
2756 u16 speed;
2757 u16 duplex;
2758
2759 netif_device_detach(netdev);
2760 if (netif_running(netdev))
2761 atl1_down(adapter);
2762
2763 retval = pci_save_state(pdev);
2764 if (retval)
2765 return retval;
2766
2767 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2768 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2769 val = ctrl & BMSR_LSTATUS;
2770 if (val)
2771 wufc &= ~ATLX_WUFC_LNKC;
2772
2773 if (val && wufc) {
2774 val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
2775 if (val) {
2776 if (netif_msg_ifdown(adapter))
2777 dev_printk(KERN_DEBUG, &pdev->dev,
2778 "error getting speed/duplex\n");
2779 goto disable_wol;
2780 }
2781
2782 ctrl = 0;
2783
2784 /* enable magic packet WOL */
2785 if (wufc & ATLX_WUFC_MAG)
2786 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
2787 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2788 ioread32(hw->hw_addr + REG_WOL_CTRL);
2789
2790 /* configure the mac */
2791 ctrl = MAC_CTRL_RX_EN;
2792 ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 :
2793 MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT);
2794 if (duplex == FULL_DUPLEX)
2795 ctrl |= MAC_CTRL_DUPLX;
2796 ctrl |= (((u32)adapter->hw.preamble_len &
2797 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
2798 if (adapter->vlgrp)
2799 ctrl |= MAC_CTRL_RMV_VLAN;
2800 if (wufc & ATLX_WUFC_MAG)
2801 ctrl |= MAC_CTRL_BC_EN;
2802 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
2803 ioread32(hw->hw_addr + REG_MAC_CTRL);
2804
2805 /* poke the PHY */
2806 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2807 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2808 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2809 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2810
2811 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2812 goto exit;
2813 }
2814
2815 if (!val && wufc) {
2816 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2817 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2818 ioread32(hw->hw_addr + REG_WOL_CTRL);
2819 iowrite32(0, hw->hw_addr + REG_MAC_CTRL);
2820 ioread32(hw->hw_addr + REG_MAC_CTRL);
2821 hw->phy_configured = false;
2822 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2823 goto exit;
2824 }
2825
2826 disable_wol:
2827 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2828 ioread32(hw->hw_addr + REG_WOL_CTRL);
2829 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2830 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2831 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2832 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2833 hw->phy_configured = false;
2834 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
2835 exit:
2836 if (netif_running(netdev))
2837 pci_disable_msi(adapter->pdev);
2838 pci_disable_device(pdev);
2839 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2840
2841 return 0;
2842 }
2843
2844 static int atl1_resume(struct pci_dev *pdev)
2845 {
2846 struct net_device *netdev = pci_get_drvdata(pdev);
2847 struct atl1_adapter *adapter = netdev_priv(netdev);
2848 u32 err;
2849
2850 pci_set_power_state(pdev, PCI_D0);
2851 pci_restore_state(pdev);
2852
2853 err = pci_enable_device(pdev);
2854 if (err) {
2855 if (netif_msg_ifup(adapter))
2856 dev_printk(KERN_DEBUG, &pdev->dev,
2857 "error enabling pci device\n");
2858 return err;
2859 }
2860
2861 pci_set_master(pdev);
2862 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
2863 pci_enable_wake(pdev, PCI_D3hot, 0);
2864 pci_enable_wake(pdev, PCI_D3cold, 0);
2865
2866 atl1_reset_hw(&adapter->hw);
2867 adapter->cmb.cmb->int_stats = 0;
2868
2869 if (netif_running(netdev))
2870 atl1_up(adapter);
2871 netif_device_attach(netdev);
2872
2873 return 0;
2874 }
2875 #else
2876 #define atl1_suspend NULL
2877 #define atl1_resume NULL
2878 #endif
2879
2880 static void atl1_shutdown(struct pci_dev *pdev)
2881 {
2882 #ifdef CONFIG_PM
2883 atl1_suspend(pdev, PMSG_SUSPEND);
2884 #endif
2885 }
2886
2887 #ifdef CONFIG_NET_POLL_CONTROLLER
2888 static void atl1_poll_controller(struct net_device *netdev)
2889 {
2890 disable_irq(netdev->irq);
2891 atl1_intr(netdev->irq, netdev);
2892 enable_irq(netdev->irq);
2893 }
2894 #endif
2895
2896 /*
2897 * atl1_probe - Device Initialization Routine
2898 * @pdev: PCI device information struct
2899 * @ent: entry in atl1_pci_tbl
2900 *
2901 * Returns 0 on success, negative on failure
2902 *
2903 * atl1_probe initializes an adapter identified by a pci_dev structure.
2904 * The OS initialization, configuring of the adapter private structure,
2905 * and a hardware reset occur.
2906 */
2907 static int __devinit atl1_probe(struct pci_dev *pdev,
2908 const struct pci_device_id *ent)
2909 {
2910 struct net_device *netdev;
2911 struct atl1_adapter *adapter;
2912 static int cards_found = 0;
2913 int err;
2914
2915 err = pci_enable_device(pdev);
2916 if (err)
2917 return err;
2918
2919 /*
2920 * The atl1 chip can DMA to 64-bit addresses, but it uses a single
2921 * shared register for the high 32 bits, so only a single, aligned,
2922 * 4 GB physical address range can be used at a time.
2923 *
2924 * Supporting 64-bit DMA on this hardware is more trouble than it's
2925 * worth. It is far easier to limit to 32-bit DMA than update
2926 * various kernel subsystems to support the mechanics required by a
2927 * fixed-high-32-bit system.
2928 */
2929 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2930 if (err) {
2931 dev_err(&pdev->dev, "no usable DMA configuration\n");
2932 goto err_dma;
2933 }
2934 /*
2935 * Mark all PCI regions associated with PCI device
2936 * pdev as being reserved by owner atl1_driver_name
2937 */
2938 err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
2939 if (err)
2940 goto err_request_regions;
2941
2942 /*
2943 * Enables bus-mastering on the device and calls
2944 * pcibios_set_master to do the needed arch specific settings
2945 */
2946 pci_set_master(pdev);
2947
2948 netdev = alloc_etherdev(sizeof(struct atl1_adapter));
2949 if (!netdev) {
2950 err = -ENOMEM;
2951 goto err_alloc_etherdev;
2952 }
2953 SET_NETDEV_DEV(netdev, &pdev->dev);
2954
2955 pci_set_drvdata(pdev, netdev);
2956 adapter = netdev_priv(netdev);
2957 adapter->netdev = netdev;
2958 adapter->pdev = pdev;
2959 adapter->hw.back = adapter;
2960 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg);
2961
2962 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2963 if (!adapter->hw.hw_addr) {
2964 err = -EIO;
2965 goto err_pci_iomap;
2966 }
2967 /* get device revision number */
2968 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
2969 (REG_MASTER_CTRL + 2));
2970 if (netif_msg_probe(adapter))
2971 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
2972
2973 /* set default ring resource counts */
2974 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
2975 adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
2976
2977 adapter->mii.dev = netdev;
2978 adapter->mii.mdio_read = mdio_read;
2979 adapter->mii.mdio_write = mdio_write;
2980 adapter->mii.phy_id_mask = 0x1f;
2981 adapter->mii.reg_num_mask = 0x1f;
2982
2983 netdev->open = &atl1_open;
2984 netdev->stop = &atl1_close;
2985 netdev->hard_start_xmit = &atl1_xmit_frame;
2986 netdev->get_stats = &atlx_get_stats;
2987 netdev->set_multicast_list = &atlx_set_multi;
2988 netdev->set_mac_address = &atl1_set_mac;
2989 netdev->change_mtu = &atl1_change_mtu;
2990 netdev->do_ioctl = &atlx_ioctl;
2991 netdev->tx_timeout = &atlx_tx_timeout;
2992 netdev->watchdog_timeo = 5 * HZ;
2993 #ifdef CONFIG_NET_POLL_CONTROLLER
2994 netdev->poll_controller = atl1_poll_controller;
2995 #endif
2996 netdev->vlan_rx_register = atlx_vlan_rx_register;
2997
2998 netdev->ethtool_ops = &atl1_ethtool_ops;
2999 adapter->bd_number = cards_found;
3000
3001 /* setup the private structure */
3002 err = atl1_sw_init(adapter);
3003 if (err)
3004 goto err_common;
3005
3006 netdev->features = NETIF_F_HW_CSUM;
3007 netdev->features |= NETIF_F_SG;
3008 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
3009
3010 /*
3011 * patch for some L1 of old version,
3012 * the final version of L1 may not need these
3013 * patches
3014 */
3015 /* atl1_pcie_patch(adapter); */
3016
3017 /* really reset GPHY core */
3018 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3019
3020 /*
3021 * reset the controller to
3022 * put the device in a known good starting state
3023 */
3024 if (atl1_reset_hw(&adapter->hw)) {
3025 err = -EIO;
3026 goto err_common;
3027 }
3028
3029 /* copy the MAC address out of the EEPROM */
3030 atl1_read_mac_addr(&adapter->hw);
3031 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
3032
3033 if (!is_valid_ether_addr(netdev->dev_addr)) {
3034 err = -EIO;
3035 goto err_common;
3036 }
3037
3038 atl1_check_options(adapter);
3039
3040 /* pre-init the MAC, and setup link */
3041 err = atl1_init_hw(&adapter->hw);
3042 if (err) {
3043 err = -EIO;
3044 goto err_common;
3045 }
3046
3047 atl1_pcie_patch(adapter);
3048 /* assume we have no link for now */
3049 netif_carrier_off(netdev);
3050 netif_stop_queue(netdev);
3051
3052 init_timer(&adapter->watchdog_timer);
3053 adapter->watchdog_timer.function = &atl1_watchdog;
3054 adapter->watchdog_timer.data = (unsigned long)adapter;
3055
3056 init_timer(&adapter->phy_config_timer);
3057 adapter->phy_config_timer.function = &atl1_phy_config;
3058 adapter->phy_config_timer.data = (unsigned long)adapter;
3059 adapter->phy_timer_pending = false;
3060
3061 INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
3062
3063 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
3064
3065 INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
3066
3067 err = register_netdev(netdev);
3068 if (err)
3069 goto err_common;
3070
3071 cards_found++;
3072 atl1_via_workaround(adapter);
3073 return 0;
3074
3075 err_common:
3076 pci_iounmap(pdev, adapter->hw.hw_addr);
3077 err_pci_iomap:
3078 free_netdev(netdev);
3079 err_alloc_etherdev:
3080 pci_release_regions(pdev);
3081 err_dma:
3082 err_request_regions:
3083 pci_disable_device(pdev);
3084 return err;
3085 }
3086
3087 /*
3088 * atl1_remove - Device Removal Routine
3089 * @pdev: PCI device information struct
3090 *
3091 * atl1_remove is called by the PCI subsystem to alert the driver
3092 * that it should release a PCI device. The could be caused by a
3093 * Hot-Plug event, or because the driver is going to be removed from
3094 * memory.
3095 */
3096 static void __devexit atl1_remove(struct pci_dev *pdev)
3097 {
3098 struct net_device *netdev = pci_get_drvdata(pdev);
3099 struct atl1_adapter *adapter;
3100 /* Device not available. Return. */
3101 if (!netdev)
3102 return;
3103
3104 adapter = netdev_priv(netdev);
3105
3106 /*
3107 * Some atl1 boards lack persistent storage for their MAC, and get it
3108 * from the BIOS during POST. If we've been messing with the MAC
3109 * address, we need to save the permanent one.
3110 */
3111 if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) {
3112 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
3113 ETH_ALEN);
3114 atl1_set_mac_addr(&adapter->hw);
3115 }
3116
3117 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3118 unregister_netdev(netdev);
3119 pci_iounmap(pdev, adapter->hw.hw_addr);
3120 pci_release_regions(pdev);
3121 free_netdev(netdev);
3122 pci_disable_device(pdev);
3123 }
3124
3125 static struct pci_driver atl1_driver = {
3126 .name = ATLX_DRIVER_NAME,
3127 .id_table = atl1_pci_tbl,
3128 .probe = atl1_probe,
3129 .remove = __devexit_p(atl1_remove),
3130 .suspend = atl1_suspend,
3131 .resume = atl1_resume,
3132 .shutdown = atl1_shutdown
3133 };
3134
3135 /*
3136 * atl1_exit_module - Driver Exit Cleanup Routine
3137 *
3138 * atl1_exit_module is called just before the driver is removed
3139 * from memory.
3140 */
3141 static void __exit atl1_exit_module(void)
3142 {
3143 pci_unregister_driver(&atl1_driver);
3144 }
3145
3146 /*
3147 * atl1_init_module - Driver Registration Routine
3148 *
3149 * atl1_init_module is the first routine called when the driver is
3150 * loaded. All it does is register with the PCI subsystem.
3151 */
3152 static int __init atl1_init_module(void)
3153 {
3154 return pci_register_driver(&atl1_driver);
3155 }
3156
3157 module_init(atl1_init_module);
3158 module_exit(atl1_exit_module);
3159
3160 struct atl1_stats {
3161 char stat_string[ETH_GSTRING_LEN];
3162 int sizeof_stat;
3163 int stat_offset;
3164 };
3165
3166 #define ATL1_STAT(m) \
3167 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
3168
3169 static struct atl1_stats atl1_gstrings_stats[] = {
3170 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
3171 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
3172 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
3173 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
3174 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
3175 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
3176 {"rx_dropped", ATL1_STAT(net_stats.rx_dropped)},
3177 {"tx_dropped", ATL1_STAT(net_stats.tx_dropped)},
3178 {"multicast", ATL1_STAT(soft_stats.multicast)},
3179 {"collisions", ATL1_STAT(soft_stats.collisions)},
3180 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
3181 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3182 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
3183 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
3184 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
3185 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3186 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
3187 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
3188 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
3189 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
3190 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
3191 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
3192 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
3193 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
3194 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
3195 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
3196 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
3197 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
3198 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
3199 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
3200 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
3201 };
3202
3203 static void atl1_get_ethtool_stats(struct net_device *netdev,
3204 struct ethtool_stats *stats, u64 *data)
3205 {
3206 struct atl1_adapter *adapter = netdev_priv(netdev);
3207 int i;
3208 char *p;
3209
3210 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3211 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
3212 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
3213 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
3214 }
3215
3216 }
3217
3218 static int atl1_get_sset_count(struct net_device *netdev, int sset)
3219 {
3220 switch (sset) {
3221 case ETH_SS_STATS:
3222 return ARRAY_SIZE(atl1_gstrings_stats);
3223 default:
3224 return -EOPNOTSUPP;
3225 }
3226 }
3227
3228 static int atl1_get_settings(struct net_device *netdev,
3229 struct ethtool_cmd *ecmd)
3230 {
3231 struct atl1_adapter *adapter = netdev_priv(netdev);
3232 struct atl1_hw *hw = &adapter->hw;
3233
3234 ecmd->supported = (SUPPORTED_10baseT_Half |
3235 SUPPORTED_10baseT_Full |
3236 SUPPORTED_100baseT_Half |
3237 SUPPORTED_100baseT_Full |
3238 SUPPORTED_1000baseT_Full |
3239 SUPPORTED_Autoneg | SUPPORTED_TP);
3240 ecmd->advertising = ADVERTISED_TP;
3241 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3242 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3243 ecmd->advertising |= ADVERTISED_Autoneg;
3244 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
3245 ecmd->advertising |= ADVERTISED_Autoneg;
3246 ecmd->advertising |=
3247 (ADVERTISED_10baseT_Half |
3248 ADVERTISED_10baseT_Full |
3249 ADVERTISED_100baseT_Half |
3250 ADVERTISED_100baseT_Full |
3251 ADVERTISED_1000baseT_Full);
3252 } else
3253 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
3254 }
3255 ecmd->port = PORT_TP;
3256 ecmd->phy_address = 0;
3257 ecmd->transceiver = XCVR_INTERNAL;
3258
3259 if (netif_carrier_ok(adapter->netdev)) {
3260 u16 link_speed, link_duplex;
3261 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
3262 ecmd->speed = link_speed;
3263 if (link_duplex == FULL_DUPLEX)
3264 ecmd->duplex = DUPLEX_FULL;
3265 else
3266 ecmd->duplex = DUPLEX_HALF;
3267 } else {
3268 ecmd->speed = -1;
3269 ecmd->duplex = -1;
3270 }
3271 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3272 hw->media_type == MEDIA_TYPE_1000M_FULL)
3273 ecmd->autoneg = AUTONEG_ENABLE;
3274 else
3275 ecmd->autoneg = AUTONEG_DISABLE;
3276
3277 return 0;
3278 }
3279
3280 static int atl1_set_settings(struct net_device *netdev,
3281 struct ethtool_cmd *ecmd)
3282 {
3283 struct atl1_adapter *adapter = netdev_priv(netdev);
3284 struct atl1_hw *hw = &adapter->hw;
3285 u16 phy_data;
3286 int ret_val = 0;
3287 u16 old_media_type = hw->media_type;
3288
3289 if (netif_running(adapter->netdev)) {
3290 if (netif_msg_link(adapter))
3291 dev_dbg(&adapter->pdev->dev,
3292 "ethtool shutting down adapter\n");
3293 atl1_down(adapter);
3294 }
3295
3296 if (ecmd->autoneg == AUTONEG_ENABLE)
3297 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
3298 else {
3299 if (ecmd->speed == SPEED_1000) {
3300 if (ecmd->duplex != DUPLEX_FULL) {
3301 if (netif_msg_link(adapter))
3302 dev_warn(&adapter->pdev->dev,
3303 "1000M half is invalid\n");
3304 ret_val = -EINVAL;
3305 goto exit_sset;
3306 }
3307 hw->media_type = MEDIA_TYPE_1000M_FULL;
3308 } else if (ecmd->speed == SPEED_100) {
3309 if (ecmd->duplex == DUPLEX_FULL)
3310 hw->media_type = MEDIA_TYPE_100M_FULL;
3311 else
3312 hw->media_type = MEDIA_TYPE_100M_HALF;
3313 } else {
3314 if (ecmd->duplex == DUPLEX_FULL)
3315 hw->media_type = MEDIA_TYPE_10M_FULL;
3316 else
3317 hw->media_type = MEDIA_TYPE_10M_HALF;
3318 }
3319 }
3320 switch (hw->media_type) {
3321 case MEDIA_TYPE_AUTO_SENSOR:
3322 ecmd->advertising =
3323 ADVERTISED_10baseT_Half |
3324 ADVERTISED_10baseT_Full |
3325 ADVERTISED_100baseT_Half |
3326 ADVERTISED_100baseT_Full |
3327 ADVERTISED_1000baseT_Full |
3328 ADVERTISED_Autoneg | ADVERTISED_TP;
3329 break;
3330 case MEDIA_TYPE_1000M_FULL:
3331 ecmd->advertising =
3332 ADVERTISED_1000baseT_Full |
3333 ADVERTISED_Autoneg | ADVERTISED_TP;
3334 break;
3335 default:
3336 ecmd->advertising = 0;
3337 break;
3338 }
3339 if (atl1_phy_setup_autoneg_adv(hw)) {
3340 ret_val = -EINVAL;
3341 if (netif_msg_link(adapter))
3342 dev_warn(&adapter->pdev->dev,
3343 "invalid ethtool speed/duplex setting\n");
3344 goto exit_sset;
3345 }
3346 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3347 hw->media_type == MEDIA_TYPE_1000M_FULL)
3348 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3349 else {
3350 switch (hw->media_type) {
3351 case MEDIA_TYPE_100M_FULL:
3352 phy_data =
3353 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
3354 MII_CR_RESET;
3355 break;
3356 case MEDIA_TYPE_100M_HALF:
3357 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3358 break;
3359 case MEDIA_TYPE_10M_FULL:
3360 phy_data =
3361 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
3362 break;
3363 default:
3364 /* MEDIA_TYPE_10M_HALF: */
3365 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3366 break;
3367 }
3368 }
3369 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3370 exit_sset:
3371 if (ret_val)
3372 hw->media_type = old_media_type;
3373
3374 if (netif_running(adapter->netdev)) {
3375 if (netif_msg_link(adapter))
3376 dev_dbg(&adapter->pdev->dev,
3377 "ethtool starting adapter\n");
3378 atl1_up(adapter);
3379 } else if (!ret_val) {
3380 if (netif_msg_link(adapter))
3381 dev_dbg(&adapter->pdev->dev,
3382 "ethtool resetting adapter\n");
3383 atl1_reset(adapter);
3384 }
3385 return ret_val;
3386 }
3387
3388 static void atl1_get_drvinfo(struct net_device *netdev,
3389 struct ethtool_drvinfo *drvinfo)
3390 {
3391 struct atl1_adapter *adapter = netdev_priv(netdev);
3392
3393 strncpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
3394 strncpy(drvinfo->version, ATLX_DRIVER_VERSION,
3395 sizeof(drvinfo->version));
3396 strncpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
3397 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
3398 sizeof(drvinfo->bus_info));
3399 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
3400 }
3401
3402 static void atl1_get_wol(struct net_device *netdev,
3403 struct ethtool_wolinfo *wol)
3404 {
3405 struct atl1_adapter *adapter = netdev_priv(netdev);
3406
3407 wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
3408 wol->wolopts = 0;
3409 if (adapter->wol & ATLX_WUFC_EX)
3410 wol->wolopts |= WAKE_UCAST;
3411 if (adapter->wol & ATLX_WUFC_MC)
3412 wol->wolopts |= WAKE_MCAST;
3413 if (adapter->wol & ATLX_WUFC_BC)
3414 wol->wolopts |= WAKE_BCAST;
3415 if (adapter->wol & ATLX_WUFC_MAG)
3416 wol->wolopts |= WAKE_MAGIC;
3417 return;
3418 }
3419
3420 static int atl1_set_wol(struct net_device *netdev,
3421 struct ethtool_wolinfo *wol)
3422 {
3423 struct atl1_adapter *adapter = netdev_priv(netdev);
3424
3425 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
3426 return -EOPNOTSUPP;
3427 adapter->wol = 0;
3428 if (wol->wolopts & WAKE_UCAST)
3429 adapter->wol |= ATLX_WUFC_EX;
3430 if (wol->wolopts & WAKE_MCAST)
3431 adapter->wol |= ATLX_WUFC_MC;
3432 if (wol->wolopts & WAKE_BCAST)
3433 adapter->wol |= ATLX_WUFC_BC;
3434 if (wol->wolopts & WAKE_MAGIC)
3435 adapter->wol |= ATLX_WUFC_MAG;
3436 return 0;
3437 }
3438
3439 static u32 atl1_get_msglevel(struct net_device *netdev)
3440 {
3441 struct atl1_adapter *adapter = netdev_priv(netdev);
3442 return adapter->msg_enable;
3443 }
3444
3445 static void atl1_set_msglevel(struct net_device *netdev, u32 value)
3446 {
3447 struct atl1_adapter *adapter = netdev_priv(netdev);
3448 adapter->msg_enable = value;
3449 }
3450
3451 static int atl1_get_regs_len(struct net_device *netdev)
3452 {
3453 return ATL1_REG_COUNT * sizeof(u32);
3454 }
3455
3456 static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
3457 void *p)
3458 {
3459 struct atl1_adapter *adapter = netdev_priv(netdev);
3460 struct atl1_hw *hw = &adapter->hw;
3461 unsigned int i;
3462 u32 *regbuf = p;
3463
3464 for (i = 0; i < ATL1_REG_COUNT; i++) {
3465 /*
3466 * This switch statement avoids reserved regions
3467 * of register space.
3468 */
3469 switch (i) {
3470 case 6 ... 9:
3471 case 14:
3472 case 29 ... 31:
3473 case 34 ... 63:
3474 case 75 ... 127:
3475 case 136 ... 1023:
3476 case 1027 ... 1087:
3477 case 1091 ... 1151:
3478 case 1194 ... 1195:
3479 case 1200 ... 1201:
3480 case 1206 ... 1213:
3481 case 1216 ... 1279:
3482 case 1290 ... 1311:
3483 case 1323 ... 1343:
3484 case 1358 ... 1359:
3485 case 1368 ... 1375:
3486 case 1378 ... 1383:
3487 case 1388 ... 1391:
3488 case 1393 ... 1395:
3489 case 1402 ... 1403:
3490 case 1410 ... 1471:
3491 case 1522 ... 1535:
3492 /* reserved region; don't read it */
3493 regbuf[i] = 0;
3494 break;
3495 default:
3496 /* unreserved region */
3497 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
3498 }
3499 }
3500 }
3501
3502 static void atl1_get_ringparam(struct net_device *netdev,
3503 struct ethtool_ringparam *ring)
3504 {
3505 struct atl1_adapter *adapter = netdev_priv(netdev);
3506 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
3507 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
3508
3509 ring->rx_max_pending = ATL1_MAX_RFD;
3510 ring->tx_max_pending = ATL1_MAX_TPD;
3511 ring->rx_mini_max_pending = 0;
3512 ring->rx_jumbo_max_pending = 0;
3513 ring->rx_pending = rxdr->count;
3514 ring->tx_pending = txdr->count;
3515 ring->rx_mini_pending = 0;
3516 ring->rx_jumbo_pending = 0;
3517 }
3518
3519 static int atl1_set_ringparam(struct net_device *netdev,
3520 struct ethtool_ringparam *ring)
3521 {
3522 struct atl1_adapter *adapter = netdev_priv(netdev);
3523 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
3524 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
3525 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
3526
3527 struct atl1_tpd_ring tpd_old, tpd_new;
3528 struct atl1_rfd_ring rfd_old, rfd_new;
3529 struct atl1_rrd_ring rrd_old, rrd_new;
3530 struct atl1_ring_header rhdr_old, rhdr_new;
3531 int err;
3532
3533 tpd_old = adapter->tpd_ring;
3534 rfd_old = adapter->rfd_ring;
3535 rrd_old = adapter->rrd_ring;
3536 rhdr_old = adapter->ring_header;
3537
3538 if (netif_running(adapter->netdev))
3539 atl1_down(adapter);
3540
3541 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
3542 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
3543 rfdr->count;
3544 rfdr->count = (rfdr->count + 3) & ~3;
3545 rrdr->count = rfdr->count;
3546
3547 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
3548 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
3549 tpdr->count;
3550 tpdr->count = (tpdr->count + 3) & ~3;
3551
3552 if (netif_running(adapter->netdev)) {
3553 /* try to get new resources before deleting old */
3554 err = atl1_setup_ring_resources(adapter);
3555 if (err)
3556 goto err_setup_ring;
3557
3558 /*
3559 * save the new, restore the old in order to free it,
3560 * then restore the new back again
3561 */
3562
3563 rfd_new = adapter->rfd_ring;
3564 rrd_new = adapter->rrd_ring;
3565 tpd_new = adapter->tpd_ring;
3566 rhdr_new = adapter->ring_header;
3567 adapter->rfd_ring = rfd_old;
3568 adapter->rrd_ring = rrd_old;
3569 adapter->tpd_ring = tpd_old;
3570 adapter->ring_header = rhdr_old;
3571 atl1_free_ring_resources(adapter);
3572 adapter->rfd_ring = rfd_new;
3573 adapter->rrd_ring = rrd_new;
3574 adapter->tpd_ring = tpd_new;
3575 adapter->ring_header = rhdr_new;
3576
3577 err = atl1_up(adapter);
3578 if (err)
3579 return err;
3580 }
3581 return 0;
3582
3583 err_setup_ring:
3584 adapter->rfd_ring = rfd_old;
3585 adapter->rrd_ring = rrd_old;
3586 adapter->tpd_ring = tpd_old;
3587 adapter->ring_header = rhdr_old;
3588 atl1_up(adapter);
3589 return err;
3590 }
3591
3592 static void atl1_get_pauseparam(struct net_device *netdev,
3593 struct ethtool_pauseparam *epause)
3594 {
3595 struct atl1_adapter *adapter = netdev_priv(netdev);
3596 struct atl1_hw *hw = &adapter->hw;
3597
3598 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3599 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3600 epause->autoneg = AUTONEG_ENABLE;
3601 } else {
3602 epause->autoneg = AUTONEG_DISABLE;
3603 }
3604 epause->rx_pause = 1;
3605 epause->tx_pause = 1;
3606 }
3607
3608 static int atl1_set_pauseparam(struct net_device *netdev,
3609 struct ethtool_pauseparam *epause)
3610 {
3611 struct atl1_adapter *adapter = netdev_priv(netdev);
3612 struct atl1_hw *hw = &adapter->hw;
3613
3614 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3615 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3616 epause->autoneg = AUTONEG_ENABLE;
3617 } else {
3618 epause->autoneg = AUTONEG_DISABLE;
3619 }
3620
3621 epause->rx_pause = 1;
3622 epause->tx_pause = 1;
3623
3624 return 0;
3625 }
3626
3627 /* FIXME: is this right? -- CHS */
3628 static u32 atl1_get_rx_csum(struct net_device *netdev)
3629 {
3630 return 1;
3631 }
3632
3633 static void atl1_get_strings(struct net_device *netdev, u32 stringset,
3634 u8 *data)
3635 {
3636 u8 *p = data;
3637 int i;
3638
3639 switch (stringset) {
3640 case ETH_SS_STATS:
3641 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3642 memcpy(p, atl1_gstrings_stats[i].stat_string,
3643 ETH_GSTRING_LEN);
3644 p += ETH_GSTRING_LEN;
3645 }
3646 break;
3647 }
3648 }
3649
3650 static int atl1_nway_reset(struct net_device *netdev)
3651 {
3652 struct atl1_adapter *adapter = netdev_priv(netdev);
3653 struct atl1_hw *hw = &adapter->hw;
3654
3655 if (netif_running(netdev)) {
3656 u16 phy_data;
3657 atl1_down(adapter);
3658
3659 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3660 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3661 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3662 } else {
3663 switch (hw->media_type) {
3664 case MEDIA_TYPE_100M_FULL:
3665 phy_data = MII_CR_FULL_DUPLEX |
3666 MII_CR_SPEED_100 | MII_CR_RESET;
3667 break;
3668 case MEDIA_TYPE_100M_HALF:
3669 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3670 break;
3671 case MEDIA_TYPE_10M_FULL:
3672 phy_data = MII_CR_FULL_DUPLEX |
3673 MII_CR_SPEED_10 | MII_CR_RESET;
3674 break;
3675 default:
3676 /* MEDIA_TYPE_10M_HALF */
3677 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3678 }
3679 }
3680 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3681 atl1_up(adapter);
3682 }
3683 return 0;
3684 }
3685
3686 const struct ethtool_ops atl1_ethtool_ops = {
3687 .get_settings = atl1_get_settings,
3688 .set_settings = atl1_set_settings,
3689 .get_drvinfo = atl1_get_drvinfo,
3690 .get_wol = atl1_get_wol,
3691 .set_wol = atl1_set_wol,
3692 .get_msglevel = atl1_get_msglevel,
3693 .set_msglevel = atl1_set_msglevel,
3694 .get_regs_len = atl1_get_regs_len,
3695 .get_regs = atl1_get_regs,
3696 .get_ringparam = atl1_get_ringparam,
3697 .set_ringparam = atl1_set_ringparam,
3698 .get_pauseparam = atl1_get_pauseparam,
3699 .set_pauseparam = atl1_set_pauseparam,
3700 .get_rx_csum = atl1_get_rx_csum,
3701 .set_tx_csum = ethtool_op_set_tx_hw_csum,
3702 .get_link = ethtool_op_get_link,
3703 .set_sg = ethtool_op_set_sg,
3704 .get_strings = atl1_get_strings,
3705 .nway_reset = atl1_nway_reset,
3706 .get_ethtool_stats = atl1_get_ethtool_stats,
3707 .get_sset_count = atl1_get_sset_count,
3708 .set_tso = ethtool_op_set_tso,
3709 };
kernel source for telekom puls (alcatel/mediatek)