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Merge branch 'staging/for_v3.4' into v4l_for_linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mtd / nand / nandsim.c
1 /*
2 * NAND flash simulator.
3 *
4 * Author: Artem B. Bityuckiy <dedekind@oktetlabs.ru>, <dedekind@infradead.org>
5 *
6 * Copyright (C) 2004 Nokia Corporation
7 *
8 * Note: NS means "NAND Simulator".
9 * Note: Input means input TO flash chip, output means output FROM chip.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2, or (at your option) any later
14 * version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
19 * Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
24 */
25
26 #include <linux/init.h>
27 #include <linux/types.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/vmalloc.h>
31 #include <asm/div64.h>
32 #include <linux/slab.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
35 #include <linux/mtd/mtd.h>
36 #include <linux/mtd/nand.h>
37 #include <linux/mtd/nand_bch.h>
38 #include <linux/mtd/partitions.h>
39 #include <linux/delay.h>
40 #include <linux/list.h>
41 #include <linux/random.h>
42 #include <linux/sched.h>
43 #include <linux/fs.h>
44 #include <linux/pagemap.h>
45
46 /* Default simulator parameters values */
47 #if !defined(CONFIG_NANDSIM_FIRST_ID_BYTE) || \
48 !defined(CONFIG_NANDSIM_SECOND_ID_BYTE) || \
49 !defined(CONFIG_NANDSIM_THIRD_ID_BYTE) || \
50 !defined(CONFIG_NANDSIM_FOURTH_ID_BYTE)
51 #define CONFIG_NANDSIM_FIRST_ID_BYTE 0x98
52 #define CONFIG_NANDSIM_SECOND_ID_BYTE 0x39
53 #define CONFIG_NANDSIM_THIRD_ID_BYTE 0xFF /* No byte */
54 #define CONFIG_NANDSIM_FOURTH_ID_BYTE 0xFF /* No byte */
55 #endif
56
57 #ifndef CONFIG_NANDSIM_ACCESS_DELAY
58 #define CONFIG_NANDSIM_ACCESS_DELAY 25
59 #endif
60 #ifndef CONFIG_NANDSIM_PROGRAMM_DELAY
61 #define CONFIG_NANDSIM_PROGRAMM_DELAY 200
62 #endif
63 #ifndef CONFIG_NANDSIM_ERASE_DELAY
64 #define CONFIG_NANDSIM_ERASE_DELAY 2
65 #endif
66 #ifndef CONFIG_NANDSIM_OUTPUT_CYCLE
67 #define CONFIG_NANDSIM_OUTPUT_CYCLE 40
68 #endif
69 #ifndef CONFIG_NANDSIM_INPUT_CYCLE
70 #define CONFIG_NANDSIM_INPUT_CYCLE 50
71 #endif
72 #ifndef CONFIG_NANDSIM_BUS_WIDTH
73 #define CONFIG_NANDSIM_BUS_WIDTH 8
74 #endif
75 #ifndef CONFIG_NANDSIM_DO_DELAYS
76 #define CONFIG_NANDSIM_DO_DELAYS 0
77 #endif
78 #ifndef CONFIG_NANDSIM_LOG
79 #define CONFIG_NANDSIM_LOG 0
80 #endif
81 #ifndef CONFIG_NANDSIM_DBG
82 #define CONFIG_NANDSIM_DBG 0
83 #endif
84 #ifndef CONFIG_NANDSIM_MAX_PARTS
85 #define CONFIG_NANDSIM_MAX_PARTS 32
86 #endif
87
88 static uint first_id_byte = CONFIG_NANDSIM_FIRST_ID_BYTE;
89 static uint second_id_byte = CONFIG_NANDSIM_SECOND_ID_BYTE;
90 static uint third_id_byte = CONFIG_NANDSIM_THIRD_ID_BYTE;
91 static uint fourth_id_byte = CONFIG_NANDSIM_FOURTH_ID_BYTE;
92 static uint access_delay = CONFIG_NANDSIM_ACCESS_DELAY;
93 static uint programm_delay = CONFIG_NANDSIM_PROGRAMM_DELAY;
94 static uint erase_delay = CONFIG_NANDSIM_ERASE_DELAY;
95 static uint output_cycle = CONFIG_NANDSIM_OUTPUT_CYCLE;
96 static uint input_cycle = CONFIG_NANDSIM_INPUT_CYCLE;
97 static uint bus_width = CONFIG_NANDSIM_BUS_WIDTH;
98 static uint do_delays = CONFIG_NANDSIM_DO_DELAYS;
99 static uint log = CONFIG_NANDSIM_LOG;
100 static uint dbg = CONFIG_NANDSIM_DBG;
101 static unsigned long parts[CONFIG_NANDSIM_MAX_PARTS];
102 static unsigned int parts_num;
103 static char *badblocks = NULL;
104 static char *weakblocks = NULL;
105 static char *weakpages = NULL;
106 static unsigned int bitflips = 0;
107 static char *gravepages = NULL;
108 static unsigned int rptwear = 0;
109 static unsigned int overridesize = 0;
110 static char *cache_file = NULL;
111 static unsigned int bbt;
112 static unsigned int bch;
113
114 module_param(first_id_byte, uint, 0400);
115 module_param(second_id_byte, uint, 0400);
116 module_param(third_id_byte, uint, 0400);
117 module_param(fourth_id_byte, uint, 0400);
118 module_param(access_delay, uint, 0400);
119 module_param(programm_delay, uint, 0400);
120 module_param(erase_delay, uint, 0400);
121 module_param(output_cycle, uint, 0400);
122 module_param(input_cycle, uint, 0400);
123 module_param(bus_width, uint, 0400);
124 module_param(do_delays, uint, 0400);
125 module_param(log, uint, 0400);
126 module_param(dbg, uint, 0400);
127 module_param_array(parts, ulong, &parts_num, 0400);
128 module_param(badblocks, charp, 0400);
129 module_param(weakblocks, charp, 0400);
130 module_param(weakpages, charp, 0400);
131 module_param(bitflips, uint, 0400);
132 module_param(gravepages, charp, 0400);
133 module_param(rptwear, uint, 0400);
134 module_param(overridesize, uint, 0400);
135 module_param(cache_file, charp, 0400);
136 module_param(bbt, uint, 0400);
137 module_param(bch, uint, 0400);
138
139 MODULE_PARM_DESC(first_id_byte, "The first byte returned by NAND Flash 'read ID' command (manufacturer ID)");
140 MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID)");
141 MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command");
142 MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command");
143 MODULE_PARM_DESC(access_delay, "Initial page access delay (microseconds)");
144 MODULE_PARM_DESC(programm_delay, "Page programm delay (microseconds");
145 MODULE_PARM_DESC(erase_delay, "Sector erase delay (milliseconds)");
146 MODULE_PARM_DESC(output_cycle, "Word output (from flash) time (nanoseconds)");
147 MODULE_PARM_DESC(input_cycle, "Word input (to flash) time (nanoseconds)");
148 MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)");
149 MODULE_PARM_DESC(do_delays, "Simulate NAND delays using busy-waits if not zero");
150 MODULE_PARM_DESC(log, "Perform logging if not zero");
151 MODULE_PARM_DESC(dbg, "Output debug information if not zero");
152 MODULE_PARM_DESC(parts, "Partition sizes (in erase blocks) separated by commas");
153 /* Page and erase block positions for the following parameters are independent of any partitions */
154 MODULE_PARM_DESC(badblocks, "Erase blocks that are initially marked bad, separated by commas");
155 MODULE_PARM_DESC(weakblocks, "Weak erase blocks [: remaining erase cycles (defaults to 3)]"
156 " separated by commas e.g. 113:2 means eb 113"
157 " can be erased only twice before failing");
158 MODULE_PARM_DESC(weakpages, "Weak pages [: maximum writes (defaults to 3)]"
159 " separated by commas e.g. 1401:2 means page 1401"
160 " can be written only twice before failing");
161 MODULE_PARM_DESC(bitflips, "Maximum number of random bit flips per page (zero by default)");
162 MODULE_PARM_DESC(gravepages, "Pages that lose data [: maximum reads (defaults to 3)]"
163 " separated by commas e.g. 1401:2 means page 1401"
164 " can be read only twice before failing");
165 MODULE_PARM_DESC(rptwear, "Number of erases between reporting wear, if not zero");
166 MODULE_PARM_DESC(overridesize, "Specifies the NAND Flash size overriding the ID bytes. "
167 "The size is specified in erase blocks and as the exponent of a power of two"
168 " e.g. 5 means a size of 32 erase blocks");
169 MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of memory");
170 MODULE_PARM_DESC(bbt, "0 OOB, 1 BBT with marker in OOB, 2 BBT with marker in data area");
171 MODULE_PARM_DESC(bch, "Enable BCH ecc and set how many bits should "
172 "be correctable in 512-byte blocks");
173
174 /* The largest possible page size */
175 #define NS_LARGEST_PAGE_SIZE 4096
176
177 /* The prefix for simulator output */
178 #define NS_OUTPUT_PREFIX "[nandsim]"
179
180 /* Simulator's output macros (logging, debugging, warning, error) */
181 #define NS_LOG(args...) \
182 do { if (log) printk(KERN_DEBUG NS_OUTPUT_PREFIX " log: " args); } while(0)
183 #define NS_DBG(args...) \
184 do { if (dbg) printk(KERN_DEBUG NS_OUTPUT_PREFIX " debug: " args); } while(0)
185 #define NS_WARN(args...) \
186 do { printk(KERN_WARNING NS_OUTPUT_PREFIX " warning: " args); } while(0)
187 #define NS_ERR(args...) \
188 do { printk(KERN_ERR NS_OUTPUT_PREFIX " error: " args); } while(0)
189 #define NS_INFO(args...) \
190 do { printk(KERN_INFO NS_OUTPUT_PREFIX " " args); } while(0)
191
192 /* Busy-wait delay macros (microseconds, milliseconds) */
193 #define NS_UDELAY(us) \
194 do { if (do_delays) udelay(us); } while(0)
195 #define NS_MDELAY(us) \
196 do { if (do_delays) mdelay(us); } while(0)
197
198 /* Is the nandsim structure initialized ? */
199 #define NS_IS_INITIALIZED(ns) ((ns)->geom.totsz != 0)
200
201 /* Good operation completion status */
202 #define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0)))
203
204 /* Operation failed completion status */
205 #define NS_STATUS_FAILED(ns) (NAND_STATUS_FAIL | NS_STATUS_OK(ns))
206
207 /* Calculate the page offset in flash RAM image by (row, column) address */
208 #define NS_RAW_OFFSET(ns) \
209 (((ns)->regs.row << (ns)->geom.pgshift) + ((ns)->regs.row * (ns)->geom.oobsz) + (ns)->regs.column)
210
211 /* Calculate the OOB offset in flash RAM image by (row, column) address */
212 #define NS_RAW_OFFSET_OOB(ns) (NS_RAW_OFFSET(ns) + ns->geom.pgsz)
213
214 /* After a command is input, the simulator goes to one of the following states */
215 #define STATE_CMD_READ0 0x00000001 /* read data from the beginning of page */
216 #define STATE_CMD_READ1 0x00000002 /* read data from the second half of page */
217 #define STATE_CMD_READSTART 0x00000003 /* read data second command (large page devices) */
218 #define STATE_CMD_PAGEPROG 0x00000004 /* start page program */
219 #define STATE_CMD_READOOB 0x00000005 /* read OOB area */
220 #define STATE_CMD_ERASE1 0x00000006 /* sector erase first command */
221 #define STATE_CMD_STATUS 0x00000007 /* read status */
222 #define STATE_CMD_STATUS_M 0x00000008 /* read multi-plane status (isn't implemented) */
223 #define STATE_CMD_SEQIN 0x00000009 /* sequential data input */
224 #define STATE_CMD_READID 0x0000000A /* read ID */
225 #define STATE_CMD_ERASE2 0x0000000B /* sector erase second command */
226 #define STATE_CMD_RESET 0x0000000C /* reset */
227 #define STATE_CMD_RNDOUT 0x0000000D /* random output command */
228 #define STATE_CMD_RNDOUTSTART 0x0000000E /* random output start command */
229 #define STATE_CMD_MASK 0x0000000F /* command states mask */
230
231 /* After an address is input, the simulator goes to one of these states */
232 #define STATE_ADDR_PAGE 0x00000010 /* full (row, column) address is accepted */
233 #define STATE_ADDR_SEC 0x00000020 /* sector address was accepted */
234 #define STATE_ADDR_COLUMN 0x00000030 /* column address was accepted */
235 #define STATE_ADDR_ZERO 0x00000040 /* one byte zero address was accepted */
236 #define STATE_ADDR_MASK 0x00000070 /* address states mask */
237
238 /* During data input/output the simulator is in these states */
239 #define STATE_DATAIN 0x00000100 /* waiting for data input */
240 #define STATE_DATAIN_MASK 0x00000100 /* data input states mask */
241
242 #define STATE_DATAOUT 0x00001000 /* waiting for page data output */
243 #define STATE_DATAOUT_ID 0x00002000 /* waiting for ID bytes output */
244 #define STATE_DATAOUT_STATUS 0x00003000 /* waiting for status output */
245 #define STATE_DATAOUT_STATUS_M 0x00004000 /* waiting for multi-plane status output */
246 #define STATE_DATAOUT_MASK 0x00007000 /* data output states mask */
247
248 /* Previous operation is done, ready to accept new requests */
249 #define STATE_READY 0x00000000
250
251 /* This state is used to mark that the next state isn't known yet */
252 #define STATE_UNKNOWN 0x10000000
253
254 /* Simulator's actions bit masks */
255 #define ACTION_CPY 0x00100000 /* copy page/OOB to the internal buffer */
256 #define ACTION_PRGPAGE 0x00200000 /* program the internal buffer to flash */
257 #define ACTION_SECERASE 0x00300000 /* erase sector */
258 #define ACTION_ZEROOFF 0x00400000 /* don't add any offset to address */
259 #define ACTION_HALFOFF 0x00500000 /* add to address half of page */
260 #define ACTION_OOBOFF 0x00600000 /* add to address OOB offset */
261 #define ACTION_MASK 0x00700000 /* action mask */
262
263 #define NS_OPER_NUM 13 /* Number of operations supported by the simulator */
264 #define NS_OPER_STATES 6 /* Maximum number of states in operation */
265
266 #define OPT_ANY 0xFFFFFFFF /* any chip supports this operation */
267 #define OPT_PAGE256 0x00000001 /* 256-byte page chips */
268 #define OPT_PAGE512 0x00000002 /* 512-byte page chips */
269 #define OPT_PAGE2048 0x00000008 /* 2048-byte page chips */
270 #define OPT_SMARTMEDIA 0x00000010 /* SmartMedia technology chips */
271 #define OPT_AUTOINCR 0x00000020 /* page number auto incrementation is possible */
272 #define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */
273 #define OPT_PAGE4096 0x00000080 /* 4096-byte page chips */
274 #define OPT_LARGEPAGE (OPT_PAGE2048 | OPT_PAGE4096) /* 2048 & 4096-byte page chips */
275 #define OPT_SMALLPAGE (OPT_PAGE256 | OPT_PAGE512) /* 256 and 512-byte page chips */
276
277 /* Remove action bits from state */
278 #define NS_STATE(x) ((x) & ~ACTION_MASK)
279
280 /*
281 * Maximum previous states which need to be saved. Currently saving is
282 * only needed for page program operation with preceded read command
283 * (which is only valid for 512-byte pages).
284 */
285 #define NS_MAX_PREVSTATES 1
286
287 /* Maximum page cache pages needed to read or write a NAND page to the cache_file */
288 #define NS_MAX_HELD_PAGES 16
289
290 /*
291 * A union to represent flash memory contents and flash buffer.
292 */
293 union ns_mem {
294 u_char *byte; /* for byte access */
295 uint16_t *word; /* for 16-bit word access */
296 };
297
298 /*
299 * The structure which describes all the internal simulator data.
300 */
301 struct nandsim {
302 struct mtd_partition partitions[CONFIG_NANDSIM_MAX_PARTS];
303 unsigned int nbparts;
304
305 uint busw; /* flash chip bus width (8 or 16) */
306 u_char ids[4]; /* chip's ID bytes */
307 uint32_t options; /* chip's characteristic bits */
308 uint32_t state; /* current chip state */
309 uint32_t nxstate; /* next expected state */
310
311 uint32_t *op; /* current operation, NULL operations isn't known yet */
312 uint32_t pstates[NS_MAX_PREVSTATES]; /* previous states */
313 uint16_t npstates; /* number of previous states saved */
314 uint16_t stateidx; /* current state index */
315
316 /* The simulated NAND flash pages array */
317 union ns_mem *pages;
318
319 /* Slab allocator for nand pages */
320 struct kmem_cache *nand_pages_slab;
321
322 /* Internal buffer of page + OOB size bytes */
323 union ns_mem buf;
324
325 /* NAND flash "geometry" */
326 struct {
327 uint64_t totsz; /* total flash size, bytes */
328 uint32_t secsz; /* flash sector (erase block) size, bytes */
329 uint pgsz; /* NAND flash page size, bytes */
330 uint oobsz; /* page OOB area size, bytes */
331 uint64_t totszoob; /* total flash size including OOB, bytes */
332 uint pgszoob; /* page size including OOB , bytes*/
333 uint secszoob; /* sector size including OOB, bytes */
334 uint pgnum; /* total number of pages */
335 uint pgsec; /* number of pages per sector */
336 uint secshift; /* bits number in sector size */
337 uint pgshift; /* bits number in page size */
338 uint oobshift; /* bits number in OOB size */
339 uint pgaddrbytes; /* bytes per page address */
340 uint secaddrbytes; /* bytes per sector address */
341 uint idbytes; /* the number ID bytes that this chip outputs */
342 } geom;
343
344 /* NAND flash internal registers */
345 struct {
346 unsigned command; /* the command register */
347 u_char status; /* the status register */
348 uint row; /* the page number */
349 uint column; /* the offset within page */
350 uint count; /* internal counter */
351 uint num; /* number of bytes which must be processed */
352 uint off; /* fixed page offset */
353 } regs;
354
355 /* NAND flash lines state */
356 struct {
357 int ce; /* chip Enable */
358 int cle; /* command Latch Enable */
359 int ale; /* address Latch Enable */
360 int wp; /* write Protect */
361 } lines;
362
363 /* Fields needed when using a cache file */
364 struct file *cfile; /* Open file */
365 unsigned char *pages_written; /* Which pages have been written */
366 void *file_buf;
367 struct page *held_pages[NS_MAX_HELD_PAGES];
368 int held_cnt;
369 };
370
371 /*
372 * Operations array. To perform any operation the simulator must pass
373 * through the correspondent states chain.
374 */
375 static struct nandsim_operations {
376 uint32_t reqopts; /* options which are required to perform the operation */
377 uint32_t states[NS_OPER_STATES]; /* operation's states */
378 } ops[NS_OPER_NUM] = {
379 /* Read page + OOB from the beginning */
380 {OPT_SMALLPAGE, {STATE_CMD_READ0 | ACTION_ZEROOFF, STATE_ADDR_PAGE | ACTION_CPY,
381 STATE_DATAOUT, STATE_READY}},
382 /* Read page + OOB from the second half */
383 {OPT_PAGE512_8BIT, {STATE_CMD_READ1 | ACTION_HALFOFF, STATE_ADDR_PAGE | ACTION_CPY,
384 STATE_DATAOUT, STATE_READY}},
385 /* Read OOB */
386 {OPT_SMALLPAGE, {STATE_CMD_READOOB | ACTION_OOBOFF, STATE_ADDR_PAGE | ACTION_CPY,
387 STATE_DATAOUT, STATE_READY}},
388 /* Program page starting from the beginning */
389 {OPT_ANY, {STATE_CMD_SEQIN, STATE_ADDR_PAGE, STATE_DATAIN,
390 STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
391 /* Program page starting from the beginning */
392 {OPT_SMALLPAGE, {STATE_CMD_READ0, STATE_CMD_SEQIN | ACTION_ZEROOFF, STATE_ADDR_PAGE,
393 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
394 /* Program page starting from the second half */
395 {OPT_PAGE512, {STATE_CMD_READ1, STATE_CMD_SEQIN | ACTION_HALFOFF, STATE_ADDR_PAGE,
396 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
397 /* Program OOB */
398 {OPT_SMALLPAGE, {STATE_CMD_READOOB, STATE_CMD_SEQIN | ACTION_OOBOFF, STATE_ADDR_PAGE,
399 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
400 /* Erase sector */
401 {OPT_ANY, {STATE_CMD_ERASE1, STATE_ADDR_SEC, STATE_CMD_ERASE2 | ACTION_SECERASE, STATE_READY}},
402 /* Read status */
403 {OPT_ANY, {STATE_CMD_STATUS, STATE_DATAOUT_STATUS, STATE_READY}},
404 /* Read multi-plane status */
405 {OPT_SMARTMEDIA, {STATE_CMD_STATUS_M, STATE_DATAOUT_STATUS_M, STATE_READY}},
406 /* Read ID */
407 {OPT_ANY, {STATE_CMD_READID, STATE_ADDR_ZERO, STATE_DATAOUT_ID, STATE_READY}},
408 /* Large page devices read page */
409 {OPT_LARGEPAGE, {STATE_CMD_READ0, STATE_ADDR_PAGE, STATE_CMD_READSTART | ACTION_CPY,
410 STATE_DATAOUT, STATE_READY}},
411 /* Large page devices random page read */
412 {OPT_LARGEPAGE, {STATE_CMD_RNDOUT, STATE_ADDR_COLUMN, STATE_CMD_RNDOUTSTART | ACTION_CPY,
413 STATE_DATAOUT, STATE_READY}},
414 };
415
416 struct weak_block {
417 struct list_head list;
418 unsigned int erase_block_no;
419 unsigned int max_erases;
420 unsigned int erases_done;
421 };
422
423 static LIST_HEAD(weak_blocks);
424
425 struct weak_page {
426 struct list_head list;
427 unsigned int page_no;
428 unsigned int max_writes;
429 unsigned int writes_done;
430 };
431
432 static LIST_HEAD(weak_pages);
433
434 struct grave_page {
435 struct list_head list;
436 unsigned int page_no;
437 unsigned int max_reads;
438 unsigned int reads_done;
439 };
440
441 static LIST_HEAD(grave_pages);
442
443 static unsigned long *erase_block_wear = NULL;
444 static unsigned int wear_eb_count = 0;
445 static unsigned long total_wear = 0;
446 static unsigned int rptwear_cnt = 0;
447
448 /* MTD structure for NAND controller */
449 static struct mtd_info *nsmtd;
450
451 static u_char ns_verify_buf[NS_LARGEST_PAGE_SIZE];
452
453 /*
454 * Allocate array of page pointers, create slab allocation for an array
455 * and initialize the array by NULL pointers.
456 *
457 * RETURNS: 0 if success, -ENOMEM if memory alloc fails.
458 */
459 static int alloc_device(struct nandsim *ns)
460 {
461 struct file *cfile;
462 int i, err;
463
464 if (cache_file) {
465 cfile = filp_open(cache_file, O_CREAT | O_RDWR | O_LARGEFILE, 0600);
466 if (IS_ERR(cfile))
467 return PTR_ERR(cfile);
468 if (!cfile->f_op || (!cfile->f_op->read && !cfile->f_op->aio_read)) {
469 NS_ERR("alloc_device: cache file not readable\n");
470 err = -EINVAL;
471 goto err_close;
472 }
473 if (!cfile->f_op->write && !cfile->f_op->aio_write) {
474 NS_ERR("alloc_device: cache file not writeable\n");
475 err = -EINVAL;
476 goto err_close;
477 }
478 ns->pages_written = vzalloc(ns->geom.pgnum);
479 if (!ns->pages_written) {
480 NS_ERR("alloc_device: unable to allocate pages written array\n");
481 err = -ENOMEM;
482 goto err_close;
483 }
484 ns->file_buf = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
485 if (!ns->file_buf) {
486 NS_ERR("alloc_device: unable to allocate file buf\n");
487 err = -ENOMEM;
488 goto err_free;
489 }
490 ns->cfile = cfile;
491 return 0;
492 }
493
494 ns->pages = vmalloc(ns->geom.pgnum * sizeof(union ns_mem));
495 if (!ns->pages) {
496 NS_ERR("alloc_device: unable to allocate page array\n");
497 return -ENOMEM;
498 }
499 for (i = 0; i < ns->geom.pgnum; i++) {
500 ns->pages[i].byte = NULL;
501 }
502 ns->nand_pages_slab = kmem_cache_create("nandsim",
503 ns->geom.pgszoob, 0, 0, NULL);
504 if (!ns->nand_pages_slab) {
505 NS_ERR("cache_create: unable to create kmem_cache\n");
506 return -ENOMEM;
507 }
508
509 return 0;
510
511 err_free:
512 vfree(ns->pages_written);
513 err_close:
514 filp_close(cfile, NULL);
515 return err;
516 }
517
518 /*
519 * Free any allocated pages, and free the array of page pointers.
520 */
521 static void free_device(struct nandsim *ns)
522 {
523 int i;
524
525 if (ns->cfile) {
526 kfree(ns->file_buf);
527 vfree(ns->pages_written);
528 filp_close(ns->cfile, NULL);
529 return;
530 }
531
532 if (ns->pages) {
533 for (i = 0; i < ns->geom.pgnum; i++) {
534 if (ns->pages[i].byte)
535 kmem_cache_free(ns->nand_pages_slab,
536 ns->pages[i].byte);
537 }
538 kmem_cache_destroy(ns->nand_pages_slab);
539 vfree(ns->pages);
540 }
541 }
542
543 static char *get_partition_name(int i)
544 {
545 char buf[64];
546 sprintf(buf, "NAND simulator partition %d", i);
547 return kstrdup(buf, GFP_KERNEL);
548 }
549
550 static uint64_t divide(uint64_t n, uint32_t d)
551 {
552 do_div(n, d);
553 return n;
554 }
555
556 /*
557 * Initialize the nandsim structure.
558 *
559 * RETURNS: 0 if success, -ERRNO if failure.
560 */
561 static int init_nandsim(struct mtd_info *mtd)
562 {
563 struct nand_chip *chip = mtd->priv;
564 struct nandsim *ns = chip->priv;
565 int i, ret = 0;
566 uint64_t remains;
567 uint64_t next_offset;
568
569 if (NS_IS_INITIALIZED(ns)) {
570 NS_ERR("init_nandsim: nandsim is already initialized\n");
571 return -EIO;
572 }
573
574 /* Force mtd to not do delays */
575 chip->chip_delay = 0;
576
577 /* Initialize the NAND flash parameters */
578 ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8;
579 ns->geom.totsz = mtd->size;
580 ns->geom.pgsz = mtd->writesize;
581 ns->geom.oobsz = mtd->oobsize;
582 ns->geom.secsz = mtd->erasesize;
583 ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz;
584 ns->geom.pgnum = divide(ns->geom.totsz, ns->geom.pgsz);
585 ns->geom.totszoob = ns->geom.totsz + (uint64_t)ns->geom.pgnum * ns->geom.oobsz;
586 ns->geom.secshift = ffs(ns->geom.secsz) - 1;
587 ns->geom.pgshift = chip->page_shift;
588 ns->geom.oobshift = ffs(ns->geom.oobsz) - 1;
589 ns->geom.pgsec = ns->geom.secsz / ns->geom.pgsz;
590 ns->geom.secszoob = ns->geom.secsz + ns->geom.oobsz * ns->geom.pgsec;
591 ns->options = 0;
592
593 if (ns->geom.pgsz == 256) {
594 ns->options |= OPT_PAGE256;
595 }
596 else if (ns->geom.pgsz == 512) {
597 ns->options |= (OPT_PAGE512 | OPT_AUTOINCR);
598 if (ns->busw == 8)
599 ns->options |= OPT_PAGE512_8BIT;
600 } else if (ns->geom.pgsz == 2048) {
601 ns->options |= OPT_PAGE2048;
602 } else if (ns->geom.pgsz == 4096) {
603 ns->options |= OPT_PAGE4096;
604 } else {
605 NS_ERR("init_nandsim: unknown page size %u\n", ns->geom.pgsz);
606 return -EIO;
607 }
608
609 if (ns->options & OPT_SMALLPAGE) {
610 if (ns->geom.totsz <= (32 << 20)) {
611 ns->geom.pgaddrbytes = 3;
612 ns->geom.secaddrbytes = 2;
613 } else {
614 ns->geom.pgaddrbytes = 4;
615 ns->geom.secaddrbytes = 3;
616 }
617 } else {
618 if (ns->geom.totsz <= (128 << 20)) {
619 ns->geom.pgaddrbytes = 4;
620 ns->geom.secaddrbytes = 2;
621 } else {
622 ns->geom.pgaddrbytes = 5;
623 ns->geom.secaddrbytes = 3;
624 }
625 }
626
627 /* Fill the partition_info structure */
628 if (parts_num > ARRAY_SIZE(ns->partitions)) {
629 NS_ERR("too many partitions.\n");
630 ret = -EINVAL;
631 goto error;
632 }
633 remains = ns->geom.totsz;
634 next_offset = 0;
635 for (i = 0; i < parts_num; ++i) {
636 uint64_t part_sz = (uint64_t)parts[i] * ns->geom.secsz;
637
638 if (!part_sz || part_sz > remains) {
639 NS_ERR("bad partition size.\n");
640 ret = -EINVAL;
641 goto error;
642 }
643 ns->partitions[i].name = get_partition_name(i);
644 ns->partitions[i].offset = next_offset;
645 ns->partitions[i].size = part_sz;
646 next_offset += ns->partitions[i].size;
647 remains -= ns->partitions[i].size;
648 }
649 ns->nbparts = parts_num;
650 if (remains) {
651 if (parts_num + 1 > ARRAY_SIZE(ns->partitions)) {
652 NS_ERR("too many partitions.\n");
653 ret = -EINVAL;
654 goto error;
655 }
656 ns->partitions[i].name = get_partition_name(i);
657 ns->partitions[i].offset = next_offset;
658 ns->partitions[i].size = remains;
659 ns->nbparts += 1;
660 }
661
662 /* Detect how many ID bytes the NAND chip outputs */
663 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
664 if (second_id_byte != nand_flash_ids[i].id)
665 continue;
666 if (!(nand_flash_ids[i].options & NAND_NO_AUTOINCR))
667 ns->options |= OPT_AUTOINCR;
668 }
669
670 if (ns->busw == 16)
671 NS_WARN("16-bit flashes support wasn't tested\n");
672
673 printk("flash size: %llu MiB\n",
674 (unsigned long long)ns->geom.totsz >> 20);
675 printk("page size: %u bytes\n", ns->geom.pgsz);
676 printk("OOB area size: %u bytes\n", ns->geom.oobsz);
677 printk("sector size: %u KiB\n", ns->geom.secsz >> 10);
678 printk("pages number: %u\n", ns->geom.pgnum);
679 printk("pages per sector: %u\n", ns->geom.pgsec);
680 printk("bus width: %u\n", ns->busw);
681 printk("bits in sector size: %u\n", ns->geom.secshift);
682 printk("bits in page size: %u\n", ns->geom.pgshift);
683 printk("bits in OOB size: %u\n", ns->geom.oobshift);
684 printk("flash size with OOB: %llu KiB\n",
685 (unsigned long long)ns->geom.totszoob >> 10);
686 printk("page address bytes: %u\n", ns->geom.pgaddrbytes);
687 printk("sector address bytes: %u\n", ns->geom.secaddrbytes);
688 printk("options: %#x\n", ns->options);
689
690 if ((ret = alloc_device(ns)) != 0)
691 goto error;
692
693 /* Allocate / initialize the internal buffer */
694 ns->buf.byte = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
695 if (!ns->buf.byte) {
696 NS_ERR("init_nandsim: unable to allocate %u bytes for the internal buffer\n",
697 ns->geom.pgszoob);
698 ret = -ENOMEM;
699 goto error;
700 }
701 memset(ns->buf.byte, 0xFF, ns->geom.pgszoob);
702
703 return 0;
704
705 error:
706 free_device(ns);
707
708 return ret;
709 }
710
711 /*
712 * Free the nandsim structure.
713 */
714 static void free_nandsim(struct nandsim *ns)
715 {
716 kfree(ns->buf.byte);
717 free_device(ns);
718
719 return;
720 }
721
722 static int parse_badblocks(struct nandsim *ns, struct mtd_info *mtd)
723 {
724 char *w;
725 int zero_ok;
726 unsigned int erase_block_no;
727 loff_t offset;
728
729 if (!badblocks)
730 return 0;
731 w = badblocks;
732 do {
733 zero_ok = (*w == '0' ? 1 : 0);
734 erase_block_no = simple_strtoul(w, &w, 0);
735 if (!zero_ok && !erase_block_no) {
736 NS_ERR("invalid badblocks.\n");
737 return -EINVAL;
738 }
739 offset = erase_block_no * ns->geom.secsz;
740 if (mtd_block_markbad(mtd, offset)) {
741 NS_ERR("invalid badblocks.\n");
742 return -EINVAL;
743 }
744 if (*w == ',')
745 w += 1;
746 } while (*w);
747 return 0;
748 }
749
750 static int parse_weakblocks(void)
751 {
752 char *w;
753 int zero_ok;
754 unsigned int erase_block_no;
755 unsigned int max_erases;
756 struct weak_block *wb;
757
758 if (!weakblocks)
759 return 0;
760 w = weakblocks;
761 do {
762 zero_ok = (*w == '0' ? 1 : 0);
763 erase_block_no = simple_strtoul(w, &w, 0);
764 if (!zero_ok && !erase_block_no) {
765 NS_ERR("invalid weakblocks.\n");
766 return -EINVAL;
767 }
768 max_erases = 3;
769 if (*w == ':') {
770 w += 1;
771 max_erases = simple_strtoul(w, &w, 0);
772 }
773 if (*w == ',')
774 w += 1;
775 wb = kzalloc(sizeof(*wb), GFP_KERNEL);
776 if (!wb) {
777 NS_ERR("unable to allocate memory.\n");
778 return -ENOMEM;
779 }
780 wb->erase_block_no = erase_block_no;
781 wb->max_erases = max_erases;
782 list_add(&wb->list, &weak_blocks);
783 } while (*w);
784 return 0;
785 }
786
787 static int erase_error(unsigned int erase_block_no)
788 {
789 struct weak_block *wb;
790
791 list_for_each_entry(wb, &weak_blocks, list)
792 if (wb->erase_block_no == erase_block_no) {
793 if (wb->erases_done >= wb->max_erases)
794 return 1;
795 wb->erases_done += 1;
796 return 0;
797 }
798 return 0;
799 }
800
801 static int parse_weakpages(void)
802 {
803 char *w;
804 int zero_ok;
805 unsigned int page_no;
806 unsigned int max_writes;
807 struct weak_page *wp;
808
809 if (!weakpages)
810 return 0;
811 w = weakpages;
812 do {
813 zero_ok = (*w == '0' ? 1 : 0);
814 page_no = simple_strtoul(w, &w, 0);
815 if (!zero_ok && !page_no) {
816 NS_ERR("invalid weakpagess.\n");
817 return -EINVAL;
818 }
819 max_writes = 3;
820 if (*w == ':') {
821 w += 1;
822 max_writes = simple_strtoul(w, &w, 0);
823 }
824 if (*w == ',')
825 w += 1;
826 wp = kzalloc(sizeof(*wp), GFP_KERNEL);
827 if (!wp) {
828 NS_ERR("unable to allocate memory.\n");
829 return -ENOMEM;
830 }
831 wp->page_no = page_no;
832 wp->max_writes = max_writes;
833 list_add(&wp->list, &weak_pages);
834 } while (*w);
835 return 0;
836 }
837
838 static int write_error(unsigned int page_no)
839 {
840 struct weak_page *wp;
841
842 list_for_each_entry(wp, &weak_pages, list)
843 if (wp->page_no == page_no) {
844 if (wp->writes_done >= wp->max_writes)
845 return 1;
846 wp->writes_done += 1;
847 return 0;
848 }
849 return 0;
850 }
851
852 static int parse_gravepages(void)
853 {
854 char *g;
855 int zero_ok;
856 unsigned int page_no;
857 unsigned int max_reads;
858 struct grave_page *gp;
859
860 if (!gravepages)
861 return 0;
862 g = gravepages;
863 do {
864 zero_ok = (*g == '0' ? 1 : 0);
865 page_no = simple_strtoul(g, &g, 0);
866 if (!zero_ok && !page_no) {
867 NS_ERR("invalid gravepagess.\n");
868 return -EINVAL;
869 }
870 max_reads = 3;
871 if (*g == ':') {
872 g += 1;
873 max_reads = simple_strtoul(g, &g, 0);
874 }
875 if (*g == ',')
876 g += 1;
877 gp = kzalloc(sizeof(*gp), GFP_KERNEL);
878 if (!gp) {
879 NS_ERR("unable to allocate memory.\n");
880 return -ENOMEM;
881 }
882 gp->page_no = page_no;
883 gp->max_reads = max_reads;
884 list_add(&gp->list, &grave_pages);
885 } while (*g);
886 return 0;
887 }
888
889 static int read_error(unsigned int page_no)
890 {
891 struct grave_page *gp;
892
893 list_for_each_entry(gp, &grave_pages, list)
894 if (gp->page_no == page_no) {
895 if (gp->reads_done >= gp->max_reads)
896 return 1;
897 gp->reads_done += 1;
898 return 0;
899 }
900 return 0;
901 }
902
903 static void free_lists(void)
904 {
905 struct list_head *pos, *n;
906 list_for_each_safe(pos, n, &weak_blocks) {
907 list_del(pos);
908 kfree(list_entry(pos, struct weak_block, list));
909 }
910 list_for_each_safe(pos, n, &weak_pages) {
911 list_del(pos);
912 kfree(list_entry(pos, struct weak_page, list));
913 }
914 list_for_each_safe(pos, n, &grave_pages) {
915 list_del(pos);
916 kfree(list_entry(pos, struct grave_page, list));
917 }
918 kfree(erase_block_wear);
919 }
920
921 static int setup_wear_reporting(struct mtd_info *mtd)
922 {
923 size_t mem;
924
925 if (!rptwear)
926 return 0;
927 wear_eb_count = divide(mtd->size, mtd->erasesize);
928 mem = wear_eb_count * sizeof(unsigned long);
929 if (mem / sizeof(unsigned long) != wear_eb_count) {
930 NS_ERR("Too many erase blocks for wear reporting\n");
931 return -ENOMEM;
932 }
933 erase_block_wear = kzalloc(mem, GFP_KERNEL);
934 if (!erase_block_wear) {
935 NS_ERR("Too many erase blocks for wear reporting\n");
936 return -ENOMEM;
937 }
938 return 0;
939 }
940
941 static void update_wear(unsigned int erase_block_no)
942 {
943 unsigned long wmin = -1, wmax = 0, avg;
944 unsigned long deciles[10], decile_max[10], tot = 0;
945 unsigned int i;
946
947 if (!erase_block_wear)
948 return;
949 total_wear += 1;
950 if (total_wear == 0)
951 NS_ERR("Erase counter total overflow\n");
952 erase_block_wear[erase_block_no] += 1;
953 if (erase_block_wear[erase_block_no] == 0)
954 NS_ERR("Erase counter overflow for erase block %u\n", erase_block_no);
955 rptwear_cnt += 1;
956 if (rptwear_cnt < rptwear)
957 return;
958 rptwear_cnt = 0;
959 /* Calc wear stats */
960 for (i = 0; i < wear_eb_count; ++i) {
961 unsigned long wear = erase_block_wear[i];
962 if (wear < wmin)
963 wmin = wear;
964 if (wear > wmax)
965 wmax = wear;
966 tot += wear;
967 }
968 for (i = 0; i < 9; ++i) {
969 deciles[i] = 0;
970 decile_max[i] = (wmax * (i + 1) + 5) / 10;
971 }
972 deciles[9] = 0;
973 decile_max[9] = wmax;
974 for (i = 0; i < wear_eb_count; ++i) {
975 int d;
976 unsigned long wear = erase_block_wear[i];
977 for (d = 0; d < 10; ++d)
978 if (wear <= decile_max[d]) {
979 deciles[d] += 1;
980 break;
981 }
982 }
983 avg = tot / wear_eb_count;
984 /* Output wear report */
985 NS_INFO("*** Wear Report ***\n");
986 NS_INFO("Total numbers of erases: %lu\n", tot);
987 NS_INFO("Number of erase blocks: %u\n", wear_eb_count);
988 NS_INFO("Average number of erases: %lu\n", avg);
989 NS_INFO("Maximum number of erases: %lu\n", wmax);
990 NS_INFO("Minimum number of erases: %lu\n", wmin);
991 for (i = 0; i < 10; ++i) {
992 unsigned long from = (i ? decile_max[i - 1] + 1 : 0);
993 if (from > decile_max[i])
994 continue;
995 NS_INFO("Number of ebs with erase counts from %lu to %lu : %lu\n",
996 from,
997 decile_max[i],
998 deciles[i]);
999 }
1000 NS_INFO("*** End of Wear Report ***\n");
1001 }
1002
1003 /*
1004 * Returns the string representation of 'state' state.
1005 */
1006 static char *get_state_name(uint32_t state)
1007 {
1008 switch (NS_STATE(state)) {
1009 case STATE_CMD_READ0:
1010 return "STATE_CMD_READ0";
1011 case STATE_CMD_READ1:
1012 return "STATE_CMD_READ1";
1013 case STATE_CMD_PAGEPROG:
1014 return "STATE_CMD_PAGEPROG";
1015 case STATE_CMD_READOOB:
1016 return "STATE_CMD_READOOB";
1017 case STATE_CMD_READSTART:
1018 return "STATE_CMD_READSTART";
1019 case STATE_CMD_ERASE1:
1020 return "STATE_CMD_ERASE1";
1021 case STATE_CMD_STATUS:
1022 return "STATE_CMD_STATUS";
1023 case STATE_CMD_STATUS_M:
1024 return "STATE_CMD_STATUS_M";
1025 case STATE_CMD_SEQIN:
1026 return "STATE_CMD_SEQIN";
1027 case STATE_CMD_READID:
1028 return "STATE_CMD_READID";
1029 case STATE_CMD_ERASE2:
1030 return "STATE_CMD_ERASE2";
1031 case STATE_CMD_RESET:
1032 return "STATE_CMD_RESET";
1033 case STATE_CMD_RNDOUT:
1034 return "STATE_CMD_RNDOUT";
1035 case STATE_CMD_RNDOUTSTART:
1036 return "STATE_CMD_RNDOUTSTART";
1037 case STATE_ADDR_PAGE:
1038 return "STATE_ADDR_PAGE";
1039 case STATE_ADDR_SEC:
1040 return "STATE_ADDR_SEC";
1041 case STATE_ADDR_ZERO:
1042 return "STATE_ADDR_ZERO";
1043 case STATE_ADDR_COLUMN:
1044 return "STATE_ADDR_COLUMN";
1045 case STATE_DATAIN:
1046 return "STATE_DATAIN";
1047 case STATE_DATAOUT:
1048 return "STATE_DATAOUT";
1049 case STATE_DATAOUT_ID:
1050 return "STATE_DATAOUT_ID";
1051 case STATE_DATAOUT_STATUS:
1052 return "STATE_DATAOUT_STATUS";
1053 case STATE_DATAOUT_STATUS_M:
1054 return "STATE_DATAOUT_STATUS_M";
1055 case STATE_READY:
1056 return "STATE_READY";
1057 case STATE_UNKNOWN:
1058 return "STATE_UNKNOWN";
1059 }
1060
1061 NS_ERR("get_state_name: unknown state, BUG\n");
1062 return NULL;
1063 }
1064
1065 /*
1066 * Check if command is valid.
1067 *
1068 * RETURNS: 1 if wrong command, 0 if right.
1069 */
1070 static int check_command(int cmd)
1071 {
1072 switch (cmd) {
1073
1074 case NAND_CMD_READ0:
1075 case NAND_CMD_READ1:
1076 case NAND_CMD_READSTART:
1077 case NAND_CMD_PAGEPROG:
1078 case NAND_CMD_READOOB:
1079 case NAND_CMD_ERASE1:
1080 case NAND_CMD_STATUS:
1081 case NAND_CMD_SEQIN:
1082 case NAND_CMD_READID:
1083 case NAND_CMD_ERASE2:
1084 case NAND_CMD_RESET:
1085 case NAND_CMD_RNDOUT:
1086 case NAND_CMD_RNDOUTSTART:
1087 return 0;
1088
1089 case NAND_CMD_STATUS_MULTI:
1090 default:
1091 return 1;
1092 }
1093 }
1094
1095 /*
1096 * Returns state after command is accepted by command number.
1097 */
1098 static uint32_t get_state_by_command(unsigned command)
1099 {
1100 switch (command) {
1101 case NAND_CMD_READ0:
1102 return STATE_CMD_READ0;
1103 case NAND_CMD_READ1:
1104 return STATE_CMD_READ1;
1105 case NAND_CMD_PAGEPROG:
1106 return STATE_CMD_PAGEPROG;
1107 case NAND_CMD_READSTART:
1108 return STATE_CMD_READSTART;
1109 case NAND_CMD_READOOB:
1110 return STATE_CMD_READOOB;
1111 case NAND_CMD_ERASE1:
1112 return STATE_CMD_ERASE1;
1113 case NAND_CMD_STATUS:
1114 return STATE_CMD_STATUS;
1115 case NAND_CMD_STATUS_MULTI:
1116 return STATE_CMD_STATUS_M;
1117 case NAND_CMD_SEQIN:
1118 return STATE_CMD_SEQIN;
1119 case NAND_CMD_READID:
1120 return STATE_CMD_READID;
1121 case NAND_CMD_ERASE2:
1122 return STATE_CMD_ERASE2;
1123 case NAND_CMD_RESET:
1124 return STATE_CMD_RESET;
1125 case NAND_CMD_RNDOUT:
1126 return STATE_CMD_RNDOUT;
1127 case NAND_CMD_RNDOUTSTART:
1128 return STATE_CMD_RNDOUTSTART;
1129 }
1130
1131 NS_ERR("get_state_by_command: unknown command, BUG\n");
1132 return 0;
1133 }
1134
1135 /*
1136 * Move an address byte to the correspondent internal register.
1137 */
1138 static inline void accept_addr_byte(struct nandsim *ns, u_char bt)
1139 {
1140 uint byte = (uint)bt;
1141
1142 if (ns->regs.count < (ns->geom.pgaddrbytes - ns->geom.secaddrbytes))
1143 ns->regs.column |= (byte << 8 * ns->regs.count);
1144 else {
1145 ns->regs.row |= (byte << 8 * (ns->regs.count -
1146 ns->geom.pgaddrbytes +
1147 ns->geom.secaddrbytes));
1148 }
1149
1150 return;
1151 }
1152
1153 /*
1154 * Switch to STATE_READY state.
1155 */
1156 static inline void switch_to_ready_state(struct nandsim *ns, u_char status)
1157 {
1158 NS_DBG("switch_to_ready_state: switch to %s state\n", get_state_name(STATE_READY));
1159
1160 ns->state = STATE_READY;
1161 ns->nxstate = STATE_UNKNOWN;
1162 ns->op = NULL;
1163 ns->npstates = 0;
1164 ns->stateidx = 0;
1165 ns->regs.num = 0;
1166 ns->regs.count = 0;
1167 ns->regs.off = 0;
1168 ns->regs.row = 0;
1169 ns->regs.column = 0;
1170 ns->regs.status = status;
1171 }
1172
1173 /*
1174 * If the operation isn't known yet, try to find it in the global array
1175 * of supported operations.
1176 *
1177 * Operation can be unknown because of the following.
1178 * 1. New command was accepted and this is the first call to find the
1179 * correspondent states chain. In this case ns->npstates = 0;
1180 * 2. There are several operations which begin with the same command(s)
1181 * (for example program from the second half and read from the
1182 * second half operations both begin with the READ1 command). In this
1183 * case the ns->pstates[] array contains previous states.
1184 *
1185 * Thus, the function tries to find operation containing the following
1186 * states (if the 'flag' parameter is 0):
1187 * ns->pstates[0], ... ns->pstates[ns->npstates], ns->state
1188 *
1189 * If (one and only one) matching operation is found, it is accepted (
1190 * ns->ops, ns->state, ns->nxstate are initialized, ns->npstate is
1191 * zeroed).
1192 *
1193 * If there are several matches, the current state is pushed to the
1194 * ns->pstates.
1195 *
1196 * The operation can be unknown only while commands are input to the chip.
1197 * As soon as address command is accepted, the operation must be known.
1198 * In such situation the function is called with 'flag' != 0, and the
1199 * operation is searched using the following pattern:
1200 * ns->pstates[0], ... ns->pstates[ns->npstates], <address input>
1201 *
1202 * It is supposed that this pattern must either match one operation or
1203 * none. There can't be ambiguity in that case.
1204 *
1205 * If no matches found, the function does the following:
1206 * 1. if there are saved states present, try to ignore them and search
1207 * again only using the last command. If nothing was found, switch
1208 * to the STATE_READY state.
1209 * 2. if there are no saved states, switch to the STATE_READY state.
1210 *
1211 * RETURNS: -2 - no matched operations found.
1212 * -1 - several matches.
1213 * 0 - operation is found.
1214 */
1215 static int find_operation(struct nandsim *ns, uint32_t flag)
1216 {
1217 int opsfound = 0;
1218 int i, j, idx = 0;
1219
1220 for (i = 0; i < NS_OPER_NUM; i++) {
1221
1222 int found = 1;
1223
1224 if (!(ns->options & ops[i].reqopts))
1225 /* Ignore operations we can't perform */
1226 continue;
1227
1228 if (flag) {
1229 if (!(ops[i].states[ns->npstates] & STATE_ADDR_MASK))
1230 continue;
1231 } else {
1232 if (NS_STATE(ns->state) != NS_STATE(ops[i].states[ns->npstates]))
1233 continue;
1234 }
1235
1236 for (j = 0; j < ns->npstates; j++)
1237 if (NS_STATE(ops[i].states[j]) != NS_STATE(ns->pstates[j])
1238 && (ns->options & ops[idx].reqopts)) {
1239 found = 0;
1240 break;
1241 }
1242
1243 if (found) {
1244 idx = i;
1245 opsfound += 1;
1246 }
1247 }
1248
1249 if (opsfound == 1) {
1250 /* Exact match */
1251 ns->op = &ops[idx].states[0];
1252 if (flag) {
1253 /*
1254 * In this case the find_operation function was
1255 * called when address has just began input. But it isn't
1256 * yet fully input and the current state must
1257 * not be one of STATE_ADDR_*, but the STATE_ADDR_*
1258 * state must be the next state (ns->nxstate).
1259 */
1260 ns->stateidx = ns->npstates - 1;
1261 } else {
1262 ns->stateidx = ns->npstates;
1263 }
1264 ns->npstates = 0;
1265 ns->state = ns->op[ns->stateidx];
1266 ns->nxstate = ns->op[ns->stateidx + 1];
1267 NS_DBG("find_operation: operation found, index: %d, state: %s, nxstate %s\n",
1268 idx, get_state_name(ns->state), get_state_name(ns->nxstate));
1269 return 0;
1270 }
1271
1272 if (opsfound == 0) {
1273 /* Nothing was found. Try to ignore previous commands (if any) and search again */
1274 if (ns->npstates != 0) {
1275 NS_DBG("find_operation: no operation found, try again with state %s\n",
1276 get_state_name(ns->state));
1277 ns->npstates = 0;
1278 return find_operation(ns, 0);
1279
1280 }
1281 NS_DBG("find_operation: no operations found\n");
1282 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1283 return -2;
1284 }
1285
1286 if (flag) {
1287 /* This shouldn't happen */
1288 NS_DBG("find_operation: BUG, operation must be known if address is input\n");
1289 return -2;
1290 }
1291
1292 NS_DBG("find_operation: there is still ambiguity\n");
1293
1294 ns->pstates[ns->npstates++] = ns->state;
1295
1296 return -1;
1297 }
1298
1299 static void put_pages(struct nandsim *ns)
1300 {
1301 int i;
1302
1303 for (i = 0; i < ns->held_cnt; i++)
1304 page_cache_release(ns->held_pages[i]);
1305 }
1306
1307 /* Get page cache pages in advance to provide NOFS memory allocation */
1308 static int get_pages(struct nandsim *ns, struct file *file, size_t count, loff_t pos)
1309 {
1310 pgoff_t index, start_index, end_index;
1311 struct page *page;
1312 struct address_space *mapping = file->f_mapping;
1313
1314 start_index = pos >> PAGE_CACHE_SHIFT;
1315 end_index = (pos + count - 1) >> PAGE_CACHE_SHIFT;
1316 if (end_index - start_index + 1 > NS_MAX_HELD_PAGES)
1317 return -EINVAL;
1318 ns->held_cnt = 0;
1319 for (index = start_index; index <= end_index; index++) {
1320 page = find_get_page(mapping, index);
1321 if (page == NULL) {
1322 page = find_or_create_page(mapping, index, GFP_NOFS);
1323 if (page == NULL) {
1324 write_inode_now(mapping->host, 1);
1325 page = find_or_create_page(mapping, index, GFP_NOFS);
1326 }
1327 if (page == NULL) {
1328 put_pages(ns);
1329 return -ENOMEM;
1330 }
1331 unlock_page(page);
1332 }
1333 ns->held_pages[ns->held_cnt++] = page;
1334 }
1335 return 0;
1336 }
1337
1338 static int set_memalloc(void)
1339 {
1340 if (current->flags & PF_MEMALLOC)
1341 return 0;
1342 current->flags |= PF_MEMALLOC;
1343 return 1;
1344 }
1345
1346 static void clear_memalloc(int memalloc)
1347 {
1348 if (memalloc)
1349 current->flags &= ~PF_MEMALLOC;
1350 }
1351
1352 static ssize_t read_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t *pos)
1353 {
1354 mm_segment_t old_fs;
1355 ssize_t tx;
1356 int err, memalloc;
1357
1358 err = get_pages(ns, file, count, *pos);
1359 if (err)
1360 return err;
1361 old_fs = get_fs();
1362 set_fs(get_ds());
1363 memalloc = set_memalloc();
1364 tx = vfs_read(file, (char __user *)buf, count, pos);
1365 clear_memalloc(memalloc);
1366 set_fs(old_fs);
1367 put_pages(ns);
1368 return tx;
1369 }
1370
1371 static ssize_t write_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t *pos)
1372 {
1373 mm_segment_t old_fs;
1374 ssize_t tx;
1375 int err, memalloc;
1376
1377 err = get_pages(ns, file, count, *pos);
1378 if (err)
1379 return err;
1380 old_fs = get_fs();
1381 set_fs(get_ds());
1382 memalloc = set_memalloc();
1383 tx = vfs_write(file, (char __user *)buf, count, pos);
1384 clear_memalloc(memalloc);
1385 set_fs(old_fs);
1386 put_pages(ns);
1387 return tx;
1388 }
1389
1390 /*
1391 * Returns a pointer to the current page.
1392 */
1393 static inline union ns_mem *NS_GET_PAGE(struct nandsim *ns)
1394 {
1395 return &(ns->pages[ns->regs.row]);
1396 }
1397
1398 /*
1399 * Retuns a pointer to the current byte, within the current page.
1400 */
1401 static inline u_char *NS_PAGE_BYTE_OFF(struct nandsim *ns)
1402 {
1403 return NS_GET_PAGE(ns)->byte + ns->regs.column + ns->regs.off;
1404 }
1405
1406 int do_read_error(struct nandsim *ns, int num)
1407 {
1408 unsigned int page_no = ns->regs.row;
1409
1410 if (read_error(page_no)) {
1411 int i;
1412 memset(ns->buf.byte, 0xFF, num);
1413 for (i = 0; i < num; ++i)
1414 ns->buf.byte[i] = random32();
1415 NS_WARN("simulating read error in page %u\n", page_no);
1416 return 1;
1417 }
1418 return 0;
1419 }
1420
1421 void do_bit_flips(struct nandsim *ns, int num)
1422 {
1423 if (bitflips && random32() < (1 << 22)) {
1424 int flips = 1;
1425 if (bitflips > 1)
1426 flips = (random32() % (int) bitflips) + 1;
1427 while (flips--) {
1428 int pos = random32() % (num * 8);
1429 ns->buf.byte[pos / 8] ^= (1 << (pos % 8));
1430 NS_WARN("read_page: flipping bit %d in page %d "
1431 "reading from %d ecc: corrected=%u failed=%u\n",
1432 pos, ns->regs.row, ns->regs.column + ns->regs.off,
1433 nsmtd->ecc_stats.corrected, nsmtd->ecc_stats.failed);
1434 }
1435 }
1436 }
1437
1438 /*
1439 * Fill the NAND buffer with data read from the specified page.
1440 */
1441 static void read_page(struct nandsim *ns, int num)
1442 {
1443 union ns_mem *mypage;
1444
1445 if (ns->cfile) {
1446 if (!ns->pages_written[ns->regs.row]) {
1447 NS_DBG("read_page: page %d not written\n", ns->regs.row);
1448 memset(ns->buf.byte, 0xFF, num);
1449 } else {
1450 loff_t pos;
1451 ssize_t tx;
1452
1453 NS_DBG("read_page: page %d written, reading from %d\n",
1454 ns->regs.row, ns->regs.column + ns->regs.off);
1455 if (do_read_error(ns, num))
1456 return;
1457 pos = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off;
1458 tx = read_file(ns, ns->cfile, ns->buf.byte, num, &pos);
1459 if (tx != num) {
1460 NS_ERR("read_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1461 return;
1462 }
1463 do_bit_flips(ns, num);
1464 }
1465 return;
1466 }
1467
1468 mypage = NS_GET_PAGE(ns);
1469 if (mypage->byte == NULL) {
1470 NS_DBG("read_page: page %d not allocated\n", ns->regs.row);
1471 memset(ns->buf.byte, 0xFF, num);
1472 } else {
1473 NS_DBG("read_page: page %d allocated, reading from %d\n",
1474 ns->regs.row, ns->regs.column + ns->regs.off);
1475 if (do_read_error(ns, num))
1476 return;
1477 memcpy(ns->buf.byte, NS_PAGE_BYTE_OFF(ns), num);
1478 do_bit_flips(ns, num);
1479 }
1480 }
1481
1482 /*
1483 * Erase all pages in the specified sector.
1484 */
1485 static void erase_sector(struct nandsim *ns)
1486 {
1487 union ns_mem *mypage;
1488 int i;
1489
1490 if (ns->cfile) {
1491 for (i = 0; i < ns->geom.pgsec; i++)
1492 if (ns->pages_written[ns->regs.row + i]) {
1493 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row + i);
1494 ns->pages_written[ns->regs.row + i] = 0;
1495 }
1496 return;
1497 }
1498
1499 mypage = NS_GET_PAGE(ns);
1500 for (i = 0; i < ns->geom.pgsec; i++) {
1501 if (mypage->byte != NULL) {
1502 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row+i);
1503 kmem_cache_free(ns->nand_pages_slab, mypage->byte);
1504 mypage->byte = NULL;
1505 }
1506 mypage++;
1507 }
1508 }
1509
1510 /*
1511 * Program the specified page with the contents from the NAND buffer.
1512 */
1513 static int prog_page(struct nandsim *ns, int num)
1514 {
1515 int i;
1516 union ns_mem *mypage;
1517 u_char *pg_off;
1518
1519 if (ns->cfile) {
1520 loff_t off, pos;
1521 ssize_t tx;
1522 int all;
1523
1524 NS_DBG("prog_page: writing page %d\n", ns->regs.row);
1525 pg_off = ns->file_buf + ns->regs.column + ns->regs.off;
1526 off = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off;
1527 if (!ns->pages_written[ns->regs.row]) {
1528 all = 1;
1529 memset(ns->file_buf, 0xff, ns->geom.pgszoob);
1530 } else {
1531 all = 0;
1532 pos = off;
1533 tx = read_file(ns, ns->cfile, pg_off, num, &pos);
1534 if (tx != num) {
1535 NS_ERR("prog_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1536 return -1;
1537 }
1538 }
1539 for (i = 0; i < num; i++)
1540 pg_off[i] &= ns->buf.byte[i];
1541 if (all) {
1542 pos = (loff_t)ns->regs.row * ns->geom.pgszoob;
1543 tx = write_file(ns, ns->cfile, ns->file_buf, ns->geom.pgszoob, &pos);
1544 if (tx != ns->geom.pgszoob) {
1545 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1546 return -1;
1547 }
1548 ns->pages_written[ns->regs.row] = 1;
1549 } else {
1550 pos = off;
1551 tx = write_file(ns, ns->cfile, pg_off, num, &pos);
1552 if (tx != num) {
1553 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1554 return -1;
1555 }
1556 }
1557 return 0;
1558 }
1559
1560 mypage = NS_GET_PAGE(ns);
1561 if (mypage->byte == NULL) {
1562 NS_DBG("prog_page: allocating page %d\n", ns->regs.row);
1563 /*
1564 * We allocate memory with GFP_NOFS because a flash FS may
1565 * utilize this. If it is holding an FS lock, then gets here,
1566 * then kernel memory alloc runs writeback which goes to the FS
1567 * again and deadlocks. This was seen in practice.
1568 */
1569 mypage->byte = kmem_cache_alloc(ns->nand_pages_slab, GFP_NOFS);
1570 if (mypage->byte == NULL) {
1571 NS_ERR("prog_page: error allocating memory for page %d\n", ns->regs.row);
1572 return -1;
1573 }
1574 memset(mypage->byte, 0xFF, ns->geom.pgszoob);
1575 }
1576
1577 pg_off = NS_PAGE_BYTE_OFF(ns);
1578 for (i = 0; i < num; i++)
1579 pg_off[i] &= ns->buf.byte[i];
1580
1581 return 0;
1582 }
1583
1584 /*
1585 * If state has any action bit, perform this action.
1586 *
1587 * RETURNS: 0 if success, -1 if error.
1588 */
1589 static int do_state_action(struct nandsim *ns, uint32_t action)
1590 {
1591 int num;
1592 int busdiv = ns->busw == 8 ? 1 : 2;
1593 unsigned int erase_block_no, page_no;
1594
1595 action &= ACTION_MASK;
1596
1597 /* Check that page address input is correct */
1598 if (action != ACTION_SECERASE && ns->regs.row >= ns->geom.pgnum) {
1599 NS_WARN("do_state_action: wrong page number (%#x)\n", ns->regs.row);
1600 return -1;
1601 }
1602
1603 switch (action) {
1604
1605 case ACTION_CPY:
1606 /*
1607 * Copy page data to the internal buffer.
1608 */
1609
1610 /* Column shouldn't be very large */
1611 if (ns->regs.column >= (ns->geom.pgszoob - ns->regs.off)) {
1612 NS_ERR("do_state_action: column number is too large\n");
1613 break;
1614 }
1615 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1616 read_page(ns, num);
1617
1618 NS_DBG("do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d\n",
1619 num, NS_RAW_OFFSET(ns) + ns->regs.off);
1620
1621 if (ns->regs.off == 0)
1622 NS_LOG("read page %d\n", ns->regs.row);
1623 else if (ns->regs.off < ns->geom.pgsz)
1624 NS_LOG("read page %d (second half)\n", ns->regs.row);
1625 else
1626 NS_LOG("read OOB of page %d\n", ns->regs.row);
1627
1628 NS_UDELAY(access_delay);
1629 NS_UDELAY(input_cycle * ns->geom.pgsz / 1000 / busdiv);
1630
1631 break;
1632
1633 case ACTION_SECERASE:
1634 /*
1635 * Erase sector.
1636 */
1637
1638 if (ns->lines.wp) {
1639 NS_ERR("do_state_action: device is write-protected, ignore sector erase\n");
1640 return -1;
1641 }
1642
1643 if (ns->regs.row >= ns->geom.pgnum - ns->geom.pgsec
1644 || (ns->regs.row & ~(ns->geom.secsz - 1))) {
1645 NS_ERR("do_state_action: wrong sector address (%#x)\n", ns->regs.row);
1646 return -1;
1647 }
1648
1649 ns->regs.row = (ns->regs.row <<
1650 8 * (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) | ns->regs.column;
1651 ns->regs.column = 0;
1652
1653 erase_block_no = ns->regs.row >> (ns->geom.secshift - ns->geom.pgshift);
1654
1655 NS_DBG("do_state_action: erase sector at address %#x, off = %d\n",
1656 ns->regs.row, NS_RAW_OFFSET(ns));
1657 NS_LOG("erase sector %u\n", erase_block_no);
1658
1659 erase_sector(ns);
1660
1661 NS_MDELAY(erase_delay);
1662
1663 if (erase_block_wear)
1664 update_wear(erase_block_no);
1665
1666 if (erase_error(erase_block_no)) {
1667 NS_WARN("simulating erase failure in erase block %u\n", erase_block_no);
1668 return -1;
1669 }
1670
1671 break;
1672
1673 case ACTION_PRGPAGE:
1674 /*
1675 * Program page - move internal buffer data to the page.
1676 */
1677
1678 if (ns->lines.wp) {
1679 NS_WARN("do_state_action: device is write-protected, programm\n");
1680 return -1;
1681 }
1682
1683 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1684 if (num != ns->regs.count) {
1685 NS_ERR("do_state_action: too few bytes were input (%d instead of %d)\n",
1686 ns->regs.count, num);
1687 return -1;
1688 }
1689
1690 if (prog_page(ns, num) == -1)
1691 return -1;
1692
1693 page_no = ns->regs.row;
1694
1695 NS_DBG("do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d\n",
1696 num, ns->regs.row, ns->regs.column, NS_RAW_OFFSET(ns) + ns->regs.off);
1697 NS_LOG("programm page %d\n", ns->regs.row);
1698
1699 NS_UDELAY(programm_delay);
1700 NS_UDELAY(output_cycle * ns->geom.pgsz / 1000 / busdiv);
1701
1702 if (write_error(page_no)) {
1703 NS_WARN("simulating write failure in page %u\n", page_no);
1704 return -1;
1705 }
1706
1707 break;
1708
1709 case ACTION_ZEROOFF:
1710 NS_DBG("do_state_action: set internal offset to 0\n");
1711 ns->regs.off = 0;
1712 break;
1713
1714 case ACTION_HALFOFF:
1715 if (!(ns->options & OPT_PAGE512_8BIT)) {
1716 NS_ERR("do_state_action: BUG! can't skip half of page for non-512"
1717 "byte page size 8x chips\n");
1718 return -1;
1719 }
1720 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz/2);
1721 ns->regs.off = ns->geom.pgsz/2;
1722 break;
1723
1724 case ACTION_OOBOFF:
1725 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz);
1726 ns->regs.off = ns->geom.pgsz;
1727 break;
1728
1729 default:
1730 NS_DBG("do_state_action: BUG! unknown action\n");
1731 }
1732
1733 return 0;
1734 }
1735
1736 /*
1737 * Switch simulator's state.
1738 */
1739 static void switch_state(struct nandsim *ns)
1740 {
1741 if (ns->op) {
1742 /*
1743 * The current operation have already been identified.
1744 * Just follow the states chain.
1745 */
1746
1747 ns->stateidx += 1;
1748 ns->state = ns->nxstate;
1749 ns->nxstate = ns->op[ns->stateidx + 1];
1750
1751 NS_DBG("switch_state: operation is known, switch to the next state, "
1752 "state: %s, nxstate: %s\n",
1753 get_state_name(ns->state), get_state_name(ns->nxstate));
1754
1755 /* See, whether we need to do some action */
1756 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1757 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1758 return;
1759 }
1760
1761 } else {
1762 /*
1763 * We don't yet know which operation we perform.
1764 * Try to identify it.
1765 */
1766
1767 /*
1768 * The only event causing the switch_state function to
1769 * be called with yet unknown operation is new command.
1770 */
1771 ns->state = get_state_by_command(ns->regs.command);
1772
1773 NS_DBG("switch_state: operation is unknown, try to find it\n");
1774
1775 if (find_operation(ns, 0) != 0)
1776 return;
1777
1778 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1779 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1780 return;
1781 }
1782 }
1783
1784 /* For 16x devices column means the page offset in words */
1785 if ((ns->nxstate & STATE_ADDR_MASK) && ns->busw == 16) {
1786 NS_DBG("switch_state: double the column number for 16x device\n");
1787 ns->regs.column <<= 1;
1788 }
1789
1790 if (NS_STATE(ns->nxstate) == STATE_READY) {
1791 /*
1792 * The current state is the last. Return to STATE_READY
1793 */
1794
1795 u_char status = NS_STATUS_OK(ns);
1796
1797 /* In case of data states, see if all bytes were input/output */
1798 if ((ns->state & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK))
1799 && ns->regs.count != ns->regs.num) {
1800 NS_WARN("switch_state: not all bytes were processed, %d left\n",
1801 ns->regs.num - ns->regs.count);
1802 status = NS_STATUS_FAILED(ns);
1803 }
1804
1805 NS_DBG("switch_state: operation complete, switch to STATE_READY state\n");
1806
1807 switch_to_ready_state(ns, status);
1808
1809 return;
1810 } else if (ns->nxstate & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK)) {
1811 /*
1812 * If the next state is data input/output, switch to it now
1813 */
1814
1815 ns->state = ns->nxstate;
1816 ns->nxstate = ns->op[++ns->stateidx + 1];
1817 ns->regs.num = ns->regs.count = 0;
1818
1819 NS_DBG("switch_state: the next state is data I/O, switch, "
1820 "state: %s, nxstate: %s\n",
1821 get_state_name(ns->state), get_state_name(ns->nxstate));
1822
1823 /*
1824 * Set the internal register to the count of bytes which
1825 * are expected to be input or output
1826 */
1827 switch (NS_STATE(ns->state)) {
1828 case STATE_DATAIN:
1829 case STATE_DATAOUT:
1830 ns->regs.num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1831 break;
1832
1833 case STATE_DATAOUT_ID:
1834 ns->regs.num = ns->geom.idbytes;
1835 break;
1836
1837 case STATE_DATAOUT_STATUS:
1838 case STATE_DATAOUT_STATUS_M:
1839 ns->regs.count = ns->regs.num = 0;
1840 break;
1841
1842 default:
1843 NS_ERR("switch_state: BUG! unknown data state\n");
1844 }
1845
1846 } else if (ns->nxstate & STATE_ADDR_MASK) {
1847 /*
1848 * If the next state is address input, set the internal
1849 * register to the number of expected address bytes
1850 */
1851
1852 ns->regs.count = 0;
1853
1854 switch (NS_STATE(ns->nxstate)) {
1855 case STATE_ADDR_PAGE:
1856 ns->regs.num = ns->geom.pgaddrbytes;
1857
1858 break;
1859 case STATE_ADDR_SEC:
1860 ns->regs.num = ns->geom.secaddrbytes;
1861 break;
1862
1863 case STATE_ADDR_ZERO:
1864 ns->regs.num = 1;
1865 break;
1866
1867 case STATE_ADDR_COLUMN:
1868 /* Column address is always 2 bytes */
1869 ns->regs.num = ns->geom.pgaddrbytes - ns->geom.secaddrbytes;
1870 break;
1871
1872 default:
1873 NS_ERR("switch_state: BUG! unknown address state\n");
1874 }
1875 } else {
1876 /*
1877 * Just reset internal counters.
1878 */
1879
1880 ns->regs.num = 0;
1881 ns->regs.count = 0;
1882 }
1883 }
1884
1885 static u_char ns_nand_read_byte(struct mtd_info *mtd)
1886 {
1887 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
1888 u_char outb = 0x00;
1889
1890 /* Sanity and correctness checks */
1891 if (!ns->lines.ce) {
1892 NS_ERR("read_byte: chip is disabled, return %#x\n", (uint)outb);
1893 return outb;
1894 }
1895 if (ns->lines.ale || ns->lines.cle) {
1896 NS_ERR("read_byte: ALE or CLE pin is high, return %#x\n", (uint)outb);
1897 return outb;
1898 }
1899 if (!(ns->state & STATE_DATAOUT_MASK)) {
1900 NS_WARN("read_byte: unexpected data output cycle, state is %s "
1901 "return %#x\n", get_state_name(ns->state), (uint)outb);
1902 return outb;
1903 }
1904
1905 /* Status register may be read as many times as it is wanted */
1906 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS) {
1907 NS_DBG("read_byte: return %#x status\n", ns->regs.status);
1908 return ns->regs.status;
1909 }
1910
1911 /* Check if there is any data in the internal buffer which may be read */
1912 if (ns->regs.count == ns->regs.num) {
1913 NS_WARN("read_byte: no more data to output, return %#x\n", (uint)outb);
1914 return outb;
1915 }
1916
1917 switch (NS_STATE(ns->state)) {
1918 case STATE_DATAOUT:
1919 if (ns->busw == 8) {
1920 outb = ns->buf.byte[ns->regs.count];
1921 ns->regs.count += 1;
1922 } else {
1923 outb = (u_char)cpu_to_le16(ns->buf.word[ns->regs.count >> 1]);
1924 ns->regs.count += 2;
1925 }
1926 break;
1927 case STATE_DATAOUT_ID:
1928 NS_DBG("read_byte: read ID byte %d, total = %d\n", ns->regs.count, ns->regs.num);
1929 outb = ns->ids[ns->regs.count];
1930 ns->regs.count += 1;
1931 break;
1932 default:
1933 BUG();
1934 }
1935
1936 if (ns->regs.count == ns->regs.num) {
1937 NS_DBG("read_byte: all bytes were read\n");
1938
1939 /*
1940 * The OPT_AUTOINCR allows to read next consecutive pages without
1941 * new read operation cycle.
1942 */
1943 if ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT) {
1944 ns->regs.count = 0;
1945 if (ns->regs.row + 1 < ns->geom.pgnum)
1946 ns->regs.row += 1;
1947 NS_DBG("read_byte: switch to the next page (%#x)\n", ns->regs.row);
1948 do_state_action(ns, ACTION_CPY);
1949 }
1950 else if (NS_STATE(ns->nxstate) == STATE_READY)
1951 switch_state(ns);
1952
1953 }
1954
1955 return outb;
1956 }
1957
1958 static void ns_nand_write_byte(struct mtd_info *mtd, u_char byte)
1959 {
1960 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
1961
1962 /* Sanity and correctness checks */
1963 if (!ns->lines.ce) {
1964 NS_ERR("write_byte: chip is disabled, ignore write\n");
1965 return;
1966 }
1967 if (ns->lines.ale && ns->lines.cle) {
1968 NS_ERR("write_byte: ALE and CLE pins are high simultaneously, ignore write\n");
1969 return;
1970 }
1971
1972 if (ns->lines.cle == 1) {
1973 /*
1974 * The byte written is a command.
1975 */
1976
1977 if (byte == NAND_CMD_RESET) {
1978 NS_LOG("reset chip\n");
1979 switch_to_ready_state(ns, NS_STATUS_OK(ns));
1980 return;
1981 }
1982
1983 /* Check that the command byte is correct */
1984 if (check_command(byte)) {
1985 NS_ERR("write_byte: unknown command %#x\n", (uint)byte);
1986 return;
1987 }
1988
1989 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS
1990 || NS_STATE(ns->state) == STATE_DATAOUT_STATUS_M
1991 || NS_STATE(ns->state) == STATE_DATAOUT) {
1992 int row = ns->regs.row;
1993
1994 switch_state(ns);
1995 if (byte == NAND_CMD_RNDOUT)
1996 ns->regs.row = row;
1997 }
1998
1999 /* Check if chip is expecting command */
2000 if (NS_STATE(ns->nxstate) != STATE_UNKNOWN && !(ns->nxstate & STATE_CMD_MASK)) {
2001 /* Do not warn if only 2 id bytes are read */
2002 if (!(ns->regs.command == NAND_CMD_READID &&
2003 NS_STATE(ns->state) == STATE_DATAOUT_ID && ns->regs.count == 2)) {
2004 /*
2005 * We are in situation when something else (not command)
2006 * was expected but command was input. In this case ignore
2007 * previous command(s)/state(s) and accept the last one.
2008 */
2009 NS_WARN("write_byte: command (%#x) wasn't expected, expected state is %s, "
2010 "ignore previous states\n", (uint)byte, get_state_name(ns->nxstate));
2011 }
2012 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2013 }
2014
2015 NS_DBG("command byte corresponding to %s state accepted\n",
2016 get_state_name(get_state_by_command(byte)));
2017 ns->regs.command = byte;
2018 switch_state(ns);
2019
2020 } else if (ns->lines.ale == 1) {
2021 /*
2022 * The byte written is an address.
2023 */
2024
2025 if (NS_STATE(ns->nxstate) == STATE_UNKNOWN) {
2026
2027 NS_DBG("write_byte: operation isn't known yet, identify it\n");
2028
2029 if (find_operation(ns, 1) < 0)
2030 return;
2031
2032 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
2033 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2034 return;
2035 }
2036
2037 ns->regs.count = 0;
2038 switch (NS_STATE(ns->nxstate)) {
2039 case STATE_ADDR_PAGE:
2040 ns->regs.num = ns->geom.pgaddrbytes;
2041 break;
2042 case STATE_ADDR_SEC:
2043 ns->regs.num = ns->geom.secaddrbytes;
2044 break;
2045 case STATE_ADDR_ZERO:
2046 ns->regs.num = 1;
2047 break;
2048 default:
2049 BUG();
2050 }
2051 }
2052
2053 /* Check that chip is expecting address */
2054 if (!(ns->nxstate & STATE_ADDR_MASK)) {
2055 NS_ERR("write_byte: address (%#x) isn't expected, expected state is %s, "
2056 "switch to STATE_READY\n", (uint)byte, get_state_name(ns->nxstate));
2057 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2058 return;
2059 }
2060
2061 /* Check if this is expected byte */
2062 if (ns->regs.count == ns->regs.num) {
2063 NS_ERR("write_byte: no more address bytes expected\n");
2064 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2065 return;
2066 }
2067
2068 accept_addr_byte(ns, byte);
2069
2070 ns->regs.count += 1;
2071
2072 NS_DBG("write_byte: address byte %#x was accepted (%d bytes input, %d expected)\n",
2073 (uint)byte, ns->regs.count, ns->regs.num);
2074
2075 if (ns->regs.count == ns->regs.num) {
2076 NS_DBG("address (%#x, %#x) is accepted\n", ns->regs.row, ns->regs.column);
2077 switch_state(ns);
2078 }
2079
2080 } else {
2081 /*
2082 * The byte written is an input data.
2083 */
2084
2085 /* Check that chip is expecting data input */
2086 if (!(ns->state & STATE_DATAIN_MASK)) {
2087 NS_ERR("write_byte: data input (%#x) isn't expected, state is %s, "
2088 "switch to %s\n", (uint)byte,
2089 get_state_name(ns->state), get_state_name(STATE_READY));
2090 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2091 return;
2092 }
2093
2094 /* Check if this is expected byte */
2095 if (ns->regs.count == ns->regs.num) {
2096 NS_WARN("write_byte: %u input bytes has already been accepted, ignore write\n",
2097 ns->regs.num);
2098 return;
2099 }
2100
2101 if (ns->busw == 8) {
2102 ns->buf.byte[ns->regs.count] = byte;
2103 ns->regs.count += 1;
2104 } else {
2105 ns->buf.word[ns->regs.count >> 1] = cpu_to_le16((uint16_t)byte);
2106 ns->regs.count += 2;
2107 }
2108 }
2109
2110 return;
2111 }
2112
2113 static void ns_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int bitmask)
2114 {
2115 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2116
2117 ns->lines.cle = bitmask & NAND_CLE ? 1 : 0;
2118 ns->lines.ale = bitmask & NAND_ALE ? 1 : 0;
2119 ns->lines.ce = bitmask & NAND_NCE ? 1 : 0;
2120
2121 if (cmd != NAND_CMD_NONE)
2122 ns_nand_write_byte(mtd, cmd);
2123 }
2124
2125 static int ns_device_ready(struct mtd_info *mtd)
2126 {
2127 NS_DBG("device_ready\n");
2128 return 1;
2129 }
2130
2131 static uint16_t ns_nand_read_word(struct mtd_info *mtd)
2132 {
2133 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
2134
2135 NS_DBG("read_word\n");
2136
2137 return chip->read_byte(mtd) | (chip->read_byte(mtd) << 8);
2138 }
2139
2140 static void ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
2141 {
2142 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2143
2144 /* Check that chip is expecting data input */
2145 if (!(ns->state & STATE_DATAIN_MASK)) {
2146 NS_ERR("write_buf: data input isn't expected, state is %s, "
2147 "switch to STATE_READY\n", get_state_name(ns->state));
2148 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2149 return;
2150 }
2151
2152 /* Check if these are expected bytes */
2153 if (ns->regs.count + len > ns->regs.num) {
2154 NS_ERR("write_buf: too many input bytes\n");
2155 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2156 return;
2157 }
2158
2159 memcpy(ns->buf.byte + ns->regs.count, buf, len);
2160 ns->regs.count += len;
2161
2162 if (ns->regs.count == ns->regs.num) {
2163 NS_DBG("write_buf: %d bytes were written\n", ns->regs.count);
2164 }
2165 }
2166
2167 static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
2168 {
2169 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2170
2171 /* Sanity and correctness checks */
2172 if (!ns->lines.ce) {
2173 NS_ERR("read_buf: chip is disabled\n");
2174 return;
2175 }
2176 if (ns->lines.ale || ns->lines.cle) {
2177 NS_ERR("read_buf: ALE or CLE pin is high\n");
2178 return;
2179 }
2180 if (!(ns->state & STATE_DATAOUT_MASK)) {
2181 NS_WARN("read_buf: unexpected data output cycle, current state is %s\n",
2182 get_state_name(ns->state));
2183 return;
2184 }
2185
2186 if (NS_STATE(ns->state) != STATE_DATAOUT) {
2187 int i;
2188
2189 for (i = 0; i < len; i++)
2190 buf[i] = ((struct nand_chip *)mtd->priv)->read_byte(mtd);
2191
2192 return;
2193 }
2194
2195 /* Check if these are expected bytes */
2196 if (ns->regs.count + len > ns->regs.num) {
2197 NS_ERR("read_buf: too many bytes to read\n");
2198 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2199 return;
2200 }
2201
2202 memcpy(buf, ns->buf.byte + ns->regs.count, len);
2203 ns->regs.count += len;
2204
2205 if (ns->regs.count == ns->regs.num) {
2206 if ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT) {
2207 ns->regs.count = 0;
2208 if (ns->regs.row + 1 < ns->geom.pgnum)
2209 ns->regs.row += 1;
2210 NS_DBG("read_buf: switch to the next page (%#x)\n", ns->regs.row);
2211 do_state_action(ns, ACTION_CPY);
2212 }
2213 else if (NS_STATE(ns->nxstate) == STATE_READY)
2214 switch_state(ns);
2215 }
2216
2217 return;
2218 }
2219
2220 static int ns_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
2221 {
2222 ns_nand_read_buf(mtd, (u_char *)&ns_verify_buf[0], len);
2223
2224 if (!memcmp(buf, &ns_verify_buf[0], len)) {
2225 NS_DBG("verify_buf: the buffer is OK\n");
2226 return 0;
2227 } else {
2228 NS_DBG("verify_buf: the buffer is wrong\n");
2229 return -EFAULT;
2230 }
2231 }
2232
2233 /*
2234 * Module initialization function
2235 */
2236 static int __init ns_init_module(void)
2237 {
2238 struct nand_chip *chip;
2239 struct nandsim *nand;
2240 int retval = -ENOMEM, i;
2241
2242 if (bus_width != 8 && bus_width != 16) {
2243 NS_ERR("wrong bus width (%d), use only 8 or 16\n", bus_width);
2244 return -EINVAL;
2245 }
2246
2247 /* Allocate and initialize mtd_info, nand_chip and nandsim structures */
2248 nsmtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip)
2249 + sizeof(struct nandsim), GFP_KERNEL);
2250 if (!nsmtd) {
2251 NS_ERR("unable to allocate core structures.\n");
2252 return -ENOMEM;
2253 }
2254 chip = (struct nand_chip *)(nsmtd + 1);
2255 nsmtd->priv = (void *)chip;
2256 nand = (struct nandsim *)(chip + 1);
2257 chip->priv = (void *)nand;
2258
2259 /*
2260 * Register simulator's callbacks.
2261 */
2262 chip->cmd_ctrl = ns_hwcontrol;
2263 chip->read_byte = ns_nand_read_byte;
2264 chip->dev_ready = ns_device_ready;
2265 chip->write_buf = ns_nand_write_buf;
2266 chip->read_buf = ns_nand_read_buf;
2267 chip->verify_buf = ns_nand_verify_buf;
2268 chip->read_word = ns_nand_read_word;
2269 chip->ecc.mode = NAND_ECC_SOFT;
2270 /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */
2271 /* and 'badblocks' parameters to work */
2272 chip->options |= NAND_SKIP_BBTSCAN;
2273
2274 switch (bbt) {
2275 case 2:
2276 chip->bbt_options |= NAND_BBT_NO_OOB;
2277 case 1:
2278 chip->bbt_options |= NAND_BBT_USE_FLASH;
2279 case 0:
2280 break;
2281 default:
2282 NS_ERR("bbt has to be 0..2\n");
2283 retval = -EINVAL;
2284 goto error;
2285 }
2286 /*
2287 * Perform minimum nandsim structure initialization to handle
2288 * the initial ID read command correctly
2289 */
2290 if (third_id_byte != 0xFF || fourth_id_byte != 0xFF)
2291 nand->geom.idbytes = 4;
2292 else
2293 nand->geom.idbytes = 2;
2294 nand->regs.status = NS_STATUS_OK(nand);
2295 nand->nxstate = STATE_UNKNOWN;
2296 nand->options |= OPT_PAGE256; /* temporary value */
2297 nand->ids[0] = first_id_byte;
2298 nand->ids[1] = second_id_byte;
2299 nand->ids[2] = third_id_byte;
2300 nand->ids[3] = fourth_id_byte;
2301 if (bus_width == 16) {
2302 nand->busw = 16;
2303 chip->options |= NAND_BUSWIDTH_16;
2304 }
2305
2306 nsmtd->owner = THIS_MODULE;
2307
2308 if ((retval = parse_weakblocks()) != 0)
2309 goto error;
2310
2311 if ((retval = parse_weakpages()) != 0)
2312 goto error;
2313
2314 if ((retval = parse_gravepages()) != 0)
2315 goto error;
2316
2317 retval = nand_scan_ident(nsmtd, 1, NULL);
2318 if (retval) {
2319 NS_ERR("cannot scan NAND Simulator device\n");
2320 if (retval > 0)
2321 retval = -ENXIO;
2322 goto error;
2323 }
2324
2325 if (bch) {
2326 unsigned int eccsteps, eccbytes;
2327 if (!mtd_nand_has_bch()) {
2328 NS_ERR("BCH ECC support is disabled\n");
2329 retval = -EINVAL;
2330 goto error;
2331 }
2332 /* use 512-byte ecc blocks */
2333 eccsteps = nsmtd->writesize/512;
2334 eccbytes = (bch*13+7)/8;
2335 /* do not bother supporting small page devices */
2336 if ((nsmtd->oobsize < 64) || !eccsteps) {
2337 NS_ERR("bch not available on small page devices\n");
2338 retval = -EINVAL;
2339 goto error;
2340 }
2341 if ((eccbytes*eccsteps+2) > nsmtd->oobsize) {
2342 NS_ERR("invalid bch value %u\n", bch);
2343 retval = -EINVAL;
2344 goto error;
2345 }
2346 chip->ecc.mode = NAND_ECC_SOFT_BCH;
2347 chip->ecc.size = 512;
2348 chip->ecc.bytes = eccbytes;
2349 NS_INFO("using %u-bit/%u bytes BCH ECC\n", bch, chip->ecc.size);
2350 }
2351
2352 retval = nand_scan_tail(nsmtd);
2353 if (retval) {
2354 NS_ERR("can't register NAND Simulator\n");
2355 if (retval > 0)
2356 retval = -ENXIO;
2357 goto error;
2358 }
2359
2360 if (overridesize) {
2361 uint64_t new_size = (uint64_t)nsmtd->erasesize << overridesize;
2362 if (new_size >> overridesize != nsmtd->erasesize) {
2363 NS_ERR("overridesize is too big\n");
2364 goto err_exit;
2365 }
2366 /* N.B. This relies on nand_scan not doing anything with the size before we change it */
2367 nsmtd->size = new_size;
2368 chip->chipsize = new_size;
2369 chip->chip_shift = ffs(nsmtd->erasesize) + overridesize - 1;
2370 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2371 }
2372
2373 if ((retval = setup_wear_reporting(nsmtd)) != 0)
2374 goto err_exit;
2375
2376 if ((retval = init_nandsim(nsmtd)) != 0)
2377 goto err_exit;
2378
2379 if ((retval = nand_default_bbt(nsmtd)) != 0)
2380 goto err_exit;
2381
2382 if ((retval = parse_badblocks(nand, nsmtd)) != 0)
2383 goto err_exit;
2384
2385 /* Register NAND partitions */
2386 retval = mtd_device_register(nsmtd, &nand->partitions[0],
2387 nand->nbparts);
2388 if (retval != 0)
2389 goto err_exit;
2390
2391 return 0;
2392
2393 err_exit:
2394 free_nandsim(nand);
2395 nand_release(nsmtd);
2396 for (i = 0;i < ARRAY_SIZE(nand->partitions); ++i)
2397 kfree(nand->partitions[i].name);
2398 error:
2399 kfree(nsmtd);
2400 free_lists();
2401
2402 return retval;
2403 }
2404
2405 module_init(ns_init_module);
2406
2407 /*
2408 * Module clean-up function
2409 */
2410 static void __exit ns_cleanup_module(void)
2411 {
2412 struct nandsim *ns = ((struct nand_chip *)nsmtd->priv)->priv;
2413 int i;
2414
2415 free_nandsim(ns); /* Free nandsim private resources */
2416 nand_release(nsmtd); /* Unregister driver */
2417 for (i = 0;i < ARRAY_SIZE(ns->partitions); ++i)
2418 kfree(ns->partitions[i].name);
2419 kfree(nsmtd); /* Free other structures */
2420 free_lists();
2421 }
2422
2423 module_exit(ns_cleanup_module);
2424
2425 MODULE_LICENSE ("GPL");
2426 MODULE_AUTHOR ("Artem B. Bityuckiy");
2427 MODULE_DESCRIPTION ("The NAND flash simulator");
kernel source for telekom puls (alcatel/mediatek)