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mtd: flash drivers set ecc strength
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mtd / nand / fsmc_nand.c
1 /*
2 * drivers/mtd/nand/fsmc_nand.c
3 *
4 * ST Microelectronics
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
7 *
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
10 * Ashish Priyadarshi
11 *
12 * Based on drivers/mtd/nand/nomadik_nand.c
13 *
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/resource.h>
24 #include <linux/sched.h>
25 #include <linux/types.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/nand_ecc.h>
29 #include <linux/platform_device.h>
30 #include <linux/mtd/partitions.h>
31 #include <linux/io.h>
32 #include <linux/slab.h>
33 #include <linux/mtd/fsmc.h>
34 #include <linux/amba/bus.h>
35 #include <mtd/mtd-abi.h>
36
37 static struct nand_ecclayout fsmc_ecc1_128_layout = {
38 .eccbytes = 24,
39 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
40 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
41 .oobfree = {
42 {.offset = 8, .length = 8},
43 {.offset = 24, .length = 8},
44 {.offset = 40, .length = 8},
45 {.offset = 56, .length = 8},
46 {.offset = 72, .length = 8},
47 {.offset = 88, .length = 8},
48 {.offset = 104, .length = 8},
49 {.offset = 120, .length = 8}
50 }
51 };
52
53 static struct nand_ecclayout fsmc_ecc1_64_layout = {
54 .eccbytes = 12,
55 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52},
56 .oobfree = {
57 {.offset = 8, .length = 8},
58 {.offset = 24, .length = 8},
59 {.offset = 40, .length = 8},
60 {.offset = 56, .length = 8},
61 }
62 };
63
64 static struct nand_ecclayout fsmc_ecc1_16_layout = {
65 .eccbytes = 3,
66 .eccpos = {2, 3, 4},
67 .oobfree = {
68 {.offset = 8, .length = 8},
69 }
70 };
71
72 /*
73 * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes
74 * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46
75 * bytes are free for use.
76 */
77 static struct nand_ecclayout fsmc_ecc4_256_layout = {
78 .eccbytes = 208,
79 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
80 9, 10, 11, 12, 13, 14,
81 18, 19, 20, 21, 22, 23, 24,
82 25, 26, 27, 28, 29, 30,
83 34, 35, 36, 37, 38, 39, 40,
84 41, 42, 43, 44, 45, 46,
85 50, 51, 52, 53, 54, 55, 56,
86 57, 58, 59, 60, 61, 62,
87 66, 67, 68, 69, 70, 71, 72,
88 73, 74, 75, 76, 77, 78,
89 82, 83, 84, 85, 86, 87, 88,
90 89, 90, 91, 92, 93, 94,
91 98, 99, 100, 101, 102, 103, 104,
92 105, 106, 107, 108, 109, 110,
93 114, 115, 116, 117, 118, 119, 120,
94 121, 122, 123, 124, 125, 126,
95 130, 131, 132, 133, 134, 135, 136,
96 137, 138, 139, 140, 141, 142,
97 146, 147, 148, 149, 150, 151, 152,
98 153, 154, 155, 156, 157, 158,
99 162, 163, 164, 165, 166, 167, 168,
100 169, 170, 171, 172, 173, 174,
101 178, 179, 180, 181, 182, 183, 184,
102 185, 186, 187, 188, 189, 190,
103 194, 195, 196, 197, 198, 199, 200,
104 201, 202, 203, 204, 205, 206,
105 210, 211, 212, 213, 214, 215, 216,
106 217, 218, 219, 220, 221, 222,
107 226, 227, 228, 229, 230, 231, 232,
108 233, 234, 235, 236, 237, 238,
109 242, 243, 244, 245, 246, 247, 248,
110 249, 250, 251, 252, 253, 254
111 },
112 .oobfree = {
113 {.offset = 15, .length = 3},
114 {.offset = 31, .length = 3},
115 {.offset = 47, .length = 3},
116 {.offset = 63, .length = 3},
117 {.offset = 79, .length = 3},
118 {.offset = 95, .length = 3},
119 {.offset = 111, .length = 3},
120 {.offset = 127, .length = 3},
121 {.offset = 143, .length = 3},
122 {.offset = 159, .length = 3},
123 {.offset = 175, .length = 3},
124 {.offset = 191, .length = 3},
125 {.offset = 207, .length = 3},
126 {.offset = 223, .length = 3},
127 {.offset = 239, .length = 3},
128 {.offset = 255, .length = 1}
129 }
130 };
131
132 /*
133 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
134 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
135 * bytes are free for use.
136 */
137 static struct nand_ecclayout fsmc_ecc4_224_layout = {
138 .eccbytes = 104,
139 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
140 9, 10, 11, 12, 13, 14,
141 18, 19, 20, 21, 22, 23, 24,
142 25, 26, 27, 28, 29, 30,
143 34, 35, 36, 37, 38, 39, 40,
144 41, 42, 43, 44, 45, 46,
145 50, 51, 52, 53, 54, 55, 56,
146 57, 58, 59, 60, 61, 62,
147 66, 67, 68, 69, 70, 71, 72,
148 73, 74, 75, 76, 77, 78,
149 82, 83, 84, 85, 86, 87, 88,
150 89, 90, 91, 92, 93, 94,
151 98, 99, 100, 101, 102, 103, 104,
152 105, 106, 107, 108, 109, 110,
153 114, 115, 116, 117, 118, 119, 120,
154 121, 122, 123, 124, 125, 126
155 },
156 .oobfree = {
157 {.offset = 15, .length = 3},
158 {.offset = 31, .length = 3},
159 {.offset = 47, .length = 3},
160 {.offset = 63, .length = 3},
161 {.offset = 79, .length = 3},
162 {.offset = 95, .length = 3},
163 {.offset = 111, .length = 3},
164 {.offset = 127, .length = 97}
165 }
166 };
167
168 /*
169 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
170 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
171 * bytes are free for use.
172 */
173 static struct nand_ecclayout fsmc_ecc4_128_layout = {
174 .eccbytes = 104,
175 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
176 9, 10, 11, 12, 13, 14,
177 18, 19, 20, 21, 22, 23, 24,
178 25, 26, 27, 28, 29, 30,
179 34, 35, 36, 37, 38, 39, 40,
180 41, 42, 43, 44, 45, 46,
181 50, 51, 52, 53, 54, 55, 56,
182 57, 58, 59, 60, 61, 62,
183 66, 67, 68, 69, 70, 71, 72,
184 73, 74, 75, 76, 77, 78,
185 82, 83, 84, 85, 86, 87, 88,
186 89, 90, 91, 92, 93, 94,
187 98, 99, 100, 101, 102, 103, 104,
188 105, 106, 107, 108, 109, 110,
189 114, 115, 116, 117, 118, 119, 120,
190 121, 122, 123, 124, 125, 126
191 },
192 .oobfree = {
193 {.offset = 15, .length = 3},
194 {.offset = 31, .length = 3},
195 {.offset = 47, .length = 3},
196 {.offset = 63, .length = 3},
197 {.offset = 79, .length = 3},
198 {.offset = 95, .length = 3},
199 {.offset = 111, .length = 3},
200 {.offset = 127, .length = 1}
201 }
202 };
203
204 /*
205 * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of
206 * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10
207 * bytes are free for use.
208 */
209 static struct nand_ecclayout fsmc_ecc4_64_layout = {
210 .eccbytes = 52,
211 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
212 9, 10, 11, 12, 13, 14,
213 18, 19, 20, 21, 22, 23, 24,
214 25, 26, 27, 28, 29, 30,
215 34, 35, 36, 37, 38, 39, 40,
216 41, 42, 43, 44, 45, 46,
217 50, 51, 52, 53, 54, 55, 56,
218 57, 58, 59, 60, 61, 62,
219 },
220 .oobfree = {
221 {.offset = 15, .length = 3},
222 {.offset = 31, .length = 3},
223 {.offset = 47, .length = 3},
224 {.offset = 63, .length = 1},
225 }
226 };
227
228 /*
229 * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of
230 * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One
231 * byte is free for use.
232 */
233 static struct nand_ecclayout fsmc_ecc4_16_layout = {
234 .eccbytes = 13,
235 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
236 9, 10, 11, 12, 13, 14
237 },
238 .oobfree = {
239 {.offset = 15, .length = 1},
240 }
241 };
242
243 /*
244 * ECC placement definitions in oobfree type format.
245 * There are 13 bytes of ecc for every 512 byte block and it has to be read
246 * consecutively and immediately after the 512 byte data block for hardware to
247 * generate the error bit offsets in 512 byte data.
248 * Managing the ecc bytes in the following way makes it easier for software to
249 * read ecc bytes consecutive to data bytes. This way is similar to
250 * oobfree structure maintained already in generic nand driver
251 */
252 static struct fsmc_eccplace fsmc_ecc4_lp_place = {
253 .eccplace = {
254 {.offset = 2, .length = 13},
255 {.offset = 18, .length = 13},
256 {.offset = 34, .length = 13},
257 {.offset = 50, .length = 13},
258 {.offset = 66, .length = 13},
259 {.offset = 82, .length = 13},
260 {.offset = 98, .length = 13},
261 {.offset = 114, .length = 13}
262 }
263 };
264
265 static struct fsmc_eccplace fsmc_ecc4_sp_place = {
266 .eccplace = {
267 {.offset = 0, .length = 4},
268 {.offset = 6, .length = 9}
269 }
270 };
271
272 /*
273 * Default partition tables to be used if the partition information not
274 * provided through platform data.
275 *
276 * Default partition layout for small page(= 512 bytes) devices
277 * Size for "Root file system" is updated in driver based on actual device size
278 */
279 static struct mtd_partition partition_info_16KB_blk[] = {
280 {
281 .name = "X-loader",
282 .offset = 0,
283 .size = 4*0x4000,
284 },
285 {
286 .name = "U-Boot",
287 .offset = 0x10000,
288 .size = 20*0x4000,
289 },
290 {
291 .name = "Kernel",
292 .offset = 0x60000,
293 .size = 256*0x4000,
294 },
295 {
296 .name = "Root File System",
297 .offset = 0x460000,
298 .size = MTDPART_SIZ_FULL,
299 },
300 };
301
302 /*
303 * Default partition layout for large page(> 512 bytes) devices
304 * Size for "Root file system" is updated in driver based on actual device size
305 */
306 static struct mtd_partition partition_info_128KB_blk[] = {
307 {
308 .name = "X-loader",
309 .offset = 0,
310 .size = 4*0x20000,
311 },
312 {
313 .name = "U-Boot",
314 .offset = 0x80000,
315 .size = 12*0x20000,
316 },
317 {
318 .name = "Kernel",
319 .offset = 0x200000,
320 .size = 48*0x20000,
321 },
322 {
323 .name = "Root File System",
324 .offset = 0x800000,
325 .size = MTDPART_SIZ_FULL,
326 },
327 };
328
329
330 /**
331 * struct fsmc_nand_data - structure for FSMC NAND device state
332 *
333 * @pid: Part ID on the AMBA PrimeCell format
334 * @mtd: MTD info for a NAND flash.
335 * @nand: Chip related info for a NAND flash.
336 *
337 * @ecc_place: ECC placing locations in oobfree type format.
338 * @bank: Bank number for probed device.
339 * @clk: Clock structure for FSMC.
340 *
341 * @data_va: NAND port for Data.
342 * @cmd_va: NAND port for Command.
343 * @addr_va: NAND port for Address.
344 * @regs_va: FSMC regs base address.
345 */
346 struct fsmc_nand_data {
347 u32 pid;
348 struct mtd_info mtd;
349 struct nand_chip nand;
350
351 struct fsmc_eccplace *ecc_place;
352 unsigned int bank;
353 struct clk *clk;
354
355 struct resource *resregs;
356 struct resource *rescmd;
357 struct resource *resaddr;
358 struct resource *resdata;
359
360 void __iomem *data_va;
361 void __iomem *cmd_va;
362 void __iomem *addr_va;
363 void __iomem *regs_va;
364
365 void (*select_chip)(uint32_t bank, uint32_t busw);
366 };
367
368 /* Assert CS signal based on chipnr */
369 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
370 {
371 struct nand_chip *chip = mtd->priv;
372 struct fsmc_nand_data *host;
373
374 host = container_of(mtd, struct fsmc_nand_data, mtd);
375
376 switch (chipnr) {
377 case -1:
378 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
379 break;
380 case 0:
381 case 1:
382 case 2:
383 case 3:
384 if (host->select_chip)
385 host->select_chip(chipnr,
386 chip->options & NAND_BUSWIDTH_16);
387 break;
388
389 default:
390 BUG();
391 }
392 }
393
394 /*
395 * fsmc_cmd_ctrl - For facilitaing Hardware access
396 * This routine allows hardware specific access to control-lines(ALE,CLE)
397 */
398 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
399 {
400 struct nand_chip *this = mtd->priv;
401 struct fsmc_nand_data *host = container_of(mtd,
402 struct fsmc_nand_data, mtd);
403 struct fsmc_regs *regs = host->regs_va;
404 unsigned int bank = host->bank;
405
406 if (ctrl & NAND_CTRL_CHANGE) {
407 if (ctrl & NAND_CLE) {
408 this->IO_ADDR_R = (void __iomem *)host->cmd_va;
409 this->IO_ADDR_W = (void __iomem *)host->cmd_va;
410 } else if (ctrl & NAND_ALE) {
411 this->IO_ADDR_R = (void __iomem *)host->addr_va;
412 this->IO_ADDR_W = (void __iomem *)host->addr_va;
413 } else {
414 this->IO_ADDR_R = (void __iomem *)host->data_va;
415 this->IO_ADDR_W = (void __iomem *)host->data_va;
416 }
417
418 if (ctrl & NAND_NCE) {
419 writel(readl(&regs->bank_regs[bank].pc) | FSMC_ENABLE,
420 &regs->bank_regs[bank].pc);
421 } else {
422 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ENABLE,
423 &regs->bank_regs[bank].pc);
424 }
425 }
426
427 mb();
428
429 if (cmd != NAND_CMD_NONE)
430 writeb(cmd, this->IO_ADDR_W);
431 }
432
433 /*
434 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
435 *
436 * This routine initializes timing parameters related to NAND memory access in
437 * FSMC registers
438 */
439 static void __init fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
440 uint32_t busw)
441 {
442 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
443
444 if (busw)
445 writel(value | FSMC_DEVWID_16, &regs->bank_regs[bank].pc);
446 else
447 writel(value | FSMC_DEVWID_8, &regs->bank_regs[bank].pc);
448
449 writel(readl(&regs->bank_regs[bank].pc) | FSMC_TCLR_1 | FSMC_TAR_1,
450 &regs->bank_regs[bank].pc);
451 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
452 &regs->bank_regs[bank].comm);
453 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
454 &regs->bank_regs[bank].attrib);
455 }
456
457 /*
458 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
459 */
460 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
461 {
462 struct fsmc_nand_data *host = container_of(mtd,
463 struct fsmc_nand_data, mtd);
464 struct fsmc_regs *regs = host->regs_va;
465 uint32_t bank = host->bank;
466
467 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256,
468 &regs->bank_regs[bank].pc);
469 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ECCEN,
470 &regs->bank_regs[bank].pc);
471 writel(readl(&regs->bank_regs[bank].pc) | FSMC_ECCEN,
472 &regs->bank_regs[bank].pc);
473 }
474
475 /*
476 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
477 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
478 * max of 8-bits)
479 */
480 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
481 uint8_t *ecc)
482 {
483 struct fsmc_nand_data *host = container_of(mtd,
484 struct fsmc_nand_data, mtd);
485 struct fsmc_regs *regs = host->regs_va;
486 uint32_t bank = host->bank;
487 uint32_t ecc_tmp;
488 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
489
490 do {
491 if (readl(&regs->bank_regs[bank].sts) & FSMC_CODE_RDY)
492 break;
493 else
494 cond_resched();
495 } while (!time_after_eq(jiffies, deadline));
496
497 ecc_tmp = readl(&regs->bank_regs[bank].ecc1);
498 ecc[0] = (uint8_t) (ecc_tmp >> 0);
499 ecc[1] = (uint8_t) (ecc_tmp >> 8);
500 ecc[2] = (uint8_t) (ecc_tmp >> 16);
501 ecc[3] = (uint8_t) (ecc_tmp >> 24);
502
503 ecc_tmp = readl(&regs->bank_regs[bank].ecc2);
504 ecc[4] = (uint8_t) (ecc_tmp >> 0);
505 ecc[5] = (uint8_t) (ecc_tmp >> 8);
506 ecc[6] = (uint8_t) (ecc_tmp >> 16);
507 ecc[7] = (uint8_t) (ecc_tmp >> 24);
508
509 ecc_tmp = readl(&regs->bank_regs[bank].ecc3);
510 ecc[8] = (uint8_t) (ecc_tmp >> 0);
511 ecc[9] = (uint8_t) (ecc_tmp >> 8);
512 ecc[10] = (uint8_t) (ecc_tmp >> 16);
513 ecc[11] = (uint8_t) (ecc_tmp >> 24);
514
515 ecc_tmp = readl(&regs->bank_regs[bank].sts);
516 ecc[12] = (uint8_t) (ecc_tmp >> 16);
517
518 return 0;
519 }
520
521 /*
522 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
523 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
524 * max of 1-bit)
525 */
526 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
527 uint8_t *ecc)
528 {
529 struct fsmc_nand_data *host = container_of(mtd,
530 struct fsmc_nand_data, mtd);
531 struct fsmc_regs *regs = host->regs_va;
532 uint32_t bank = host->bank;
533 uint32_t ecc_tmp;
534
535 ecc_tmp = readl(&regs->bank_regs[bank].ecc1);
536 ecc[0] = (uint8_t) (ecc_tmp >> 0);
537 ecc[1] = (uint8_t) (ecc_tmp >> 8);
538 ecc[2] = (uint8_t) (ecc_tmp >> 16);
539
540 return 0;
541 }
542
543 /* Count the number of 0's in buff upto a max of max_bits */
544 static int count_written_bits(uint8_t *buff, int size, int max_bits)
545 {
546 int k, written_bits = 0;
547
548 for (k = 0; k < size; k++) {
549 written_bits += hweight8(~buff[k]);
550 if (written_bits > max_bits)
551 break;
552 }
553
554 return written_bits;
555 }
556
557 /*
558 * fsmc_read_page_hwecc
559 * @mtd: mtd info structure
560 * @chip: nand chip info structure
561 * @buf: buffer to store read data
562 * @page: page number to read
563 *
564 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
565 * performed in a strict sequence as follows:
566 * data(512 byte) -> ecc(13 byte)
567 * After this read, fsmc hardware generates and reports error data bits(up to a
568 * max of 8 bits)
569 */
570 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
571 uint8_t *buf, int page)
572 {
573 struct fsmc_nand_data *host = container_of(mtd,
574 struct fsmc_nand_data, mtd);
575 struct fsmc_eccplace *ecc_place = host->ecc_place;
576 int i, j, s, stat, eccsize = chip->ecc.size;
577 int eccbytes = chip->ecc.bytes;
578 int eccsteps = chip->ecc.steps;
579 uint8_t *p = buf;
580 uint8_t *ecc_calc = chip->buffers->ecccalc;
581 uint8_t *ecc_code = chip->buffers->ecccode;
582 int off, len, group = 0;
583 /*
584 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
585 * end up reading 14 bytes (7 words) from oob. The local array is
586 * to maintain word alignment
587 */
588 uint16_t ecc_oob[7];
589 uint8_t *oob = (uint8_t *)&ecc_oob[0];
590
591 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
592 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
593 chip->ecc.hwctl(mtd, NAND_ECC_READ);
594 chip->read_buf(mtd, p, eccsize);
595
596 for (j = 0; j < eccbytes;) {
597 off = ecc_place->eccplace[group].offset;
598 len = ecc_place->eccplace[group].length;
599 group++;
600
601 /*
602 * length is intentionally kept a higher multiple of 2
603 * to read at least 13 bytes even in case of 16 bit NAND
604 * devices
605 */
606 len = roundup(len, 2);
607 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
608 chip->read_buf(mtd, oob + j, len);
609 j += len;
610 }
611
612 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
613 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
614
615 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
616 if (stat < 0)
617 mtd->ecc_stats.failed++;
618 else
619 mtd->ecc_stats.corrected += stat;
620 }
621
622 return 0;
623 }
624
625 /*
626 * fsmc_bch8_correct_data
627 * @mtd: mtd info structure
628 * @dat: buffer of read data
629 * @read_ecc: ecc read from device spare area
630 * @calc_ecc: ecc calculated from read data
631 *
632 * calc_ecc is a 104 bit information containing maximum of 8 error
633 * offset informations of 13 bits each in 512 bytes of read data.
634 */
635 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
636 uint8_t *read_ecc, uint8_t *calc_ecc)
637 {
638 struct fsmc_nand_data *host = container_of(mtd,
639 struct fsmc_nand_data, mtd);
640 struct nand_chip *chip = mtd->priv;
641 struct fsmc_regs *regs = host->regs_va;
642 unsigned int bank = host->bank;
643 uint32_t err_idx[8];
644 uint32_t num_err, i;
645 uint32_t ecc1, ecc2, ecc3, ecc4;
646
647 num_err = (readl(&regs->bank_regs[bank].sts) >> 10) & 0xF;
648
649 /* no bit flipping */
650 if (likely(num_err == 0))
651 return 0;
652
653 /* too many errors */
654 if (unlikely(num_err > 8)) {
655 /*
656 * This is a temporary erase check. A newly erased page read
657 * would result in an ecc error because the oob data is also
658 * erased to FF and the calculated ecc for an FF data is not
659 * FF..FF.
660 * This is a workaround to skip performing correction in case
661 * data is FF..FF
662 *
663 * Logic:
664 * For every page, each bit written as 0 is counted until these
665 * number of bits are greater than 8 (the maximum correction
666 * capability of FSMC for each 512 + 13 bytes)
667 */
668
669 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
670 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
671
672 if ((bits_ecc + bits_data) <= 8) {
673 if (bits_data)
674 memset(dat, 0xff, chip->ecc.size);
675 return bits_data;
676 }
677
678 return -EBADMSG;
679 }
680
681 /*
682 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
683 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
684 *
685 * calc_ecc is a 104 bit information containing maximum of 8 error
686 * offset informations of 13 bits each. calc_ecc is copied into a
687 * uint64_t array and error offset indexes are populated in err_idx
688 * array
689 */
690 ecc1 = readl(&regs->bank_regs[bank].ecc1);
691 ecc2 = readl(&regs->bank_regs[bank].ecc2);
692 ecc3 = readl(&regs->bank_regs[bank].ecc3);
693 ecc4 = readl(&regs->bank_regs[bank].sts);
694
695 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
696 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
697 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
698 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
699 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
700 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
701 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
702 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
703
704 i = 0;
705 while (num_err--) {
706 change_bit(0, (unsigned long *)&err_idx[i]);
707 change_bit(1, (unsigned long *)&err_idx[i]);
708
709 if (err_idx[i] <= chip->ecc.size * 8) {
710 change_bit(err_idx[i], (unsigned long *)dat);
711 i++;
712 }
713 }
714 return i;
715 }
716
717 /*
718 * fsmc_nand_probe - Probe function
719 * @pdev: platform device structure
720 */
721 static int __init fsmc_nand_probe(struct platform_device *pdev)
722 {
723 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
724 struct fsmc_nand_data *host;
725 struct mtd_info *mtd;
726 struct nand_chip *nand;
727 struct fsmc_regs *regs;
728 struct resource *res;
729 int ret = 0;
730 u32 pid;
731 int i;
732
733 if (!pdata) {
734 dev_err(&pdev->dev, "platform data is NULL\n");
735 return -EINVAL;
736 }
737
738 /* Allocate memory for the device structure (and zero it) */
739 host = kzalloc(sizeof(*host), GFP_KERNEL);
740 if (!host) {
741 dev_err(&pdev->dev, "failed to allocate device structure\n");
742 return -ENOMEM;
743 }
744
745 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
746 if (!res) {
747 ret = -EIO;
748 goto err_probe1;
749 }
750
751 host->resdata = request_mem_region(res->start, resource_size(res),
752 pdev->name);
753 if (!host->resdata) {
754 ret = -EIO;
755 goto err_probe1;
756 }
757
758 host->data_va = ioremap(res->start, resource_size(res));
759 if (!host->data_va) {
760 ret = -EIO;
761 goto err_probe1;
762 }
763
764 host->resaddr = request_mem_region(res->start + pdata->ale_off,
765 resource_size(res), pdev->name);
766 if (!host->resaddr) {
767 ret = -EIO;
768 goto err_probe1;
769 }
770
771 host->addr_va = ioremap(res->start + pdata->ale_off,
772 resource_size(res));
773 if (!host->addr_va) {
774 ret = -EIO;
775 goto err_probe1;
776 }
777
778 host->rescmd = request_mem_region(res->start + pdata->cle_off,
779 resource_size(res), pdev->name);
780 if (!host->rescmd) {
781 ret = -EIO;
782 goto err_probe1;
783 }
784
785 host->cmd_va = ioremap(res->start + pdata->cle_off, resource_size(res));
786 if (!host->cmd_va) {
787 ret = -EIO;
788 goto err_probe1;
789 }
790
791 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
792 if (!res) {
793 ret = -EIO;
794 goto err_probe1;
795 }
796
797 host->resregs = request_mem_region(res->start, resource_size(res),
798 pdev->name);
799 if (!host->resregs) {
800 ret = -EIO;
801 goto err_probe1;
802 }
803
804 host->regs_va = ioremap(res->start, resource_size(res));
805 if (!host->regs_va) {
806 ret = -EIO;
807 goto err_probe1;
808 }
809
810 host->clk = clk_get(&pdev->dev, NULL);
811 if (IS_ERR(host->clk)) {
812 dev_err(&pdev->dev, "failed to fetch block clock\n");
813 ret = PTR_ERR(host->clk);
814 host->clk = NULL;
815 goto err_probe1;
816 }
817
818 ret = clk_enable(host->clk);
819 if (ret)
820 goto err_probe1;
821
822 /*
823 * This device ID is actually a common AMBA ID as used on the
824 * AMBA PrimeCell bus. However it is not a PrimeCell.
825 */
826 for (pid = 0, i = 0; i < 4; i++)
827 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
828 host->pid = pid;
829 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
830 "revision %02x, config %02x\n",
831 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
832 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
833
834 host->bank = pdata->bank;
835 host->select_chip = pdata->select_bank;
836 regs = host->regs_va;
837
838 /* Link all private pointers */
839 mtd = &host->mtd;
840 nand = &host->nand;
841 mtd->priv = nand;
842 nand->priv = host;
843
844 host->mtd.owner = THIS_MODULE;
845 nand->IO_ADDR_R = host->data_va;
846 nand->IO_ADDR_W = host->data_va;
847 nand->cmd_ctrl = fsmc_cmd_ctrl;
848 nand->chip_delay = 30;
849
850 nand->ecc.mode = NAND_ECC_HW;
851 nand->ecc.hwctl = fsmc_enable_hwecc;
852 nand->ecc.size = 512;
853 nand->options = pdata->options;
854 nand->select_chip = fsmc_select_chip;
855
856 if (pdata->width == FSMC_NAND_BW16)
857 nand->options |= NAND_BUSWIDTH_16;
858
859 fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16);
860
861 if (AMBA_REV_BITS(host->pid) >= 8) {
862 nand->ecc.read_page = fsmc_read_page_hwecc;
863 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
864 nand->ecc.correct = fsmc_bch8_correct_data;
865 nand->ecc.bytes = 13;
866 nand->ecc.strength = 8;
867 } else {
868 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
869 nand->ecc.correct = nand_correct_data;
870 nand->ecc.bytes = 3;
871 nand->ecc.strength = 1;
872 }
873
874 /*
875 * Scan to find existence of the device
876 */
877 if (nand_scan_ident(&host->mtd, 1, NULL)) {
878 ret = -ENXIO;
879 dev_err(&pdev->dev, "No NAND Device found!\n");
880 goto err_probe;
881 }
882
883 if (AMBA_REV_BITS(host->pid) >= 8) {
884 switch (host->mtd.oobsize) {
885 case 16:
886 nand->ecc.layout = &fsmc_ecc4_16_layout;
887 host->ecc_place = &fsmc_ecc4_sp_place;
888 break;
889 case 64:
890 nand->ecc.layout = &fsmc_ecc4_64_layout;
891 host->ecc_place = &fsmc_ecc4_lp_place;
892 break;
893 case 128:
894 nand->ecc.layout = &fsmc_ecc4_128_layout;
895 host->ecc_place = &fsmc_ecc4_lp_place;
896 break;
897 case 224:
898 nand->ecc.layout = &fsmc_ecc4_224_layout;
899 host->ecc_place = &fsmc_ecc4_lp_place;
900 break;
901 case 256:
902 nand->ecc.layout = &fsmc_ecc4_256_layout;
903 host->ecc_place = &fsmc_ecc4_lp_place;
904 break;
905 default:
906 printk(KERN_WARNING "No oob scheme defined for "
907 "oobsize %d\n", mtd->oobsize);
908 BUG();
909 }
910 } else {
911 switch (host->mtd.oobsize) {
912 case 16:
913 nand->ecc.layout = &fsmc_ecc1_16_layout;
914 break;
915 case 64:
916 nand->ecc.layout = &fsmc_ecc1_64_layout;
917 break;
918 case 128:
919 nand->ecc.layout = &fsmc_ecc1_128_layout;
920 break;
921 default:
922 printk(KERN_WARNING "No oob scheme defined for "
923 "oobsize %d\n", mtd->oobsize);
924 BUG();
925 }
926 }
927
928 /* Second stage of scan to fill MTD data-structures */
929 if (nand_scan_tail(&host->mtd)) {
930 ret = -ENXIO;
931 goto err_probe;
932 }
933
934 /*
935 * The partition information can is accessed by (in the same precedence)
936 *
937 * command line through Bootloader,
938 * platform data,
939 * default partition information present in driver.
940 */
941 /*
942 * Check for partition info passed
943 */
944 host->mtd.name = "nand";
945 ret = mtd_device_parse_register(&host->mtd, NULL, NULL,
946 host->mtd.size <= 0x04000000 ?
947 partition_info_16KB_blk :
948 partition_info_128KB_blk,
949 host->mtd.size <= 0x04000000 ?
950 ARRAY_SIZE(partition_info_16KB_blk) :
951 ARRAY_SIZE(partition_info_128KB_blk));
952 if (ret)
953 goto err_probe;
954
955 platform_set_drvdata(pdev, host);
956 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
957 return 0;
958
959 err_probe:
960 clk_disable(host->clk);
961 err_probe1:
962 if (host->clk)
963 clk_put(host->clk);
964 if (host->regs_va)
965 iounmap(host->regs_va);
966 if (host->resregs)
967 release_mem_region(host->resregs->start,
968 resource_size(host->resregs));
969 if (host->cmd_va)
970 iounmap(host->cmd_va);
971 if (host->rescmd)
972 release_mem_region(host->rescmd->start,
973 resource_size(host->rescmd));
974 if (host->addr_va)
975 iounmap(host->addr_va);
976 if (host->resaddr)
977 release_mem_region(host->resaddr->start,
978 resource_size(host->resaddr));
979 if (host->data_va)
980 iounmap(host->data_va);
981 if (host->resdata)
982 release_mem_region(host->resdata->start,
983 resource_size(host->resdata));
984
985 kfree(host);
986 return ret;
987 }
988
989 /*
990 * Clean up routine
991 */
992 static int fsmc_nand_remove(struct platform_device *pdev)
993 {
994 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
995
996 platform_set_drvdata(pdev, NULL);
997
998 if (host) {
999 nand_release(&host->mtd);
1000 clk_disable(host->clk);
1001 clk_put(host->clk);
1002
1003 iounmap(host->regs_va);
1004 release_mem_region(host->resregs->start,
1005 resource_size(host->resregs));
1006 iounmap(host->cmd_va);
1007 release_mem_region(host->rescmd->start,
1008 resource_size(host->rescmd));
1009 iounmap(host->addr_va);
1010 release_mem_region(host->resaddr->start,
1011 resource_size(host->resaddr));
1012 iounmap(host->data_va);
1013 release_mem_region(host->resdata->start,
1014 resource_size(host->resdata));
1015
1016 kfree(host);
1017 }
1018 return 0;
1019 }
1020
1021 #ifdef CONFIG_PM
1022 static int fsmc_nand_suspend(struct device *dev)
1023 {
1024 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1025 if (host)
1026 clk_disable(host->clk);
1027 return 0;
1028 }
1029
1030 static int fsmc_nand_resume(struct device *dev)
1031 {
1032 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1033 if (host)
1034 clk_enable(host->clk);
1035 return 0;
1036 }
1037
1038 static const struct dev_pm_ops fsmc_nand_pm_ops = {
1039 .suspend = fsmc_nand_suspend,
1040 .resume = fsmc_nand_resume,
1041 };
1042 #endif
1043
1044 static struct platform_driver fsmc_nand_driver = {
1045 .remove = fsmc_nand_remove,
1046 .driver = {
1047 .owner = THIS_MODULE,
1048 .name = "fsmc-nand",
1049 #ifdef CONFIG_PM
1050 .pm = &fsmc_nand_pm_ops,
1051 #endif
1052 },
1053 };
1054
1055 static int __init fsmc_nand_init(void)
1056 {
1057 return platform_driver_probe(&fsmc_nand_driver,
1058 fsmc_nand_probe);
1059 }
1060 module_init(fsmc_nand_init);
1061
1062 static void __exit fsmc_nand_exit(void)
1063 {
1064 platform_driver_unregister(&fsmc_nand_driver);
1065 }
1066 module_exit(fsmc_nand_exit);
1067
1068 MODULE_LICENSE("GPL");
1069 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1070 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
kernel source for telekom puls (alcatel/mediatek)