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mmc: wbsd: Remove driver version
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / omap.c
1 /*
2 * linux/drivers/media/mmc/omap.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/timer.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/protocol.h>
26 #include <linux/mmc/card.h>
27 #include <linux/clk.h>
28
29 #include <asm/io.h>
30 #include <asm/irq.h>
31 #include <asm/scatterlist.h>
32 #include <asm/mach-types.h>
33
34 #include <asm/arch/board.h>
35 #include <asm/arch/gpio.h>
36 #include <asm/arch/dma.h>
37 #include <asm/arch/mux.h>
38 #include <asm/arch/fpga.h>
39 #include <asm/arch/tps65010.h>
40
41 #define OMAP_MMC_REG_CMD 0x00
42 #define OMAP_MMC_REG_ARGL 0x04
43 #define OMAP_MMC_REG_ARGH 0x08
44 #define OMAP_MMC_REG_CON 0x0c
45 #define OMAP_MMC_REG_STAT 0x10
46 #define OMAP_MMC_REG_IE 0x14
47 #define OMAP_MMC_REG_CTO 0x18
48 #define OMAP_MMC_REG_DTO 0x1c
49 #define OMAP_MMC_REG_DATA 0x20
50 #define OMAP_MMC_REG_BLEN 0x24
51 #define OMAP_MMC_REG_NBLK 0x28
52 #define OMAP_MMC_REG_BUF 0x2c
53 #define OMAP_MMC_REG_SDIO 0x34
54 #define OMAP_MMC_REG_REV 0x3c
55 #define OMAP_MMC_REG_RSP0 0x40
56 #define OMAP_MMC_REG_RSP1 0x44
57 #define OMAP_MMC_REG_RSP2 0x48
58 #define OMAP_MMC_REG_RSP3 0x4c
59 #define OMAP_MMC_REG_RSP4 0x50
60 #define OMAP_MMC_REG_RSP5 0x54
61 #define OMAP_MMC_REG_RSP6 0x58
62 #define OMAP_MMC_REG_RSP7 0x5c
63 #define OMAP_MMC_REG_IOSR 0x60
64 #define OMAP_MMC_REG_SYSC 0x64
65 #define OMAP_MMC_REG_SYSS 0x68
66
67 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
68 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
69 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
70 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
71 #define OMAP_MMC_STAT_A_FULL (1 << 10)
72 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
73 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
74 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
75 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
76 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
77 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
78 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
79 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
80
81 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
82 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
83
84 /*
85 * Command types
86 */
87 #define OMAP_MMC_CMDTYPE_BC 0
88 #define OMAP_MMC_CMDTYPE_BCR 1
89 #define OMAP_MMC_CMDTYPE_AC 2
90 #define OMAP_MMC_CMDTYPE_ADTC 3
91
92
93 #define DRIVER_NAME "mmci-omap"
94
95 /* Specifies how often in millisecs to poll for card status changes
96 * when the cover switch is open */
97 #define OMAP_MMC_SWITCH_POLL_DELAY 500
98
99 static int mmc_omap_enable_poll = 1;
100
101 struct mmc_omap_host {
102 int initialized;
103 int suspended;
104 struct mmc_request * mrq;
105 struct mmc_command * cmd;
106 struct mmc_data * data;
107 struct mmc_host * mmc;
108 struct device * dev;
109 unsigned char id; /* 16xx chips have 2 MMC blocks */
110 struct clk * iclk;
111 struct clk * fclk;
112 struct resource *mem_res;
113 void __iomem *virt_base;
114 unsigned int phys_base;
115 int irq;
116 unsigned char bus_mode;
117 unsigned char hw_bus_mode;
118
119 unsigned int sg_len;
120 int sg_idx;
121 u16 * buffer;
122 u32 buffer_bytes_left;
123 u32 total_bytes_left;
124
125 unsigned use_dma:1;
126 unsigned brs_received:1, dma_done:1;
127 unsigned dma_is_read:1;
128 unsigned dma_in_use:1;
129 int dma_ch;
130 spinlock_t dma_lock;
131 struct timer_list dma_timer;
132 unsigned dma_len;
133
134 short power_pin;
135 short wp_pin;
136
137 int switch_pin;
138 struct work_struct switch_work;
139 struct timer_list switch_timer;
140 int switch_last_state;
141 };
142
143 static inline int
144 mmc_omap_cover_is_open(struct mmc_omap_host *host)
145 {
146 if (host->switch_pin < 0)
147 return 0;
148 return omap_get_gpio_datain(host->switch_pin);
149 }
150
151 static ssize_t
152 mmc_omap_show_cover_switch(struct device *dev,
153 struct device_attribute *attr, char *buf)
154 {
155 struct mmc_omap_host *host = dev_get_drvdata(dev);
156
157 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(host) ? "open" :
158 "closed");
159 }
160
161 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
162
163 static ssize_t
164 mmc_omap_show_enable_poll(struct device *dev,
165 struct device_attribute *attr, char *buf)
166 {
167 return snprintf(buf, PAGE_SIZE, "%d\n", mmc_omap_enable_poll);
168 }
169
170 static ssize_t
171 mmc_omap_store_enable_poll(struct device *dev,
172 struct device_attribute *attr, const char *buf,
173 size_t size)
174 {
175 int enable_poll;
176
177 if (sscanf(buf, "%10d", &enable_poll) != 1)
178 return -EINVAL;
179
180 if (enable_poll != mmc_omap_enable_poll) {
181 struct mmc_omap_host *host = dev_get_drvdata(dev);
182
183 mmc_omap_enable_poll = enable_poll;
184 if (enable_poll && host->switch_pin >= 0)
185 schedule_work(&host->switch_work);
186 }
187 return size;
188 }
189
190 static DEVICE_ATTR(enable_poll, 0664,
191 mmc_omap_show_enable_poll, mmc_omap_store_enable_poll);
192
193 static void
194 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
195 {
196 u32 cmdreg;
197 u32 resptype;
198 u32 cmdtype;
199
200 host->cmd = cmd;
201
202 resptype = 0;
203 cmdtype = 0;
204
205 /* Our hardware needs to know exact type */
206 switch (mmc_resp_type(cmd)) {
207 case MMC_RSP_NONE:
208 break;
209 case MMC_RSP_R1:
210 case MMC_RSP_R1B:
211 /* resp 1, 1b, 6, 7 */
212 resptype = 1;
213 break;
214 case MMC_RSP_R2:
215 resptype = 2;
216 break;
217 case MMC_RSP_R3:
218 resptype = 3;
219 break;
220 default:
221 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
222 break;
223 }
224
225 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
226 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
227 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
228 cmdtype = OMAP_MMC_CMDTYPE_BC;
229 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
230 cmdtype = OMAP_MMC_CMDTYPE_BCR;
231 } else {
232 cmdtype = OMAP_MMC_CMDTYPE_AC;
233 }
234
235 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
236
237 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
238 cmdreg |= 1 << 6;
239
240 if (cmd->flags & MMC_RSP_BUSY)
241 cmdreg |= 1 << 11;
242
243 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
244 cmdreg |= 1 << 15;
245
246 clk_enable(host->fclk);
247
248 OMAP_MMC_WRITE(host, CTO, 200);
249 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
250 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
251 OMAP_MMC_WRITE(host, IE,
252 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
253 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
254 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
255 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
256 OMAP_MMC_STAT_END_OF_DATA);
257 OMAP_MMC_WRITE(host, CMD, cmdreg);
258 }
259
260 static void
261 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
262 {
263 if (host->dma_in_use) {
264 enum dma_data_direction dma_data_dir;
265
266 BUG_ON(host->dma_ch < 0);
267 if (data->error != MMC_ERR_NONE)
268 omap_stop_dma(host->dma_ch);
269 /* Release DMA channel lazily */
270 mod_timer(&host->dma_timer, jiffies + HZ);
271 if (data->flags & MMC_DATA_WRITE)
272 dma_data_dir = DMA_TO_DEVICE;
273 else
274 dma_data_dir = DMA_FROM_DEVICE;
275 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
276 dma_data_dir);
277 }
278 host->data = NULL;
279 host->sg_len = 0;
280 clk_disable(host->fclk);
281
282 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
283 * dozens of requests until the card finishes writing data.
284 * It'd be cheaper to just wait till an EOFB interrupt arrives...
285 */
286
287 if (!data->stop) {
288 host->mrq = NULL;
289 mmc_request_done(host->mmc, data->mrq);
290 return;
291 }
292
293 mmc_omap_start_command(host, data->stop);
294 }
295
296 static void
297 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
298 {
299 unsigned long flags;
300 int done;
301
302 if (!host->dma_in_use) {
303 mmc_omap_xfer_done(host, data);
304 return;
305 }
306 done = 0;
307 spin_lock_irqsave(&host->dma_lock, flags);
308 if (host->dma_done)
309 done = 1;
310 else
311 host->brs_received = 1;
312 spin_unlock_irqrestore(&host->dma_lock, flags);
313 if (done)
314 mmc_omap_xfer_done(host, data);
315 }
316
317 static void
318 mmc_omap_dma_timer(unsigned long data)
319 {
320 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
321
322 BUG_ON(host->dma_ch < 0);
323 omap_free_dma(host->dma_ch);
324 host->dma_ch = -1;
325 }
326
327 static void
328 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
329 {
330 unsigned long flags;
331 int done;
332
333 done = 0;
334 spin_lock_irqsave(&host->dma_lock, flags);
335 if (host->brs_received)
336 done = 1;
337 else
338 host->dma_done = 1;
339 spin_unlock_irqrestore(&host->dma_lock, flags);
340 if (done)
341 mmc_omap_xfer_done(host, data);
342 }
343
344 static void
345 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
346 {
347 host->cmd = NULL;
348
349 if (cmd->flags & MMC_RSP_PRESENT) {
350 if (cmd->flags & MMC_RSP_136) {
351 /* response type 2 */
352 cmd->resp[3] =
353 OMAP_MMC_READ(host, RSP0) |
354 (OMAP_MMC_READ(host, RSP1) << 16);
355 cmd->resp[2] =
356 OMAP_MMC_READ(host, RSP2) |
357 (OMAP_MMC_READ(host, RSP3) << 16);
358 cmd->resp[1] =
359 OMAP_MMC_READ(host, RSP4) |
360 (OMAP_MMC_READ(host, RSP5) << 16);
361 cmd->resp[0] =
362 OMAP_MMC_READ(host, RSP6) |
363 (OMAP_MMC_READ(host, RSP7) << 16);
364 } else {
365 /* response types 1, 1b, 3, 4, 5, 6 */
366 cmd->resp[0] =
367 OMAP_MMC_READ(host, RSP6) |
368 (OMAP_MMC_READ(host, RSP7) << 16);
369 }
370 }
371
372 if (host->data == NULL || cmd->error != MMC_ERR_NONE) {
373 host->mrq = NULL;
374 clk_disable(host->fclk);
375 mmc_request_done(host->mmc, cmd->mrq);
376 }
377 }
378
379 /* PIO only */
380 static void
381 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
382 {
383 struct scatterlist *sg;
384
385 sg = host->data->sg + host->sg_idx;
386 host->buffer_bytes_left = sg->length;
387 host->buffer = page_address(sg->page) + sg->offset;
388 if (host->buffer_bytes_left > host->total_bytes_left)
389 host->buffer_bytes_left = host->total_bytes_left;
390 }
391
392 /* PIO only */
393 static void
394 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
395 {
396 int n;
397
398 if (host->buffer_bytes_left == 0) {
399 host->sg_idx++;
400 BUG_ON(host->sg_idx == host->sg_len);
401 mmc_omap_sg_to_buf(host);
402 }
403 n = 64;
404 if (n > host->buffer_bytes_left)
405 n = host->buffer_bytes_left;
406 host->buffer_bytes_left -= n;
407 host->total_bytes_left -= n;
408 host->data->bytes_xfered += n;
409
410 if (write) {
411 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
412 } else {
413 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
414 }
415 }
416
417 static inline void mmc_omap_report_irq(u16 status)
418 {
419 static const char *mmc_omap_status_bits[] = {
420 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
421 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
422 };
423 int i, c = 0;
424
425 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
426 if (status & (1 << i)) {
427 if (c)
428 printk(" ");
429 printk("%s", mmc_omap_status_bits[i]);
430 c++;
431 }
432 }
433
434 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
435 {
436 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
437 u16 status;
438 int end_command;
439 int end_transfer;
440 int transfer_error;
441
442 if (host->cmd == NULL && host->data == NULL) {
443 status = OMAP_MMC_READ(host, STAT);
444 dev_info(mmc_dev(host->mmc),"spurious irq 0x%04x\n", status);
445 if (status != 0) {
446 OMAP_MMC_WRITE(host, STAT, status);
447 OMAP_MMC_WRITE(host, IE, 0);
448 }
449 return IRQ_HANDLED;
450 }
451
452 end_command = 0;
453 end_transfer = 0;
454 transfer_error = 0;
455
456 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
457 OMAP_MMC_WRITE(host, STAT, status);
458 #ifdef CONFIG_MMC_DEBUG
459 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
460 status, host->cmd != NULL ? host->cmd->opcode : -1);
461 mmc_omap_report_irq(status);
462 printk("\n");
463 #endif
464 if (host->total_bytes_left) {
465 if ((status & OMAP_MMC_STAT_A_FULL) ||
466 (status & OMAP_MMC_STAT_END_OF_DATA))
467 mmc_omap_xfer_data(host, 0);
468 if (status & OMAP_MMC_STAT_A_EMPTY)
469 mmc_omap_xfer_data(host, 1);
470 }
471
472 if (status & OMAP_MMC_STAT_END_OF_DATA) {
473 end_transfer = 1;
474 }
475
476 if (status & OMAP_MMC_STAT_DATA_TOUT) {
477 dev_dbg(mmc_dev(host->mmc), "data timeout\n");
478 if (host->data) {
479 host->data->error |= MMC_ERR_TIMEOUT;
480 transfer_error = 1;
481 }
482 }
483
484 if (status & OMAP_MMC_STAT_DATA_CRC) {
485 if (host->data) {
486 host->data->error |= MMC_ERR_BADCRC;
487 dev_dbg(mmc_dev(host->mmc),
488 "data CRC error, bytes left %d\n",
489 host->total_bytes_left);
490 transfer_error = 1;
491 } else {
492 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
493 }
494 }
495
496 if (status & OMAP_MMC_STAT_CMD_TOUT) {
497 /* Timeouts are routine with some commands */
498 if (host->cmd) {
499 if (host->cmd->opcode != MMC_ALL_SEND_CID &&
500 host->cmd->opcode !=
501 MMC_SEND_OP_COND &&
502 host->cmd->opcode !=
503 MMC_APP_CMD &&
504 !mmc_omap_cover_is_open(host))
505 dev_err(mmc_dev(host->mmc),
506 "command timeout, CMD %d\n",
507 host->cmd->opcode);
508 host->cmd->error = MMC_ERR_TIMEOUT;
509 end_command = 1;
510 }
511 }
512
513 if (status & OMAP_MMC_STAT_CMD_CRC) {
514 if (host->cmd) {
515 dev_err(mmc_dev(host->mmc),
516 "command CRC error (CMD%d, arg 0x%08x)\n",
517 host->cmd->opcode, host->cmd->arg);
518 host->cmd->error = MMC_ERR_BADCRC;
519 end_command = 1;
520 } else
521 dev_err(mmc_dev(host->mmc),
522 "command CRC error without cmd?\n");
523 }
524
525 if (status & OMAP_MMC_STAT_CARD_ERR) {
526 if (host->cmd && host->cmd->opcode == MMC_STOP_TRANSMISSION) {
527 u32 response = OMAP_MMC_READ(host, RSP6)
528 | (OMAP_MMC_READ(host, RSP7) << 16);
529 /* STOP sometimes sets must-ignore bits */
530 if (!(response & (R1_CC_ERROR
531 | R1_ILLEGAL_COMMAND
532 | R1_COM_CRC_ERROR))) {
533 end_command = 1;
534 continue;
535 }
536 }
537
538 dev_dbg(mmc_dev(host->mmc), "card status error (CMD%d)\n",
539 host->cmd->opcode);
540 if (host->cmd) {
541 host->cmd->error = MMC_ERR_FAILED;
542 end_command = 1;
543 }
544 if (host->data) {
545 host->data->error = MMC_ERR_FAILED;
546 transfer_error = 1;
547 }
548 }
549
550 /*
551 * NOTE: On 1610 the END_OF_CMD may come too early when
552 * starting a write
553 */
554 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
555 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
556 end_command = 1;
557 }
558 }
559
560 if (end_command) {
561 mmc_omap_cmd_done(host, host->cmd);
562 }
563 if (transfer_error)
564 mmc_omap_xfer_done(host, host->data);
565 else if (end_transfer)
566 mmc_omap_end_of_data(host, host->data);
567
568 return IRQ_HANDLED;
569 }
570
571 static irqreturn_t mmc_omap_switch_irq(int irq, void *dev_id)
572 {
573 struct mmc_omap_host *host = (struct mmc_omap_host *) dev_id;
574
575 schedule_work(&host->switch_work);
576
577 return IRQ_HANDLED;
578 }
579
580 static void mmc_omap_switch_timer(unsigned long arg)
581 {
582 struct mmc_omap_host *host = (struct mmc_omap_host *) arg;
583
584 schedule_work(&host->switch_work);
585 }
586
587 static void mmc_omap_switch_handler(struct work_struct *work)
588 {
589 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, switch_work);
590 struct mmc_card *card;
591 static int complained = 0;
592 int cards = 0, cover_open;
593
594 if (host->switch_pin == -1)
595 return;
596 cover_open = mmc_omap_cover_is_open(host);
597 if (cover_open != host->switch_last_state) {
598 kobject_uevent(&host->dev->kobj, KOBJ_CHANGE);
599 host->switch_last_state = cover_open;
600 }
601 mmc_detect_change(host->mmc, 0);
602 list_for_each_entry(card, &host->mmc->cards, node) {
603 if (mmc_card_present(card))
604 cards++;
605 }
606 if (mmc_omap_cover_is_open(host)) {
607 if (!complained) {
608 dev_info(mmc_dev(host->mmc), "cover is open");
609 complained = 1;
610 }
611 if (mmc_omap_enable_poll)
612 mod_timer(&host->switch_timer, jiffies +
613 msecs_to_jiffies(OMAP_MMC_SWITCH_POLL_DELAY));
614 } else {
615 complained = 0;
616 }
617 }
618
619 /* Prepare to transfer the next segment of a scatterlist */
620 static void
621 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
622 {
623 int dma_ch = host->dma_ch;
624 unsigned long data_addr;
625 u16 buf, frame;
626 u32 count;
627 struct scatterlist *sg = &data->sg[host->sg_idx];
628 int src_port = 0;
629 int dst_port = 0;
630 int sync_dev = 0;
631
632 data_addr = host->phys_base + OMAP_MMC_REG_DATA;
633 frame = data->blksz;
634 count = sg_dma_len(sg);
635
636 if ((data->blocks == 1) && (count > data->blksz))
637 count = frame;
638
639 host->dma_len = count;
640
641 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
642 * Use 16 or 32 word frames when the blocksize is at least that large.
643 * Blocksize is usually 512 bytes; but not for some SD reads.
644 */
645 if (cpu_is_omap15xx() && frame > 32)
646 frame = 32;
647 else if (frame > 64)
648 frame = 64;
649 count /= frame;
650 frame >>= 1;
651
652 if (!(data->flags & MMC_DATA_WRITE)) {
653 buf = 0x800f | ((frame - 1) << 8);
654
655 if (cpu_class_is_omap1()) {
656 src_port = OMAP_DMA_PORT_TIPB;
657 dst_port = OMAP_DMA_PORT_EMIFF;
658 }
659 if (cpu_is_omap24xx())
660 sync_dev = OMAP24XX_DMA_MMC1_RX;
661
662 omap_set_dma_src_params(dma_ch, src_port,
663 OMAP_DMA_AMODE_CONSTANT,
664 data_addr, 0, 0);
665 omap_set_dma_dest_params(dma_ch, dst_port,
666 OMAP_DMA_AMODE_POST_INC,
667 sg_dma_address(sg), 0, 0);
668 omap_set_dma_dest_data_pack(dma_ch, 1);
669 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
670 } else {
671 buf = 0x0f80 | ((frame - 1) << 0);
672
673 if (cpu_class_is_omap1()) {
674 src_port = OMAP_DMA_PORT_EMIFF;
675 dst_port = OMAP_DMA_PORT_TIPB;
676 }
677 if (cpu_is_omap24xx())
678 sync_dev = OMAP24XX_DMA_MMC1_TX;
679
680 omap_set_dma_dest_params(dma_ch, dst_port,
681 OMAP_DMA_AMODE_CONSTANT,
682 data_addr, 0, 0);
683 omap_set_dma_src_params(dma_ch, src_port,
684 OMAP_DMA_AMODE_POST_INC,
685 sg_dma_address(sg), 0, 0);
686 omap_set_dma_src_data_pack(dma_ch, 1);
687 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
688 }
689
690 /* Max limit for DMA frame count is 0xffff */
691 BUG_ON(count > 0xffff);
692
693 OMAP_MMC_WRITE(host, BUF, buf);
694 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
695 frame, count, OMAP_DMA_SYNC_FRAME,
696 sync_dev, 0);
697 }
698
699 /* A scatterlist segment completed */
700 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
701 {
702 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
703 struct mmc_data *mmcdat = host->data;
704
705 if (unlikely(host->dma_ch < 0)) {
706 dev_err(mmc_dev(host->mmc),
707 "DMA callback while DMA not enabled\n");
708 return;
709 }
710 /* FIXME: We really should do something to _handle_ the errors */
711 if (ch_status & OMAP1_DMA_TOUT_IRQ) {
712 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
713 return;
714 }
715 if (ch_status & OMAP_DMA_DROP_IRQ) {
716 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
717 return;
718 }
719 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
720 return;
721 }
722 mmcdat->bytes_xfered += host->dma_len;
723 host->sg_idx++;
724 if (host->sg_idx < host->sg_len) {
725 mmc_omap_prepare_dma(host, host->data);
726 omap_start_dma(host->dma_ch);
727 } else
728 mmc_omap_dma_done(host, host->data);
729 }
730
731 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
732 {
733 const char *dev_name;
734 int sync_dev, dma_ch, is_read, r;
735
736 is_read = !(data->flags & MMC_DATA_WRITE);
737 del_timer_sync(&host->dma_timer);
738 if (host->dma_ch >= 0) {
739 if (is_read == host->dma_is_read)
740 return 0;
741 omap_free_dma(host->dma_ch);
742 host->dma_ch = -1;
743 }
744
745 if (is_read) {
746 if (host->id == 1) {
747 sync_dev = OMAP_DMA_MMC_RX;
748 dev_name = "MMC1 read";
749 } else {
750 sync_dev = OMAP_DMA_MMC2_RX;
751 dev_name = "MMC2 read";
752 }
753 } else {
754 if (host->id == 1) {
755 sync_dev = OMAP_DMA_MMC_TX;
756 dev_name = "MMC1 write";
757 } else {
758 sync_dev = OMAP_DMA_MMC2_TX;
759 dev_name = "MMC2 write";
760 }
761 }
762 r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
763 host, &dma_ch);
764 if (r != 0) {
765 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
766 return r;
767 }
768 host->dma_ch = dma_ch;
769 host->dma_is_read = is_read;
770
771 return 0;
772 }
773
774 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
775 {
776 u16 reg;
777
778 reg = OMAP_MMC_READ(host, SDIO);
779 reg &= ~(1 << 5);
780 OMAP_MMC_WRITE(host, SDIO, reg);
781 /* Set maximum timeout */
782 OMAP_MMC_WRITE(host, CTO, 0xff);
783 }
784
785 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
786 {
787 int timeout;
788 u16 reg;
789
790 /* Convert ns to clock cycles by assuming 20MHz frequency
791 * 1 cycle at 20MHz = 500 ns
792 */
793 timeout = req->data->timeout_clks + req->data->timeout_ns / 500;
794
795 /* Check if we need to use timeout multiplier register */
796 reg = OMAP_MMC_READ(host, SDIO);
797 if (timeout > 0xffff) {
798 reg |= (1 << 5);
799 timeout /= 1024;
800 } else
801 reg &= ~(1 << 5);
802 OMAP_MMC_WRITE(host, SDIO, reg);
803 OMAP_MMC_WRITE(host, DTO, timeout);
804 }
805
806 static void
807 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
808 {
809 struct mmc_data *data = req->data;
810 int i, use_dma, block_size;
811 unsigned sg_len;
812
813 host->data = data;
814 if (data == NULL) {
815 OMAP_MMC_WRITE(host, BLEN, 0);
816 OMAP_MMC_WRITE(host, NBLK, 0);
817 OMAP_MMC_WRITE(host, BUF, 0);
818 host->dma_in_use = 0;
819 set_cmd_timeout(host, req);
820 return;
821 }
822
823 block_size = data->blksz;
824
825 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
826 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
827 set_data_timeout(host, req);
828
829 /* cope with calling layer confusion; it issues "single
830 * block" writes using multi-block scatterlists.
831 */
832 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
833
834 /* Only do DMA for entire blocks */
835 use_dma = host->use_dma;
836 if (use_dma) {
837 for (i = 0; i < sg_len; i++) {
838 if ((data->sg[i].length % block_size) != 0) {
839 use_dma = 0;
840 break;
841 }
842 }
843 }
844
845 host->sg_idx = 0;
846 if (use_dma) {
847 if (mmc_omap_get_dma_channel(host, data) == 0) {
848 enum dma_data_direction dma_data_dir;
849
850 if (data->flags & MMC_DATA_WRITE)
851 dma_data_dir = DMA_TO_DEVICE;
852 else
853 dma_data_dir = DMA_FROM_DEVICE;
854
855 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
856 sg_len, dma_data_dir);
857 host->total_bytes_left = 0;
858 mmc_omap_prepare_dma(host, req->data);
859 host->brs_received = 0;
860 host->dma_done = 0;
861 host->dma_in_use = 1;
862 } else
863 use_dma = 0;
864 }
865
866 /* Revert to PIO? */
867 if (!use_dma) {
868 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
869 host->total_bytes_left = data->blocks * block_size;
870 host->sg_len = sg_len;
871 mmc_omap_sg_to_buf(host);
872 host->dma_in_use = 0;
873 }
874 }
875
876 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
877 {
878 struct mmc_omap_host *host = mmc_priv(mmc);
879
880 WARN_ON(host->mrq != NULL);
881
882 host->mrq = req;
883
884 /* only touch fifo AFTER the controller readies it */
885 mmc_omap_prepare_data(host, req);
886 mmc_omap_start_command(host, req->cmd);
887 if (host->dma_in_use)
888 omap_start_dma(host->dma_ch);
889 }
890
891 static void innovator_fpga_socket_power(int on)
892 {
893 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP15XX)
894 if (on) {
895 fpga_write(fpga_read(OMAP1510_FPGA_POWER) | (1 << 3),
896 OMAP1510_FPGA_POWER);
897 } else {
898 fpga_write(fpga_read(OMAP1510_FPGA_POWER) & ~(1 << 3),
899 OMAP1510_FPGA_POWER);
900 }
901 #endif
902 }
903
904 /*
905 * Turn the socket power on/off. Innovator uses FPGA, most boards
906 * probably use GPIO.
907 */
908 static void mmc_omap_power(struct mmc_omap_host *host, int on)
909 {
910 if (on) {
911 if (machine_is_omap_innovator())
912 innovator_fpga_socket_power(1);
913 else if (machine_is_omap_h2())
914 tps65010_set_gpio_out_value(GPIO3, HIGH);
915 else if (machine_is_omap_h3())
916 /* GPIO 4 of TPS65010 sends SD_EN signal */
917 tps65010_set_gpio_out_value(GPIO4, HIGH);
918 else if (cpu_is_omap24xx()) {
919 u16 reg = OMAP_MMC_READ(host, CON);
920 OMAP_MMC_WRITE(host, CON, reg | (1 << 11));
921 } else
922 if (host->power_pin >= 0)
923 omap_set_gpio_dataout(host->power_pin, 1);
924 } else {
925 if (machine_is_omap_innovator())
926 innovator_fpga_socket_power(0);
927 else if (machine_is_omap_h2())
928 tps65010_set_gpio_out_value(GPIO3, LOW);
929 else if (machine_is_omap_h3())
930 tps65010_set_gpio_out_value(GPIO4, LOW);
931 else if (cpu_is_omap24xx()) {
932 u16 reg = OMAP_MMC_READ(host, CON);
933 OMAP_MMC_WRITE(host, CON, reg & ~(1 << 11));
934 } else
935 if (host->power_pin >= 0)
936 omap_set_gpio_dataout(host->power_pin, 0);
937 }
938 }
939
940 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
941 {
942 struct mmc_omap_host *host = mmc_priv(mmc);
943 int dsor;
944 int realclock, i;
945
946 realclock = ios->clock;
947
948 if (ios->clock == 0)
949 dsor = 0;
950 else {
951 int func_clk_rate = clk_get_rate(host->fclk);
952
953 dsor = func_clk_rate / realclock;
954 if (dsor < 1)
955 dsor = 1;
956
957 if (func_clk_rate / dsor > realclock)
958 dsor++;
959
960 if (dsor > 250)
961 dsor = 250;
962 dsor++;
963
964 if (ios->bus_width == MMC_BUS_WIDTH_4)
965 dsor |= 1 << 15;
966 }
967
968 switch (ios->power_mode) {
969 case MMC_POWER_OFF:
970 mmc_omap_power(host, 0);
971 break;
972 case MMC_POWER_UP:
973 case MMC_POWER_ON:
974 mmc_omap_power(host, 1);
975 dsor |= 1 << 11;
976 break;
977 }
978
979 host->bus_mode = ios->bus_mode;
980 host->hw_bus_mode = host->bus_mode;
981
982 clk_enable(host->fclk);
983
984 /* On insanely high arm_per frequencies something sometimes
985 * goes somehow out of sync, and the POW bit is not being set,
986 * which results in the while loop below getting stuck.
987 * Writing to the CON register twice seems to do the trick. */
988 for (i = 0; i < 2; i++)
989 OMAP_MMC_WRITE(host, CON, dsor);
990 if (ios->power_mode == MMC_POWER_UP) {
991 /* Send clock cycles, poll completion */
992 OMAP_MMC_WRITE(host, IE, 0);
993 OMAP_MMC_WRITE(host, STAT, 0xffff);
994 OMAP_MMC_WRITE(host, CMD, 1 << 7);
995 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
996 OMAP_MMC_WRITE(host, STAT, 1);
997 }
998 clk_disable(host->fclk);
999 }
1000
1001 static int mmc_omap_get_ro(struct mmc_host *mmc)
1002 {
1003 struct mmc_omap_host *host = mmc_priv(mmc);
1004
1005 return host->wp_pin && omap_get_gpio_datain(host->wp_pin);
1006 }
1007
1008 static const struct mmc_host_ops mmc_omap_ops = {
1009 .request = mmc_omap_request,
1010 .set_ios = mmc_omap_set_ios,
1011 .get_ro = mmc_omap_get_ro,
1012 };
1013
1014 static int __init mmc_omap_probe(struct platform_device *pdev)
1015 {
1016 struct omap_mmc_conf *minfo = pdev->dev.platform_data;
1017 struct mmc_host *mmc;
1018 struct mmc_omap_host *host = NULL;
1019 struct resource *res;
1020 int ret = 0;
1021 int irq;
1022
1023 if (minfo == NULL) {
1024 dev_err(&pdev->dev, "platform data missing\n");
1025 return -ENXIO;
1026 }
1027
1028 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1029 irq = platform_get_irq(pdev, 0);
1030 if (res == NULL || irq < 0)
1031 return -ENXIO;
1032
1033 res = request_mem_region(res->start, res->end - res->start + 1,
1034 pdev->name);
1035 if (res == NULL)
1036 return -EBUSY;
1037
1038 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1039 if (mmc == NULL) {
1040 ret = -ENOMEM;
1041 goto err_free_mem_region;
1042 }
1043
1044 host = mmc_priv(mmc);
1045 host->mmc = mmc;
1046
1047 spin_lock_init(&host->dma_lock);
1048 init_timer(&host->dma_timer);
1049 host->dma_timer.function = mmc_omap_dma_timer;
1050 host->dma_timer.data = (unsigned long) host;
1051
1052 host->id = pdev->id;
1053 host->mem_res = res;
1054 host->irq = irq;
1055
1056 if (cpu_is_omap24xx()) {
1057 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1058 if (IS_ERR(host->iclk))
1059 goto err_free_mmc_host;
1060 clk_enable(host->iclk);
1061 }
1062
1063 if (!cpu_is_omap24xx())
1064 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1065 else
1066 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1067
1068 if (IS_ERR(host->fclk)) {
1069 ret = PTR_ERR(host->fclk);
1070 goto err_free_iclk;
1071 }
1072
1073 /* REVISIT:
1074 * Also, use minfo->cover to decide how to manage
1075 * the card detect sensing.
1076 */
1077 host->power_pin = minfo->power_pin;
1078 host->switch_pin = minfo->switch_pin;
1079 host->wp_pin = minfo->wp_pin;
1080 host->use_dma = 1;
1081 host->dma_ch = -1;
1082
1083 host->irq = irq;
1084 host->phys_base = host->mem_res->start;
1085 host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1086
1087 mmc->ops = &mmc_omap_ops;
1088 mmc->f_min = 400000;
1089 mmc->f_max = 24000000;
1090 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1091 mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1092
1093 if (minfo->wire4)
1094 mmc->caps |= MMC_CAP_4_BIT_DATA;
1095
1096 /* Use scatterlist DMA to reduce per-transfer costs.
1097 * NOTE max_seg_size assumption that small blocks aren't
1098 * normally used (except e.g. for reading SD registers).
1099 */
1100 mmc->max_phys_segs = 32;
1101 mmc->max_hw_segs = 32;
1102 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1103 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1104 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1105 mmc->max_seg_size = mmc->max_req_size;
1106
1107 if (host->power_pin >= 0) {
1108 if ((ret = omap_request_gpio(host->power_pin)) != 0) {
1109 dev_err(mmc_dev(host->mmc),
1110 "Unable to get GPIO pin for MMC power\n");
1111 goto err_free_fclk;
1112 }
1113 omap_set_gpio_direction(host->power_pin, 0);
1114 }
1115
1116 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1117 if (ret)
1118 goto err_free_power_gpio;
1119
1120 host->dev = &pdev->dev;
1121 platform_set_drvdata(pdev, host);
1122
1123 if (host->switch_pin >= 0) {
1124 INIT_WORK(&host->switch_work, mmc_omap_switch_handler);
1125 init_timer(&host->switch_timer);
1126 host->switch_timer.function = mmc_omap_switch_timer;
1127 host->switch_timer.data = (unsigned long) host;
1128 if (omap_request_gpio(host->switch_pin) != 0) {
1129 dev_warn(mmc_dev(host->mmc), "Unable to get GPIO pin for MMC cover switch\n");
1130 host->switch_pin = -1;
1131 goto no_switch;
1132 }
1133
1134 omap_set_gpio_direction(host->switch_pin, 1);
1135 ret = request_irq(OMAP_GPIO_IRQ(host->switch_pin),
1136 mmc_omap_switch_irq, IRQF_TRIGGER_RISING, DRIVER_NAME, host);
1137 if (ret) {
1138 dev_warn(mmc_dev(host->mmc), "Unable to get IRQ for MMC cover switch\n");
1139 omap_free_gpio(host->switch_pin);
1140 host->switch_pin = -1;
1141 goto no_switch;
1142 }
1143 ret = device_create_file(&pdev->dev, &dev_attr_cover_switch);
1144 if (ret == 0) {
1145 ret = device_create_file(&pdev->dev, &dev_attr_enable_poll);
1146 if (ret != 0)
1147 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1148 }
1149 if (ret) {
1150 dev_warn(mmc_dev(host->mmc), "Unable to create sysfs attributes\n");
1151 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1152 omap_free_gpio(host->switch_pin);
1153 host->switch_pin = -1;
1154 goto no_switch;
1155 }
1156 if (mmc_omap_enable_poll && mmc_omap_cover_is_open(host))
1157 schedule_work(&host->switch_work);
1158 }
1159
1160 mmc_add_host(mmc);
1161
1162 return 0;
1163
1164 no_switch:
1165 /* FIXME: Free other resources too. */
1166 if (host) {
1167 if (host->iclk && !IS_ERR(host->iclk))
1168 clk_put(host->iclk);
1169 if (host->fclk && !IS_ERR(host->fclk))
1170 clk_put(host->fclk);
1171 mmc_free_host(host->mmc);
1172 }
1173 err_free_power_gpio:
1174 if (host->power_pin >= 0)
1175 omap_free_gpio(host->power_pin);
1176 err_free_fclk:
1177 clk_put(host->fclk);
1178 err_free_iclk:
1179 if (host->iclk != NULL) {
1180 clk_disable(host->iclk);
1181 clk_put(host->iclk);
1182 }
1183 err_free_mmc_host:
1184 mmc_free_host(host->mmc);
1185 err_free_mem_region:
1186 release_mem_region(res->start, res->end - res->start + 1);
1187 return ret;
1188 }
1189
1190 static int mmc_omap_remove(struct platform_device *pdev)
1191 {
1192 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1193
1194 platform_set_drvdata(pdev, NULL);
1195
1196 BUG_ON(host == NULL);
1197
1198 mmc_remove_host(host->mmc);
1199 free_irq(host->irq, host);
1200
1201 if (host->power_pin >= 0)
1202 omap_free_gpio(host->power_pin);
1203 if (host->switch_pin >= 0) {
1204 device_remove_file(&pdev->dev, &dev_attr_enable_poll);
1205 device_remove_file(&pdev->dev, &dev_attr_cover_switch);
1206 free_irq(OMAP_GPIO_IRQ(host->switch_pin), host);
1207 omap_free_gpio(host->switch_pin);
1208 host->switch_pin = -1;
1209 del_timer_sync(&host->switch_timer);
1210 flush_scheduled_work();
1211 }
1212 if (host->iclk && !IS_ERR(host->iclk))
1213 clk_put(host->iclk);
1214 if (host->fclk && !IS_ERR(host->fclk))
1215 clk_put(host->fclk);
1216
1217 release_mem_region(pdev->resource[0].start,
1218 pdev->resource[0].end - pdev->resource[0].start + 1);
1219
1220 mmc_free_host(host->mmc);
1221
1222 return 0;
1223 }
1224
1225 #ifdef CONFIG_PM
1226 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1227 {
1228 int ret = 0;
1229 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1230
1231 if (host && host->suspended)
1232 return 0;
1233
1234 if (host) {
1235 ret = mmc_suspend_host(host->mmc, mesg);
1236 if (ret == 0)
1237 host->suspended = 1;
1238 }
1239 return ret;
1240 }
1241
1242 static int mmc_omap_resume(struct platform_device *pdev)
1243 {
1244 int ret = 0;
1245 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1246
1247 if (host && !host->suspended)
1248 return 0;
1249
1250 if (host) {
1251 ret = mmc_resume_host(host->mmc);
1252 if (ret == 0)
1253 host->suspended = 0;
1254 }
1255
1256 return ret;
1257 }
1258 #else
1259 #define mmc_omap_suspend NULL
1260 #define mmc_omap_resume NULL
1261 #endif
1262
1263 static struct platform_driver mmc_omap_driver = {
1264 .probe = mmc_omap_probe,
1265 .remove = mmc_omap_remove,
1266 .suspend = mmc_omap_suspend,
1267 .resume = mmc_omap_resume,
1268 .driver = {
1269 .name = DRIVER_NAME,
1270 },
1271 };
1272
1273 static int __init mmc_omap_init(void)
1274 {
1275 return platform_driver_register(&mmc_omap_driver);
1276 }
1277
1278 static void __exit mmc_omap_exit(void)
1279 {
1280 platform_driver_unregister(&mmc_omap_driver);
1281 }
1282
1283 module_init(mmc_omap_init);
1284 module_exit(mmc_omap_exit);
1285
1286 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1287 MODULE_LICENSE("GPL");
1288 MODULE_ALIAS(DRIVER_NAME);
1289 MODULE_AUTHOR("Juha Yrjölä");
kernel source for telekom puls (alcatel/mediatek)