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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
21
22 #include <linux/leds.h>
23
24 #include <linux/mmc/host.h>
25
26 #include "sdhci.h"
27
28 #define DRIVER_NAME "sdhci"
29
30 #define DBG(f, x...) \
31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
32
33 static unsigned int debug_quirks = 0;
34
35 /*
36 * Different quirks to handle when the hardware deviates from a strict
37 * interpretation of the SDHCI specification.
38 */
39
40 /* Controller doesn't honor resets unless we touch the clock register */
41 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
42 /* Controller has bad caps bits, but really supports DMA */
43 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
44 /* Controller doesn't like to be reset when there is no card inserted. */
45 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
46 /* Controller doesn't like clearing the power reg before a change */
47 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
48 /* Controller has flaky internal state so reset it on each ios change */
49 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
50 /* Controller has an unusable DMA engine */
51 #define SDHCI_QUIRK_BROKEN_DMA (1<<5)
52 /* Controller can only DMA from 32-bit aligned addresses */
53 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<6)
54 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
55 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7)
56 /* Controller needs to be reset after each request to stay stable */
57 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<8)
58
59 static const struct pci_device_id pci_ids[] __devinitdata = {
60 {
61 .vendor = PCI_VENDOR_ID_RICOH,
62 .device = PCI_DEVICE_ID_RICOH_R5C822,
63 .subvendor = PCI_VENDOR_ID_IBM,
64 .subdevice = PCI_ANY_ID,
65 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
66 SDHCI_QUIRK_FORCE_DMA,
67 },
68
69 {
70 .vendor = PCI_VENDOR_ID_RICOH,
71 .device = PCI_DEVICE_ID_RICOH_R5C822,
72 .subvendor = PCI_VENDOR_ID_SAMSUNG,
73 .subdevice = PCI_ANY_ID,
74 .driver_data = SDHCI_QUIRK_FORCE_DMA |
75 SDHCI_QUIRK_NO_CARD_NO_RESET,
76 },
77
78 {
79 .vendor = PCI_VENDOR_ID_RICOH,
80 .device = PCI_DEVICE_ID_RICOH_R5C822,
81 .subvendor = PCI_ANY_ID,
82 .subdevice = PCI_ANY_ID,
83 .driver_data = SDHCI_QUIRK_FORCE_DMA,
84 },
85
86 {
87 .vendor = PCI_VENDOR_ID_TI,
88 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
89 .subvendor = PCI_ANY_ID,
90 .subdevice = PCI_ANY_ID,
91 .driver_data = SDHCI_QUIRK_FORCE_DMA,
92 },
93
94 {
95 .vendor = PCI_VENDOR_ID_ENE,
96 .device = PCI_DEVICE_ID_ENE_CB712_SD,
97 .subvendor = PCI_ANY_ID,
98 .subdevice = PCI_ANY_ID,
99 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
100 SDHCI_QUIRK_BROKEN_DMA,
101 },
102
103 {
104 .vendor = PCI_VENDOR_ID_ENE,
105 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
106 .subvendor = PCI_ANY_ID,
107 .subdevice = PCI_ANY_ID,
108 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
109 SDHCI_QUIRK_BROKEN_DMA,
110 },
111
112 {
113 .vendor = PCI_VENDOR_ID_ENE,
114 .device = PCI_DEVICE_ID_ENE_CB714_SD,
115 .subvendor = PCI_ANY_ID,
116 .subdevice = PCI_ANY_ID,
117 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
118 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
119 },
120
121 {
122 .vendor = PCI_VENDOR_ID_ENE,
123 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
124 .subvendor = PCI_ANY_ID,
125 .subdevice = PCI_ANY_ID,
126 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
127 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
128 },
129
130 {
131 .vendor = PCI_VENDOR_ID_JMICRON,
132 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
133 .subvendor = PCI_ANY_ID,
134 .subdevice = PCI_ANY_ID,
135 .driver_data = SDHCI_QUIRK_32BIT_DMA_ADDR |
136 SDHCI_QUIRK_32BIT_DMA_SIZE |
137 SDHCI_QUIRK_RESET_AFTER_REQUEST,
138 },
139
140 { /* Generic SD host controller */
141 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
142 },
143
144 { /* end: all zeroes */ },
145 };
146
147 MODULE_DEVICE_TABLE(pci, pci_ids);
148
149 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
150 static void sdhci_finish_data(struct sdhci_host *);
151
152 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
153 static void sdhci_finish_command(struct sdhci_host *);
154
155 static void sdhci_dumpregs(struct sdhci_host *host)
156 {
157 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
158
159 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
160 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
161 readw(host->ioaddr + SDHCI_HOST_VERSION));
162 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
163 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
164 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
165 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
166 readl(host->ioaddr + SDHCI_ARGUMENT),
167 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
168 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
169 readl(host->ioaddr + SDHCI_PRESENT_STATE),
170 readb(host->ioaddr + SDHCI_HOST_CONTROL));
171 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
172 readb(host->ioaddr + SDHCI_POWER_CONTROL),
173 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
174 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
175 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
176 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
177 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
178 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
179 readl(host->ioaddr + SDHCI_INT_STATUS));
180 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
181 readl(host->ioaddr + SDHCI_INT_ENABLE),
182 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
183 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
184 readw(host->ioaddr + SDHCI_ACMD12_ERR),
185 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
186 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
187 readl(host->ioaddr + SDHCI_CAPABILITIES),
188 readl(host->ioaddr + SDHCI_MAX_CURRENT));
189
190 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
191 }
192
193 /*****************************************************************************\
194 * *
195 * Low level functions *
196 * *
197 \*****************************************************************************/
198
199 static void sdhci_reset(struct sdhci_host *host, u8 mask)
200 {
201 unsigned long timeout;
202
203 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
204 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
205 SDHCI_CARD_PRESENT))
206 return;
207 }
208
209 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
210
211 if (mask & SDHCI_RESET_ALL)
212 host->clock = 0;
213
214 /* Wait max 100 ms */
215 timeout = 100;
216
217 /* hw clears the bit when it's done */
218 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
219 if (timeout == 0) {
220 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
221 mmc_hostname(host->mmc), (int)mask);
222 sdhci_dumpregs(host);
223 return;
224 }
225 timeout--;
226 mdelay(1);
227 }
228 }
229
230 static void sdhci_init(struct sdhci_host *host)
231 {
232 u32 intmask;
233
234 sdhci_reset(host, SDHCI_RESET_ALL);
235
236 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
237 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
238 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
239 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
240 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
241 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
242
243 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
244 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
245 }
246
247 static void sdhci_activate_led(struct sdhci_host *host)
248 {
249 u8 ctrl;
250
251 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
252 ctrl |= SDHCI_CTRL_LED;
253 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
254 }
255
256 static void sdhci_deactivate_led(struct sdhci_host *host)
257 {
258 u8 ctrl;
259
260 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
261 ctrl &= ~SDHCI_CTRL_LED;
262 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
263 }
264
265 #ifdef CONFIG_LEDS_CLASS
266 static void sdhci_led_control(struct led_classdev *led,
267 enum led_brightness brightness)
268 {
269 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
270 unsigned long flags;
271
272 spin_lock_irqsave(&host->lock, flags);
273
274 if (brightness == LED_OFF)
275 sdhci_deactivate_led(host);
276 else
277 sdhci_activate_led(host);
278
279 spin_unlock_irqrestore(&host->lock, flags);
280 }
281 #endif
282
283 /*****************************************************************************\
284 * *
285 * Core functions *
286 * *
287 \*****************************************************************************/
288
289 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
290 {
291 return sg_virt(host->cur_sg);
292 }
293
294 static inline int sdhci_next_sg(struct sdhci_host* host)
295 {
296 /*
297 * Skip to next SG entry.
298 */
299 host->cur_sg++;
300 host->num_sg--;
301
302 /*
303 * Any entries left?
304 */
305 if (host->num_sg > 0) {
306 host->offset = 0;
307 host->remain = host->cur_sg->length;
308 }
309
310 return host->num_sg;
311 }
312
313 static void sdhci_read_block_pio(struct sdhci_host *host)
314 {
315 int blksize, chunk_remain;
316 u32 data;
317 char *buffer;
318 int size;
319
320 DBG("PIO reading\n");
321
322 blksize = host->data->blksz;
323 chunk_remain = 0;
324 data = 0;
325
326 buffer = sdhci_sg_to_buffer(host) + host->offset;
327
328 while (blksize) {
329 if (chunk_remain == 0) {
330 data = readl(host->ioaddr + SDHCI_BUFFER);
331 chunk_remain = min(blksize, 4);
332 }
333
334 size = min(host->remain, chunk_remain);
335
336 chunk_remain -= size;
337 blksize -= size;
338 host->offset += size;
339 host->remain -= size;
340
341 while (size) {
342 *buffer = data & 0xFF;
343 buffer++;
344 data >>= 8;
345 size--;
346 }
347
348 if (host->remain == 0) {
349 if (sdhci_next_sg(host) == 0) {
350 BUG_ON(blksize != 0);
351 return;
352 }
353 buffer = sdhci_sg_to_buffer(host);
354 }
355 }
356 }
357
358 static void sdhci_write_block_pio(struct sdhci_host *host)
359 {
360 int blksize, chunk_remain;
361 u32 data;
362 char *buffer;
363 int bytes, size;
364
365 DBG("PIO writing\n");
366
367 blksize = host->data->blksz;
368 chunk_remain = 4;
369 data = 0;
370
371 bytes = 0;
372 buffer = sdhci_sg_to_buffer(host) + host->offset;
373
374 while (blksize) {
375 size = min(host->remain, chunk_remain);
376
377 chunk_remain -= size;
378 blksize -= size;
379 host->offset += size;
380 host->remain -= size;
381
382 while (size) {
383 data >>= 8;
384 data |= (u32)*buffer << 24;
385 buffer++;
386 size--;
387 }
388
389 if (chunk_remain == 0) {
390 writel(data, host->ioaddr + SDHCI_BUFFER);
391 chunk_remain = min(blksize, 4);
392 }
393
394 if (host->remain == 0) {
395 if (sdhci_next_sg(host) == 0) {
396 BUG_ON(blksize != 0);
397 return;
398 }
399 buffer = sdhci_sg_to_buffer(host);
400 }
401 }
402 }
403
404 static void sdhci_transfer_pio(struct sdhci_host *host)
405 {
406 u32 mask;
407
408 BUG_ON(!host->data);
409
410 if (host->num_sg == 0)
411 return;
412
413 if (host->data->flags & MMC_DATA_READ)
414 mask = SDHCI_DATA_AVAILABLE;
415 else
416 mask = SDHCI_SPACE_AVAILABLE;
417
418 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
419 if (host->data->flags & MMC_DATA_READ)
420 sdhci_read_block_pio(host);
421 else
422 sdhci_write_block_pio(host);
423
424 if (host->num_sg == 0)
425 break;
426 }
427
428 DBG("PIO transfer complete.\n");
429 }
430
431 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
432 {
433 u8 count;
434 unsigned target_timeout, current_timeout;
435
436 WARN_ON(host->data);
437
438 if (data == NULL)
439 return;
440
441 /* Sanity checks */
442 BUG_ON(data->blksz * data->blocks > 524288);
443 BUG_ON(data->blksz > host->mmc->max_blk_size);
444 BUG_ON(data->blocks > 65535);
445
446 host->data = data;
447 host->data_early = 0;
448
449 /* timeout in us */
450 target_timeout = data->timeout_ns / 1000 +
451 data->timeout_clks / host->clock;
452
453 /*
454 * Figure out needed cycles.
455 * We do this in steps in order to fit inside a 32 bit int.
456 * The first step is the minimum timeout, which will have a
457 * minimum resolution of 6 bits:
458 * (1) 2^13*1000 > 2^22,
459 * (2) host->timeout_clk < 2^16
460 * =>
461 * (1) / (2) > 2^6
462 */
463 count = 0;
464 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
465 while (current_timeout < target_timeout) {
466 count++;
467 current_timeout <<= 1;
468 if (count >= 0xF)
469 break;
470 }
471
472 if (count >= 0xF) {
473 printk(KERN_WARNING "%s: Too large timeout requested!\n",
474 mmc_hostname(host->mmc));
475 count = 0xE;
476 }
477
478 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
479
480 if (host->flags & SDHCI_USE_DMA)
481 host->flags |= SDHCI_REQ_USE_DMA;
482
483 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
484 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
485 ((data->blksz * data->blocks) & 0x3))) {
486 DBG("Reverting to PIO because of transfer size (%d)\n",
487 data->blksz * data->blocks);
488 host->flags &= ~SDHCI_REQ_USE_DMA;
489 }
490
491 /*
492 * The assumption here being that alignment is the same after
493 * translation to device address space.
494 */
495 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
496 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
497 (data->sg->offset & 0x3))) {
498 DBG("Reverting to PIO because of bad alignment\n");
499 host->flags &= ~SDHCI_REQ_USE_DMA;
500 }
501
502 if (host->flags & SDHCI_REQ_USE_DMA) {
503 int count;
504
505 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
506 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
507 BUG_ON(count != 1);
508
509 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
510 } else {
511 host->cur_sg = data->sg;
512 host->num_sg = data->sg_len;
513
514 host->offset = 0;
515 host->remain = host->cur_sg->length;
516 }
517
518 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
519 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
520 host->ioaddr + SDHCI_BLOCK_SIZE);
521 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
522 }
523
524 static void sdhci_set_transfer_mode(struct sdhci_host *host,
525 struct mmc_data *data)
526 {
527 u16 mode;
528
529 if (data == NULL)
530 return;
531
532 WARN_ON(!host->data);
533
534 mode = SDHCI_TRNS_BLK_CNT_EN;
535 if (data->blocks > 1)
536 mode |= SDHCI_TRNS_MULTI;
537 if (data->flags & MMC_DATA_READ)
538 mode |= SDHCI_TRNS_READ;
539 if (host->flags & SDHCI_REQ_USE_DMA)
540 mode |= SDHCI_TRNS_DMA;
541
542 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
543 }
544
545 static void sdhci_finish_data(struct sdhci_host *host)
546 {
547 struct mmc_data *data;
548 u16 blocks;
549
550 BUG_ON(!host->data);
551
552 data = host->data;
553 host->data = NULL;
554
555 if (host->flags & SDHCI_REQ_USE_DMA) {
556 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
557 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
558 }
559
560 /*
561 * Controller doesn't count down when in single block mode.
562 */
563 if (data->blocks == 1)
564 blocks = (data->error == 0) ? 0 : 1;
565 else
566 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
567 data->bytes_xfered = data->blksz * (data->blocks - blocks);
568
569 if (!data->error && blocks) {
570 printk(KERN_ERR "%s: Controller signalled completion even "
571 "though there were blocks left.\n",
572 mmc_hostname(host->mmc));
573 data->error = -EIO;
574 }
575
576 if (data->stop) {
577 /*
578 * The controller needs a reset of internal state machines
579 * upon error conditions.
580 */
581 if (data->error) {
582 sdhci_reset(host, SDHCI_RESET_CMD);
583 sdhci_reset(host, SDHCI_RESET_DATA);
584 }
585
586 sdhci_send_command(host, data->stop);
587 } else
588 tasklet_schedule(&host->finish_tasklet);
589 }
590
591 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
592 {
593 int flags;
594 u32 mask;
595 unsigned long timeout;
596
597 WARN_ON(host->cmd);
598
599 /* Wait max 10 ms */
600 timeout = 10;
601
602 mask = SDHCI_CMD_INHIBIT;
603 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
604 mask |= SDHCI_DATA_INHIBIT;
605
606 /* We shouldn't wait for data inihibit for stop commands, even
607 though they might use busy signaling */
608 if (host->mrq->data && (cmd == host->mrq->data->stop))
609 mask &= ~SDHCI_DATA_INHIBIT;
610
611 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
612 if (timeout == 0) {
613 printk(KERN_ERR "%s: Controller never released "
614 "inhibit bit(s).\n", mmc_hostname(host->mmc));
615 sdhci_dumpregs(host);
616 cmd->error = -EIO;
617 tasklet_schedule(&host->finish_tasklet);
618 return;
619 }
620 timeout--;
621 mdelay(1);
622 }
623
624 mod_timer(&host->timer, jiffies + 10 * HZ);
625
626 host->cmd = cmd;
627
628 sdhci_prepare_data(host, cmd->data);
629
630 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
631
632 sdhci_set_transfer_mode(host, cmd->data);
633
634 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
635 printk(KERN_ERR "%s: Unsupported response type!\n",
636 mmc_hostname(host->mmc));
637 cmd->error = -EINVAL;
638 tasklet_schedule(&host->finish_tasklet);
639 return;
640 }
641
642 if (!(cmd->flags & MMC_RSP_PRESENT))
643 flags = SDHCI_CMD_RESP_NONE;
644 else if (cmd->flags & MMC_RSP_136)
645 flags = SDHCI_CMD_RESP_LONG;
646 else if (cmd->flags & MMC_RSP_BUSY)
647 flags = SDHCI_CMD_RESP_SHORT_BUSY;
648 else
649 flags = SDHCI_CMD_RESP_SHORT;
650
651 if (cmd->flags & MMC_RSP_CRC)
652 flags |= SDHCI_CMD_CRC;
653 if (cmd->flags & MMC_RSP_OPCODE)
654 flags |= SDHCI_CMD_INDEX;
655 if (cmd->data)
656 flags |= SDHCI_CMD_DATA;
657
658 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
659 host->ioaddr + SDHCI_COMMAND);
660 }
661
662 static void sdhci_finish_command(struct sdhci_host *host)
663 {
664 int i;
665
666 BUG_ON(host->cmd == NULL);
667
668 if (host->cmd->flags & MMC_RSP_PRESENT) {
669 if (host->cmd->flags & MMC_RSP_136) {
670 /* CRC is stripped so we need to do some shifting. */
671 for (i = 0;i < 4;i++) {
672 host->cmd->resp[i] = readl(host->ioaddr +
673 SDHCI_RESPONSE + (3-i)*4) << 8;
674 if (i != 3)
675 host->cmd->resp[i] |=
676 readb(host->ioaddr +
677 SDHCI_RESPONSE + (3-i)*4-1);
678 }
679 } else {
680 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
681 }
682 }
683
684 host->cmd->error = 0;
685
686 if (host->data && host->data_early)
687 sdhci_finish_data(host);
688
689 if (!host->cmd->data)
690 tasklet_schedule(&host->finish_tasklet);
691
692 host->cmd = NULL;
693 }
694
695 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
696 {
697 int div;
698 u16 clk;
699 unsigned long timeout;
700
701 if (clock == host->clock)
702 return;
703
704 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
705
706 if (clock == 0)
707 goto out;
708
709 for (div = 1;div < 256;div *= 2) {
710 if ((host->max_clk / div) <= clock)
711 break;
712 }
713 div >>= 1;
714
715 clk = div << SDHCI_DIVIDER_SHIFT;
716 clk |= SDHCI_CLOCK_INT_EN;
717 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
718
719 /* Wait max 10 ms */
720 timeout = 10;
721 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
722 & SDHCI_CLOCK_INT_STABLE)) {
723 if (timeout == 0) {
724 printk(KERN_ERR "%s: Internal clock never "
725 "stabilised.\n", mmc_hostname(host->mmc));
726 sdhci_dumpregs(host);
727 return;
728 }
729 timeout--;
730 mdelay(1);
731 }
732
733 clk |= SDHCI_CLOCK_CARD_EN;
734 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
735
736 out:
737 host->clock = clock;
738 }
739
740 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
741 {
742 u8 pwr;
743
744 if (host->power == power)
745 return;
746
747 if (power == (unsigned short)-1) {
748 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
749 goto out;
750 }
751
752 /*
753 * Spec says that we should clear the power reg before setting
754 * a new value. Some controllers don't seem to like this though.
755 */
756 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
757 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
758
759 pwr = SDHCI_POWER_ON;
760
761 switch (1 << power) {
762 case MMC_VDD_165_195:
763 pwr |= SDHCI_POWER_180;
764 break;
765 case MMC_VDD_29_30:
766 case MMC_VDD_30_31:
767 pwr |= SDHCI_POWER_300;
768 break;
769 case MMC_VDD_32_33:
770 case MMC_VDD_33_34:
771 pwr |= SDHCI_POWER_330;
772 break;
773 default:
774 BUG();
775 }
776
777 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
778
779 out:
780 host->power = power;
781 }
782
783 /*****************************************************************************\
784 * *
785 * MMC callbacks *
786 * *
787 \*****************************************************************************/
788
789 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
790 {
791 struct sdhci_host *host;
792 unsigned long flags;
793
794 host = mmc_priv(mmc);
795
796 spin_lock_irqsave(&host->lock, flags);
797
798 WARN_ON(host->mrq != NULL);
799
800 #ifndef CONFIG_LEDS_CLASS
801 sdhci_activate_led(host);
802 #endif
803
804 host->mrq = mrq;
805
806 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
807 host->mrq->cmd->error = -ENOMEDIUM;
808 tasklet_schedule(&host->finish_tasklet);
809 } else
810 sdhci_send_command(host, mrq->cmd);
811
812 mmiowb();
813 spin_unlock_irqrestore(&host->lock, flags);
814 }
815
816 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
817 {
818 struct sdhci_host *host;
819 unsigned long flags;
820 u8 ctrl;
821
822 host = mmc_priv(mmc);
823
824 spin_lock_irqsave(&host->lock, flags);
825
826 /*
827 * Reset the chip on each power off.
828 * Should clear out any weird states.
829 */
830 if (ios->power_mode == MMC_POWER_OFF) {
831 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
832 sdhci_init(host);
833 }
834
835 sdhci_set_clock(host, ios->clock);
836
837 if (ios->power_mode == MMC_POWER_OFF)
838 sdhci_set_power(host, -1);
839 else
840 sdhci_set_power(host, ios->vdd);
841
842 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
843
844 if (ios->bus_width == MMC_BUS_WIDTH_4)
845 ctrl |= SDHCI_CTRL_4BITBUS;
846 else
847 ctrl &= ~SDHCI_CTRL_4BITBUS;
848
849 if (ios->timing == MMC_TIMING_SD_HS)
850 ctrl |= SDHCI_CTRL_HISPD;
851 else
852 ctrl &= ~SDHCI_CTRL_HISPD;
853
854 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
855
856 /*
857 * Some (ENE) controllers go apeshit on some ios operation,
858 * signalling timeout and CRC errors even on CMD0. Resetting
859 * it on each ios seems to solve the problem.
860 */
861 if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
862 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
863
864 mmiowb();
865 spin_unlock_irqrestore(&host->lock, flags);
866 }
867
868 static int sdhci_get_ro(struct mmc_host *mmc)
869 {
870 struct sdhci_host *host;
871 unsigned long flags;
872 int present;
873
874 host = mmc_priv(mmc);
875
876 spin_lock_irqsave(&host->lock, flags);
877
878 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
879
880 spin_unlock_irqrestore(&host->lock, flags);
881
882 return !(present & SDHCI_WRITE_PROTECT);
883 }
884
885 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
886 {
887 struct sdhci_host *host;
888 unsigned long flags;
889 u32 ier;
890
891 host = mmc_priv(mmc);
892
893 spin_lock_irqsave(&host->lock, flags);
894
895 ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
896
897 ier &= ~SDHCI_INT_CARD_INT;
898 if (enable)
899 ier |= SDHCI_INT_CARD_INT;
900
901 writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
902 writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
903
904 mmiowb();
905
906 spin_unlock_irqrestore(&host->lock, flags);
907 }
908
909 static const struct mmc_host_ops sdhci_ops = {
910 .request = sdhci_request,
911 .set_ios = sdhci_set_ios,
912 .get_ro = sdhci_get_ro,
913 .enable_sdio_irq = sdhci_enable_sdio_irq,
914 };
915
916 /*****************************************************************************\
917 * *
918 * Tasklets *
919 * *
920 \*****************************************************************************/
921
922 static void sdhci_tasklet_card(unsigned long param)
923 {
924 struct sdhci_host *host;
925 unsigned long flags;
926
927 host = (struct sdhci_host*)param;
928
929 spin_lock_irqsave(&host->lock, flags);
930
931 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
932 if (host->mrq) {
933 printk(KERN_ERR "%s: Card removed during transfer!\n",
934 mmc_hostname(host->mmc));
935 printk(KERN_ERR "%s: Resetting controller.\n",
936 mmc_hostname(host->mmc));
937
938 sdhci_reset(host, SDHCI_RESET_CMD);
939 sdhci_reset(host, SDHCI_RESET_DATA);
940
941 host->mrq->cmd->error = -ENOMEDIUM;
942 tasklet_schedule(&host->finish_tasklet);
943 }
944 }
945
946 spin_unlock_irqrestore(&host->lock, flags);
947
948 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
949 }
950
951 static void sdhci_tasklet_finish(unsigned long param)
952 {
953 struct sdhci_host *host;
954 unsigned long flags;
955 struct mmc_request *mrq;
956
957 host = (struct sdhci_host*)param;
958
959 spin_lock_irqsave(&host->lock, flags);
960
961 del_timer(&host->timer);
962
963 mrq = host->mrq;
964
965 /*
966 * The controller needs a reset of internal state machines
967 * upon error conditions.
968 */
969 if (mrq->cmd->error ||
970 (mrq->data && (mrq->data->error ||
971 (mrq->data->stop && mrq->data->stop->error))) ||
972 (host->chip->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
973
974 /* Some controllers need this kick or reset won't work here */
975 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
976 unsigned int clock;
977
978 /* This is to force an update */
979 clock = host->clock;
980 host->clock = 0;
981 sdhci_set_clock(host, clock);
982 }
983
984 /* Spec says we should do both at the same time, but Ricoh
985 controllers do not like that. */
986 sdhci_reset(host, SDHCI_RESET_CMD);
987 sdhci_reset(host, SDHCI_RESET_DATA);
988 }
989
990 host->mrq = NULL;
991 host->cmd = NULL;
992 host->data = NULL;
993
994 #ifndef CONFIG_LEDS_CLASS
995 sdhci_deactivate_led(host);
996 #endif
997
998 mmiowb();
999 spin_unlock_irqrestore(&host->lock, flags);
1000
1001 mmc_request_done(host->mmc, mrq);
1002 }
1003
1004 static void sdhci_timeout_timer(unsigned long data)
1005 {
1006 struct sdhci_host *host;
1007 unsigned long flags;
1008
1009 host = (struct sdhci_host*)data;
1010
1011 spin_lock_irqsave(&host->lock, flags);
1012
1013 if (host->mrq) {
1014 printk(KERN_ERR "%s: Timeout waiting for hardware "
1015 "interrupt.\n", mmc_hostname(host->mmc));
1016 sdhci_dumpregs(host);
1017
1018 if (host->data) {
1019 host->data->error = -ETIMEDOUT;
1020 sdhci_finish_data(host);
1021 } else {
1022 if (host->cmd)
1023 host->cmd->error = -ETIMEDOUT;
1024 else
1025 host->mrq->cmd->error = -ETIMEDOUT;
1026
1027 tasklet_schedule(&host->finish_tasklet);
1028 }
1029 }
1030
1031 mmiowb();
1032 spin_unlock_irqrestore(&host->lock, flags);
1033 }
1034
1035 /*****************************************************************************\
1036 * *
1037 * Interrupt handling *
1038 * *
1039 \*****************************************************************************/
1040
1041 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1042 {
1043 BUG_ON(intmask == 0);
1044
1045 if (!host->cmd) {
1046 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1047 "though no command operation was in progress.\n",
1048 mmc_hostname(host->mmc), (unsigned)intmask);
1049 sdhci_dumpregs(host);
1050 return;
1051 }
1052
1053 if (intmask & SDHCI_INT_TIMEOUT)
1054 host->cmd->error = -ETIMEDOUT;
1055 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1056 SDHCI_INT_INDEX))
1057 host->cmd->error = -EILSEQ;
1058
1059 if (host->cmd->error)
1060 tasklet_schedule(&host->finish_tasklet);
1061 else if (intmask & SDHCI_INT_RESPONSE)
1062 sdhci_finish_command(host);
1063 }
1064
1065 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1066 {
1067 BUG_ON(intmask == 0);
1068
1069 if (!host->data) {
1070 /*
1071 * A data end interrupt is sent together with the response
1072 * for the stop command.
1073 */
1074 if (intmask & SDHCI_INT_DATA_END)
1075 return;
1076
1077 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1078 "though no data operation was in progress.\n",
1079 mmc_hostname(host->mmc), (unsigned)intmask);
1080 sdhci_dumpregs(host);
1081
1082 return;
1083 }
1084
1085 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1086 host->data->error = -ETIMEDOUT;
1087 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1088 host->data->error = -EILSEQ;
1089
1090 if (host->data->error)
1091 sdhci_finish_data(host);
1092 else {
1093 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1094 sdhci_transfer_pio(host);
1095
1096 /*
1097 * We currently don't do anything fancy with DMA
1098 * boundaries, but as we can't disable the feature
1099 * we need to at least restart the transfer.
1100 */
1101 if (intmask & SDHCI_INT_DMA_END)
1102 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1103 host->ioaddr + SDHCI_DMA_ADDRESS);
1104
1105 if (intmask & SDHCI_INT_DATA_END) {
1106 if (host->cmd) {
1107 /*
1108 * Data managed to finish before the
1109 * command completed. Make sure we do
1110 * things in the proper order.
1111 */
1112 host->data_early = 1;
1113 } else {
1114 sdhci_finish_data(host);
1115 }
1116 }
1117 }
1118 }
1119
1120 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1121 {
1122 irqreturn_t result;
1123 struct sdhci_host* host = dev_id;
1124 u32 intmask;
1125 int cardint = 0;
1126
1127 spin_lock(&host->lock);
1128
1129 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1130
1131 if (!intmask || intmask == 0xffffffff) {
1132 result = IRQ_NONE;
1133 goto out;
1134 }
1135
1136 DBG("*** %s got interrupt: 0x%08x\n",
1137 mmc_hostname(host->mmc), intmask);
1138
1139 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1140 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1141 host->ioaddr + SDHCI_INT_STATUS);
1142 tasklet_schedule(&host->card_tasklet);
1143 }
1144
1145 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1146
1147 if (intmask & SDHCI_INT_CMD_MASK) {
1148 writel(intmask & SDHCI_INT_CMD_MASK,
1149 host->ioaddr + SDHCI_INT_STATUS);
1150 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1151 }
1152
1153 if (intmask & SDHCI_INT_DATA_MASK) {
1154 writel(intmask & SDHCI_INT_DATA_MASK,
1155 host->ioaddr + SDHCI_INT_STATUS);
1156 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1157 }
1158
1159 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1160
1161 intmask &= ~SDHCI_INT_ERROR;
1162
1163 if (intmask & SDHCI_INT_BUS_POWER) {
1164 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1165 mmc_hostname(host->mmc));
1166 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1167 }
1168
1169 intmask &= ~SDHCI_INT_BUS_POWER;
1170
1171 if (intmask & SDHCI_INT_CARD_INT)
1172 cardint = 1;
1173
1174 intmask &= ~SDHCI_INT_CARD_INT;
1175
1176 if (intmask) {
1177 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1178 mmc_hostname(host->mmc), intmask);
1179 sdhci_dumpregs(host);
1180
1181 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1182 }
1183
1184 result = IRQ_HANDLED;
1185
1186 mmiowb();
1187 out:
1188 spin_unlock(&host->lock);
1189
1190 /*
1191 * We have to delay this as it calls back into the driver.
1192 */
1193 if (cardint)
1194 mmc_signal_sdio_irq(host->mmc);
1195
1196 return result;
1197 }
1198
1199 /*****************************************************************************\
1200 * *
1201 * Suspend/resume *
1202 * *
1203 \*****************************************************************************/
1204
1205 #ifdef CONFIG_PM
1206
1207 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1208 {
1209 struct sdhci_chip *chip;
1210 int i, ret;
1211
1212 chip = pci_get_drvdata(pdev);
1213 if (!chip)
1214 return 0;
1215
1216 DBG("Suspending...\n");
1217
1218 for (i = 0;i < chip->num_slots;i++) {
1219 if (!chip->hosts[i])
1220 continue;
1221 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1222 if (ret) {
1223 for (i--;i >= 0;i--)
1224 mmc_resume_host(chip->hosts[i]->mmc);
1225 return ret;
1226 }
1227 }
1228
1229 pci_save_state(pdev);
1230 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1231
1232 for (i = 0;i < chip->num_slots;i++) {
1233 if (!chip->hosts[i])
1234 continue;
1235 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1236 }
1237
1238 pci_disable_device(pdev);
1239 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1240
1241 return 0;
1242 }
1243
1244 static int sdhci_resume (struct pci_dev *pdev)
1245 {
1246 struct sdhci_chip *chip;
1247 int i, ret;
1248
1249 chip = pci_get_drvdata(pdev);
1250 if (!chip)
1251 return 0;
1252
1253 DBG("Resuming...\n");
1254
1255 pci_set_power_state(pdev, PCI_D0);
1256 pci_restore_state(pdev);
1257 ret = pci_enable_device(pdev);
1258 if (ret)
1259 return ret;
1260
1261 for (i = 0;i < chip->num_slots;i++) {
1262 if (!chip->hosts[i])
1263 continue;
1264 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1265 pci_set_master(pdev);
1266 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1267 IRQF_SHARED, mmc_hostname(chip->hosts[i]->mmc),
1268 chip->hosts[i]);
1269 if (ret)
1270 return ret;
1271 sdhci_init(chip->hosts[i]);
1272 mmiowb();
1273 ret = mmc_resume_host(chip->hosts[i]->mmc);
1274 if (ret)
1275 return ret;
1276 }
1277
1278 return 0;
1279 }
1280
1281 #else /* CONFIG_PM */
1282
1283 #define sdhci_suspend NULL
1284 #define sdhci_resume NULL
1285
1286 #endif /* CONFIG_PM */
1287
1288 /*****************************************************************************\
1289 * *
1290 * Device probing/removal *
1291 * *
1292 \*****************************************************************************/
1293
1294 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1295 {
1296 int ret;
1297 unsigned int version;
1298 struct sdhci_chip *chip;
1299 struct mmc_host *mmc;
1300 struct sdhci_host *host;
1301
1302 u8 first_bar;
1303 unsigned int caps;
1304
1305 chip = pci_get_drvdata(pdev);
1306 BUG_ON(!chip);
1307
1308 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1309 if (ret)
1310 return ret;
1311
1312 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1313
1314 if (first_bar > 5) {
1315 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1316 return -ENODEV;
1317 }
1318
1319 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1320 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1321 return -ENODEV;
1322 }
1323
1324 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1325 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1326 "You may experience problems.\n");
1327 }
1328
1329 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1330 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1331 return -ENODEV;
1332 }
1333
1334 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1335 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1336 return -ENODEV;
1337 }
1338
1339 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1340 if (!mmc)
1341 return -ENOMEM;
1342
1343 host = mmc_priv(mmc);
1344 host->mmc = mmc;
1345
1346 host->chip = chip;
1347 chip->hosts[slot] = host;
1348
1349 host->bar = first_bar + slot;
1350
1351 host->addr = pci_resource_start(pdev, host->bar);
1352 host->irq = pdev->irq;
1353
1354 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1355
1356 ret = pci_request_region(pdev, host->bar, mmc_hostname(mmc));
1357 if (ret)
1358 goto free;
1359
1360 host->ioaddr = ioremap_nocache(host->addr,
1361 pci_resource_len(pdev, host->bar));
1362 if (!host->ioaddr) {
1363 ret = -ENOMEM;
1364 goto release;
1365 }
1366
1367 sdhci_reset(host, SDHCI_RESET_ALL);
1368
1369 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1370 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1371 if (version > 1) {
1372 printk(KERN_ERR "%s: Unknown controller version (%d). "
1373 "You may experience problems.\n", mmc_hostname(mmc),
1374 version);
1375 }
1376
1377 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1378
1379 if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1380 host->flags |= SDHCI_USE_DMA;
1381 else if (!(caps & SDHCI_CAN_DO_DMA))
1382 DBG("Controller doesn't have DMA capability\n");
1383 else
1384 host->flags |= SDHCI_USE_DMA;
1385
1386 if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1387 (host->flags & SDHCI_USE_DMA)) {
1388 DBG("Disabling DMA as it is marked broken\n");
1389 host->flags &= ~SDHCI_USE_DMA;
1390 }
1391
1392 if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1393 (host->flags & SDHCI_USE_DMA)) {
1394 printk(KERN_WARNING "%s: Will use DMA "
1395 "mode even though HW doesn't fully "
1396 "claim to support it.\n", mmc_hostname(mmc));
1397 }
1398
1399 if (host->flags & SDHCI_USE_DMA) {
1400 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1401 printk(KERN_WARNING "%s: No suitable DMA available. "
1402 "Falling back to PIO.\n", mmc_hostname(mmc));
1403 host->flags &= ~SDHCI_USE_DMA;
1404 }
1405 }
1406
1407 if (host->flags & SDHCI_USE_DMA)
1408 pci_set_master(pdev);
1409 else /* XXX: Hack to get MMC layer to avoid highmem */
1410 pdev->dma_mask = 0;
1411
1412 host->max_clk =
1413 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1414 if (host->max_clk == 0) {
1415 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1416 "frequency.\n", mmc_hostname(mmc));
1417 ret = -ENODEV;
1418 goto unmap;
1419 }
1420 host->max_clk *= 1000000;
1421
1422 host->timeout_clk =
1423 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1424 if (host->timeout_clk == 0) {
1425 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1426 "frequency.\n", mmc_hostname(mmc));
1427 ret = -ENODEV;
1428 goto unmap;
1429 }
1430 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1431 host->timeout_clk *= 1000;
1432
1433 /*
1434 * Set host parameters.
1435 */
1436 mmc->ops = &sdhci_ops;
1437 mmc->f_min = host->max_clk / 256;
1438 mmc->f_max = host->max_clk;
1439 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ;
1440
1441 if (caps & SDHCI_CAN_DO_HISPD)
1442 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1443
1444 mmc->ocr_avail = 0;
1445 if (caps & SDHCI_CAN_VDD_330)
1446 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1447 if (caps & SDHCI_CAN_VDD_300)
1448 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1449 if (caps & SDHCI_CAN_VDD_180)
1450 mmc->ocr_avail |= MMC_VDD_165_195;
1451
1452 if (mmc->ocr_avail == 0) {
1453 printk(KERN_ERR "%s: Hardware doesn't report any "
1454 "support voltages.\n", mmc_hostname(mmc));
1455 ret = -ENODEV;
1456 goto unmap;
1457 }
1458
1459 spin_lock_init(&host->lock);
1460
1461 /*
1462 * Maximum number of segments. Hardware cannot do scatter lists.
1463 */
1464 if (host->flags & SDHCI_USE_DMA)
1465 mmc->max_hw_segs = 1;
1466 else
1467 mmc->max_hw_segs = 16;
1468 mmc->max_phys_segs = 16;
1469
1470 /*
1471 * Maximum number of sectors in one transfer. Limited by DMA boundary
1472 * size (512KiB).
1473 */
1474 mmc->max_req_size = 524288;
1475
1476 /*
1477 * Maximum segment size. Could be one segment with the maximum number
1478 * of bytes.
1479 */
1480 mmc->max_seg_size = mmc->max_req_size;
1481
1482 /*
1483 * Maximum block size. This varies from controller to controller and
1484 * is specified in the capabilities register.
1485 */
1486 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1487 if (mmc->max_blk_size >= 3) {
1488 printk(KERN_WARNING "%s: Invalid maximum block size, "
1489 "assuming 512 bytes\n", mmc_hostname(mmc));
1490 mmc->max_blk_size = 512;
1491 } else
1492 mmc->max_blk_size = 512 << mmc->max_blk_size;
1493
1494 /*
1495 * Maximum block count.
1496 */
1497 mmc->max_blk_count = 65535;
1498
1499 /*
1500 * Init tasklets.
1501 */
1502 tasklet_init(&host->card_tasklet,
1503 sdhci_tasklet_card, (unsigned long)host);
1504 tasklet_init(&host->finish_tasklet,
1505 sdhci_tasklet_finish, (unsigned long)host);
1506
1507 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1508
1509 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1510 mmc_hostname(mmc), host);
1511 if (ret)
1512 goto untasklet;
1513
1514 sdhci_init(host);
1515
1516 #ifdef CONFIG_MMC_DEBUG
1517 sdhci_dumpregs(host);
1518 #endif
1519
1520 #ifdef CONFIG_LEDS_CLASS
1521 host->led.name = mmc_hostname(mmc);
1522 host->led.brightness = LED_OFF;
1523 host->led.default_trigger = mmc_hostname(mmc);
1524 host->led.brightness_set = sdhci_led_control;
1525
1526 ret = led_classdev_register(&pdev->dev, &host->led);
1527 if (ret)
1528 goto reset;
1529 #endif
1530
1531 mmiowb();
1532
1533 mmc_add_host(mmc);
1534
1535 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n",
1536 mmc_hostname(mmc), host->addr, host->irq,
1537 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1538
1539 return 0;
1540
1541 #ifdef CONFIG_LEDS_CLASS
1542 reset:
1543 sdhci_reset(host, SDHCI_RESET_ALL);
1544 free_irq(host->irq, host);
1545 #endif
1546 untasklet:
1547 tasklet_kill(&host->card_tasklet);
1548 tasklet_kill(&host->finish_tasklet);
1549 unmap:
1550 iounmap(host->ioaddr);
1551 release:
1552 pci_release_region(pdev, host->bar);
1553 free:
1554 mmc_free_host(mmc);
1555
1556 return ret;
1557 }
1558
1559 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1560 {
1561 struct sdhci_chip *chip;
1562 struct mmc_host *mmc;
1563 struct sdhci_host *host;
1564
1565 chip = pci_get_drvdata(pdev);
1566 host = chip->hosts[slot];
1567 mmc = host->mmc;
1568
1569 chip->hosts[slot] = NULL;
1570
1571 mmc_remove_host(mmc);
1572
1573 #ifdef CONFIG_LEDS_CLASS
1574 led_classdev_unregister(&host->led);
1575 #endif
1576
1577 sdhci_reset(host, SDHCI_RESET_ALL);
1578
1579 free_irq(host->irq, host);
1580
1581 del_timer_sync(&host->timer);
1582
1583 tasklet_kill(&host->card_tasklet);
1584 tasklet_kill(&host->finish_tasklet);
1585
1586 iounmap(host->ioaddr);
1587
1588 pci_release_region(pdev, host->bar);
1589
1590 mmc_free_host(mmc);
1591 }
1592
1593 static int __devinit sdhci_probe(struct pci_dev *pdev,
1594 const struct pci_device_id *ent)
1595 {
1596 int ret, i;
1597 u8 slots, rev;
1598 struct sdhci_chip *chip;
1599
1600 BUG_ON(pdev == NULL);
1601 BUG_ON(ent == NULL);
1602
1603 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1604
1605 printk(KERN_INFO DRIVER_NAME
1606 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1607 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1608 (int)rev);
1609
1610 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1611 if (ret)
1612 return ret;
1613
1614 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1615 DBG("found %d slot(s)\n", slots);
1616 if (slots == 0)
1617 return -ENODEV;
1618
1619 ret = pci_enable_device(pdev);
1620 if (ret)
1621 return ret;
1622
1623 chip = kzalloc(sizeof(struct sdhci_chip) +
1624 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1625 if (!chip) {
1626 ret = -ENOMEM;
1627 goto err;
1628 }
1629
1630 chip->pdev = pdev;
1631 chip->quirks = ent->driver_data;
1632
1633 if (debug_quirks)
1634 chip->quirks = debug_quirks;
1635
1636 chip->num_slots = slots;
1637 pci_set_drvdata(pdev, chip);
1638
1639 for (i = 0;i < slots;i++) {
1640 ret = sdhci_probe_slot(pdev, i);
1641 if (ret) {
1642 for (i--;i >= 0;i--)
1643 sdhci_remove_slot(pdev, i);
1644 goto free;
1645 }
1646 }
1647
1648 return 0;
1649
1650 free:
1651 pci_set_drvdata(pdev, NULL);
1652 kfree(chip);
1653
1654 err:
1655 pci_disable_device(pdev);
1656 return ret;
1657 }
1658
1659 static void __devexit sdhci_remove(struct pci_dev *pdev)
1660 {
1661 int i;
1662 struct sdhci_chip *chip;
1663
1664 chip = pci_get_drvdata(pdev);
1665
1666 if (chip) {
1667 for (i = 0;i < chip->num_slots;i++)
1668 sdhci_remove_slot(pdev, i);
1669
1670 pci_set_drvdata(pdev, NULL);
1671
1672 kfree(chip);
1673 }
1674
1675 pci_disable_device(pdev);
1676 }
1677
1678 static struct pci_driver sdhci_driver = {
1679 .name = DRIVER_NAME,
1680 .id_table = pci_ids,
1681 .probe = sdhci_probe,
1682 .remove = __devexit_p(sdhci_remove),
1683 .suspend = sdhci_suspend,
1684 .resume = sdhci_resume,
1685 };
1686
1687 /*****************************************************************************\
1688 * *
1689 * Driver init/exit *
1690 * *
1691 \*****************************************************************************/
1692
1693 static int __init sdhci_drv_init(void)
1694 {
1695 printk(KERN_INFO DRIVER_NAME
1696 ": Secure Digital Host Controller Interface driver\n");
1697 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1698
1699 return pci_register_driver(&sdhci_driver);
1700 }
1701
1702 static void __exit sdhci_drv_exit(void)
1703 {
1704 DBG("Exiting\n");
1705
1706 pci_unregister_driver(&sdhci_driver);
1707 }
1708
1709 module_init(sdhci_drv_init);
1710 module_exit(sdhci_drv_exit);
1711
1712 module_param(debug_quirks, uint, 0444);
1713
1714 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1715 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1716 MODULE_LICENSE("GPL");
1717
1718 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
kernel source for telekom puls (alcatel/mediatek)