2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
22 #include <linux/leds.h>
24 #include <linux/mmc/host.h>
28 #define DRIVER_NAME "sdhci"
30 #define DBG(f, x...) \
31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
33 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
34 defined(CONFIG_MMC_SDHCI_MODULE))
35 #define SDHCI_USE_LEDS_CLASS
38 static unsigned int debug_quirks
= 0;
40 static void sdhci_prepare_data(struct sdhci_host
*, struct mmc_data
*);
41 static void sdhci_finish_data(struct sdhci_host
*);
43 static void sdhci_send_command(struct sdhci_host
*, struct mmc_command
*);
44 static void sdhci_finish_command(struct sdhci_host
*);
46 static void sdhci_dumpregs(struct sdhci_host
*host
)
48 printk(KERN_DEBUG DRIVER_NAME
": ============== REGISTER DUMP ==============\n");
50 printk(KERN_DEBUG DRIVER_NAME
": Sys addr: 0x%08x | Version: 0x%08x\n",
51 readl(host
->ioaddr
+ SDHCI_DMA_ADDRESS
),
52 readw(host
->ioaddr
+ SDHCI_HOST_VERSION
));
53 printk(KERN_DEBUG DRIVER_NAME
": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
54 readw(host
->ioaddr
+ SDHCI_BLOCK_SIZE
),
55 readw(host
->ioaddr
+ SDHCI_BLOCK_COUNT
));
56 printk(KERN_DEBUG DRIVER_NAME
": Argument: 0x%08x | Trn mode: 0x%08x\n",
57 readl(host
->ioaddr
+ SDHCI_ARGUMENT
),
58 readw(host
->ioaddr
+ SDHCI_TRANSFER_MODE
));
59 printk(KERN_DEBUG DRIVER_NAME
": Present: 0x%08x | Host ctl: 0x%08x\n",
60 readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
),
61 readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
));
62 printk(KERN_DEBUG DRIVER_NAME
": Power: 0x%08x | Blk gap: 0x%08x\n",
63 readb(host
->ioaddr
+ SDHCI_POWER_CONTROL
),
64 readb(host
->ioaddr
+ SDHCI_BLOCK_GAP_CONTROL
));
65 printk(KERN_DEBUG DRIVER_NAME
": Wake-up: 0x%08x | Clock: 0x%08x\n",
66 readb(host
->ioaddr
+ SDHCI_WAKE_UP_CONTROL
),
67 readw(host
->ioaddr
+ SDHCI_CLOCK_CONTROL
));
68 printk(KERN_DEBUG DRIVER_NAME
": Timeout: 0x%08x | Int stat: 0x%08x\n",
69 readb(host
->ioaddr
+ SDHCI_TIMEOUT_CONTROL
),
70 readl(host
->ioaddr
+ SDHCI_INT_STATUS
));
71 printk(KERN_DEBUG DRIVER_NAME
": Int enab: 0x%08x | Sig enab: 0x%08x\n",
72 readl(host
->ioaddr
+ SDHCI_INT_ENABLE
),
73 readl(host
->ioaddr
+ SDHCI_SIGNAL_ENABLE
));
74 printk(KERN_DEBUG DRIVER_NAME
": AC12 err: 0x%08x | Slot int: 0x%08x\n",
75 readw(host
->ioaddr
+ SDHCI_ACMD12_ERR
),
76 readw(host
->ioaddr
+ SDHCI_SLOT_INT_STATUS
));
77 printk(KERN_DEBUG DRIVER_NAME
": Caps: 0x%08x | Max curr: 0x%08x\n",
78 readl(host
->ioaddr
+ SDHCI_CAPABILITIES
),
79 readl(host
->ioaddr
+ SDHCI_MAX_CURRENT
));
81 printk(KERN_DEBUG DRIVER_NAME
": ===========================================\n");
84 /*****************************************************************************\
86 * Low level functions *
88 \*****************************************************************************/
90 static void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
92 unsigned long timeout
;
94 if (host
->quirks
& SDHCI_QUIRK_NO_CARD_NO_RESET
) {
95 if (!(readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) &
100 writeb(mask
, host
->ioaddr
+ SDHCI_SOFTWARE_RESET
);
102 if (mask
& SDHCI_RESET_ALL
)
105 /* Wait max 100 ms */
108 /* hw clears the bit when it's done */
109 while (readb(host
->ioaddr
+ SDHCI_SOFTWARE_RESET
) & mask
) {
111 printk(KERN_ERR
"%s: Reset 0x%x never completed.\n",
112 mmc_hostname(host
->mmc
), (int)mask
);
113 sdhci_dumpregs(host
);
121 static void sdhci_init(struct sdhci_host
*host
)
125 sdhci_reset(host
, SDHCI_RESET_ALL
);
127 intmask
= SDHCI_INT_BUS_POWER
| SDHCI_INT_DATA_END_BIT
|
128 SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_TIMEOUT
| SDHCI_INT_INDEX
|
129 SDHCI_INT_END_BIT
| SDHCI_INT_CRC
| SDHCI_INT_TIMEOUT
|
130 SDHCI_INT_CARD_REMOVE
| SDHCI_INT_CARD_INSERT
|
131 SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
|
132 SDHCI_INT_DMA_END
| SDHCI_INT_DATA_END
| SDHCI_INT_RESPONSE
|
133 SDHCI_INT_ADMA_ERROR
;
135 writel(intmask
, host
->ioaddr
+ SDHCI_INT_ENABLE
);
136 writel(intmask
, host
->ioaddr
+ SDHCI_SIGNAL_ENABLE
);
139 static void sdhci_activate_led(struct sdhci_host
*host
)
143 ctrl
= readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
);
144 ctrl
|= SDHCI_CTRL_LED
;
145 writeb(ctrl
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
148 static void sdhci_deactivate_led(struct sdhci_host
*host
)
152 ctrl
= readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
);
153 ctrl
&= ~SDHCI_CTRL_LED
;
154 writeb(ctrl
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
157 #ifdef SDHCI_USE_LEDS_CLASS
158 static void sdhci_led_control(struct led_classdev
*led
,
159 enum led_brightness brightness
)
161 struct sdhci_host
*host
= container_of(led
, struct sdhci_host
, led
);
164 spin_lock_irqsave(&host
->lock
, flags
);
166 if (brightness
== LED_OFF
)
167 sdhci_deactivate_led(host
);
169 sdhci_activate_led(host
);
171 spin_unlock_irqrestore(&host
->lock
, flags
);
175 /*****************************************************************************\
179 \*****************************************************************************/
181 static void sdhci_read_block_pio(struct sdhci_host
*host
)
184 size_t blksize
, len
, chunk
;
185 u32
uninitialized_var(scratch
);
188 DBG("PIO reading\n");
190 blksize
= host
->data
->blksz
;
193 local_irq_save(flags
);
196 if (!sg_miter_next(&host
->sg_miter
))
199 len
= min(host
->sg_miter
.length
, blksize
);
202 host
->sg_miter
.consumed
= len
;
204 buf
= host
->sg_miter
.addr
;
208 scratch
= readl(host
->ioaddr
+ SDHCI_BUFFER
);
212 *buf
= scratch
& 0xFF;
221 sg_miter_stop(&host
->sg_miter
);
223 local_irq_restore(flags
);
226 static void sdhci_write_block_pio(struct sdhci_host
*host
)
229 size_t blksize
, len
, chunk
;
233 DBG("PIO writing\n");
235 blksize
= host
->data
->blksz
;
239 local_irq_save(flags
);
242 if (!sg_miter_next(&host
->sg_miter
))
245 len
= min(host
->sg_miter
.length
, blksize
);
248 host
->sg_miter
.consumed
= len
;
250 buf
= host
->sg_miter
.addr
;
253 scratch
|= (u32
)*buf
<< (chunk
* 8);
259 if ((chunk
== 4) || ((len
== 0) && (blksize
== 0))) {
260 writel(scratch
, host
->ioaddr
+ SDHCI_BUFFER
);
267 sg_miter_stop(&host
->sg_miter
);
269 local_irq_restore(flags
);
272 static void sdhci_transfer_pio(struct sdhci_host
*host
)
278 if (host
->blocks
== 0)
281 if (host
->data
->flags
& MMC_DATA_READ
)
282 mask
= SDHCI_DATA_AVAILABLE
;
284 mask
= SDHCI_SPACE_AVAILABLE
;
287 * Some controllers (JMicron JMB38x) mess up the buffer bits
288 * for transfers < 4 bytes. As long as it is just one block,
289 * we can ignore the bits.
291 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_SMALL_PIO
) &&
292 (host
->data
->blocks
== 1))
295 while (readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) & mask
) {
296 if (host
->data
->flags
& MMC_DATA_READ
)
297 sdhci_read_block_pio(host
);
299 sdhci_write_block_pio(host
);
302 if (host
->blocks
== 0)
306 DBG("PIO transfer complete.\n");
309 static char *sdhci_kmap_atomic(struct scatterlist
*sg
, unsigned long *flags
)
311 local_irq_save(*flags
);
312 return kmap_atomic(sg_page(sg
), KM_BIO_SRC_IRQ
) + sg
->offset
;
315 static void sdhci_kunmap_atomic(void *buffer
, unsigned long *flags
)
317 kunmap_atomic(buffer
, KM_BIO_SRC_IRQ
);
318 local_irq_restore(*flags
);
321 static int sdhci_adma_table_pre(struct sdhci_host
*host
,
322 struct mmc_data
*data
)
329 dma_addr_t align_addr
;
332 struct scatterlist
*sg
;
338 * The spec does not specify endianness of descriptor table.
339 * We currently guess that it is LE.
342 if (data
->flags
& MMC_DATA_READ
)
343 direction
= DMA_FROM_DEVICE
;
345 direction
= DMA_TO_DEVICE
;
348 * The ADMA descriptor table is mapped further down as we
349 * need to fill it with data first.
352 host
->align_addr
= dma_map_single(mmc_dev(host
->mmc
),
353 host
->align_buffer
, 128 * 4, direction
);
354 if (dma_mapping_error(mmc_dev(host
->mmc
), host
->align_addr
))
356 BUG_ON(host
->align_addr
& 0x3);
358 host
->sg_count
= dma_map_sg(mmc_dev(host
->mmc
),
359 data
->sg
, data
->sg_len
, direction
);
360 if (host
->sg_count
== 0)
363 desc
= host
->adma_desc
;
364 align
= host
->align_buffer
;
366 align_addr
= host
->align_addr
;
368 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
369 addr
= sg_dma_address(sg
);
370 len
= sg_dma_len(sg
);
373 * The SDHCI specification states that ADMA
374 * addresses must be 32-bit aligned. If they
375 * aren't, then we use a bounce buffer for
376 * the (up to three) bytes that screw up the
379 offset
= (4 - (addr
& 0x3)) & 0x3;
381 if (data
->flags
& MMC_DATA_WRITE
) {
382 buffer
= sdhci_kmap_atomic(sg
, &flags
);
383 WARN_ON(((long)buffer
& PAGE_MASK
) > (PAGE_SIZE
- 3));
384 memcpy(align
, buffer
, offset
);
385 sdhci_kunmap_atomic(buffer
, &flags
);
388 desc
[7] = (align_addr
>> 24) & 0xff;
389 desc
[6] = (align_addr
>> 16) & 0xff;
390 desc
[5] = (align_addr
>> 8) & 0xff;
391 desc
[4] = (align_addr
>> 0) & 0xff;
393 BUG_ON(offset
> 65536);
395 desc
[3] = (offset
>> 8) & 0xff;
396 desc
[2] = (offset
>> 0) & 0xff;
399 desc
[0] = 0x21; /* tran, valid */
410 desc
[7] = (addr
>> 24) & 0xff;
411 desc
[6] = (addr
>> 16) & 0xff;
412 desc
[5] = (addr
>> 8) & 0xff;
413 desc
[4] = (addr
>> 0) & 0xff;
417 desc
[3] = (len
>> 8) & 0xff;
418 desc
[2] = (len
>> 0) & 0xff;
421 desc
[0] = 0x21; /* tran, valid */
426 * If this triggers then we have a calculation bug
429 WARN_ON((desc
- host
->adma_desc
) > (128 * 2 + 1) * 4);
433 * Add a terminating entry.
444 desc
[0] = 0x03; /* nop, end, valid */
447 * Resync align buffer as we might have changed it.
449 if (data
->flags
& MMC_DATA_WRITE
) {
450 dma_sync_single_for_device(mmc_dev(host
->mmc
),
451 host
->align_addr
, 128 * 4, direction
);
454 host
->adma_addr
= dma_map_single(mmc_dev(host
->mmc
),
455 host
->adma_desc
, (128 * 2 + 1) * 4, DMA_TO_DEVICE
);
456 if (dma_mapping_error(mmc_dev(host
->mmc
), host
->adma_addr
))
458 BUG_ON(host
->adma_addr
& 0x3);
463 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
464 data
->sg_len
, direction
);
466 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
472 static void sdhci_adma_table_post(struct sdhci_host
*host
,
473 struct mmc_data
*data
)
477 struct scatterlist
*sg
;
483 if (data
->flags
& MMC_DATA_READ
)
484 direction
= DMA_FROM_DEVICE
;
486 direction
= DMA_TO_DEVICE
;
488 dma_unmap_single(mmc_dev(host
->mmc
), host
->adma_addr
,
489 (128 * 2 + 1) * 4, DMA_TO_DEVICE
);
491 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
494 if (data
->flags
& MMC_DATA_READ
) {
495 dma_sync_sg_for_cpu(mmc_dev(host
->mmc
), data
->sg
,
496 data
->sg_len
, direction
);
498 align
= host
->align_buffer
;
500 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
501 if (sg_dma_address(sg
) & 0x3) {
502 size
= 4 - (sg_dma_address(sg
) & 0x3);
504 buffer
= sdhci_kmap_atomic(sg
, &flags
);
505 WARN_ON(((long)buffer
& PAGE_MASK
) > (PAGE_SIZE
- 3));
506 memcpy(buffer
, align
, size
);
507 sdhci_kunmap_atomic(buffer
, &flags
);
514 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
515 data
->sg_len
, direction
);
518 static u8
sdhci_calc_timeout(struct sdhci_host
*host
, struct mmc_data
*data
)
521 unsigned target_timeout
, current_timeout
;
524 * If the host controller provides us with an incorrect timeout
525 * value, just skip the check and use 0xE. The hardware may take
526 * longer to time out, but that's much better than having a too-short
529 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
))
533 target_timeout
= data
->timeout_ns
/ 1000 +
534 data
->timeout_clks
/ host
->clock
;
537 * Figure out needed cycles.
538 * We do this in steps in order to fit inside a 32 bit int.
539 * The first step is the minimum timeout, which will have a
540 * minimum resolution of 6 bits:
541 * (1) 2^13*1000 > 2^22,
542 * (2) host->timeout_clk < 2^16
547 current_timeout
= (1 << 13) * 1000 / host
->timeout_clk
;
548 while (current_timeout
< target_timeout
) {
550 current_timeout
<<= 1;
556 printk(KERN_WARNING
"%s: Too large timeout requested!\n",
557 mmc_hostname(host
->mmc
));
564 static void sdhci_prepare_data(struct sdhci_host
*host
, struct mmc_data
*data
)
576 BUG_ON(data
->blksz
* data
->blocks
> 524288);
577 BUG_ON(data
->blksz
> host
->mmc
->max_blk_size
);
578 BUG_ON(data
->blocks
> 65535);
581 host
->data_early
= 0;
583 count
= sdhci_calc_timeout(host
, data
);
584 writeb(count
, host
->ioaddr
+ SDHCI_TIMEOUT_CONTROL
);
586 if (host
->flags
& SDHCI_USE_DMA
)
587 host
->flags
|= SDHCI_REQ_USE_DMA
;
590 * FIXME: This doesn't account for merging when mapping the
593 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
595 struct scatterlist
*sg
;
598 if (host
->flags
& SDHCI_USE_ADMA
) {
599 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
602 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_SIZE
)
606 if (unlikely(broken
)) {
607 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
608 if (sg
->length
& 0x3) {
609 DBG("Reverting to PIO because of "
610 "transfer size (%d)\n",
612 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
620 * The assumption here being that alignment is the same after
621 * translation to device address space.
623 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
625 struct scatterlist
*sg
;
628 if (host
->flags
& SDHCI_USE_ADMA
) {
630 * As we use 3 byte chunks to work around
631 * alignment problems, we need to check this
634 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
637 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
)
641 if (unlikely(broken
)) {
642 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
643 if (sg
->offset
& 0x3) {
644 DBG("Reverting to PIO because of "
646 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
653 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
654 if (host
->flags
& SDHCI_USE_ADMA
) {
655 ret
= sdhci_adma_table_pre(host
, data
);
658 * This only happens when someone fed
659 * us an invalid request.
662 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
664 writel(host
->adma_addr
,
665 host
->ioaddr
+ SDHCI_ADMA_ADDRESS
);
670 sg_cnt
= dma_map_sg(mmc_dev(host
->mmc
),
671 data
->sg
, data
->sg_len
,
672 (data
->flags
& MMC_DATA_READ
) ?
677 * This only happens when someone fed
678 * us an invalid request.
681 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
683 WARN_ON(sg_cnt
!= 1);
684 writel(sg_dma_address(data
->sg
),
685 host
->ioaddr
+ SDHCI_DMA_ADDRESS
);
691 * Always adjust the DMA selection as some controllers
692 * (e.g. JMicron) can't do PIO properly when the selection
695 if (host
->version
>= SDHCI_SPEC_200
) {
696 ctrl
= readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
);
697 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
698 if ((host
->flags
& SDHCI_REQ_USE_DMA
) &&
699 (host
->flags
& SDHCI_USE_ADMA
))
700 ctrl
|= SDHCI_CTRL_ADMA32
;
702 ctrl
|= SDHCI_CTRL_SDMA
;
703 writeb(ctrl
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
706 if (!(host
->flags
& SDHCI_REQ_USE_DMA
)) {
707 sg_miter_start(&host
->sg_miter
,
708 data
->sg
, data
->sg_len
, SG_MITER_ATOMIC
);
709 host
->blocks
= data
->blocks
;
712 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
713 writew(SDHCI_MAKE_BLKSZ(7, data
->blksz
),
714 host
->ioaddr
+ SDHCI_BLOCK_SIZE
);
715 writew(data
->blocks
, host
->ioaddr
+ SDHCI_BLOCK_COUNT
);
718 static void sdhci_set_transfer_mode(struct sdhci_host
*host
,
719 struct mmc_data
*data
)
726 WARN_ON(!host
->data
);
728 mode
= SDHCI_TRNS_BLK_CNT_EN
;
729 if (data
->blocks
> 1)
730 mode
|= SDHCI_TRNS_MULTI
;
731 if (data
->flags
& MMC_DATA_READ
)
732 mode
|= SDHCI_TRNS_READ
;
733 if (host
->flags
& SDHCI_REQ_USE_DMA
)
734 mode
|= SDHCI_TRNS_DMA
;
736 writew(mode
, host
->ioaddr
+ SDHCI_TRANSFER_MODE
);
739 static void sdhci_finish_data(struct sdhci_host
*host
)
741 struct mmc_data
*data
;
748 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
749 if (host
->flags
& SDHCI_USE_ADMA
)
750 sdhci_adma_table_post(host
, data
);
752 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
753 data
->sg_len
, (data
->flags
& MMC_DATA_READ
) ?
754 DMA_FROM_DEVICE
: DMA_TO_DEVICE
);
759 * The specification states that the block count register must
760 * be updated, but it does not specify at what point in the
761 * data flow. That makes the register entirely useless to read
762 * back so we have to assume that nothing made it to the card
763 * in the event of an error.
766 data
->bytes_xfered
= 0;
768 data
->bytes_xfered
= data
->blksz
* data
->blocks
;
772 * The controller needs a reset of internal state machines
773 * upon error conditions.
776 sdhci_reset(host
, SDHCI_RESET_CMD
);
777 sdhci_reset(host
, SDHCI_RESET_DATA
);
780 sdhci_send_command(host
, data
->stop
);
782 tasklet_schedule(&host
->finish_tasklet
);
785 static void sdhci_send_command(struct sdhci_host
*host
, struct mmc_command
*cmd
)
789 unsigned long timeout
;
796 mask
= SDHCI_CMD_INHIBIT
;
797 if ((cmd
->data
!= NULL
) || (cmd
->flags
& MMC_RSP_BUSY
))
798 mask
|= SDHCI_DATA_INHIBIT
;
800 /* We shouldn't wait for data inihibit for stop commands, even
801 though they might use busy signaling */
802 if (host
->mrq
->data
&& (cmd
== host
->mrq
->data
->stop
))
803 mask
&= ~SDHCI_DATA_INHIBIT
;
805 while (readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) & mask
) {
807 printk(KERN_ERR
"%s: Controller never released "
808 "inhibit bit(s).\n", mmc_hostname(host
->mmc
));
809 sdhci_dumpregs(host
);
811 tasklet_schedule(&host
->finish_tasklet
);
818 mod_timer(&host
->timer
, jiffies
+ 10 * HZ
);
822 sdhci_prepare_data(host
, cmd
->data
);
824 writel(cmd
->arg
, host
->ioaddr
+ SDHCI_ARGUMENT
);
826 sdhci_set_transfer_mode(host
, cmd
->data
);
828 if ((cmd
->flags
& MMC_RSP_136
) && (cmd
->flags
& MMC_RSP_BUSY
)) {
829 printk(KERN_ERR
"%s: Unsupported response type!\n",
830 mmc_hostname(host
->mmc
));
831 cmd
->error
= -EINVAL
;
832 tasklet_schedule(&host
->finish_tasklet
);
836 if (!(cmd
->flags
& MMC_RSP_PRESENT
))
837 flags
= SDHCI_CMD_RESP_NONE
;
838 else if (cmd
->flags
& MMC_RSP_136
)
839 flags
= SDHCI_CMD_RESP_LONG
;
840 else if (cmd
->flags
& MMC_RSP_BUSY
)
841 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
843 flags
= SDHCI_CMD_RESP_SHORT
;
845 if (cmd
->flags
& MMC_RSP_CRC
)
846 flags
|= SDHCI_CMD_CRC
;
847 if (cmd
->flags
& MMC_RSP_OPCODE
)
848 flags
|= SDHCI_CMD_INDEX
;
850 flags
|= SDHCI_CMD_DATA
;
852 writew(SDHCI_MAKE_CMD(cmd
->opcode
, flags
),
853 host
->ioaddr
+ SDHCI_COMMAND
);
856 static void sdhci_finish_command(struct sdhci_host
*host
)
860 BUG_ON(host
->cmd
== NULL
);
862 if (host
->cmd
->flags
& MMC_RSP_PRESENT
) {
863 if (host
->cmd
->flags
& MMC_RSP_136
) {
864 /* CRC is stripped so we need to do some shifting. */
865 for (i
= 0;i
< 4;i
++) {
866 host
->cmd
->resp
[i
] = readl(host
->ioaddr
+
867 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
869 host
->cmd
->resp
[i
] |=
871 SDHCI_RESPONSE
+ (3-i
)*4-1);
874 host
->cmd
->resp
[0] = readl(host
->ioaddr
+ SDHCI_RESPONSE
);
878 host
->cmd
->error
= 0;
880 if (host
->data
&& host
->data_early
)
881 sdhci_finish_data(host
);
883 if (!host
->cmd
->data
)
884 tasklet_schedule(&host
->finish_tasklet
);
889 static void sdhci_set_clock(struct sdhci_host
*host
, unsigned int clock
)
893 unsigned long timeout
;
895 if (clock
== host
->clock
)
898 writew(0, host
->ioaddr
+ SDHCI_CLOCK_CONTROL
);
903 for (div
= 1;div
< 256;div
*= 2) {
904 if ((host
->max_clk
/ div
) <= clock
)
909 clk
= div
<< SDHCI_DIVIDER_SHIFT
;
910 clk
|= SDHCI_CLOCK_INT_EN
;
911 writew(clk
, host
->ioaddr
+ SDHCI_CLOCK_CONTROL
);
915 while (!((clk
= readw(host
->ioaddr
+ SDHCI_CLOCK_CONTROL
))
916 & SDHCI_CLOCK_INT_STABLE
)) {
918 printk(KERN_ERR
"%s: Internal clock never "
919 "stabilised.\n", mmc_hostname(host
->mmc
));
920 sdhci_dumpregs(host
);
927 clk
|= SDHCI_CLOCK_CARD_EN
;
928 writew(clk
, host
->ioaddr
+ SDHCI_CLOCK_CONTROL
);
934 static void sdhci_set_power(struct sdhci_host
*host
, unsigned short power
)
938 if (host
->power
== power
)
941 if (power
== (unsigned short)-1) {
942 writeb(0, host
->ioaddr
+ SDHCI_POWER_CONTROL
);
947 * Spec says that we should clear the power reg before setting
948 * a new value. Some controllers don't seem to like this though.
950 if (!(host
->quirks
& SDHCI_QUIRK_SINGLE_POWER_WRITE
))
951 writeb(0, host
->ioaddr
+ SDHCI_POWER_CONTROL
);
953 pwr
= SDHCI_POWER_ON
;
955 switch (1 << power
) {
956 case MMC_VDD_165_195
:
957 pwr
|= SDHCI_POWER_180
;
961 pwr
|= SDHCI_POWER_300
;
965 pwr
|= SDHCI_POWER_330
;
972 * At least the Marvell CaFe chip gets confused if we set the voltage
973 * and set turn on power at the same time, so set the voltage first.
975 if ((host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
))
976 writeb(pwr
& ~SDHCI_POWER_ON
,
977 host
->ioaddr
+ SDHCI_POWER_CONTROL
);
979 writeb(pwr
, host
->ioaddr
+ SDHCI_POWER_CONTROL
);
985 /*****************************************************************************\
989 \*****************************************************************************/
991 static void sdhci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
993 struct sdhci_host
*host
;
996 host
= mmc_priv(mmc
);
998 spin_lock_irqsave(&host
->lock
, flags
);
1000 WARN_ON(host
->mrq
!= NULL
);
1002 #ifndef SDHCI_USE_LEDS_CLASS
1003 sdhci_activate_led(host
);
1008 if (!(readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
)
1009 || (host
->flags
& SDHCI_DEVICE_DEAD
)) {
1010 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1011 tasklet_schedule(&host
->finish_tasklet
);
1013 sdhci_send_command(host
, mrq
->cmd
);
1016 spin_unlock_irqrestore(&host
->lock
, flags
);
1019 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1021 struct sdhci_host
*host
;
1022 unsigned long flags
;
1025 host
= mmc_priv(mmc
);
1027 spin_lock_irqsave(&host
->lock
, flags
);
1029 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1033 * Reset the chip on each power off.
1034 * Should clear out any weird states.
1036 if (ios
->power_mode
== MMC_POWER_OFF
) {
1037 writel(0, host
->ioaddr
+ SDHCI_SIGNAL_ENABLE
);
1041 sdhci_set_clock(host
, ios
->clock
);
1043 if (ios
->power_mode
== MMC_POWER_OFF
)
1044 sdhci_set_power(host
, -1);
1046 sdhci_set_power(host
, ios
->vdd
);
1048 ctrl
= readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
);
1050 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
1051 ctrl
|= SDHCI_CTRL_4BITBUS
;
1053 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1055 if (ios
->timing
== MMC_TIMING_SD_HS
)
1056 ctrl
|= SDHCI_CTRL_HISPD
;
1058 ctrl
&= ~SDHCI_CTRL_HISPD
;
1060 writeb(ctrl
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
1063 * Some (ENE) controllers go apeshit on some ios operation,
1064 * signalling timeout and CRC errors even on CMD0. Resetting
1065 * it on each ios seems to solve the problem.
1067 if(host
->quirks
& SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
)
1068 sdhci_reset(host
, SDHCI_RESET_CMD
| SDHCI_RESET_DATA
);
1072 spin_unlock_irqrestore(&host
->lock
, flags
);
1075 static int sdhci_get_ro(struct mmc_host
*mmc
)
1077 struct sdhci_host
*host
;
1078 unsigned long flags
;
1081 host
= mmc_priv(mmc
);
1083 spin_lock_irqsave(&host
->lock
, flags
);
1085 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1088 present
= readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
);
1090 spin_unlock_irqrestore(&host
->lock
, flags
);
1092 return !(present
& SDHCI_WRITE_PROTECT
);
1095 static void sdhci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1097 struct sdhci_host
*host
;
1098 unsigned long flags
;
1101 host
= mmc_priv(mmc
);
1103 spin_lock_irqsave(&host
->lock
, flags
);
1105 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1108 ier
= readl(host
->ioaddr
+ SDHCI_INT_ENABLE
);
1110 ier
&= ~SDHCI_INT_CARD_INT
;
1112 ier
|= SDHCI_INT_CARD_INT
;
1114 writel(ier
, host
->ioaddr
+ SDHCI_INT_ENABLE
);
1115 writel(ier
, host
->ioaddr
+ SDHCI_SIGNAL_ENABLE
);
1120 spin_unlock_irqrestore(&host
->lock
, flags
);
1123 static const struct mmc_host_ops sdhci_ops
= {
1124 .request
= sdhci_request
,
1125 .set_ios
= sdhci_set_ios
,
1126 .get_ro
= sdhci_get_ro
,
1127 .enable_sdio_irq
= sdhci_enable_sdio_irq
,
1130 /*****************************************************************************\
1134 \*****************************************************************************/
1136 static void sdhci_tasklet_card(unsigned long param
)
1138 struct sdhci_host
*host
;
1139 unsigned long flags
;
1141 host
= (struct sdhci_host
*)param
;
1143 spin_lock_irqsave(&host
->lock
, flags
);
1145 if (!(readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
)) {
1147 printk(KERN_ERR
"%s: Card removed during transfer!\n",
1148 mmc_hostname(host
->mmc
));
1149 printk(KERN_ERR
"%s: Resetting controller.\n",
1150 mmc_hostname(host
->mmc
));
1152 sdhci_reset(host
, SDHCI_RESET_CMD
);
1153 sdhci_reset(host
, SDHCI_RESET_DATA
);
1155 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1156 tasklet_schedule(&host
->finish_tasklet
);
1160 spin_unlock_irqrestore(&host
->lock
, flags
);
1162 mmc_detect_change(host
->mmc
, msecs_to_jiffies(200));
1165 static void sdhci_tasklet_finish(unsigned long param
)
1167 struct sdhci_host
*host
;
1168 unsigned long flags
;
1169 struct mmc_request
*mrq
;
1171 host
= (struct sdhci_host
*)param
;
1173 spin_lock_irqsave(&host
->lock
, flags
);
1175 del_timer(&host
->timer
);
1180 * The controller needs a reset of internal state machines
1181 * upon error conditions.
1183 if (!(host
->flags
& SDHCI_DEVICE_DEAD
) &&
1185 (mrq
->data
&& (mrq
->data
->error
||
1186 (mrq
->data
->stop
&& mrq
->data
->stop
->error
))) ||
1187 (host
->quirks
& SDHCI_QUIRK_RESET_AFTER_REQUEST
))) {
1189 /* Some controllers need this kick or reset won't work here */
1190 if (host
->quirks
& SDHCI_QUIRK_CLOCK_BEFORE_RESET
) {
1193 /* This is to force an update */
1194 clock
= host
->clock
;
1196 sdhci_set_clock(host
, clock
);
1199 /* Spec says we should do both at the same time, but Ricoh
1200 controllers do not like that. */
1201 sdhci_reset(host
, SDHCI_RESET_CMD
);
1202 sdhci_reset(host
, SDHCI_RESET_DATA
);
1209 #ifndef SDHCI_USE_LEDS_CLASS
1210 sdhci_deactivate_led(host
);
1214 spin_unlock_irqrestore(&host
->lock
, flags
);
1216 mmc_request_done(host
->mmc
, mrq
);
1219 static void sdhci_timeout_timer(unsigned long data
)
1221 struct sdhci_host
*host
;
1222 unsigned long flags
;
1224 host
= (struct sdhci_host
*)data
;
1226 spin_lock_irqsave(&host
->lock
, flags
);
1229 printk(KERN_ERR
"%s: Timeout waiting for hardware "
1230 "interrupt.\n", mmc_hostname(host
->mmc
));
1231 sdhci_dumpregs(host
);
1234 host
->data
->error
= -ETIMEDOUT
;
1235 sdhci_finish_data(host
);
1238 host
->cmd
->error
= -ETIMEDOUT
;
1240 host
->mrq
->cmd
->error
= -ETIMEDOUT
;
1242 tasklet_schedule(&host
->finish_tasklet
);
1247 spin_unlock_irqrestore(&host
->lock
, flags
);
1250 /*****************************************************************************\
1252 * Interrupt handling *
1254 \*****************************************************************************/
1256 static void sdhci_cmd_irq(struct sdhci_host
*host
, u32 intmask
)
1258 BUG_ON(intmask
== 0);
1261 printk(KERN_ERR
"%s: Got command interrupt 0x%08x even "
1262 "though no command operation was in progress.\n",
1263 mmc_hostname(host
->mmc
), (unsigned)intmask
);
1264 sdhci_dumpregs(host
);
1268 if (intmask
& SDHCI_INT_TIMEOUT
)
1269 host
->cmd
->error
= -ETIMEDOUT
;
1270 else if (intmask
& (SDHCI_INT_CRC
| SDHCI_INT_END_BIT
|
1272 host
->cmd
->error
= -EILSEQ
;
1274 if (host
->cmd
->error
) {
1275 tasklet_schedule(&host
->finish_tasklet
);
1280 * The host can send and interrupt when the busy state has
1281 * ended, allowing us to wait without wasting CPU cycles.
1282 * Unfortunately this is overloaded on the "data complete"
1283 * interrupt, so we need to take some care when handling
1286 * Note: The 1.0 specification is a bit ambiguous about this
1287 * feature so there might be some problems with older
1290 if (host
->cmd
->flags
& MMC_RSP_BUSY
) {
1291 if (host
->cmd
->data
)
1292 DBG("Cannot wait for busy signal when also "
1293 "doing a data transfer");
1294 else if (!(host
->quirks
& SDHCI_QUIRK_NO_BUSY_IRQ
))
1297 /* The controller does not support the end-of-busy IRQ,
1298 * fall through and take the SDHCI_INT_RESPONSE */
1301 if (intmask
& SDHCI_INT_RESPONSE
)
1302 sdhci_finish_command(host
);
1305 static void sdhci_data_irq(struct sdhci_host
*host
, u32 intmask
)
1307 BUG_ON(intmask
== 0);
1311 * The "data complete" interrupt is also used to
1312 * indicate that a busy state has ended. See comment
1313 * above in sdhci_cmd_irq().
1315 if (host
->cmd
&& (host
->cmd
->flags
& MMC_RSP_BUSY
)) {
1316 if (intmask
& SDHCI_INT_DATA_END
) {
1317 sdhci_finish_command(host
);
1322 printk(KERN_ERR
"%s: Got data interrupt 0x%08x even "
1323 "though no data operation was in progress.\n",
1324 mmc_hostname(host
->mmc
), (unsigned)intmask
);
1325 sdhci_dumpregs(host
);
1330 if (intmask
& SDHCI_INT_DATA_TIMEOUT
)
1331 host
->data
->error
= -ETIMEDOUT
;
1332 else if (intmask
& (SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_END_BIT
))
1333 host
->data
->error
= -EILSEQ
;
1334 else if (intmask
& SDHCI_INT_ADMA_ERROR
)
1335 host
->data
->error
= -EIO
;
1337 if (host
->data
->error
)
1338 sdhci_finish_data(host
);
1340 if (intmask
& (SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
))
1341 sdhci_transfer_pio(host
);
1344 * We currently don't do anything fancy with DMA
1345 * boundaries, but as we can't disable the feature
1346 * we need to at least restart the transfer.
1348 if (intmask
& SDHCI_INT_DMA_END
)
1349 writel(readl(host
->ioaddr
+ SDHCI_DMA_ADDRESS
),
1350 host
->ioaddr
+ SDHCI_DMA_ADDRESS
);
1352 if (intmask
& SDHCI_INT_DATA_END
) {
1355 * Data managed to finish before the
1356 * command completed. Make sure we do
1357 * things in the proper order.
1359 host
->data_early
= 1;
1361 sdhci_finish_data(host
);
1367 static irqreturn_t
sdhci_irq(int irq
, void *dev_id
)
1370 struct sdhci_host
* host
= dev_id
;
1374 spin_lock(&host
->lock
);
1376 intmask
= readl(host
->ioaddr
+ SDHCI_INT_STATUS
);
1378 if (!intmask
|| intmask
== 0xffffffff) {
1383 DBG("*** %s got interrupt: 0x%08x\n",
1384 mmc_hostname(host
->mmc
), intmask
);
1386 if (intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
1387 writel(intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
),
1388 host
->ioaddr
+ SDHCI_INT_STATUS
);
1389 tasklet_schedule(&host
->card_tasklet
);
1392 intmask
&= ~(SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
);
1394 if (intmask
& SDHCI_INT_CMD_MASK
) {
1395 writel(intmask
& SDHCI_INT_CMD_MASK
,
1396 host
->ioaddr
+ SDHCI_INT_STATUS
);
1397 sdhci_cmd_irq(host
, intmask
& SDHCI_INT_CMD_MASK
);
1400 if (intmask
& SDHCI_INT_DATA_MASK
) {
1401 writel(intmask
& SDHCI_INT_DATA_MASK
,
1402 host
->ioaddr
+ SDHCI_INT_STATUS
);
1403 sdhci_data_irq(host
, intmask
& SDHCI_INT_DATA_MASK
);
1406 intmask
&= ~(SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
);
1408 intmask
&= ~SDHCI_INT_ERROR
;
1410 if (intmask
& SDHCI_INT_BUS_POWER
) {
1411 printk(KERN_ERR
"%s: Card is consuming too much power!\n",
1412 mmc_hostname(host
->mmc
));
1413 writel(SDHCI_INT_BUS_POWER
, host
->ioaddr
+ SDHCI_INT_STATUS
);
1416 intmask
&= ~SDHCI_INT_BUS_POWER
;
1418 if (intmask
& SDHCI_INT_CARD_INT
)
1421 intmask
&= ~SDHCI_INT_CARD_INT
;
1424 printk(KERN_ERR
"%s: Unexpected interrupt 0x%08x.\n",
1425 mmc_hostname(host
->mmc
), intmask
);
1426 sdhci_dumpregs(host
);
1428 writel(intmask
, host
->ioaddr
+ SDHCI_INT_STATUS
);
1431 result
= IRQ_HANDLED
;
1435 spin_unlock(&host
->lock
);
1438 * We have to delay this as it calls back into the driver.
1441 mmc_signal_sdio_irq(host
->mmc
);
1446 /*****************************************************************************\
1450 \*****************************************************************************/
1454 int sdhci_suspend_host(struct sdhci_host
*host
, pm_message_t state
)
1458 ret
= mmc_suspend_host(host
->mmc
, state
);
1462 free_irq(host
->irq
, host
);
1467 EXPORT_SYMBOL_GPL(sdhci_suspend_host
);
1469 int sdhci_resume_host(struct sdhci_host
*host
)
1473 if (host
->flags
& SDHCI_USE_DMA
) {
1474 if (host
->ops
->enable_dma
)
1475 host
->ops
->enable_dma(host
);
1478 ret
= request_irq(host
->irq
, sdhci_irq
, IRQF_SHARED
,
1479 mmc_hostname(host
->mmc
), host
);
1486 ret
= mmc_resume_host(host
->mmc
);
1493 EXPORT_SYMBOL_GPL(sdhci_resume_host
);
1495 #endif /* CONFIG_PM */
1497 /*****************************************************************************\
1499 * Device allocation/registration *
1501 \*****************************************************************************/
1503 struct sdhci_host
*sdhci_alloc_host(struct device
*dev
,
1506 struct mmc_host
*mmc
;
1507 struct sdhci_host
*host
;
1509 WARN_ON(dev
== NULL
);
1511 mmc
= mmc_alloc_host(sizeof(struct sdhci_host
) + priv_size
, dev
);
1513 return ERR_PTR(-ENOMEM
);
1515 host
= mmc_priv(mmc
);
1521 EXPORT_SYMBOL_GPL(sdhci_alloc_host
);
1523 int sdhci_add_host(struct sdhci_host
*host
)
1525 struct mmc_host
*mmc
;
1529 WARN_ON(host
== NULL
);
1536 host
->quirks
= debug_quirks
;
1538 sdhci_reset(host
, SDHCI_RESET_ALL
);
1540 host
->version
= readw(host
->ioaddr
+ SDHCI_HOST_VERSION
);
1541 host
->version
= (host
->version
& SDHCI_SPEC_VER_MASK
)
1542 >> SDHCI_SPEC_VER_SHIFT
;
1543 if (host
->version
> SDHCI_SPEC_200
) {
1544 printk(KERN_ERR
"%s: Unknown controller version (%d). "
1545 "You may experience problems.\n", mmc_hostname(mmc
),
1549 caps
= readl(host
->ioaddr
+ SDHCI_CAPABILITIES
);
1551 if (host
->quirks
& SDHCI_QUIRK_FORCE_DMA
)
1552 host
->flags
|= SDHCI_USE_DMA
;
1553 else if (!(caps
& SDHCI_CAN_DO_DMA
))
1554 DBG("Controller doesn't have DMA capability\n");
1556 host
->flags
|= SDHCI_USE_DMA
;
1558 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_DMA
) &&
1559 (host
->flags
& SDHCI_USE_DMA
)) {
1560 DBG("Disabling DMA as it is marked broken\n");
1561 host
->flags
&= ~SDHCI_USE_DMA
;
1564 if (host
->flags
& SDHCI_USE_DMA
) {
1565 if ((host
->version
>= SDHCI_SPEC_200
) &&
1566 (caps
& SDHCI_CAN_DO_ADMA2
))
1567 host
->flags
|= SDHCI_USE_ADMA
;
1570 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA
) &&
1571 (host
->flags
& SDHCI_USE_ADMA
)) {
1572 DBG("Disabling ADMA as it is marked broken\n");
1573 host
->flags
&= ~SDHCI_USE_ADMA
;
1576 if (host
->flags
& SDHCI_USE_DMA
) {
1577 if (host
->ops
->enable_dma
) {
1578 if (host
->ops
->enable_dma(host
)) {
1579 printk(KERN_WARNING
"%s: No suitable DMA "
1580 "available. Falling back to PIO.\n",
1582 host
->flags
&= ~(SDHCI_USE_DMA
| SDHCI_USE_ADMA
);
1587 if (host
->flags
& SDHCI_USE_ADMA
) {
1589 * We need to allocate descriptors for all sg entries
1590 * (128) and potentially one alignment transfer for
1591 * each of those entries.
1593 host
->adma_desc
= kmalloc((128 * 2 + 1) * 4, GFP_KERNEL
);
1594 host
->align_buffer
= kmalloc(128 * 4, GFP_KERNEL
);
1595 if (!host
->adma_desc
|| !host
->align_buffer
) {
1596 kfree(host
->adma_desc
);
1597 kfree(host
->align_buffer
);
1598 printk(KERN_WARNING
"%s: Unable to allocate ADMA "
1599 "buffers. Falling back to standard DMA.\n",
1601 host
->flags
&= ~SDHCI_USE_ADMA
;
1606 * If we use DMA, then it's up to the caller to set the DMA
1607 * mask, but PIO does not need the hw shim so we set a new
1608 * mask here in that case.
1610 if (!(host
->flags
& SDHCI_USE_DMA
)) {
1611 host
->dma_mask
= DMA_BIT_MASK(64);
1612 mmc_dev(host
->mmc
)->dma_mask
= &host
->dma_mask
;
1616 (caps
& SDHCI_CLOCK_BASE_MASK
) >> SDHCI_CLOCK_BASE_SHIFT
;
1617 if (host
->max_clk
== 0) {
1618 printk(KERN_ERR
"%s: Hardware doesn't specify base clock "
1619 "frequency.\n", mmc_hostname(mmc
));
1622 host
->max_clk
*= 1000000;
1625 (caps
& SDHCI_TIMEOUT_CLK_MASK
) >> SDHCI_TIMEOUT_CLK_SHIFT
;
1626 if (host
->timeout_clk
== 0) {
1627 printk(KERN_ERR
"%s: Hardware doesn't specify timeout clock "
1628 "frequency.\n", mmc_hostname(mmc
));
1631 if (caps
& SDHCI_TIMEOUT_CLK_UNIT
)
1632 host
->timeout_clk
*= 1000;
1635 * Set host parameters.
1637 mmc
->ops
= &sdhci_ops
;
1638 mmc
->f_min
= host
->max_clk
/ 256;
1639 mmc
->f_max
= host
->max_clk
;
1640 mmc
->caps
= MMC_CAP_4_BIT_DATA
| MMC_CAP_SDIO_IRQ
;
1642 if (caps
& SDHCI_CAN_DO_HISPD
)
1643 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
;
1646 if (caps
& SDHCI_CAN_VDD_330
)
1647 mmc
->ocr_avail
|= MMC_VDD_32_33
|MMC_VDD_33_34
;
1648 if (caps
& SDHCI_CAN_VDD_300
)
1649 mmc
->ocr_avail
|= MMC_VDD_29_30
|MMC_VDD_30_31
;
1650 if (caps
& SDHCI_CAN_VDD_180
)
1651 mmc
->ocr_avail
|= MMC_VDD_165_195
;
1653 if (mmc
->ocr_avail
== 0) {
1654 printk(KERN_ERR
"%s: Hardware doesn't report any "
1655 "support voltages.\n", mmc_hostname(mmc
));
1659 spin_lock_init(&host
->lock
);
1662 * Maximum number of segments. Depends on if the hardware
1663 * can do scatter/gather or not.
1665 if (host
->flags
& SDHCI_USE_ADMA
)
1666 mmc
->max_hw_segs
= 128;
1667 else if (host
->flags
& SDHCI_USE_DMA
)
1668 mmc
->max_hw_segs
= 1;
1670 mmc
->max_hw_segs
= 128;
1671 mmc
->max_phys_segs
= 128;
1674 * Maximum number of sectors in one transfer. Limited by DMA boundary
1677 mmc
->max_req_size
= 524288;
1680 * Maximum segment size. Could be one segment with the maximum number
1681 * of bytes. When doing hardware scatter/gather, each entry cannot
1682 * be larger than 64 KiB though.
1684 if (host
->flags
& SDHCI_USE_ADMA
)
1685 mmc
->max_seg_size
= 65536;
1687 mmc
->max_seg_size
= mmc
->max_req_size
;
1690 * Maximum block size. This varies from controller to controller and
1691 * is specified in the capabilities register.
1693 mmc
->max_blk_size
= (caps
& SDHCI_MAX_BLOCK_MASK
) >> SDHCI_MAX_BLOCK_SHIFT
;
1694 if (mmc
->max_blk_size
>= 3) {
1695 printk(KERN_WARNING
"%s: Invalid maximum block size, "
1696 "assuming 512 bytes\n", mmc_hostname(mmc
));
1697 mmc
->max_blk_size
= 512;
1699 mmc
->max_blk_size
= 512 << mmc
->max_blk_size
;
1702 * Maximum block count.
1704 mmc
->max_blk_count
= 65535;
1709 tasklet_init(&host
->card_tasklet
,
1710 sdhci_tasklet_card
, (unsigned long)host
);
1711 tasklet_init(&host
->finish_tasklet
,
1712 sdhci_tasklet_finish
, (unsigned long)host
);
1714 setup_timer(&host
->timer
, sdhci_timeout_timer
, (unsigned long)host
);
1716 ret
= request_irq(host
->irq
, sdhci_irq
, IRQF_SHARED
,
1717 mmc_hostname(mmc
), host
);
1723 #ifdef CONFIG_MMC_DEBUG
1724 sdhci_dumpregs(host
);
1727 #ifdef SDHCI_USE_LEDS_CLASS
1728 snprintf(host
->led_name
, sizeof(host
->led_name
),
1729 "%s::", mmc_hostname(mmc
));
1730 host
->led
.name
= host
->led_name
;
1731 host
->led
.brightness
= LED_OFF
;
1732 host
->led
.default_trigger
= mmc_hostname(mmc
);
1733 host
->led
.brightness_set
= sdhci_led_control
;
1735 ret
= led_classdev_register(mmc_dev(mmc
), &host
->led
);
1744 printk(KERN_INFO
"%s: SDHCI controller on %s [%s] using %s%s\n",
1745 mmc_hostname(mmc
), host
->hw_name
, dev_name(mmc_dev(mmc
)),
1746 (host
->flags
& SDHCI_USE_ADMA
)?"A":"",
1747 (host
->flags
& SDHCI_USE_DMA
)?"DMA":"PIO");
1751 #ifdef SDHCI_USE_LEDS_CLASS
1753 sdhci_reset(host
, SDHCI_RESET_ALL
);
1754 free_irq(host
->irq
, host
);
1757 tasklet_kill(&host
->card_tasklet
);
1758 tasklet_kill(&host
->finish_tasklet
);
1763 EXPORT_SYMBOL_GPL(sdhci_add_host
);
1765 void sdhci_remove_host(struct sdhci_host
*host
, int dead
)
1767 unsigned long flags
;
1770 spin_lock_irqsave(&host
->lock
, flags
);
1772 host
->flags
|= SDHCI_DEVICE_DEAD
;
1775 printk(KERN_ERR
"%s: Controller removed during "
1776 " transfer!\n", mmc_hostname(host
->mmc
));
1778 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1779 tasklet_schedule(&host
->finish_tasklet
);
1782 spin_unlock_irqrestore(&host
->lock
, flags
);
1785 mmc_remove_host(host
->mmc
);
1787 #ifdef SDHCI_USE_LEDS_CLASS
1788 led_classdev_unregister(&host
->led
);
1792 sdhci_reset(host
, SDHCI_RESET_ALL
);
1794 free_irq(host
->irq
, host
);
1796 del_timer_sync(&host
->timer
);
1798 tasklet_kill(&host
->card_tasklet
);
1799 tasklet_kill(&host
->finish_tasklet
);
1801 kfree(host
->adma_desc
);
1802 kfree(host
->align_buffer
);
1804 host
->adma_desc
= NULL
;
1805 host
->align_buffer
= NULL
;
1808 EXPORT_SYMBOL_GPL(sdhci_remove_host
);
1810 void sdhci_free_host(struct sdhci_host
*host
)
1812 mmc_free_host(host
->mmc
);
1815 EXPORT_SYMBOL_GPL(sdhci_free_host
);
1817 /*****************************************************************************\
1819 * Driver init/exit *
1821 \*****************************************************************************/
1823 static int __init
sdhci_drv_init(void)
1825 printk(KERN_INFO DRIVER_NAME
1826 ": Secure Digital Host Controller Interface driver\n");
1827 printk(KERN_INFO DRIVER_NAME
": Copyright(c) Pierre Ossman\n");
1832 static void __exit
sdhci_drv_exit(void)
1836 module_init(sdhci_drv_init
);
1837 module_exit(sdhci_drv_exit
);
1839 module_param(debug_quirks
, uint
, 0444);
1841 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1842 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
1843 MODULE_LICENSE("GPL");
1845 MODULE_PARM_DESC(debug_quirks
, "Force certain quirks.");