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TOMOYO: Fix wrong domainname validation.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mmc / host / sdhci-pci.c
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/pci.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/slab.h>
20 #include <linux/device.h>
21
22 #include <linux/mmc/host.h>
23
24 #include <asm/scatterlist.h>
25 #include <asm/io.h>
26
27 #include "sdhci.h"
28
29 /*
30 * PCI registers
31 */
32
33 #define PCI_SDHCI_IFPIO 0x00
34 #define PCI_SDHCI_IFDMA 0x01
35 #define PCI_SDHCI_IFVENDOR 0x02
36
37 #define PCI_SLOT_INFO 0x40 /* 8 bits */
38 #define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
39 #define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
40
41 #define MAX_SLOTS 8
42
43 struct sdhci_pci_chip;
44 struct sdhci_pci_slot;
45
46 struct sdhci_pci_fixes {
47 unsigned int quirks;
48
49 int (*probe)(struct sdhci_pci_chip*);
50
51 int (*probe_slot)(struct sdhci_pci_slot*);
52 void (*remove_slot)(struct sdhci_pci_slot*, int);
53
54 int (*suspend)(struct sdhci_pci_chip*,
55 pm_message_t);
56 int (*resume)(struct sdhci_pci_chip*);
57 };
58
59 struct sdhci_pci_slot {
60 struct sdhci_pci_chip *chip;
61 struct sdhci_host *host;
62
63 int pci_bar;
64 };
65
66 struct sdhci_pci_chip {
67 struct pci_dev *pdev;
68
69 unsigned int quirks;
70 const struct sdhci_pci_fixes *fixes;
71
72 int num_slots; /* Slots on controller */
73 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
74 };
75
76
77 /*****************************************************************************\
78 * *
79 * Hardware specific quirk handling *
80 * *
81 \*****************************************************************************/
82
83 static int ricoh_probe(struct sdhci_pci_chip *chip)
84 {
85 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
86 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
87 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
88 return 0;
89 }
90
91 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
92 {
93 slot->host->caps =
94 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
95 & SDHCI_TIMEOUT_CLK_MASK) |
96
97 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
98 & SDHCI_CLOCK_BASE_MASK) |
99
100 SDHCI_TIMEOUT_CLK_UNIT |
101 SDHCI_CAN_VDD_330 |
102 SDHCI_CAN_DO_SDMA;
103 return 0;
104 }
105
106 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
107 {
108 /* Apply a delay to allow controller to settle */
109 /* Otherwise it becomes confused if card state changed
110 during suspend */
111 msleep(500);
112 return 0;
113 }
114
115 static const struct sdhci_pci_fixes sdhci_ricoh = {
116 .probe = ricoh_probe,
117 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
118 SDHCI_QUIRK_FORCE_DMA |
119 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
120 };
121
122 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
123 .probe_slot = ricoh_mmc_probe_slot,
124 .resume = ricoh_mmc_resume,
125 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
126 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
127 SDHCI_QUIRK_NO_CARD_NO_RESET |
128 SDHCI_QUIRK_MISSING_CAPS
129 };
130
131 static const struct sdhci_pci_fixes sdhci_ene_712 = {
132 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
133 SDHCI_QUIRK_BROKEN_DMA,
134 };
135
136 static const struct sdhci_pci_fixes sdhci_ene_714 = {
137 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
138 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
139 SDHCI_QUIRK_BROKEN_DMA,
140 };
141
142 static const struct sdhci_pci_fixes sdhci_cafe = {
143 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
144 SDHCI_QUIRK_NO_BUSY_IRQ |
145 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
146 };
147
148 /*
149 * ADMA operation is disabled for Moorestown platform due to
150 * hardware bugs.
151 */
152 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
153 {
154 /*
155 * slots number is fixed here for MRST as SDIO3/5 are never used and
156 * have hardware bugs.
157 */
158 chip->num_slots = 1;
159 return 0;
160 }
161
162 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
163 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
164 };
165
166 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
167 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
168 .probe = mrst_hc_probe,
169 };
170
171 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
172 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
173 };
174
175 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc_sdio = {
176 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
177 };
178
179 /* O2Micro extra registers */
180 #define O2_SD_LOCK_WP 0xD3
181 #define O2_SD_MULTI_VCC3V 0xEE
182 #define O2_SD_CLKREQ 0xEC
183 #define O2_SD_CAPS 0xE0
184 #define O2_SD_ADMA1 0xE2
185 #define O2_SD_ADMA2 0xE7
186 #define O2_SD_INF_MOD 0xF1
187
188 static int o2_probe(struct sdhci_pci_chip *chip)
189 {
190 int ret;
191 u8 scratch;
192
193 switch (chip->pdev->device) {
194 case PCI_DEVICE_ID_O2_8220:
195 case PCI_DEVICE_ID_O2_8221:
196 case PCI_DEVICE_ID_O2_8320:
197 case PCI_DEVICE_ID_O2_8321:
198 /* This extra setup is required due to broken ADMA. */
199 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
200 if (ret)
201 return ret;
202 scratch &= 0x7f;
203 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
204
205 /* Set Multi 3 to VCC3V# */
206 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
207
208 /* Disable CLK_REQ# support after media DET */
209 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
210 if (ret)
211 return ret;
212 scratch |= 0x20;
213 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
214
215 /* Choose capabilities, enable SDMA. We have to write 0x01
216 * to the capabilities register first to unlock it.
217 */
218 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
219 if (ret)
220 return ret;
221 scratch |= 0x01;
222 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
223 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
224
225 /* Disable ADMA1/2 */
226 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
227 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
228
229 /* Disable the infinite transfer mode */
230 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
231 if (ret)
232 return ret;
233 scratch |= 0x08;
234 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
235
236 /* Lock WP */
237 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
238 if (ret)
239 return ret;
240 scratch |= 0x80;
241 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
242 }
243
244 return 0;
245 }
246
247 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
248 {
249 u8 scratch;
250 int ret;
251
252 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
253 if (ret)
254 return ret;
255
256 /*
257 * Turn PMOS on [bit 0], set over current detection to 2.4 V
258 * [bit 1:2] and enable over current debouncing [bit 6].
259 */
260 if (on)
261 scratch |= 0x47;
262 else
263 scratch &= ~0x47;
264
265 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
266 if (ret)
267 return ret;
268
269 return 0;
270 }
271
272 static int jmicron_probe(struct sdhci_pci_chip *chip)
273 {
274 int ret;
275 u16 mmcdev = 0;
276
277 if (chip->pdev->revision == 0) {
278 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
279 SDHCI_QUIRK_32BIT_DMA_SIZE |
280 SDHCI_QUIRK_32BIT_ADMA_SIZE |
281 SDHCI_QUIRK_RESET_AFTER_REQUEST |
282 SDHCI_QUIRK_BROKEN_SMALL_PIO;
283 }
284
285 /*
286 * JMicron chips can have two interfaces to the same hardware
287 * in order to work around limitations in Microsoft's driver.
288 * We need to make sure we only bind to one of them.
289 *
290 * This code assumes two things:
291 *
292 * 1. The PCI code adds subfunctions in order.
293 *
294 * 2. The MMC interface has a lower subfunction number
295 * than the SD interface.
296 */
297 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
298 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
299 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
300 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
301
302 if (mmcdev) {
303 struct pci_dev *sd_dev;
304
305 sd_dev = NULL;
306 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
307 mmcdev, sd_dev)) != NULL) {
308 if ((PCI_SLOT(chip->pdev->devfn) ==
309 PCI_SLOT(sd_dev->devfn)) &&
310 (chip->pdev->bus == sd_dev->bus))
311 break;
312 }
313
314 if (sd_dev) {
315 pci_dev_put(sd_dev);
316 dev_info(&chip->pdev->dev, "Refusing to bind to "
317 "secondary interface.\n");
318 return -ENODEV;
319 }
320 }
321
322 /*
323 * JMicron chips need a bit of a nudge to enable the power
324 * output pins.
325 */
326 ret = jmicron_pmos(chip, 1);
327 if (ret) {
328 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
329 return ret;
330 }
331
332 return 0;
333 }
334
335 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
336 {
337 u8 scratch;
338
339 scratch = readb(host->ioaddr + 0xC0);
340
341 if (on)
342 scratch |= 0x01;
343 else
344 scratch &= ~0x01;
345
346 writeb(scratch, host->ioaddr + 0xC0);
347 }
348
349 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
350 {
351 if (slot->chip->pdev->revision == 0) {
352 u16 version;
353
354 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
355 version = (version & SDHCI_VENDOR_VER_MASK) >>
356 SDHCI_VENDOR_VER_SHIFT;
357
358 /*
359 * Older versions of the chip have lots of nasty glitches
360 * in the ADMA engine. It's best just to avoid it
361 * completely.
362 */
363 if (version < 0xAC)
364 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
365 }
366
367 /* JM388 MMC doesn't support 1.8V while SD supports it */
368 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
369 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
370 MMC_VDD_29_30 | MMC_VDD_30_31 |
371 MMC_VDD_165_195; /* allow 1.8V */
372 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
373 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
374 }
375
376 /*
377 * The secondary interface requires a bit set to get the
378 * interrupts.
379 */
380 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
381 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
382 jmicron_enable_mmc(slot->host, 1);
383
384 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
385
386 return 0;
387 }
388
389 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
390 {
391 if (dead)
392 return;
393
394 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
395 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
396 jmicron_enable_mmc(slot->host, 0);
397 }
398
399 static int jmicron_suspend(struct sdhci_pci_chip *chip, pm_message_t state)
400 {
401 int i;
402
403 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
404 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
405 for (i = 0;i < chip->num_slots;i++)
406 jmicron_enable_mmc(chip->slots[i]->host, 0);
407 }
408
409 return 0;
410 }
411
412 static int jmicron_resume(struct sdhci_pci_chip *chip)
413 {
414 int ret, i;
415
416 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
417 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
418 for (i = 0;i < chip->num_slots;i++)
419 jmicron_enable_mmc(chip->slots[i]->host, 1);
420 }
421
422 ret = jmicron_pmos(chip, 1);
423 if (ret) {
424 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
425 return ret;
426 }
427
428 return 0;
429 }
430
431 static const struct sdhci_pci_fixes sdhci_o2 = {
432 .probe = o2_probe,
433 };
434
435 static const struct sdhci_pci_fixes sdhci_jmicron = {
436 .probe = jmicron_probe,
437
438 .probe_slot = jmicron_probe_slot,
439 .remove_slot = jmicron_remove_slot,
440
441 .suspend = jmicron_suspend,
442 .resume = jmicron_resume,
443 };
444
445 /* SysKonnect CardBus2SDIO extra registers */
446 #define SYSKT_CTRL 0x200
447 #define SYSKT_RDFIFO_STAT 0x204
448 #define SYSKT_WRFIFO_STAT 0x208
449 #define SYSKT_POWER_DATA 0x20c
450 #define SYSKT_POWER_330 0xef
451 #define SYSKT_POWER_300 0xf8
452 #define SYSKT_POWER_184 0xcc
453 #define SYSKT_POWER_CMD 0x20d
454 #define SYSKT_POWER_START (1 << 7)
455 #define SYSKT_POWER_STATUS 0x20e
456 #define SYSKT_POWER_STATUS_OK (1 << 0)
457 #define SYSKT_BOARD_REV 0x210
458 #define SYSKT_CHIP_REV 0x211
459 #define SYSKT_CONF_DATA 0x212
460 #define SYSKT_CONF_DATA_1V8 (1 << 2)
461 #define SYSKT_CONF_DATA_2V5 (1 << 1)
462 #define SYSKT_CONF_DATA_3V3 (1 << 0)
463
464 static int syskt_probe(struct sdhci_pci_chip *chip)
465 {
466 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
467 chip->pdev->class &= ~0x0000FF;
468 chip->pdev->class |= PCI_SDHCI_IFDMA;
469 }
470 return 0;
471 }
472
473 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
474 {
475 int tm, ps;
476
477 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
478 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
479 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
480 "board rev %d.%d, chip rev %d.%d\n",
481 board_rev >> 4, board_rev & 0xf,
482 chip_rev >> 4, chip_rev & 0xf);
483 if (chip_rev >= 0x20)
484 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
485
486 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
487 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
488 udelay(50);
489 tm = 10; /* Wait max 1 ms */
490 do {
491 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
492 if (ps & SYSKT_POWER_STATUS_OK)
493 break;
494 udelay(100);
495 } while (--tm);
496 if (!tm) {
497 dev_err(&slot->chip->pdev->dev,
498 "power regulator never stabilized");
499 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
500 return -ENODEV;
501 }
502
503 return 0;
504 }
505
506 static const struct sdhci_pci_fixes sdhci_syskt = {
507 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
508 .probe = syskt_probe,
509 .probe_slot = syskt_probe_slot,
510 };
511
512 static int via_probe(struct sdhci_pci_chip *chip)
513 {
514 if (chip->pdev->revision == 0x10)
515 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
516
517 return 0;
518 }
519
520 static const struct sdhci_pci_fixes sdhci_via = {
521 .probe = via_probe,
522 };
523
524 static const struct pci_device_id pci_ids[] __devinitdata = {
525 {
526 .vendor = PCI_VENDOR_ID_RICOH,
527 .device = PCI_DEVICE_ID_RICOH_R5C822,
528 .subvendor = PCI_ANY_ID,
529 .subdevice = PCI_ANY_ID,
530 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
531 },
532
533 {
534 .vendor = PCI_VENDOR_ID_RICOH,
535 .device = 0x843,
536 .subvendor = PCI_ANY_ID,
537 .subdevice = PCI_ANY_ID,
538 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
539 },
540
541 {
542 .vendor = PCI_VENDOR_ID_RICOH,
543 .device = 0xe822,
544 .subvendor = PCI_ANY_ID,
545 .subdevice = PCI_ANY_ID,
546 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
547 },
548
549 {
550 .vendor = PCI_VENDOR_ID_RICOH,
551 .device = 0xe823,
552 .subvendor = PCI_ANY_ID,
553 .subdevice = PCI_ANY_ID,
554 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
555 },
556
557 {
558 .vendor = PCI_VENDOR_ID_ENE,
559 .device = PCI_DEVICE_ID_ENE_CB712_SD,
560 .subvendor = PCI_ANY_ID,
561 .subdevice = PCI_ANY_ID,
562 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
563 },
564
565 {
566 .vendor = PCI_VENDOR_ID_ENE,
567 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
568 .subvendor = PCI_ANY_ID,
569 .subdevice = PCI_ANY_ID,
570 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
571 },
572
573 {
574 .vendor = PCI_VENDOR_ID_ENE,
575 .device = PCI_DEVICE_ID_ENE_CB714_SD,
576 .subvendor = PCI_ANY_ID,
577 .subdevice = PCI_ANY_ID,
578 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
579 },
580
581 {
582 .vendor = PCI_VENDOR_ID_ENE,
583 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
584 .subvendor = PCI_ANY_ID,
585 .subdevice = PCI_ANY_ID,
586 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
587 },
588
589 {
590 .vendor = PCI_VENDOR_ID_MARVELL,
591 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
592 .subvendor = PCI_ANY_ID,
593 .subdevice = PCI_ANY_ID,
594 .driver_data = (kernel_ulong_t)&sdhci_cafe,
595 },
596
597 {
598 .vendor = PCI_VENDOR_ID_JMICRON,
599 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
600 .subvendor = PCI_ANY_ID,
601 .subdevice = PCI_ANY_ID,
602 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
603 },
604
605 {
606 .vendor = PCI_VENDOR_ID_JMICRON,
607 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
608 .subvendor = PCI_ANY_ID,
609 .subdevice = PCI_ANY_ID,
610 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
611 },
612
613 {
614 .vendor = PCI_VENDOR_ID_JMICRON,
615 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
616 .subvendor = PCI_ANY_ID,
617 .subdevice = PCI_ANY_ID,
618 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
619 },
620
621 {
622 .vendor = PCI_VENDOR_ID_JMICRON,
623 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
624 .subvendor = PCI_ANY_ID,
625 .subdevice = PCI_ANY_ID,
626 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
627 },
628
629 {
630 .vendor = PCI_VENDOR_ID_SYSKONNECT,
631 .device = 0x8000,
632 .subvendor = PCI_ANY_ID,
633 .subdevice = PCI_ANY_ID,
634 .driver_data = (kernel_ulong_t)&sdhci_syskt,
635 },
636
637 {
638 .vendor = PCI_VENDOR_ID_VIA,
639 .device = 0x95d0,
640 .subvendor = PCI_ANY_ID,
641 .subdevice = PCI_ANY_ID,
642 .driver_data = (kernel_ulong_t)&sdhci_via,
643 },
644
645 {
646 .vendor = PCI_VENDOR_ID_INTEL,
647 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
648 .subvendor = PCI_ANY_ID,
649 .subdevice = PCI_ANY_ID,
650 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
651 },
652
653 {
654 .vendor = PCI_VENDOR_ID_INTEL,
655 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
656 .subvendor = PCI_ANY_ID,
657 .subdevice = PCI_ANY_ID,
658 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
659 },
660
661 {
662 .vendor = PCI_VENDOR_ID_INTEL,
663 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
664 .subvendor = PCI_ANY_ID,
665 .subdevice = PCI_ANY_ID,
666 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
667 },
668
669 {
670 .vendor = PCI_VENDOR_ID_INTEL,
671 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
672 .subvendor = PCI_ANY_ID,
673 .subdevice = PCI_ANY_ID,
674 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
675 },
676
677 {
678 .vendor = PCI_VENDOR_ID_INTEL,
679 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
680 .subvendor = PCI_ANY_ID,
681 .subdevice = PCI_ANY_ID,
682 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
683 },
684
685 {
686 .vendor = PCI_VENDOR_ID_INTEL,
687 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
688 .subvendor = PCI_ANY_ID,
689 .subdevice = PCI_ANY_ID,
690 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
691 },
692
693 {
694 .vendor = PCI_VENDOR_ID_INTEL,
695 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
696 .subvendor = PCI_ANY_ID,
697 .subdevice = PCI_ANY_ID,
698 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
699 },
700
701 {
702 .vendor = PCI_VENDOR_ID_INTEL,
703 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
704 .subvendor = PCI_ANY_ID,
705 .subdevice = PCI_ANY_ID,
706 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio,
707 },
708
709 {
710 .vendor = PCI_VENDOR_ID_O2,
711 .device = PCI_DEVICE_ID_O2_8120,
712 .subvendor = PCI_ANY_ID,
713 .subdevice = PCI_ANY_ID,
714 .driver_data = (kernel_ulong_t)&sdhci_o2,
715 },
716
717 {
718 .vendor = PCI_VENDOR_ID_O2,
719 .device = PCI_DEVICE_ID_O2_8220,
720 .subvendor = PCI_ANY_ID,
721 .subdevice = PCI_ANY_ID,
722 .driver_data = (kernel_ulong_t)&sdhci_o2,
723 },
724
725 {
726 .vendor = PCI_VENDOR_ID_O2,
727 .device = PCI_DEVICE_ID_O2_8221,
728 .subvendor = PCI_ANY_ID,
729 .subdevice = PCI_ANY_ID,
730 .driver_data = (kernel_ulong_t)&sdhci_o2,
731 },
732
733 {
734 .vendor = PCI_VENDOR_ID_O2,
735 .device = PCI_DEVICE_ID_O2_8320,
736 .subvendor = PCI_ANY_ID,
737 .subdevice = PCI_ANY_ID,
738 .driver_data = (kernel_ulong_t)&sdhci_o2,
739 },
740
741 {
742 .vendor = PCI_VENDOR_ID_O2,
743 .device = PCI_DEVICE_ID_O2_8321,
744 .subvendor = PCI_ANY_ID,
745 .subdevice = PCI_ANY_ID,
746 .driver_data = (kernel_ulong_t)&sdhci_o2,
747 },
748
749 { /* Generic SD host controller */
750 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
751 },
752
753 { /* end: all zeroes */ },
754 };
755
756 MODULE_DEVICE_TABLE(pci, pci_ids);
757
758 /*****************************************************************************\
759 * *
760 * SDHCI core callbacks *
761 * *
762 \*****************************************************************************/
763
764 static int sdhci_pci_enable_dma(struct sdhci_host *host)
765 {
766 struct sdhci_pci_slot *slot;
767 struct pci_dev *pdev;
768 int ret;
769
770 slot = sdhci_priv(host);
771 pdev = slot->chip->pdev;
772
773 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
774 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
775 (host->flags & SDHCI_USE_SDMA)) {
776 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
777 "doesn't fully claim to support it.\n");
778 }
779
780 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
781 if (ret)
782 return ret;
783
784 pci_set_master(pdev);
785
786 return 0;
787 }
788
789 static struct sdhci_ops sdhci_pci_ops = {
790 .enable_dma = sdhci_pci_enable_dma,
791 };
792
793 /*****************************************************************************\
794 * *
795 * Suspend/resume *
796 * *
797 \*****************************************************************************/
798
799 #ifdef CONFIG_PM
800
801 static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state)
802 {
803 struct sdhci_pci_chip *chip;
804 struct sdhci_pci_slot *slot;
805 mmc_pm_flag_t slot_pm_flags;
806 mmc_pm_flag_t pm_flags = 0;
807 int i, ret;
808
809 chip = pci_get_drvdata(pdev);
810 if (!chip)
811 return 0;
812
813 for (i = 0;i < chip->num_slots;i++) {
814 slot = chip->slots[i];
815 if (!slot)
816 continue;
817
818 ret = sdhci_suspend_host(slot->host, state);
819
820 if (ret) {
821 for (i--;i >= 0;i--)
822 sdhci_resume_host(chip->slots[i]->host);
823 return ret;
824 }
825
826 slot_pm_flags = slot->host->mmc->pm_flags;
827 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
828 sdhci_enable_irq_wakeups(slot->host);
829
830 pm_flags |= slot_pm_flags;
831 }
832
833 if (chip->fixes && chip->fixes->suspend) {
834 ret = chip->fixes->suspend(chip, state);
835 if (ret) {
836 for (i = chip->num_slots - 1;i >= 0;i--)
837 sdhci_resume_host(chip->slots[i]->host);
838 return ret;
839 }
840 }
841
842 pci_save_state(pdev);
843 if (pm_flags & MMC_PM_KEEP_POWER) {
844 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
845 pci_pme_active(pdev, true);
846 pci_enable_wake(pdev, PCI_D3hot, 1);
847 }
848 pci_set_power_state(pdev, PCI_D3hot);
849 } else {
850 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
851 pci_disable_device(pdev);
852 pci_set_power_state(pdev, pci_choose_state(pdev, state));
853 }
854
855 return 0;
856 }
857
858 static int sdhci_pci_resume (struct pci_dev *pdev)
859 {
860 struct sdhci_pci_chip *chip;
861 struct sdhci_pci_slot *slot;
862 int i, ret;
863
864 chip = pci_get_drvdata(pdev);
865 if (!chip)
866 return 0;
867
868 pci_set_power_state(pdev, PCI_D0);
869 pci_restore_state(pdev);
870 ret = pci_enable_device(pdev);
871 if (ret)
872 return ret;
873
874 if (chip->fixes && chip->fixes->resume) {
875 ret = chip->fixes->resume(chip);
876 if (ret)
877 return ret;
878 }
879
880 for (i = 0;i < chip->num_slots;i++) {
881 slot = chip->slots[i];
882 if (!slot)
883 continue;
884
885 ret = sdhci_resume_host(slot->host);
886 if (ret)
887 return ret;
888 }
889
890 return 0;
891 }
892
893 #else /* CONFIG_PM */
894
895 #define sdhci_pci_suspend NULL
896 #define sdhci_pci_resume NULL
897
898 #endif /* CONFIG_PM */
899
900 /*****************************************************************************\
901 * *
902 * Device probing/removal *
903 * *
904 \*****************************************************************************/
905
906 static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
907 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int bar)
908 {
909 struct sdhci_pci_slot *slot;
910 struct sdhci_host *host;
911 int ret;
912
913 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
914 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
915 return ERR_PTR(-ENODEV);
916 }
917
918 if (pci_resource_len(pdev, bar) != 0x100) {
919 dev_err(&pdev->dev, "Invalid iomem size. You may "
920 "experience problems.\n");
921 }
922
923 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
924 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
925 return ERR_PTR(-ENODEV);
926 }
927
928 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
929 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
930 return ERR_PTR(-ENODEV);
931 }
932
933 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
934 if (IS_ERR(host)) {
935 dev_err(&pdev->dev, "cannot allocate host\n");
936 return ERR_CAST(host);
937 }
938
939 slot = sdhci_priv(host);
940
941 slot->chip = chip;
942 slot->host = host;
943 slot->pci_bar = bar;
944
945 host->hw_name = "PCI";
946 host->ops = &sdhci_pci_ops;
947 host->quirks = chip->quirks;
948
949 host->irq = pdev->irq;
950
951 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
952 if (ret) {
953 dev_err(&pdev->dev, "cannot request region\n");
954 goto free;
955 }
956
957 host->ioaddr = pci_ioremap_bar(pdev, bar);
958 if (!host->ioaddr) {
959 dev_err(&pdev->dev, "failed to remap registers\n");
960 goto release;
961 }
962
963 if (chip->fixes && chip->fixes->probe_slot) {
964 ret = chip->fixes->probe_slot(slot);
965 if (ret)
966 goto unmap;
967 }
968
969 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
970
971 ret = sdhci_add_host(host);
972 if (ret)
973 goto remove;
974
975 return slot;
976
977 remove:
978 if (chip->fixes && chip->fixes->remove_slot)
979 chip->fixes->remove_slot(slot, 0);
980
981 unmap:
982 iounmap(host->ioaddr);
983
984 release:
985 pci_release_region(pdev, bar);
986
987 free:
988 sdhci_free_host(host);
989
990 return ERR_PTR(ret);
991 }
992
993 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
994 {
995 int dead;
996 u32 scratch;
997
998 dead = 0;
999 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1000 if (scratch == (u32)-1)
1001 dead = 1;
1002
1003 sdhci_remove_host(slot->host, dead);
1004
1005 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1006 slot->chip->fixes->remove_slot(slot, dead);
1007
1008 pci_release_region(slot->chip->pdev, slot->pci_bar);
1009
1010 sdhci_free_host(slot->host);
1011 }
1012
1013 static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
1014 const struct pci_device_id *ent)
1015 {
1016 struct sdhci_pci_chip *chip;
1017 struct sdhci_pci_slot *slot;
1018
1019 u8 slots, first_bar;
1020 int ret, i;
1021
1022 BUG_ON(pdev == NULL);
1023 BUG_ON(ent == NULL);
1024
1025 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1026 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1027
1028 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1029 if (ret)
1030 return ret;
1031
1032 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1033 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1034 if (slots == 0)
1035 return -ENODEV;
1036
1037 BUG_ON(slots > MAX_SLOTS);
1038
1039 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1040 if (ret)
1041 return ret;
1042
1043 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1044
1045 if (first_bar > 5) {
1046 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1047 return -ENODEV;
1048 }
1049
1050 ret = pci_enable_device(pdev);
1051 if (ret)
1052 return ret;
1053
1054 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1055 if (!chip) {
1056 ret = -ENOMEM;
1057 goto err;
1058 }
1059
1060 chip->pdev = pdev;
1061 chip->fixes = (const struct sdhci_pci_fixes*)ent->driver_data;
1062 if (chip->fixes)
1063 chip->quirks = chip->fixes->quirks;
1064 chip->num_slots = slots;
1065
1066 pci_set_drvdata(pdev, chip);
1067
1068 if (chip->fixes && chip->fixes->probe) {
1069 ret = chip->fixes->probe(chip);
1070 if (ret)
1071 goto free;
1072 }
1073
1074 slots = chip->num_slots; /* Quirk may have changed this */
1075
1076 for (i = 0;i < slots;i++) {
1077 slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i);
1078 if (IS_ERR(slot)) {
1079 for (i--;i >= 0;i--)
1080 sdhci_pci_remove_slot(chip->slots[i]);
1081 ret = PTR_ERR(slot);
1082 goto free;
1083 }
1084
1085 chip->slots[i] = slot;
1086 }
1087
1088 return 0;
1089
1090 free:
1091 pci_set_drvdata(pdev, NULL);
1092 kfree(chip);
1093
1094 err:
1095 pci_disable_device(pdev);
1096 return ret;
1097 }
1098
1099 static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
1100 {
1101 int i;
1102 struct sdhci_pci_chip *chip;
1103
1104 chip = pci_get_drvdata(pdev);
1105
1106 if (chip) {
1107 for (i = 0;i < chip->num_slots; i++)
1108 sdhci_pci_remove_slot(chip->slots[i]);
1109
1110 pci_set_drvdata(pdev, NULL);
1111 kfree(chip);
1112 }
1113
1114 pci_disable_device(pdev);
1115 }
1116
1117 static struct pci_driver sdhci_driver = {
1118 .name = "sdhci-pci",
1119 .id_table = pci_ids,
1120 .probe = sdhci_pci_probe,
1121 .remove = __devexit_p(sdhci_pci_remove),
1122 .suspend = sdhci_pci_suspend,
1123 .resume = sdhci_pci_resume,
1124 };
1125
1126 /*****************************************************************************\
1127 * *
1128 * Driver init/exit *
1129 * *
1130 \*****************************************************************************/
1131
1132 static int __init sdhci_drv_init(void)
1133 {
1134 return pci_register_driver(&sdhci_driver);
1135 }
1136
1137 static void __exit sdhci_drv_exit(void)
1138 {
1139 pci_unregister_driver(&sdhci_driver);
1140 }
1141
1142 module_init(sdhci_drv_init);
1143 module_exit(sdhci_drv_exit);
1144
1145 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1146 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1147 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)