2 * Atmel SDMMC controller driver.
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
21 #include <linux/kernel.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/slot-gpio.h>
24 #include <linux/module.h>
26 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
30 #include "sdhci-pltfm.h"
32 #define SDMMC_MC1R 0x204
33 #define SDMMC_MC1R_DDR BIT(3)
34 #define SDMMC_MC1R_FCD BIT(7)
35 #define SDMMC_CACR 0x230
36 #define SDMMC_CACR_CAPWREN BIT(0)
37 #define SDMMC_CACR_KEY (0x46 << 8)
39 #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */
41 struct sdhci_at91_priv
{
48 static void sdhci_at91_set_force_card_detect(struct sdhci_host
*host
)
52 mc1r
= readb(host
->ioaddr
+ SDMMC_MC1R
);
53 mc1r
|= SDMMC_MC1R_FCD
;
54 writeb(mc1r
, host
->ioaddr
+ SDMMC_MC1R
);
57 static void sdhci_at91_set_clock(struct sdhci_host
*host
, unsigned int clock
)
60 unsigned long timeout
;
62 host
->mmc
->actual_clock
= 0;
65 * There is no requirement to disable the internal clock before
66 * changing the SD clock configuration. Moreover, disabling the
67 * internal clock, changing the configuration and re-enabling the
68 * internal clock causes some bugs. It can prevent to get the internal
69 * clock stable flag ready and an unexpected switch to the base clock
72 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
73 clk
&= SDHCI_CLOCK_INT_EN
;
74 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
79 clk
= sdhci_calc_clk(host
, clock
, &host
->mmc
->actual_clock
);
81 clk
|= SDHCI_CLOCK_INT_EN
;
82 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
86 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
87 & SDHCI_CLOCK_INT_STABLE
)) {
89 pr_err("%s: Internal clock never stabilised.\n",
90 mmc_hostname(host
->mmc
));
97 clk
|= SDHCI_CLOCK_CARD_EN
;
98 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
102 * In this specific implementation of the SDHCI controller, the power register
103 * needs to have a valid voltage set even when the power supply is managed by
104 * an external regulator.
106 static void sdhci_at91_set_power(struct sdhci_host
*host
, unsigned char mode
,
109 if (!IS_ERR(host
->mmc
->supply
.vmmc
)) {
110 struct mmc_host
*mmc
= host
->mmc
;
112 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, vdd
);
114 sdhci_set_power_noreg(host
, mode
, vdd
);
117 void sdhci_at91_set_uhs_signaling(struct sdhci_host
*host
, unsigned int timing
)
119 if (timing
== MMC_TIMING_MMC_DDR52
)
120 sdhci_writeb(host
, SDMMC_MC1R_DDR
, SDMMC_MC1R
);
121 sdhci_set_uhs_signaling(host
, timing
);
124 static void sdhci_at91_reset(struct sdhci_host
*host
, u8 mask
)
126 sdhci_reset(host
, mask
);
128 if (host
->mmc
->caps
& MMC_CAP_NONREMOVABLE
)
129 sdhci_at91_set_force_card_detect(host
);
132 static const struct sdhci_ops sdhci_at91_sama5d2_ops
= {
133 .set_clock
= sdhci_at91_set_clock
,
134 .set_bus_width
= sdhci_set_bus_width
,
135 .reset
= sdhci_at91_reset
,
136 .set_uhs_signaling
= sdhci_at91_set_uhs_signaling
,
137 .set_power
= sdhci_at91_set_power
,
140 static const struct sdhci_pltfm_data soc_data_sama5d2
= {
141 .ops
= &sdhci_at91_sama5d2_ops
,
144 static const struct of_device_id sdhci_at91_dt_match
[] = {
145 { .compatible
= "atmel,sama5d2-sdhci", .data
= &soc_data_sama5d2
},
148 MODULE_DEVICE_TABLE(of
, sdhci_at91_dt_match
);
150 static int sdhci_at91_set_clks_presets(struct device
*dev
)
152 struct sdhci_host
*host
= dev_get_drvdata(dev
);
153 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
154 struct sdhci_at91_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
156 unsigned int caps0
, caps1
;
157 unsigned int clk_base
, clk_mul
;
158 unsigned int gck_rate
, real_gck_rate
;
159 unsigned int preset_div
;
162 * The mult clock is provided by as a generated clock by the PMC
163 * controller. In order to set the rate of gck, we have to get the
164 * base clock rate and the clock mult from capabilities.
166 clk_prepare_enable(priv
->hclock
);
167 caps0
= readl(host
->ioaddr
+ SDHCI_CAPABILITIES
);
168 caps1
= readl(host
->ioaddr
+ SDHCI_CAPABILITIES_1
);
169 clk_base
= (caps0
& SDHCI_CLOCK_V3_BASE_MASK
) >> SDHCI_CLOCK_BASE_SHIFT
;
170 clk_mul
= (caps1
& SDHCI_CLOCK_MUL_MASK
) >> SDHCI_CLOCK_MUL_SHIFT
;
171 gck_rate
= clk_base
* 1000000 * (clk_mul
+ 1);
172 ret
= clk_set_rate(priv
->gck
, gck_rate
);
174 dev_err(dev
, "failed to set gck");
175 clk_disable_unprepare(priv
->hclock
);
179 * We need to check if we have the requested rate for gck because in
180 * some cases this rate could be not supported. If it happens, the rate
181 * is the closest one gck can provide. We have to update the value
184 real_gck_rate
= clk_get_rate(priv
->gck
);
185 if (real_gck_rate
!= gck_rate
) {
186 clk_mul
= real_gck_rate
/ (clk_base
* 1000000) - 1;
187 caps1
&= (~SDHCI_CLOCK_MUL_MASK
);
188 caps1
|= ((clk_mul
<< SDHCI_CLOCK_MUL_SHIFT
) &
189 SDHCI_CLOCK_MUL_MASK
);
190 /* Set capabilities in r/w mode. */
191 writel(SDMMC_CACR_KEY
| SDMMC_CACR_CAPWREN
,
192 host
->ioaddr
+ SDMMC_CACR
);
193 writel(caps1
, host
->ioaddr
+ SDHCI_CAPABILITIES_1
);
194 /* Set capabilities in ro mode. */
195 writel(0, host
->ioaddr
+ SDMMC_CACR
);
196 dev_info(dev
, "update clk mul to %u as gck rate is %u Hz\n",
197 clk_mul
, real_gck_rate
);
201 * We have to set preset values because it depends on the clk_mul
202 * value. Moreover, SDR104 is supported in a degraded mode since the
203 * maximum sd clock value is 120 MHz instead of 208 MHz. For that
204 * reason, we need to use presets to support SDR104.
206 preset_div
= DIV_ROUND_UP(real_gck_rate
, 24000000) - 1;
207 writew(SDHCI_AT91_PRESET_COMMON_CONF
| preset_div
,
208 host
->ioaddr
+ SDHCI_PRESET_FOR_SDR12
);
209 preset_div
= DIV_ROUND_UP(real_gck_rate
, 50000000) - 1;
210 writew(SDHCI_AT91_PRESET_COMMON_CONF
| preset_div
,
211 host
->ioaddr
+ SDHCI_PRESET_FOR_SDR25
);
212 preset_div
= DIV_ROUND_UP(real_gck_rate
, 100000000) - 1;
213 writew(SDHCI_AT91_PRESET_COMMON_CONF
| preset_div
,
214 host
->ioaddr
+ SDHCI_PRESET_FOR_SDR50
);
215 preset_div
= DIV_ROUND_UP(real_gck_rate
, 120000000) - 1;
216 writew(SDHCI_AT91_PRESET_COMMON_CONF
| preset_div
,
217 host
->ioaddr
+ SDHCI_PRESET_FOR_SDR104
);
218 preset_div
= DIV_ROUND_UP(real_gck_rate
, 50000000) - 1;
219 writew(SDHCI_AT91_PRESET_COMMON_CONF
| preset_div
,
220 host
->ioaddr
+ SDHCI_PRESET_FOR_DDR50
);
222 clk_prepare_enable(priv
->mainck
);
223 clk_prepare_enable(priv
->gck
);
228 #ifdef CONFIG_PM_SLEEP
229 static int sdhci_at91_suspend(struct device
*dev
)
231 struct sdhci_host
*host
= dev_get_drvdata(dev
);
232 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
233 struct sdhci_at91_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
236 ret
= pm_runtime_force_suspend(dev
);
238 priv
->restore_needed
= true;
242 #endif /* CONFIG_PM_SLEEP */
245 static int sdhci_at91_runtime_suspend(struct device
*dev
)
247 struct sdhci_host
*host
= dev_get_drvdata(dev
);
248 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
249 struct sdhci_at91_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
252 ret
= sdhci_runtime_suspend_host(host
);
254 if (host
->tuning_mode
!= SDHCI_TUNING_MODE_3
)
255 mmc_retune_needed(host
->mmc
);
257 clk_disable_unprepare(priv
->gck
);
258 clk_disable_unprepare(priv
->hclock
);
259 clk_disable_unprepare(priv
->mainck
);
264 static int sdhci_at91_runtime_resume(struct device
*dev
)
266 struct sdhci_host
*host
= dev_get_drvdata(dev
);
267 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
268 struct sdhci_at91_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
271 if (priv
->restore_needed
) {
272 ret
= sdhci_at91_set_clks_presets(dev
);
276 priv
->restore_needed
= false;
280 ret
= clk_prepare_enable(priv
->mainck
);
282 dev_err(dev
, "can't enable mainck\n");
286 ret
= clk_prepare_enable(priv
->hclock
);
288 dev_err(dev
, "can't enable hclock\n");
292 ret
= clk_prepare_enable(priv
->gck
);
294 dev_err(dev
, "can't enable gck\n");
299 return sdhci_runtime_resume_host(host
);
301 #endif /* CONFIG_PM */
303 static const struct dev_pm_ops sdhci_at91_dev_pm_ops
= {
304 SET_SYSTEM_SLEEP_PM_OPS(sdhci_at91_suspend
, pm_runtime_force_resume
)
305 SET_RUNTIME_PM_OPS(sdhci_at91_runtime_suspend
,
306 sdhci_at91_runtime_resume
,
310 static int sdhci_at91_probe(struct platform_device
*pdev
)
312 const struct of_device_id
*match
;
313 const struct sdhci_pltfm_data
*soc_data
;
314 struct sdhci_host
*host
;
315 struct sdhci_pltfm_host
*pltfm_host
;
316 struct sdhci_at91_priv
*priv
;
319 match
= of_match_device(sdhci_at91_dt_match
, &pdev
->dev
);
322 soc_data
= match
->data
;
324 host
= sdhci_pltfm_init(pdev
, soc_data
, sizeof(*priv
));
326 return PTR_ERR(host
);
328 pltfm_host
= sdhci_priv(host
);
329 priv
= sdhci_pltfm_priv(pltfm_host
);
331 priv
->mainck
= devm_clk_get(&pdev
->dev
, "baseclk");
332 if (IS_ERR(priv
->mainck
)) {
333 dev_err(&pdev
->dev
, "failed to get baseclk\n");
334 return PTR_ERR(priv
->mainck
);
337 priv
->hclock
= devm_clk_get(&pdev
->dev
, "hclock");
338 if (IS_ERR(priv
->hclock
)) {
339 dev_err(&pdev
->dev
, "failed to get hclock\n");
340 return PTR_ERR(priv
->hclock
);
343 priv
->gck
= devm_clk_get(&pdev
->dev
, "multclk");
344 if (IS_ERR(priv
->gck
)) {
345 dev_err(&pdev
->dev
, "failed to get multclk\n");
346 return PTR_ERR(priv
->gck
);
349 ret
= sdhci_at91_set_clks_presets(&pdev
->dev
);
351 goto sdhci_pltfm_free
;
353 priv
->restore_needed
= false;
355 ret
= mmc_of_parse(host
->mmc
);
357 goto clocks_disable_unprepare
;
359 sdhci_get_of_property(pdev
);
361 pm_runtime_get_noresume(&pdev
->dev
);
362 pm_runtime_set_active(&pdev
->dev
);
363 pm_runtime_enable(&pdev
->dev
);
364 pm_runtime_set_autosuspend_delay(&pdev
->dev
, 50);
365 pm_runtime_use_autosuspend(&pdev
->dev
);
367 ret
= sdhci_add_host(host
);
369 goto pm_runtime_disable
;
372 * When calling sdhci_runtime_suspend_host(), the sdhci layer makes
373 * the assumption that all the clocks of the controller are disabled.
374 * It means we can't get irq from it when it is runtime suspended.
375 * For that reason, it is not planned to wake-up on a card detect irq
376 * from the controller.
377 * If we want to use runtime PM and to be able to wake-up on card
378 * insertion, we have to use a GPIO for the card detection or we can
379 * use polling. Be aware that using polling will resume/suspend the
380 * controller between each attempt.
381 * Disable SDHCI_QUIRK_BROKEN_CARD_DETECTION to be sure nobody tries
382 * to enable polling via device tree with broken-cd property.
384 if (mmc_card_is_removable(host
->mmc
) &&
385 mmc_gpio_get_cd(host
->mmc
) < 0) {
386 host
->mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
387 host
->quirks
&= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
391 * If the device attached to the MMC bus is not removable, it is safer
392 * to set the Force Card Detect bit. People often don't connect the
393 * card detect signal and use this pin for another purpose. If the card
394 * detect pin is not muxed to SDHCI controller, a default value is
395 * used. This value can be different from a SoC revision to another
396 * one. Problems come when this default value is not card present. To
397 * avoid this case, if the device is non removable then the card
398 * detection procedure using the SDMCC_CD signal is bypassed.
399 * This bit is reset when a software reset for all command is performed
400 * so we need to implement our own reset function to set back this bit.
402 if (host
->mmc
->caps
& MMC_CAP_NONREMOVABLE
)
403 sdhci_at91_set_force_card_detect(host
);
405 pm_runtime_put_autosuspend(&pdev
->dev
);
410 pm_runtime_disable(&pdev
->dev
);
411 pm_runtime_set_suspended(&pdev
->dev
);
412 pm_runtime_put_noidle(&pdev
->dev
);
413 clocks_disable_unprepare
:
414 clk_disable_unprepare(priv
->gck
);
415 clk_disable_unprepare(priv
->mainck
);
416 clk_disable_unprepare(priv
->hclock
);
418 sdhci_pltfm_free(pdev
);
422 static int sdhci_at91_remove(struct platform_device
*pdev
)
424 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
425 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
426 struct sdhci_at91_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
427 struct clk
*gck
= priv
->gck
;
428 struct clk
*hclock
= priv
->hclock
;
429 struct clk
*mainck
= priv
->mainck
;
431 pm_runtime_get_sync(&pdev
->dev
);
432 pm_runtime_disable(&pdev
->dev
);
433 pm_runtime_put_noidle(&pdev
->dev
);
435 sdhci_pltfm_unregister(pdev
);
437 clk_disable_unprepare(gck
);
438 clk_disable_unprepare(hclock
);
439 clk_disable_unprepare(mainck
);
444 static struct platform_driver sdhci_at91_driver
= {
446 .name
= "sdhci-at91",
447 .of_match_table
= sdhci_at91_dt_match
,
448 .pm
= &sdhci_at91_dev_pm_ops
,
450 .probe
= sdhci_at91_probe
,
451 .remove
= sdhci_at91_remove
,
454 module_platform_driver(sdhci_at91_driver
);
456 MODULE_DESCRIPTION("SDHCI driver for at91");
457 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
458 MODULE_LICENSE("GPL v2");