2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/delay.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/slab.h>
23 #include <linux/iopoll.h>
25 #include "sdhci-pltfm.h"
27 #define CORE_MCI_VERSION 0x50
28 #define CORE_VERSION_MAJOR_SHIFT 28
29 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
30 #define CORE_VERSION_MINOR_MASK 0xff
32 #define CORE_HC_MODE 0x78
33 #define HC_MODE_EN 0x1
34 #define CORE_POWER 0x0
35 #define CORE_SW_RST BIT(7)
36 #define FF_CLK_SW_RST_DIS BIT(13)
38 #define CORE_PWRCTL_STATUS 0xdc
39 #define CORE_PWRCTL_MASK 0xe0
40 #define CORE_PWRCTL_CLEAR 0xe4
41 #define CORE_PWRCTL_CTL 0xe8
42 #define CORE_PWRCTL_BUS_OFF BIT(0)
43 #define CORE_PWRCTL_BUS_ON BIT(1)
44 #define CORE_PWRCTL_IO_LOW BIT(2)
45 #define CORE_PWRCTL_IO_HIGH BIT(3)
46 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
47 #define CORE_PWRCTL_IO_SUCCESS BIT(2)
48 #define REQ_BUS_OFF BIT(0)
49 #define REQ_BUS_ON BIT(1)
50 #define REQ_IO_LOW BIT(2)
51 #define REQ_IO_HIGH BIT(3)
54 #define CORE_DLL_LOCK BIT(7)
55 #define CORE_DDR_DLL_LOCK BIT(11)
56 #define CORE_DLL_EN BIT(16)
57 #define CORE_CDR_EN BIT(17)
58 #define CORE_CK_OUT_EN BIT(18)
59 #define CORE_CDR_EXT_EN BIT(19)
60 #define CORE_DLL_PDN BIT(29)
61 #define CORE_DLL_RST BIT(30)
62 #define CORE_DLL_CONFIG 0x100
63 #define CORE_CMD_DAT_TRACK_SEL BIT(0)
64 #define CORE_DLL_STATUS 0x108
66 #define CORE_DLL_CONFIG_2 0x1b4
67 #define CORE_DDR_CAL_EN BIT(0)
68 #define CORE_FLL_CYCLE_CNT BIT(18)
69 #define CORE_DLL_CLOCK_DISABLE BIT(21)
71 #define CORE_VENDOR_SPEC 0x10c
72 #define CORE_VENDOR_SPEC_POR_VAL 0xa1c
73 #define CORE_CLK_PWRSAVE BIT(1)
74 #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
75 #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
76 #define CORE_HC_MCLK_SEL_MASK (3 << 8)
77 #define CORE_HC_SELECT_IN_EN BIT(18)
78 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
79 #define CORE_HC_SELECT_IN_MASK (7 << 19)
81 #define CORE_CSR_CDC_CTLR_CFG0 0x130
82 #define CORE_SW_TRIG_FULL_CALIB BIT(16)
83 #define CORE_HW_AUTOCAL_ENA BIT(17)
85 #define CORE_CSR_CDC_CTLR_CFG1 0x134
86 #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
87 #define CORE_TIMER_ENA BIT(16)
89 #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
90 #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
91 #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
92 #define CORE_CDC_OFFSET_CFG 0x14C
93 #define CORE_CSR_CDC_DELAY_CFG 0x150
94 #define CORE_CDC_SLAVE_DDA_CFG 0x160
95 #define CORE_CSR_CDC_STATUS0 0x164
96 #define CORE_CALIBRATION_DONE BIT(0)
98 #define CORE_CDC_ERROR_CODE_MASK 0x7000000
100 #define CORE_CSR_CDC_GEN_CFG 0x178
101 #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
102 #define CORE_CDC_SWITCH_RC_EN BIT(1)
104 #define CORE_DDR_200_CFG 0x184
105 #define CORE_CDC_T4_DLY_SEL BIT(0)
106 #define CORE_CMDIN_RCLK_EN BIT(1)
107 #define CORE_START_CDC_TRAFFIC BIT(6)
108 #define CORE_VENDOR_SPEC3 0x1b0
109 #define CORE_PWRSAVE_DLL BIT(3)
111 #define CORE_DDR_CONFIG 0x1b8
112 #define DDR_CONFIG_POR_VAL 0x80040853
114 #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
116 #define INVALID_TUNING_PHASE -1
117 #define SDHCI_MSM_MIN_CLOCK 400000
118 #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
120 #define CDR_SELEXT_SHIFT 20
121 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
122 #define CMUX_SHIFT_PHASE_SHIFT 24
123 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
125 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
126 struct sdhci_msm_host
{
127 struct platform_device
*pdev
;
128 void __iomem
*core_mem
; /* MSM SDCC mapped address */
129 int pwr_irq
; /* power irq */
130 struct clk
*clk
; /* main SD/MMC bus clock */
131 struct clk
*pclk
; /* SDHC peripheral bus clock */
132 struct clk
*bus_clk
; /* SDHC bus voter clock */
133 struct clk
*xo_clk
; /* TCXO clk needed for FLL feature of cm_dll*/
134 unsigned long clk_rate
;
135 struct mmc_host
*mmc
;
136 bool use_14lpp_dll_reset
;
138 bool calibration_done
;
139 u8 saved_tuning_phase
;
145 static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host
*host
,
148 struct mmc_ios ios
= host
->mmc
->ios
;
150 * The SDHC requires internal clock frequency to be double the
151 * actual clock that will be set for DDR mode. The controller
152 * uses the faster clock(100/400MHz) for some of its parts and
153 * send the actual required clock (50/200MHz) to the card.
155 if (ios
.timing
== MMC_TIMING_UHS_DDR50
||
156 ios
.timing
== MMC_TIMING_MMC_DDR52
||
157 ios
.timing
== MMC_TIMING_MMC_HS400
||
158 host
->flags
& SDHCI_HS400_TUNING
)
163 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host
*host
,
166 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
167 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
168 struct mmc_ios curr_ios
= host
->mmc
->ios
;
171 clock
= msm_get_clock_rate_for_bus_mode(host
, clock
);
172 rc
= clk_set_rate(msm_host
->clk
, clock
);
174 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
175 mmc_hostname(host
->mmc
), clock
,
179 msm_host
->clk_rate
= clock
;
180 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
181 mmc_hostname(host
->mmc
), clk_get_rate(msm_host
->clk
),
185 /* Platform specific tuning */
186 static inline int msm_dll_poll_ck_out_en(struct sdhci_host
*host
, u8 poll
)
190 struct mmc_host
*mmc
= host
->mmc
;
192 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
193 ck_out_en
= !!(readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
) &
196 while (ck_out_en
!= poll
) {
197 if (--wait_cnt
== 0) {
198 dev_err(mmc_dev(mmc
), "%s: CK_OUT_EN bit is not %d\n",
199 mmc_hostname(mmc
), poll
);
204 ck_out_en
= !!(readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
) &
211 static int msm_config_cm_dll_phase(struct sdhci_host
*host
, u8 phase
)
214 static const u8 grey_coded_phase_table
[] = {
215 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
216 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
220 struct mmc_host
*mmc
= host
->mmc
;
225 spin_lock_irqsave(&host
->lock
, flags
);
227 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
228 config
&= ~(CORE_CDR_EN
| CORE_CK_OUT_EN
);
229 config
|= (CORE_CDR_EXT_EN
| CORE_DLL_EN
);
230 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
232 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
233 rc
= msm_dll_poll_ck_out_en(host
, 0);
238 * Write the selected DLL clock output phase (0 ... 15)
239 * to CDR_SELEXT bit field of DLL_CONFIG register.
241 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
242 config
&= ~CDR_SELEXT_MASK
;
243 config
|= grey_coded_phase_table
[phase
] << CDR_SELEXT_SHIFT
;
244 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
246 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
247 config
|= CORE_CK_OUT_EN
;
248 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
250 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
251 rc
= msm_dll_poll_ck_out_en(host
, 1);
255 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
256 config
|= CORE_CDR_EN
;
257 config
&= ~CORE_CDR_EXT_EN
;
258 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
262 dev_err(mmc_dev(mmc
), "%s: Failed to set DLL phase: %d\n",
263 mmc_hostname(mmc
), phase
);
265 spin_unlock_irqrestore(&host
->lock
, flags
);
270 * Find out the greatest range of consecuitive selected
271 * DLL clock output phases that can be used as sampling
272 * setting for SD3.0 UHS-I card read operation (in SDR104
273 * timing mode) or for eMMC4.5 card read operation (in
274 * HS400/HS200 timing mode).
275 * Select the 3/4 of the range and configure the DLL with the
276 * selected DLL clock output phase.
279 static int msm_find_most_appropriate_phase(struct sdhci_host
*host
,
280 u8
*phase_table
, u8 total_phases
)
283 u8 ranges
[MAX_PHASES
][MAX_PHASES
] = { {0}, {0} };
284 u8 phases_per_row
[MAX_PHASES
] = { 0 };
285 int row_index
= 0, col_index
= 0, selected_row_index
= 0, curr_max
= 0;
286 int i
, cnt
, phase_0_raw_index
= 0, phase_15_raw_index
= 0;
287 bool phase_0_found
= false, phase_15_found
= false;
288 struct mmc_host
*mmc
= host
->mmc
;
290 if (!total_phases
|| (total_phases
> MAX_PHASES
)) {
291 dev_err(mmc_dev(mmc
), "%s: Invalid argument: total_phases=%d\n",
292 mmc_hostname(mmc
), total_phases
);
296 for (cnt
= 0; cnt
< total_phases
; cnt
++) {
297 ranges
[row_index
][col_index
] = phase_table
[cnt
];
298 phases_per_row
[row_index
] += 1;
301 if ((cnt
+ 1) == total_phases
) {
303 /* check if next phase in phase_table is consecutive or not */
304 } else if ((phase_table
[cnt
] + 1) != phase_table
[cnt
+ 1]) {
310 if (row_index
>= MAX_PHASES
)
313 /* Check if phase-0 is present in first valid window? */
315 phase_0_found
= true;
316 phase_0_raw_index
= 0;
317 /* Check if cycle exist between 2 valid windows */
318 for (cnt
= 1; cnt
<= row_index
; cnt
++) {
319 if (phases_per_row
[cnt
]) {
320 for (i
= 0; i
< phases_per_row
[cnt
]; i
++) {
321 if (ranges
[cnt
][i
] == 15) {
322 phase_15_found
= true;
323 phase_15_raw_index
= cnt
;
331 /* If 2 valid windows form cycle then merge them as single window */
332 if (phase_0_found
&& phase_15_found
) {
333 /* number of phases in raw where phase 0 is present */
334 u8 phases_0
= phases_per_row
[phase_0_raw_index
];
335 /* number of phases in raw where phase 15 is present */
336 u8 phases_15
= phases_per_row
[phase_15_raw_index
];
338 if (phases_0
+ phases_15
>= MAX_PHASES
)
340 * If there are more than 1 phase windows then total
341 * number of phases in both the windows should not be
342 * more than or equal to MAX_PHASES.
346 /* Merge 2 cyclic windows */
348 for (cnt
= 0; cnt
< phases_0
; cnt
++) {
349 ranges
[phase_15_raw_index
][i
] =
350 ranges
[phase_0_raw_index
][cnt
];
351 if (++i
>= MAX_PHASES
)
355 phases_per_row
[phase_0_raw_index
] = 0;
356 phases_per_row
[phase_15_raw_index
] = phases_15
+ phases_0
;
359 for (cnt
= 0; cnt
<= row_index
; cnt
++) {
360 if (phases_per_row
[cnt
] > curr_max
) {
361 curr_max
= phases_per_row
[cnt
];
362 selected_row_index
= cnt
;
366 i
= (curr_max
* 3) / 4;
370 ret
= ranges
[selected_row_index
][i
];
372 if (ret
>= MAX_PHASES
) {
374 dev_err(mmc_dev(mmc
), "%s: Invalid phase selected=%d\n",
375 mmc_hostname(mmc
), ret
);
381 static inline void msm_cm_dll_set_freq(struct sdhci_host
*host
)
383 u32 mclk_freq
= 0, config
;
385 /* Program the MCLK value to MCLK_FREQ bit field */
386 if (host
->clock
<= 112000000)
388 else if (host
->clock
<= 125000000)
390 else if (host
->clock
<= 137000000)
392 else if (host
->clock
<= 150000000)
394 else if (host
->clock
<= 162000000)
396 else if (host
->clock
<= 175000000)
398 else if (host
->clock
<= 187000000)
400 else if (host
->clock
<= 200000000)
403 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
404 config
&= ~CMUX_SHIFT_PHASE_MASK
;
405 config
|= mclk_freq
<< CMUX_SHIFT_PHASE_SHIFT
;
406 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
409 /* Initialize the DLL (Programmable Delay Line) */
410 static int msm_init_cm_dll(struct sdhci_host
*host
)
412 struct mmc_host
*mmc
= host
->mmc
;
413 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
414 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
419 spin_lock_irqsave(&host
->lock
, flags
);
422 * Make sure that clock is always enabled when DLL
423 * tuning is in progress. Keeping PWRSAVE ON may
424 * turn off the clock.
426 config
= readl_relaxed(host
->ioaddr
+ CORE_VENDOR_SPEC
);
427 config
&= ~CORE_CLK_PWRSAVE
;
428 writel_relaxed(config
, host
->ioaddr
+ CORE_VENDOR_SPEC
);
430 if (msm_host
->use_14lpp_dll_reset
) {
431 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
432 config
&= ~CORE_CK_OUT_EN
;
433 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
435 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG_2
);
436 config
|= CORE_DLL_CLOCK_DISABLE
;
437 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG_2
);
440 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
441 config
|= CORE_DLL_RST
;
442 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
444 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
445 config
|= CORE_DLL_PDN
;
446 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
447 msm_cm_dll_set_freq(host
);
449 if (msm_host
->use_14lpp_dll_reset
&&
450 !IS_ERR_OR_NULL(msm_host
->xo_clk
)) {
453 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG_2
);
454 config
&= CORE_FLL_CYCLE_CNT
;
456 mclk_freq
= DIV_ROUND_CLOSEST_ULL((host
->clock
* 8),
457 clk_get_rate(msm_host
->xo_clk
));
459 mclk_freq
= DIV_ROUND_CLOSEST_ULL((host
->clock
* 4),
460 clk_get_rate(msm_host
->xo_clk
));
462 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG_2
);
463 config
&= ~(0xFF << 10);
464 config
|= mclk_freq
<< 10;
466 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG_2
);
467 /* wait for 5us before enabling DLL clock */
471 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
472 config
&= ~CORE_DLL_RST
;
473 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
475 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
476 config
&= ~CORE_DLL_PDN
;
477 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
479 if (msm_host
->use_14lpp_dll_reset
) {
480 msm_cm_dll_set_freq(host
);
481 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG_2
);
482 config
&= ~CORE_DLL_CLOCK_DISABLE
;
483 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG_2
);
486 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
487 config
|= CORE_DLL_EN
;
488 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
490 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
491 config
|= CORE_CK_OUT_EN
;
492 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
494 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
495 while (!(readl_relaxed(host
->ioaddr
+ CORE_DLL_STATUS
) &
497 /* max. wait for 50us sec for LOCK bit to be set */
498 if (--wait_cnt
== 0) {
499 dev_err(mmc_dev(mmc
), "%s: DLL failed to LOCK\n",
501 spin_unlock_irqrestore(&host
->lock
, flags
);
507 spin_unlock_irqrestore(&host
->lock
, flags
);
511 static void msm_hc_select_default(struct sdhci_host
*host
)
513 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
514 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
517 if (!msm_host
->use_cdclp533
) {
518 config
= readl_relaxed(host
->ioaddr
+
520 config
&= ~CORE_PWRSAVE_DLL
;
521 writel_relaxed(config
, host
->ioaddr
+
525 config
= readl_relaxed(host
->ioaddr
+ CORE_VENDOR_SPEC
);
526 config
&= ~CORE_HC_MCLK_SEL_MASK
;
527 config
|= CORE_HC_MCLK_SEL_DFLT
;
528 writel_relaxed(config
, host
->ioaddr
+ CORE_VENDOR_SPEC
);
531 * Disable HC_SELECT_IN to be able to use the UHS mode select
532 * configuration from Host Control2 register for all other
534 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
535 * in VENDOR_SPEC_FUNC
537 config
= readl_relaxed(host
->ioaddr
+ CORE_VENDOR_SPEC
);
538 config
&= ~CORE_HC_SELECT_IN_EN
;
539 config
&= ~CORE_HC_SELECT_IN_MASK
;
540 writel_relaxed(config
, host
->ioaddr
+ CORE_VENDOR_SPEC
);
543 * Make sure above writes impacting free running MCLK are completed
544 * before changing the clk_rate at GCC.
549 static void msm_hc_select_hs400(struct sdhci_host
*host
)
551 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
552 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
553 struct mmc_ios ios
= host
->mmc
->ios
;
554 u32 config
, dll_lock
;
557 /* Select the divided clock (free running MCLK/2) */
558 config
= readl_relaxed(host
->ioaddr
+ CORE_VENDOR_SPEC
);
559 config
&= ~CORE_HC_MCLK_SEL_MASK
;
560 config
|= CORE_HC_MCLK_SEL_HS400
;
562 writel_relaxed(config
, host
->ioaddr
+ CORE_VENDOR_SPEC
);
564 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
567 if ((msm_host
->tuning_done
|| ios
.enhanced_strobe
) &&
568 !msm_host
->calibration_done
) {
569 config
= readl_relaxed(host
->ioaddr
+ CORE_VENDOR_SPEC
);
570 config
|= CORE_HC_SELECT_IN_HS400
;
571 config
|= CORE_HC_SELECT_IN_EN
;
572 writel_relaxed(config
, host
->ioaddr
+ CORE_VENDOR_SPEC
);
574 if (!msm_host
->clk_rate
&& !msm_host
->use_cdclp533
) {
576 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
577 * CORE_DLL_STATUS to be set. This should get set
578 * within 15 us at 200 MHz.
580 rc
= readl_relaxed_poll_timeout(host
->ioaddr
+
585 CORE_DDR_DLL_LOCK
)), 10,
587 if (rc
== -ETIMEDOUT
)
588 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
589 mmc_hostname(host
->mmc
), dll_lock
);
592 * Make sure above writes impacting free running MCLK are completed
593 * before changing the clk_rate at GCC.
599 * sdhci_msm_hc_select_mode :- In general all timing modes are
600 * controlled via UHS mode select in Host Control2 register.
601 * eMMC specific HS200/HS400 doesn't have their respective modes
602 * defined here, hence we use these values.
604 * HS200 - SDR104 (Since they both are equivalent in functionality)
605 * HS400 - This involves multiple configurations
606 * Initially SDR104 - when tuning is required as HS200
607 * Then when switching to DDR @ 400MHz (HS400) we use
608 * the vendor specific HC_SELECT_IN to control the mode.
610 * In addition to controlling the modes we also need to select the
611 * correct input clock for DLL depending on the mode.
613 * HS400 - divided clock (free running MCLK/2)
614 * All other modes - default (free running MCLK)
616 static void sdhci_msm_hc_select_mode(struct sdhci_host
*host
)
618 struct mmc_ios ios
= host
->mmc
->ios
;
620 if (ios
.timing
== MMC_TIMING_MMC_HS400
||
621 host
->flags
& SDHCI_HS400_TUNING
)
622 msm_hc_select_hs400(host
);
624 msm_hc_select_default(host
);
627 static int sdhci_msm_cdclp533_calibration(struct sdhci_host
*host
)
629 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
630 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
631 u32 config
, calib_done
;
634 pr_debug("%s: %s: Enter\n", mmc_hostname(host
->mmc
), __func__
);
637 * Retuning in HS400 (DDR mode) will fail, just reset the
638 * tuning block and restore the saved tuning phase.
640 ret
= msm_init_cm_dll(host
);
644 /* Set the selected phase in delay line hw block */
645 ret
= msm_config_cm_dll_phase(host
, msm_host
->saved_tuning_phase
);
649 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
650 config
|= CORE_CMD_DAT_TRACK_SEL
;
651 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
653 config
= readl_relaxed(host
->ioaddr
+ CORE_DDR_200_CFG
);
654 config
&= ~CORE_CDC_T4_DLY_SEL
;
655 writel_relaxed(config
, host
->ioaddr
+ CORE_DDR_200_CFG
);
657 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
658 config
&= ~CORE_CDC_SWITCH_BYPASS_OFF
;
659 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
661 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
662 config
|= CORE_CDC_SWITCH_RC_EN
;
663 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
665 config
= readl_relaxed(host
->ioaddr
+ CORE_DDR_200_CFG
);
666 config
&= ~CORE_START_CDC_TRAFFIC
;
667 writel_relaxed(config
, host
->ioaddr
+ CORE_DDR_200_CFG
);
669 /* Perform CDC Register Initialization Sequence */
671 writel_relaxed(0x11800EC, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
672 writel_relaxed(0x3011111, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG1
);
673 writel_relaxed(0x1201000, host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG0
);
674 writel_relaxed(0x4, host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG1
);
675 writel_relaxed(0xCB732020, host
->ioaddr
+ CORE_CSR_CDC_REFCOUNT_CFG
);
676 writel_relaxed(0xB19, host
->ioaddr
+ CORE_CSR_CDC_COARSE_CAL_CFG
);
677 writel_relaxed(0x4E2, host
->ioaddr
+ CORE_CSR_CDC_DELAY_CFG
);
678 writel_relaxed(0x0, host
->ioaddr
+ CORE_CDC_OFFSET_CFG
);
679 writel_relaxed(0x16334, host
->ioaddr
+ CORE_CDC_SLAVE_DDA_CFG
);
681 /* CDC HW Calibration */
683 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
684 config
|= CORE_SW_TRIG_FULL_CALIB
;
685 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
687 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
688 config
&= ~CORE_SW_TRIG_FULL_CALIB
;
689 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
691 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
692 config
|= CORE_HW_AUTOCAL_ENA
;
693 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
695 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG0
);
696 config
|= CORE_TIMER_ENA
;
697 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG0
);
699 ret
= readl_relaxed_poll_timeout(host
->ioaddr
+ CORE_CSR_CDC_STATUS0
,
701 (calib_done
& CORE_CALIBRATION_DONE
),
704 if (ret
== -ETIMEDOUT
) {
705 pr_err("%s: %s: CDC calibration was not completed\n",
706 mmc_hostname(host
->mmc
), __func__
);
710 ret
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_STATUS0
)
711 & CORE_CDC_ERROR_CODE_MASK
;
713 pr_err("%s: %s: CDC error code %d\n",
714 mmc_hostname(host
->mmc
), __func__
, ret
);
719 config
= readl_relaxed(host
->ioaddr
+ CORE_DDR_200_CFG
);
720 config
|= CORE_START_CDC_TRAFFIC
;
721 writel_relaxed(config
, host
->ioaddr
+ CORE_DDR_200_CFG
);
723 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host
->mmc
),
728 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host
*host
)
730 struct mmc_host
*mmc
= host
->mmc
;
731 u32 dll_status
, config
;
734 pr_debug("%s: %s: Enter\n", mmc_hostname(host
->mmc
), __func__
);
737 * Currently the CORE_DDR_CONFIG register defaults to desired
738 * configuration on reset. Currently reprogramming the power on
739 * reset (POR) value in case it might have been modified by
740 * bootloaders. In the future, if this changes, then the desired
741 * values will need to be programmed appropriately.
743 writel_relaxed(DDR_CONFIG_POR_VAL
, host
->ioaddr
+ CORE_DDR_CONFIG
);
745 if (mmc
->ios
.enhanced_strobe
) {
746 config
= readl_relaxed(host
->ioaddr
+ CORE_DDR_200_CFG
);
747 config
|= CORE_CMDIN_RCLK_EN
;
748 writel_relaxed(config
, host
->ioaddr
+ CORE_DDR_200_CFG
);
751 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG_2
);
752 config
|= CORE_DDR_CAL_EN
;
753 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG_2
);
755 ret
= readl_relaxed_poll_timeout(host
->ioaddr
+ CORE_DLL_STATUS
,
757 (dll_status
& CORE_DDR_DLL_LOCK
),
760 if (ret
== -ETIMEDOUT
) {
761 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
762 mmc_hostname(host
->mmc
), __func__
);
766 config
= readl_relaxed(host
->ioaddr
+ CORE_VENDOR_SPEC3
);
767 config
|= CORE_PWRSAVE_DLL
;
768 writel_relaxed(config
, host
->ioaddr
+ CORE_VENDOR_SPEC3
);
771 * Drain writebuffer to ensure above DLL calibration
772 * and PWRSAVE DLL is enabled.
776 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host
->mmc
),
781 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host
*host
)
783 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
784 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
785 struct mmc_host
*mmc
= host
->mmc
;
789 pr_debug("%s: %s: Enter\n", mmc_hostname(host
->mmc
), __func__
);
792 * Retuning in HS400 (DDR mode) will fail, just reset the
793 * tuning block and restore the saved tuning phase.
795 ret
= msm_init_cm_dll(host
);
799 if (!mmc
->ios
.enhanced_strobe
) {
800 /* Set the selected phase in delay line hw block */
801 ret
= msm_config_cm_dll_phase(host
,
802 msm_host
->saved_tuning_phase
);
805 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
806 config
|= CORE_CMD_DAT_TRACK_SEL
;
807 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
810 if (msm_host
->use_cdclp533
)
811 ret
= sdhci_msm_cdclp533_calibration(host
);
813 ret
= sdhci_msm_cm_dll_sdc4_calibration(host
);
815 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host
->mmc
),
820 static void sdhci_msm_set_cdr(struct sdhci_host
*host
, bool enable
)
822 u32 config
, oldconfig
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
826 config
|= CORE_CDR_EN
;
827 config
&= ~CORE_CDR_EXT_EN
;
829 config
&= ~CORE_CDR_EN
;
830 config
|= CORE_CDR_EXT_EN
;
833 if (config
!= oldconfig
)
834 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
837 static int sdhci_msm_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
839 struct sdhci_host
*host
= mmc_priv(mmc
);
840 int tuning_seq_cnt
= 3;
841 u8 phase
, tuned_phases
[16], tuned_phase_cnt
= 0;
843 struct mmc_ios ios
= host
->mmc
->ios
;
844 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
845 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
848 * Tuning is required for SDR104, HS200 and HS400 cards and
849 * if clock frequency is greater than 100MHz in these modes.
851 if (host
->clock
<= CORE_FREQ_100MHZ
||
852 !(ios
.timing
== MMC_TIMING_MMC_HS400
||
853 ios
.timing
== MMC_TIMING_MMC_HS200
||
854 ios
.timing
== MMC_TIMING_UHS_SDR104
)) {
855 msm_host
->use_cdr
= false;
856 sdhci_msm_set_cdr(host
, false);
860 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
861 msm_host
->use_cdr
= true;
864 * For HS400 tuning in HS200 timing requires:
865 * - select MCLK/2 in VENDOR_SPEC
866 * - program MCLK to 400MHz (or nearest supported) in GCC
868 if (host
->flags
& SDHCI_HS400_TUNING
) {
869 sdhci_msm_hc_select_mode(host
);
870 msm_set_clock_rate_for_bus_mode(host
, ios
.clock
);
871 host
->flags
&= ~SDHCI_HS400_TUNING
;
875 /* First of all reset the tuning block */
876 rc
= msm_init_cm_dll(host
);
882 /* Set the phase in delay line hw block */
883 rc
= msm_config_cm_dll_phase(host
, phase
);
887 msm_host
->saved_tuning_phase
= phase
;
888 rc
= mmc_send_tuning(mmc
, opcode
, NULL
);
890 /* Tuning is successful at this tuning point */
891 tuned_phases
[tuned_phase_cnt
++] = phase
;
892 dev_dbg(mmc_dev(mmc
), "%s: Found good phase = %d\n",
893 mmc_hostname(mmc
), phase
);
895 } while (++phase
< ARRAY_SIZE(tuned_phases
));
897 if (tuned_phase_cnt
) {
898 rc
= msm_find_most_appropriate_phase(host
, tuned_phases
,
906 * Finally set the selected phase in delay
909 rc
= msm_config_cm_dll_phase(host
, phase
);
912 dev_dbg(mmc_dev(mmc
), "%s: Setting the tuning phase to %d\n",
913 mmc_hostname(mmc
), phase
);
915 if (--tuning_seq_cnt
)
918 dev_dbg(mmc_dev(mmc
), "%s: No tuning point found\n",
924 msm_host
->tuning_done
= true;
929 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
930 * This needs to be done for both tuning and enhanced_strobe mode.
931 * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
932 * fixed feedback clock is used.
934 static void sdhci_msm_hs400(struct sdhci_host
*host
, struct mmc_ios
*ios
)
936 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
937 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
940 if (host
->clock
> CORE_FREQ_100MHZ
&&
941 (msm_host
->tuning_done
|| ios
->enhanced_strobe
) &&
942 !msm_host
->calibration_done
) {
943 ret
= sdhci_msm_hs400_dll_calibration(host
);
945 msm_host
->calibration_done
= true;
947 pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
948 mmc_hostname(host
->mmc
), ret
);
952 static void sdhci_msm_set_uhs_signaling(struct sdhci_host
*host
,
955 struct mmc_host
*mmc
= host
->mmc
;
956 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
957 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
961 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
962 /* Select Bus Speed Mode for host */
963 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
965 case MMC_TIMING_UHS_SDR12
:
966 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
968 case MMC_TIMING_UHS_SDR25
:
969 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
971 case MMC_TIMING_UHS_SDR50
:
972 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
;
974 case MMC_TIMING_MMC_HS400
:
975 case MMC_TIMING_MMC_HS200
:
976 case MMC_TIMING_UHS_SDR104
:
977 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
;
979 case MMC_TIMING_UHS_DDR50
:
980 case MMC_TIMING_MMC_DDR52
:
981 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
;
986 * When clock frequency is less than 100MHz, the feedback clock must be
987 * provided and DLL must not be used so that tuning can be skipped. To
988 * provide feedback clock, the mode selection can be any value less
989 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
991 if (host
->clock
<= CORE_FREQ_100MHZ
) {
992 if (uhs
== MMC_TIMING_MMC_HS400
||
993 uhs
== MMC_TIMING_MMC_HS200
||
994 uhs
== MMC_TIMING_UHS_SDR104
)
995 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
997 * DLL is not required for clock <= 100MHz
998 * Thus, make sure DLL it is disabled when not required
1000 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
1001 config
|= CORE_DLL_RST
;
1002 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
1004 config
= readl_relaxed(host
->ioaddr
+ CORE_DLL_CONFIG
);
1005 config
|= CORE_DLL_PDN
;
1006 writel_relaxed(config
, host
->ioaddr
+ CORE_DLL_CONFIG
);
1009 * The DLL needs to be restored and CDCLP533 recalibrated
1010 * when the clock frequency is set back to 400MHz.
1012 msm_host
->calibration_done
= false;
1015 dev_dbg(mmc_dev(mmc
), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1016 mmc_hostname(host
->mmc
), host
->clock
, uhs
, ctrl_2
);
1017 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1019 if (mmc
->ios
.timing
== MMC_TIMING_MMC_HS400
)
1020 sdhci_msm_hs400(host
, &mmc
->ios
);
1023 static void sdhci_msm_voltage_switch(struct sdhci_host
*host
)
1025 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1026 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1027 u32 irq_status
, irq_ack
= 0;
1029 irq_status
= readl_relaxed(msm_host
->core_mem
+ CORE_PWRCTL_STATUS
);
1030 irq_status
&= INT_MASK
;
1032 writel_relaxed(irq_status
, msm_host
->core_mem
+ CORE_PWRCTL_CLEAR
);
1034 if (irq_status
& (CORE_PWRCTL_BUS_ON
| CORE_PWRCTL_BUS_OFF
))
1035 irq_ack
|= CORE_PWRCTL_BUS_SUCCESS
;
1036 if (irq_status
& (CORE_PWRCTL_IO_LOW
| CORE_PWRCTL_IO_HIGH
))
1037 irq_ack
|= CORE_PWRCTL_IO_SUCCESS
;
1040 * The driver has to acknowledge the interrupt, switch voltages and
1041 * report back if it succeded or not to this register. The voltage
1042 * switches are handled by the sdhci core, so just report success.
1044 writel_relaxed(irq_ack
, msm_host
->core_mem
+ CORE_PWRCTL_CTL
);
1047 static irqreturn_t
sdhci_msm_pwr_irq(int irq
, void *data
)
1049 struct sdhci_host
*host
= (struct sdhci_host
*)data
;
1051 sdhci_msm_voltage_switch(host
);
1056 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host
*host
)
1058 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1059 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1061 return clk_round_rate(msm_host
->clk
, ULONG_MAX
);
1064 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host
*host
)
1066 return SDHCI_MSM_MIN_CLOCK
;
1070 * __sdhci_msm_set_clock - sdhci_msm clock control.
1073 * MSM controller does not use internal divider and
1074 * instead directly control the GCC clock as per
1075 * HW recommendation.
1077 static void __sdhci_msm_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1081 * Keep actual_clock as zero -
1082 * - since there is no divider used so no need of having actual_clock.
1083 * - MSM controller uses SDCLK for data timeout calculation. If
1084 * actual_clock is zero, host->clock is taken for calculation.
1086 host
->mmc
->actual_clock
= 0;
1088 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
1094 * MSM controller do not use clock divider.
1095 * Thus read SDHCI_CLOCK_CONTROL and only enable
1096 * clock with no divider value programmed.
1098 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1099 sdhci_enable_clk(host
, clk
);
1102 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1103 static void sdhci_msm_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1105 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1106 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1109 msm_host
->clk_rate
= clock
;
1113 sdhci_msm_hc_select_mode(host
);
1115 msm_set_clock_rate_for_bus_mode(host
, clock
);
1117 __sdhci_msm_set_clock(host
, clock
);
1120 static void sdhci_msm_write_w(struct sdhci_host
*host
, u16 val
, int reg
)
1122 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1123 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1126 case SDHCI_TRANSFER_MODE
:
1127 msm_host
->transfer_mode
= val
;
1130 if (!msm_host
->use_cdr
)
1132 if ((msm_host
->transfer_mode
& SDHCI_TRNS_READ
) &&
1133 (SDHCI_GET_CMD(val
) != MMC_SEND_TUNING_BLOCK_HS200
) &&
1134 (SDHCI_GET_CMD(val
) != MMC_SEND_TUNING_BLOCK
))
1135 sdhci_msm_set_cdr(host
, true);
1137 sdhci_msm_set_cdr(host
, false);
1140 writew(val
, host
->ioaddr
+ reg
);
1143 static const struct of_device_id sdhci_msm_dt_match
[] = {
1144 { .compatible
= "qcom,sdhci-msm-v4" },
1148 MODULE_DEVICE_TABLE(of
, sdhci_msm_dt_match
);
1150 static const struct sdhci_ops sdhci_msm_ops
= {
1151 .reset
= sdhci_reset
,
1152 .set_clock
= sdhci_msm_set_clock
,
1153 .get_min_clock
= sdhci_msm_get_min_clock
,
1154 .get_max_clock
= sdhci_msm_get_max_clock
,
1155 .set_bus_width
= sdhci_set_bus_width
,
1156 .set_uhs_signaling
= sdhci_msm_set_uhs_signaling
,
1157 .voltage_switch
= sdhci_msm_voltage_switch
,
1158 .write_w
= sdhci_msm_write_w
,
1161 static const struct sdhci_pltfm_data sdhci_msm_pdata
= {
1162 .quirks
= SDHCI_QUIRK_BROKEN_CARD_DETECTION
|
1163 SDHCI_QUIRK_NO_CARD_NO_RESET
|
1164 SDHCI_QUIRK_SINGLE_POWER_WRITE
|
1165 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
,
1166 .quirks2
= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
,
1167 .ops
= &sdhci_msm_ops
,
1170 static int sdhci_msm_probe(struct platform_device
*pdev
)
1172 struct sdhci_host
*host
;
1173 struct sdhci_pltfm_host
*pltfm_host
;
1174 struct sdhci_msm_host
*msm_host
;
1175 struct resource
*core_memres
;
1177 u16 host_version
, core_minor
;
1178 u32 core_version
, config
;
1181 host
= sdhci_pltfm_init(pdev
, &sdhci_msm_pdata
, sizeof(*msm_host
));
1183 return PTR_ERR(host
);
1185 host
->sdma_boundary
= 0;
1186 pltfm_host
= sdhci_priv(host
);
1187 msm_host
= sdhci_pltfm_priv(pltfm_host
);
1188 msm_host
->mmc
= host
->mmc
;
1189 msm_host
->pdev
= pdev
;
1191 ret
= mmc_of_parse(host
->mmc
);
1195 sdhci_get_of_property(pdev
);
1197 msm_host
->saved_tuning_phase
= INVALID_TUNING_PHASE
;
1199 /* Setup SDCC bus voter clock. */
1200 msm_host
->bus_clk
= devm_clk_get(&pdev
->dev
, "bus");
1201 if (!IS_ERR(msm_host
->bus_clk
)) {
1202 /* Vote for max. clk rate for max. performance */
1203 ret
= clk_set_rate(msm_host
->bus_clk
, INT_MAX
);
1206 ret
= clk_prepare_enable(msm_host
->bus_clk
);
1211 /* Setup main peripheral bus clock */
1212 msm_host
->pclk
= devm_clk_get(&pdev
->dev
, "iface");
1213 if (IS_ERR(msm_host
->pclk
)) {
1214 ret
= PTR_ERR(msm_host
->pclk
);
1215 dev_err(&pdev
->dev
, "Peripheral clk setup failed (%d)\n", ret
);
1216 goto bus_clk_disable
;
1219 ret
= clk_prepare_enable(msm_host
->pclk
);
1221 goto bus_clk_disable
;
1223 /* Setup SDC MMC clock */
1224 msm_host
->clk
= devm_clk_get(&pdev
->dev
, "core");
1225 if (IS_ERR(msm_host
->clk
)) {
1226 ret
= PTR_ERR(msm_host
->clk
);
1227 dev_err(&pdev
->dev
, "SDC MMC clk setup failed (%d)\n", ret
);
1232 * xo clock is needed for FLL feature of cm_dll.
1233 * In case if xo clock is not mentioned in DT, warn and proceed.
1235 msm_host
->xo_clk
= devm_clk_get(&pdev
->dev
, "xo");
1236 if (IS_ERR(msm_host
->xo_clk
)) {
1237 ret
= PTR_ERR(msm_host
->xo_clk
);
1238 dev_warn(&pdev
->dev
, "TCXO clk not present (%d)\n", ret
);
1241 /* Vote for maximum clock rate for maximum performance */
1242 ret
= clk_set_rate(msm_host
->clk
, INT_MAX
);
1244 dev_warn(&pdev
->dev
, "core clock boost failed\n");
1246 ret
= clk_prepare_enable(msm_host
->clk
);
1250 core_memres
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1251 msm_host
->core_mem
= devm_ioremap_resource(&pdev
->dev
, core_memres
);
1253 if (IS_ERR(msm_host
->core_mem
)) {
1254 dev_err(&pdev
->dev
, "Failed to remap registers\n");
1255 ret
= PTR_ERR(msm_host
->core_mem
);
1259 /* Reset the vendor spec register to power on reset state */
1260 writel_relaxed(CORE_VENDOR_SPEC_POR_VAL
,
1261 host
->ioaddr
+ CORE_VENDOR_SPEC
);
1263 /* Set HC_MODE_EN bit in HC_MODE register */
1264 writel_relaxed(HC_MODE_EN
, (msm_host
->core_mem
+ CORE_HC_MODE
));
1266 config
= readl_relaxed(msm_host
->core_mem
+ CORE_HC_MODE
);
1267 config
|= FF_CLK_SW_RST_DIS
;
1268 writel_relaxed(config
, msm_host
->core_mem
+ CORE_HC_MODE
);
1270 host_version
= readw_relaxed((host
->ioaddr
+ SDHCI_HOST_VERSION
));
1271 dev_dbg(&pdev
->dev
, "Host Version: 0x%x Vendor Version 0x%x\n",
1272 host_version
, ((host_version
& SDHCI_VENDOR_VER_MASK
) >>
1273 SDHCI_VENDOR_VER_SHIFT
));
1275 core_version
= readl_relaxed(msm_host
->core_mem
+ CORE_MCI_VERSION
);
1276 core_major
= (core_version
& CORE_VERSION_MAJOR_MASK
) >>
1277 CORE_VERSION_MAJOR_SHIFT
;
1278 core_minor
= core_version
& CORE_VERSION_MINOR_MASK
;
1279 dev_dbg(&pdev
->dev
, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
1280 core_version
, core_major
, core_minor
);
1282 if (core_major
== 1 && core_minor
>= 0x42)
1283 msm_host
->use_14lpp_dll_reset
= true;
1286 * SDCC 5 controller with major version 1, minor version 0x34 and later
1287 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
1289 if (core_major
== 1 && core_minor
< 0x34)
1290 msm_host
->use_cdclp533
= true;
1293 * Support for some capabilities is not advertised by newer
1294 * controller versions and must be explicitly enabled.
1296 if (core_major
>= 1 && core_minor
!= 0x11 && core_minor
!= 0x12) {
1297 config
= readl_relaxed(host
->ioaddr
+ SDHCI_CAPABILITIES
);
1298 config
|= SDHCI_CAN_VDD_300
| SDHCI_CAN_DO_8BIT
;
1299 writel_relaxed(config
, host
->ioaddr
+
1300 CORE_VENDOR_SPEC_CAPABILITIES0
);
1304 * Power on reset state may trigger power irq if previous status of
1305 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
1306 * interrupt in GIC, any pending power irq interrupt should be
1307 * acknowledged. Otherwise power irq interrupt handler would be
1308 * fired prematurely.
1310 sdhci_msm_voltage_switch(host
);
1313 * Ensure that above writes are propogated before interrupt enablement
1318 /* Setup IRQ for handling power/voltage tasks with PMIC */
1319 msm_host
->pwr_irq
= platform_get_irq_byname(pdev
, "pwr_irq");
1320 if (msm_host
->pwr_irq
< 0) {
1321 dev_err(&pdev
->dev
, "Get pwr_irq failed (%d)\n",
1323 ret
= msm_host
->pwr_irq
;
1327 /* Enable pwr irq interrupts */
1328 writel_relaxed(INT_MASK
, msm_host
->core_mem
+ CORE_PWRCTL_MASK
);
1330 ret
= devm_request_threaded_irq(&pdev
->dev
, msm_host
->pwr_irq
, NULL
,
1331 sdhci_msm_pwr_irq
, IRQF_ONESHOT
,
1332 dev_name(&pdev
->dev
), host
);
1334 dev_err(&pdev
->dev
, "Request IRQ failed (%d)\n", ret
);
1338 pm_runtime_get_noresume(&pdev
->dev
);
1339 pm_runtime_set_active(&pdev
->dev
);
1340 pm_runtime_enable(&pdev
->dev
);
1341 pm_runtime_set_autosuspend_delay(&pdev
->dev
,
1342 MSM_MMC_AUTOSUSPEND_DELAY_MS
);
1343 pm_runtime_use_autosuspend(&pdev
->dev
);
1345 host
->mmc_host_ops
.execute_tuning
= sdhci_msm_execute_tuning
;
1346 ret
= sdhci_add_host(host
);
1348 goto pm_runtime_disable
;
1350 pm_runtime_mark_last_busy(&pdev
->dev
);
1351 pm_runtime_put_autosuspend(&pdev
->dev
);
1356 pm_runtime_disable(&pdev
->dev
);
1357 pm_runtime_set_suspended(&pdev
->dev
);
1358 pm_runtime_put_noidle(&pdev
->dev
);
1360 clk_disable_unprepare(msm_host
->clk
);
1362 clk_disable_unprepare(msm_host
->pclk
);
1364 if (!IS_ERR(msm_host
->bus_clk
))
1365 clk_disable_unprepare(msm_host
->bus_clk
);
1367 sdhci_pltfm_free(pdev
);
1371 static int sdhci_msm_remove(struct platform_device
*pdev
)
1373 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
1374 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1375 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1376 int dead
= (readl_relaxed(host
->ioaddr
+ SDHCI_INT_STATUS
) ==
1379 sdhci_remove_host(host
, dead
);
1381 pm_runtime_get_sync(&pdev
->dev
);
1382 pm_runtime_disable(&pdev
->dev
);
1383 pm_runtime_put_noidle(&pdev
->dev
);
1385 clk_disable_unprepare(msm_host
->clk
);
1386 clk_disable_unprepare(msm_host
->pclk
);
1387 if (!IS_ERR(msm_host
->bus_clk
))
1388 clk_disable_unprepare(msm_host
->bus_clk
);
1389 sdhci_pltfm_free(pdev
);
1394 static int sdhci_msm_runtime_suspend(struct device
*dev
)
1396 struct sdhci_host
*host
= dev_get_drvdata(dev
);
1397 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1398 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1400 clk_disable_unprepare(msm_host
->clk
);
1401 clk_disable_unprepare(msm_host
->pclk
);
1406 static int sdhci_msm_runtime_resume(struct device
*dev
)
1408 struct sdhci_host
*host
= dev_get_drvdata(dev
);
1409 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1410 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1413 ret
= clk_prepare_enable(msm_host
->clk
);
1415 dev_err(dev
, "clk_enable failed for core_clk: %d\n", ret
);
1418 ret
= clk_prepare_enable(msm_host
->pclk
);
1420 dev_err(dev
, "clk_enable failed for iface_clk: %d\n", ret
);
1421 clk_disable_unprepare(msm_host
->clk
);
1429 static const struct dev_pm_ops sdhci_msm_pm_ops
= {
1430 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend
,
1431 pm_runtime_force_resume
)
1432 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend
,
1433 sdhci_msm_runtime_resume
,
1437 static struct platform_driver sdhci_msm_driver
= {
1438 .probe
= sdhci_msm_probe
,
1439 .remove
= sdhci_msm_remove
,
1441 .name
= "sdhci_msm",
1442 .of_match_table
= sdhci_msm_dt_match
,
1443 .pm
= &sdhci_msm_pm_ops
,
1447 module_platform_driver(sdhci_msm_driver
);
1449 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
1450 MODULE_LICENSE("GPL v2");