drivers/mmc/host/sdhci-cadence.c

   1 /*
   2  * Copyright (C) 2016 Socionext Inc.
   3  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/bitops.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/module.h>
  19 #include <linux/mmc/host.h>
  20 #include <linux/mmc/mmc.h>
  21 #include <linux/of.h>
  22
  23 #include "sdhci-pltfm.h"
  24
  25 /* HRS - Host Register Set (specific to Cadence) */
  26 #define SDHCI_CDNS_HRS04                0x10            /* PHY access port */
  27 #define   SDHCI_CDNS_HRS04_ACK                  BIT(26)
  28 #define   SDHCI_CDNS_HRS04_RD                   BIT(25)
  29 #define   SDHCI_CDNS_HRS04_WR                   BIT(24)
  30 #define   SDHCI_CDNS_HRS04_RDATA_SHIFT          16
  31 #define   SDHCI_CDNS_HRS04_WDATA_SHIFT          8
  32 #define   SDHCI_CDNS_HRS04_ADDR_SHIFT           0
  33
  34 #define SDHCI_CDNS_HRS06                0x18            /* eMMC control */
  35 #define   SDHCI_CDNS_HRS06_TUNE_UP              BIT(15)
  36 #define   SDHCI_CDNS_HRS06_TUNE_SHIFT           8
  37 #define   SDHCI_CDNS_HRS06_TUNE_MASK            0x3f
  38 #define   SDHCI_CDNS_HRS06_MODE_MASK            0x7
  39 #define   SDHCI_CDNS_HRS06_MODE_SD              0x0
  40 #define   SDHCI_CDNS_HRS06_MODE_MMC_SDR         0x2
  41 #define   SDHCI_CDNS_HRS06_MODE_MMC_DDR         0x3
  42 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS200       0x4
  43 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS400       0x5
  44 #define   SDHCI_CDNS_HRS06_MODE_MMC_HS400ES     0x6
  45
  46 /* SRS - Slot Register Set (SDHCI-compatible) */
  47 #define SDHCI_CDNS_SRS_BASE             0x200
  48
  49 /* PHY */
  50 #define SDHCI_CDNS_PHY_DLY_SD_HS        0x00
  51 #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT   0x01
  52 #define SDHCI_CDNS_PHY_DLY_UHS_SDR12    0x02
  53 #define SDHCI_CDNS_PHY_DLY_UHS_SDR25    0x03
  54 #define SDHCI_CDNS_PHY_DLY_UHS_SDR50    0x04
  55 #define SDHCI_CDNS_PHY_DLY_UHS_DDR50    0x05
  56 #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY  0x06
  57 #define SDHCI_CDNS_PHY_DLY_EMMC_SDR     0x07
  58 #define SDHCI_CDNS_PHY_DLY_EMMC_DDR     0x08
  59 #define SDHCI_CDNS_PHY_DLY_SDCLK        0x0b
  60 #define SDHCI_CDNS_PHY_DLY_HSMMC        0x0c
  61 #define SDHCI_CDNS_PHY_DLY_STROBE       0x0d
  62
  63 /*
  64  * The tuned val register is 6 bit-wide, but not the whole of the range is
  65  * available.  The range 0-42 seems to be available (then 43 wraps around to 0)
  66  * but I am not quite sure if it is official.  Use only 0 to 39 for safety.
  67  */
  68 #define SDHCI_CDNS_MAX_TUNING_LOOP      40
  69
  70 struct sdhci_cdns_priv {
  71         void __iomem *hrs_addr;
  72         bool enhanced_strobe;
  73 };
  74
  75 struct sdhci_cdns_phy_cfg {
  76         const char *property;
  77         u8 addr;
  78 };
  79
  80 static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
  81         { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
  82         { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
  83         { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
  84         { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
  85         { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
  86         { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
  87         { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
  88         { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
  89         { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
  90         { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
  91         { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
  92 };
  93
  94 static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
  95                                     u8 addr, u8 data)
  96 {
  97         void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
  98         u32 tmp;
  99         int ret;
 100
 101         tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
 102               (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
 103         writel(tmp, reg);
 104
 105         tmp |= SDHCI_CDNS_HRS04_WR;
 106         writel(tmp, reg);
 107
 108         ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
 109         if (ret)
 110                 return ret;
 111
 112         tmp &= ~SDHCI_CDNS_HRS04_WR;
 113         writel(tmp, reg);
 114
 115         return 0;
 116 }
 117
 118 static int sdhci_cdns_phy_init(struct device_node *np,
 119                                struct sdhci_cdns_priv *priv)
 120 {
 121         u32 val;
 122         int ret, i;
 123
 124         for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
 125                 ret = of_property_read_u32(np, sdhci_cdns_phy_cfgs[i].property,
 126                                            &val);
 127                 if (ret)
 128                         continue;
 129
 130                 ret = sdhci_cdns_write_phy_reg(priv,
 131                                                sdhci_cdns_phy_cfgs[i].addr,
 132                                                val);
 133                 if (ret)
 134                         return ret;
 135         }
 136
 137         return 0;
 138 }
 139
 140 static inline void *sdhci_cdns_priv(struct sdhci_host *host)
 141 {
 142         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 143
 144         return sdhci_pltfm_priv(pltfm_host);
 145 }
 146
 147 static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
 148 {
 149         /*
 150          * Cadence's spec says the Timeout Clock Frequency is the same as the
 151          * Base Clock Frequency.
 152          */
 153         return host->max_clk;
 154 }
 155
 156 static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
 157 {
 158         u32 tmp;
 159
 160         /* The speed mode for eMMC is selected by HRS06 register */
 161         tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
 162         tmp &= ~SDHCI_CDNS_HRS06_MODE_MASK;
 163         tmp |= mode;
 164         writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
 165 }
 166
 167 static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
 168 {
 169         u32 tmp;
 170
 171         tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
 172         return tmp & SDHCI_CDNS_HRS06_MODE_MASK;
 173 }
 174
 175 static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
 176                                          unsigned int timing)
 177 {
 178         struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
 179         u32 mode;
 180
 181         switch (timing) {
 182         case MMC_TIMING_MMC_HS:
 183                 mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
 184                 break;
 185         case MMC_TIMING_MMC_DDR52:
 186                 mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
 187                 break;
 188         case MMC_TIMING_MMC_HS200:
 189                 mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
 190                 break;
 191         case MMC_TIMING_MMC_HS400:
 192                 if (priv->enhanced_strobe)
 193                         mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES;
 194                 else
 195                         mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
 196                 break;
 197         default:
 198                 mode = SDHCI_CDNS_HRS06_MODE_SD;
 199                 break;
 200         }
 201
 202         sdhci_cdns_set_emmc_mode(priv, mode);
 203
 204         /* For SD, fall back to the default handler */
 205         if (mode == SDHCI_CDNS_HRS06_MODE_SD)
 206                 sdhci_set_uhs_signaling(host, timing);
 207 }
 208
 209 static const struct sdhci_ops sdhci_cdns_ops = {
 210         .set_clock = sdhci_set_clock,
 211         .get_timeout_clock = sdhci_cdns_get_timeout_clock,
 212         .set_bus_width = sdhci_set_bus_width,
 213         .reset = sdhci_reset,
 214         .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
 215 };
 216
 217 static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
 218         .ops = &sdhci_cdns_ops,
 219 };
 220
 221 static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
 222 {
 223         struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
 224         void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
 225         u32 tmp;
 226
 227         if (WARN_ON(val > SDHCI_CDNS_HRS06_TUNE_MASK))
 228                 return -EINVAL;
 229
 230         tmp = readl(reg);
 231         tmp &= ~(SDHCI_CDNS_HRS06_TUNE_MASK << SDHCI_CDNS_HRS06_TUNE_SHIFT);
 232         tmp |= val << SDHCI_CDNS_HRS06_TUNE_SHIFT;
 233         tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
 234         writel(tmp, reg);
 235
 236         return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
 237                                   0, 1);
 238 }
 239
 240 static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode)
 241 {
 242         struct sdhci_host *host = mmc_priv(mmc);
 243         int cur_streak = 0;
 244         int max_streak = 0;
 245         int end_of_streak = 0;
 246         int i;
 247
 248         /*
 249          * This handler only implements the eMMC tuning that is specific to
 250          * this controller.  Fall back to the standard method for SD timing.
 251          */
 252         if (host->timing != MMC_TIMING_MMC_HS200)
 253                 return sdhci_execute_tuning(mmc, opcode);
 254
 255         if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
 256                 return -EINVAL;
 257
 258         for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
 259                 if (sdhci_cdns_set_tune_val(host, i) ||
 260                     mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
 261                         cur_streak = 0;
 262                 } else { /* good */
 263                         cur_streak++;
 264                         if (cur_streak > max_streak) {
 265                                 max_streak = cur_streak;
 266                                 end_of_streak = i;
 267                         }
 268                 }
 269         }
 270
 271         if (!max_streak) {
 272                 dev_err(mmc_dev(host->mmc), "no tuning point found\n");
 273                 return -EIO;
 274         }
 275
 276         return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
 277 }
 278
 279 static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
 280                                              struct mmc_ios *ios)
 281 {
 282         struct sdhci_host *host = mmc_priv(mmc);
 283         struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
 284         u32 mode;
 285
 286         priv->enhanced_strobe = ios->enhanced_strobe;
 287
 288         mode = sdhci_cdns_get_emmc_mode(priv);
 289
 290         if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400 && ios->enhanced_strobe)
 291                 sdhci_cdns_set_emmc_mode(priv,
 292                                          SDHCI_CDNS_HRS06_MODE_MMC_HS400ES);
 293
 294         if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400ES && !ios->enhanced_strobe)
 295                 sdhci_cdns_set_emmc_mode(priv,
 296                                          SDHCI_CDNS_HRS06_MODE_MMC_HS400);
 297 }
 298
 299 static int sdhci_cdns_probe(struct platform_device *pdev)
 300 {
 301         struct sdhci_host *host;
 302         struct sdhci_pltfm_host *pltfm_host;
 303         struct sdhci_cdns_priv *priv;
 304         struct clk *clk;
 305         int ret;
 306         struct device *dev = &pdev->dev;
 307
 308         clk = devm_clk_get(dev, NULL);
 309         if (IS_ERR(clk))
 310                 return PTR_ERR(clk);
 311
 312         ret = clk_prepare_enable(clk);
 313         if (ret)
 314                 return ret;
 315
 316         host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data, sizeof(*priv));
 317         if (IS_ERR(host)) {
 318                 ret = PTR_ERR(host);
 319                 goto disable_clk;
 320         }
 321
 322         pltfm_host = sdhci_priv(host);
 323         pltfm_host->clk = clk;
 324
 325         priv = sdhci_cdns_priv(host);
 326         priv->hrs_addr = host->ioaddr;
 327         priv->enhanced_strobe = false;
 328         host->ioaddr += SDHCI_CDNS_SRS_BASE;
 329         host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning;
 330         host->mmc_host_ops.hs400_enhanced_strobe =
 331                                 sdhci_cdns_hs400_enhanced_strobe;
 332
 333         sdhci_get_of_property(pdev);
 334
 335         ret = mmc_of_parse(host->mmc);
 336         if (ret)
 337                 goto free;
 338
 339         ret = sdhci_cdns_phy_init(dev->of_node, priv);
 340         if (ret)
 341                 goto free;
 342
 343         ret = sdhci_add_host(host);
 344         if (ret)
 345                 goto free;
 346
 347         return 0;
 348 free:
 349         sdhci_pltfm_free(pdev);
 350 disable_clk:
 351         clk_disable_unprepare(clk);
 352
 353         return ret;
 354 }
 355
 356 static const struct of_device_id sdhci_cdns_match[] = {
 357         { .compatible = "socionext,uniphier-sd4hc" },
 358         { .compatible = "cdns,sd4hc" },
 359         { /* sentinel */ }
 360 };
 361 MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
 362
 363 static struct platform_driver sdhci_cdns_driver = {
 364         .driver = {
 365                 .name = "sdhci-cdns",
 366                 .pm = &sdhci_pltfm_pmops,
 367                 .of_match_table = sdhci_cdns_match,
 368         },
 369         .probe = sdhci_cdns_probe,
 370         .remove = sdhci_pltfm_unregister,
 371 };
 372 module_platform_driver(sdhci_cdns_driver);
 373
 374 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
 375 MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver");
 376 MODULE_LICENSE("GPL");