2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_device.h>
26 #include <linux/workqueue.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
31 #include <linux/mmc/mmc.h>
33 #include <linux/semaphore.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/consumer.h>
37 #include <mach/hardware.h>
38 #include <plat/board.h>
42 /* OMAP HSMMC Host Controller Registers */
43 #define OMAP_HSMMC_SYSCONFIG 0x0010
44 #define OMAP_HSMMC_SYSSTATUS 0x0014
45 #define OMAP_HSMMC_CON 0x002C
46 #define OMAP_HSMMC_BLK 0x0104
47 #define OMAP_HSMMC_ARG 0x0108
48 #define OMAP_HSMMC_CMD 0x010C
49 #define OMAP_HSMMC_RSP10 0x0110
50 #define OMAP_HSMMC_RSP32 0x0114
51 #define OMAP_HSMMC_RSP54 0x0118
52 #define OMAP_HSMMC_RSP76 0x011C
53 #define OMAP_HSMMC_DATA 0x0120
54 #define OMAP_HSMMC_HCTL 0x0128
55 #define OMAP_HSMMC_SYSCTL 0x012C
56 #define OMAP_HSMMC_STAT 0x0130
57 #define OMAP_HSMMC_IE 0x0134
58 #define OMAP_HSMMC_ISE 0x0138
59 #define OMAP_HSMMC_CAPA 0x0140
61 #define VS18 (1 << 26)
62 #define VS30 (1 << 25)
63 #define SDVS18 (0x5 << 9)
64 #define SDVS30 (0x6 << 9)
65 #define SDVS33 (0x7 << 9)
66 #define SDVS_MASK 0x00000E00
67 #define SDVSCLR 0xFFFFF1FF
68 #define SDVSDET 0x00000400
75 #define CLKD_MASK 0x0000FFC0
77 #define DTO_MASK 0x000F0000
79 #define INT_EN_MASK 0x307F0033
80 #define BWR_ENABLE (1 << 4)
81 #define BRR_ENABLE (1 << 5)
82 #define DTO_ENABLE (1 << 20)
83 #define INIT_STREAM (1 << 1)
84 #define DP_SELECT (1 << 21)
89 #define FOUR_BIT (1 << 1)
95 #define CMD_TIMEOUT (1 << 16)
96 #define DATA_TIMEOUT (1 << 20)
97 #define CMD_CRC (1 << 17)
98 #define DATA_CRC (1 << 21)
99 #define CARD_ERR (1 << 28)
100 #define STAT_CLEAR 0xFFFFFFFF
101 #define INIT_STREAM_CMD 0x00000000
102 #define DUAL_VOLT_OCR_BIT 7
103 #define SRC (1 << 25)
104 #define SRD (1 << 26)
105 #define SOFTRESET (1 << 1)
106 #define RESETDONE (1 << 0)
109 * FIXME: Most likely all the data using these _DEVID defines should come
110 * from the platform_data, or implemented in controller and slot specific
113 #define OMAP_MMC1_DEVID 0
114 #define OMAP_MMC2_DEVID 1
115 #define OMAP_MMC3_DEVID 2
116 #define OMAP_MMC4_DEVID 3
117 #define OMAP_MMC5_DEVID 4
119 #define MMC_TIMEOUT_MS 20
120 #define OMAP_MMC_MASTER_CLOCK 96000000
121 #define DRIVER_NAME "mmci-omap-hs"
123 /* Timeouts for entering power saving states on inactivity, msec */
124 #define OMAP_MMC_DISABLED_TIMEOUT 100
125 #define OMAP_MMC_SLEEP_TIMEOUT 1000
126 #define OMAP_MMC_OFF_TIMEOUT 8000
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
133 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
136 * MMC Host controller read/write API's
138 #define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
141 #define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
144 struct omap_hsmmc_host
{
146 struct mmc_host
*mmc
;
147 struct mmc_request
*mrq
;
148 struct mmc_command
*cmd
;
149 struct mmc_data
*data
;
154 * vcc == configured supply
155 * vcc_aux == optional
156 * - MMC1, supply for DAT4..DAT7
157 * - MMC2/MMC2, external level shifter voltage supply, for
158 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
160 struct regulator
*vcc
;
161 struct regulator
*vcc_aux
;
162 struct work_struct mmc_carddetect_work
;
164 resource_size_t mapbase
;
165 spinlock_t irq_lock
; /* Prevent races with irq handler */
167 unsigned int dma_len
;
168 unsigned int dma_sg_idx
;
169 unsigned char bus_mode
;
170 unsigned char power_mode
;
176 int dma_line_tx
, dma_line_rx
;
188 struct omap_mmc_platform_data
*pdata
;
191 static int omap_hsmmc_card_detect(struct device
*dev
, int slot
)
193 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
195 /* NOTE: assumes card detect signal is active-low */
196 return !gpio_get_value_cansleep(mmc
->slots
[0].switch_pin
);
199 static int omap_hsmmc_get_wp(struct device
*dev
, int slot
)
201 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
203 /* NOTE: assumes write protect signal is active-high */
204 return gpio_get_value_cansleep(mmc
->slots
[0].gpio_wp
);
207 static int omap_hsmmc_get_cover_state(struct device
*dev
, int slot
)
209 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
211 /* NOTE: assumes card detect signal is active-low */
212 return !gpio_get_value_cansleep(mmc
->slots
[0].switch_pin
);
217 static int omap_hsmmc_suspend_cdirq(struct device
*dev
, int slot
)
219 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
221 disable_irq(mmc
->slots
[0].card_detect_irq
);
225 static int omap_hsmmc_resume_cdirq(struct device
*dev
, int slot
)
227 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
229 enable_irq(mmc
->slots
[0].card_detect_irq
);
235 #define omap_hsmmc_suspend_cdirq NULL
236 #define omap_hsmmc_resume_cdirq NULL
240 #ifdef CONFIG_REGULATOR
242 static int omap_hsmmc_1_set_power(struct device
*dev
, int slot
, int power_on
,
245 struct omap_hsmmc_host
*host
=
246 platform_get_drvdata(to_platform_device(dev
));
249 if (mmc_slot(host
).before_set_reg
)
250 mmc_slot(host
).before_set_reg(dev
, slot
, power_on
, vdd
);
253 ret
= mmc_regulator_set_ocr(host
->mmc
, host
->vcc
, vdd
);
255 ret
= mmc_regulator_set_ocr(host
->mmc
, host
->vcc
, 0);
257 if (mmc_slot(host
).after_set_reg
)
258 mmc_slot(host
).after_set_reg(dev
, slot
, power_on
, vdd
);
263 static int omap_hsmmc_23_set_power(struct device
*dev
, int slot
, int power_on
,
266 struct omap_hsmmc_host
*host
=
267 platform_get_drvdata(to_platform_device(dev
));
271 * If we don't see a Vcc regulator, assume it's a fixed
272 * voltage always-on regulator.
277 if (mmc_slot(host
).before_set_reg
)
278 mmc_slot(host
).before_set_reg(dev
, slot
, power_on
, vdd
);
281 * Assume Vcc regulator is used only to power the card ... OMAP
282 * VDDS is used to power the pins, optionally with a transceiver to
283 * support cards using voltages other than VDDS (1.8V nominal). When a
284 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
286 * In some cases this regulator won't support enable/disable;
287 * e.g. it's a fixed rail for a WLAN chip.
289 * In other cases vcc_aux switches interface power. Example, for
290 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
291 * chips/cards need an interface voltage rail too.
294 ret
= mmc_regulator_set_ocr(host
->mmc
, host
->vcc
, vdd
);
295 /* Enable interface voltage rail, if needed */
296 if (ret
== 0 && host
->vcc_aux
) {
297 ret
= regulator_enable(host
->vcc_aux
);
299 ret
= mmc_regulator_set_ocr(host
->mmc
,
303 /* Shut down the rail */
305 ret
= regulator_disable(host
->vcc_aux
);
307 /* Then proceed to shut down the local regulator */
308 ret
= mmc_regulator_set_ocr(host
->mmc
,
313 if (mmc_slot(host
).after_set_reg
)
314 mmc_slot(host
).after_set_reg(dev
, slot
, power_on
, vdd
);
319 static int omap_hsmmc_1_set_sleep(struct device
*dev
, int slot
, int sleep
,
320 int vdd
, int cardsleep
)
322 struct omap_hsmmc_host
*host
=
323 platform_get_drvdata(to_platform_device(dev
));
324 int mode
= sleep
? REGULATOR_MODE_STANDBY
: REGULATOR_MODE_NORMAL
;
326 return regulator_set_mode(host
->vcc
, mode
);
329 static int omap_hsmmc_23_set_sleep(struct device
*dev
, int slot
, int sleep
,
330 int vdd
, int cardsleep
)
332 struct omap_hsmmc_host
*host
=
333 platform_get_drvdata(to_platform_device(dev
));
337 * If we don't see a Vcc regulator, assume it's a fixed
338 * voltage always-on regulator.
343 mode
= sleep
? REGULATOR_MODE_STANDBY
: REGULATOR_MODE_NORMAL
;
346 return regulator_set_mode(host
->vcc
, mode
);
349 /* VCC can be turned off if card is asleep */
351 err
= mmc_regulator_set_ocr(host
->mmc
, host
->vcc
, 0);
353 err
= mmc_regulator_set_ocr(host
->mmc
, host
->vcc
, vdd
);
355 err
= regulator_set_mode(host
->vcc
, mode
);
359 if (!mmc_slot(host
).vcc_aux_disable_is_sleep
)
360 return regulator_set_mode(host
->vcc_aux
, mode
);
363 return regulator_disable(host
->vcc_aux
);
365 return regulator_enable(host
->vcc_aux
);
368 static int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host
)
370 struct regulator
*reg
;
375 case OMAP_MMC1_DEVID
:
376 /* On-chip level shifting via PBIAS0/PBIAS1 */
377 mmc_slot(host
).set_power
= omap_hsmmc_1_set_power
;
378 mmc_slot(host
).set_sleep
= omap_hsmmc_1_set_sleep
;
380 case OMAP_MMC2_DEVID
:
381 case OMAP_MMC3_DEVID
:
382 /* Off-chip level shifting, or none */
383 mmc_slot(host
).set_power
= omap_hsmmc_23_set_power
;
384 mmc_slot(host
).set_sleep
= omap_hsmmc_23_set_sleep
;
387 pr_err("MMC%d configuration not supported!\n", host
->id
);
391 reg
= regulator_get(host
->dev
, "vmmc");
393 dev_dbg(host
->dev
, "vmmc regulator missing\n");
395 * HACK: until fixed.c regulator is usable,
396 * we don't require a main regulator
399 if (host
->id
== OMAP_MMC1_DEVID
) {
405 ocr_value
= mmc_regulator_get_ocrmask(reg
);
406 if (!mmc_slot(host
).ocr_mask
) {
407 mmc_slot(host
).ocr_mask
= ocr_value
;
409 if (!(mmc_slot(host
).ocr_mask
& ocr_value
)) {
410 pr_err("MMC%d ocrmask %x is not supported\n",
411 host
->id
, mmc_slot(host
).ocr_mask
);
412 mmc_slot(host
).ocr_mask
= 0;
416 mmc_slot(host
).ocr_mask
= mmc_regulator_get_ocrmask(reg
);
418 /* Allow an aux regulator */
419 reg
= regulator_get(host
->dev
, "vmmc_aux");
420 host
->vcc_aux
= IS_ERR(reg
) ? NULL
: reg
;
423 * UGLY HACK: workaround regulator framework bugs.
424 * When the bootloader leaves a supply active, it's
425 * initialized with zero usecount ... and we can't
426 * disable it without first enabling it. Until the
427 * framework is fixed, we need a workaround like this
428 * (which is safe for MMC, but not in general).
430 if (regulator_is_enabled(host
->vcc
) > 0) {
431 regulator_enable(host
->vcc
);
432 regulator_disable(host
->vcc
);
435 if (regulator_is_enabled(reg
) > 0) {
436 regulator_enable(reg
);
437 regulator_disable(reg
);
445 mmc_slot(host
).set_power
= NULL
;
446 mmc_slot(host
).set_sleep
= NULL
;
450 static void omap_hsmmc_reg_put(struct omap_hsmmc_host
*host
)
452 regulator_put(host
->vcc
);
453 regulator_put(host
->vcc_aux
);
454 mmc_slot(host
).set_power
= NULL
;
455 mmc_slot(host
).set_sleep
= NULL
;
458 static inline int omap_hsmmc_have_reg(void)
465 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host
)
470 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host
*host
)
474 static inline int omap_hsmmc_have_reg(void)
481 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data
*pdata
)
485 if (gpio_is_valid(pdata
->slots
[0].switch_pin
)) {
486 if (pdata
->slots
[0].cover
)
487 pdata
->slots
[0].get_cover_state
=
488 omap_hsmmc_get_cover_state
;
490 pdata
->slots
[0].card_detect
= omap_hsmmc_card_detect
;
491 pdata
->slots
[0].card_detect_irq
=
492 gpio_to_irq(pdata
->slots
[0].switch_pin
);
493 ret
= gpio_request(pdata
->slots
[0].switch_pin
, "mmc_cd");
496 ret
= gpio_direction_input(pdata
->slots
[0].switch_pin
);
500 pdata
->slots
[0].switch_pin
= -EINVAL
;
502 if (gpio_is_valid(pdata
->slots
[0].gpio_wp
)) {
503 pdata
->slots
[0].get_ro
= omap_hsmmc_get_wp
;
504 ret
= gpio_request(pdata
->slots
[0].gpio_wp
, "mmc_wp");
507 ret
= gpio_direction_input(pdata
->slots
[0].gpio_wp
);
511 pdata
->slots
[0].gpio_wp
= -EINVAL
;
516 gpio_free(pdata
->slots
[0].gpio_wp
);
518 if (gpio_is_valid(pdata
->slots
[0].switch_pin
))
520 gpio_free(pdata
->slots
[0].switch_pin
);
524 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data
*pdata
)
526 if (gpio_is_valid(pdata
->slots
[0].gpio_wp
))
527 gpio_free(pdata
->slots
[0].gpio_wp
);
528 if (gpio_is_valid(pdata
->slots
[0].switch_pin
))
529 gpio_free(pdata
->slots
[0].switch_pin
);
533 * Stop clock to the card
535 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host
*host
)
537 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
538 OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ~CEN
);
539 if ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & CEN
) != 0x0)
540 dev_dbg(mmc_dev(host
->mmc
), "MMC Clock is not stoped\n");
543 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host
*host
,
544 struct mmc_command
*cmd
)
546 unsigned int irq_mask
;
549 irq_mask
= INT_EN_MASK
& ~(BRR_ENABLE
| BWR_ENABLE
);
551 irq_mask
= INT_EN_MASK
;
553 /* Disable timeout for erases */
554 if (cmd
->opcode
== MMC_ERASE
)
555 irq_mask
&= ~DTO_ENABLE
;
557 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
558 OMAP_HSMMC_WRITE(host
->base
, ISE
, irq_mask
);
559 OMAP_HSMMC_WRITE(host
->base
, IE
, irq_mask
);
562 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host
*host
)
564 OMAP_HSMMC_WRITE(host
->base
, ISE
, 0);
565 OMAP_HSMMC_WRITE(host
->base
, IE
, 0);
566 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
572 * Restore the MMC host context, if it was lost as result of a
573 * power state change.
575 static int omap_hsmmc_context_restore(struct omap_hsmmc_host
*host
)
577 struct mmc_ios
*ios
= &host
->mmc
->ios
;
578 struct omap_mmc_platform_data
*pdata
= host
->pdata
;
579 int context_loss
= 0;
582 unsigned long timeout
;
584 if (pdata
->get_context_loss_count
) {
585 context_loss
= pdata
->get_context_loss_count(host
->dev
);
586 if (context_loss
< 0)
590 dev_dbg(mmc_dev(host
->mmc
), "context was %slost\n",
591 context_loss
== host
->context_loss
? "not " : "");
592 if (host
->context_loss
== context_loss
)
595 /* Wait for hardware reset */
596 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
597 while ((OMAP_HSMMC_READ(host
->base
, SYSSTATUS
) & RESETDONE
) != RESETDONE
598 && time_before(jiffies
, timeout
))
601 /* Do software reset */
602 OMAP_HSMMC_WRITE(host
->base
, SYSCONFIG
, SOFTRESET
);
603 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
604 while ((OMAP_HSMMC_READ(host
->base
, SYSSTATUS
) & RESETDONE
) != RESETDONE
605 && time_before(jiffies
, timeout
))
608 OMAP_HSMMC_WRITE(host
->base
, SYSCONFIG
,
609 OMAP_HSMMC_READ(host
->base
, SYSCONFIG
) | AUTOIDLE
);
611 if (host
->id
== OMAP_MMC1_DEVID
) {
612 if (host
->power_mode
!= MMC_POWER_OFF
&&
613 (1 << ios
->vdd
) <= MMC_VDD_23_24
)
623 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
624 OMAP_HSMMC_READ(host
->base
, HCTL
) | hctl
);
626 OMAP_HSMMC_WRITE(host
->base
, CAPA
,
627 OMAP_HSMMC_READ(host
->base
, CAPA
) | capa
);
629 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
630 OMAP_HSMMC_READ(host
->base
, HCTL
) | SDBP
);
632 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
633 while ((OMAP_HSMMC_READ(host
->base
, HCTL
) & SDBP
) != SDBP
634 && time_before(jiffies
, timeout
))
637 omap_hsmmc_disable_irq(host
);
639 /* Do not initialize card-specific things if the power is off */
640 if (host
->power_mode
== MMC_POWER_OFF
)
643 con
= OMAP_HSMMC_READ(host
->base
, CON
);
644 switch (ios
->bus_width
) {
645 case MMC_BUS_WIDTH_8
:
646 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| DW8
);
648 case MMC_BUS_WIDTH_4
:
649 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
650 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
651 OMAP_HSMMC_READ(host
->base
, HCTL
) | FOUR_BIT
);
653 case MMC_BUS_WIDTH_1
:
654 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
655 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
656 OMAP_HSMMC_READ(host
->base
, HCTL
) & ~FOUR_BIT
);
661 dsor
= OMAP_MMC_MASTER_CLOCK
/ ios
->clock
;
665 if (OMAP_MMC_MASTER_CLOCK
/ dsor
> ios
->clock
)
672 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
673 OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ~CEN
);
674 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
, (dsor
<< 6) | (DTO
<< 16));
675 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
676 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | ICE
);
678 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
679 while ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ICS
) != ICS
680 && time_before(jiffies
, timeout
))
683 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
684 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | CEN
);
686 con
= OMAP_HSMMC_READ(host
->base
, CON
);
687 if (ios
->bus_mode
== MMC_BUSMODE_OPENDRAIN
)
688 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| OD
);
690 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~OD
);
692 host
->context_loss
= context_loss
;
694 dev_dbg(mmc_dev(host
->mmc
), "context is restored\n");
699 * Save the MMC host context (store the number of power state changes so far).
701 static void omap_hsmmc_context_save(struct omap_hsmmc_host
*host
)
703 struct omap_mmc_platform_data
*pdata
= host
->pdata
;
706 if (pdata
->get_context_loss_count
) {
707 context_loss
= pdata
->get_context_loss_count(host
->dev
);
708 if (context_loss
< 0)
710 host
->context_loss
= context_loss
;
716 static int omap_hsmmc_context_restore(struct omap_hsmmc_host
*host
)
721 static void omap_hsmmc_context_save(struct omap_hsmmc_host
*host
)
728 * Send init stream sequence to card
729 * before sending IDLE command
731 static void send_init_stream(struct omap_hsmmc_host
*host
)
734 unsigned long timeout
;
736 if (host
->protect_card
)
739 disable_irq(host
->irq
);
741 OMAP_HSMMC_WRITE(host
->base
, IE
, INT_EN_MASK
);
742 OMAP_HSMMC_WRITE(host
->base
, CON
,
743 OMAP_HSMMC_READ(host
->base
, CON
) | INIT_STREAM
);
744 OMAP_HSMMC_WRITE(host
->base
, CMD
, INIT_STREAM_CMD
);
746 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
747 while ((reg
!= CC
) && time_before(jiffies
, timeout
))
748 reg
= OMAP_HSMMC_READ(host
->base
, STAT
) & CC
;
750 OMAP_HSMMC_WRITE(host
->base
, CON
,
751 OMAP_HSMMC_READ(host
->base
, CON
) & ~INIT_STREAM
);
753 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
754 OMAP_HSMMC_READ(host
->base
, STAT
);
756 enable_irq(host
->irq
);
760 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host
*host
)
764 if (mmc_slot(host
).get_cover_state
)
765 r
= mmc_slot(host
).get_cover_state(host
->dev
, host
->slot_id
);
770 omap_hsmmc_show_cover_switch(struct device
*dev
, struct device_attribute
*attr
,
773 struct mmc_host
*mmc
= container_of(dev
, struct mmc_host
, class_dev
);
774 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
776 return sprintf(buf
, "%s\n",
777 omap_hsmmc_cover_is_closed(host
) ? "closed" : "open");
780 static DEVICE_ATTR(cover_switch
, S_IRUGO
, omap_hsmmc_show_cover_switch
, NULL
);
783 omap_hsmmc_show_slot_name(struct device
*dev
, struct device_attribute
*attr
,
786 struct mmc_host
*mmc
= container_of(dev
, struct mmc_host
, class_dev
);
787 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
789 return sprintf(buf
, "%s\n", mmc_slot(host
).name
);
792 static DEVICE_ATTR(slot_name
, S_IRUGO
, omap_hsmmc_show_slot_name
, NULL
);
795 * Configure the response type and send the cmd.
798 omap_hsmmc_start_command(struct omap_hsmmc_host
*host
, struct mmc_command
*cmd
,
799 struct mmc_data
*data
)
801 int cmdreg
= 0, resptype
= 0, cmdtype
= 0;
803 dev_dbg(mmc_dev(host
->mmc
), "%s: CMD%d, argument 0x%08x\n",
804 mmc_hostname(host
->mmc
), cmd
->opcode
, cmd
->arg
);
807 omap_hsmmc_enable_irq(host
, cmd
);
809 host
->response_busy
= 0;
810 if (cmd
->flags
& MMC_RSP_PRESENT
) {
811 if (cmd
->flags
& MMC_RSP_136
)
813 else if (cmd
->flags
& MMC_RSP_BUSY
) {
815 host
->response_busy
= 1;
821 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
822 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
823 * a val of 0x3, rest 0x0.
825 if (cmd
== host
->mrq
->stop
)
828 cmdreg
= (cmd
->opcode
<< 24) | (resptype
<< 16) | (cmdtype
<< 22);
831 cmdreg
|= DP_SELECT
| MSBS
| BCE
;
832 if (data
->flags
& MMC_DATA_READ
)
841 host
->req_in_progress
= 1;
843 OMAP_HSMMC_WRITE(host
->base
, ARG
, cmd
->arg
);
844 OMAP_HSMMC_WRITE(host
->base
, CMD
, cmdreg
);
848 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host
*host
, struct mmc_data
*data
)
850 if (data
->flags
& MMC_DATA_WRITE
)
851 return DMA_TO_DEVICE
;
853 return DMA_FROM_DEVICE
;
856 static void omap_hsmmc_request_done(struct omap_hsmmc_host
*host
, struct mmc_request
*mrq
)
860 spin_lock(&host
->irq_lock
);
861 host
->req_in_progress
= 0;
862 dma_ch
= host
->dma_ch
;
863 spin_unlock(&host
->irq_lock
);
865 omap_hsmmc_disable_irq(host
);
866 /* Do not complete the request if DMA is still in progress */
867 if (mrq
->data
&& host
->use_dma
&& dma_ch
!= -1)
870 mmc_request_done(host
->mmc
, mrq
);
874 * Notify the transfer complete to MMC core
877 omap_hsmmc_xfer_done(struct omap_hsmmc_host
*host
, struct mmc_data
*data
)
880 struct mmc_request
*mrq
= host
->mrq
;
882 /* TC before CC from CMD6 - don't know why, but it happens */
883 if (host
->cmd
&& host
->cmd
->opcode
== 6 &&
884 host
->response_busy
) {
885 host
->response_busy
= 0;
889 omap_hsmmc_request_done(host
, mrq
);
896 data
->bytes_xfered
+= data
->blocks
* (data
->blksz
);
898 data
->bytes_xfered
= 0;
901 omap_hsmmc_request_done(host
, data
->mrq
);
904 omap_hsmmc_start_command(host
, data
->stop
, NULL
);
908 * Notify the core about command completion
911 omap_hsmmc_cmd_done(struct omap_hsmmc_host
*host
, struct mmc_command
*cmd
)
915 if (cmd
->flags
& MMC_RSP_PRESENT
) {
916 if (cmd
->flags
& MMC_RSP_136
) {
917 /* response type 2 */
918 cmd
->resp
[3] = OMAP_HSMMC_READ(host
->base
, RSP10
);
919 cmd
->resp
[2] = OMAP_HSMMC_READ(host
->base
, RSP32
);
920 cmd
->resp
[1] = OMAP_HSMMC_READ(host
->base
, RSP54
);
921 cmd
->resp
[0] = OMAP_HSMMC_READ(host
->base
, RSP76
);
923 /* response types 1, 1b, 3, 4, 5, 6 */
924 cmd
->resp
[0] = OMAP_HSMMC_READ(host
->base
, RSP10
);
927 if ((host
->data
== NULL
&& !host
->response_busy
) || cmd
->error
)
928 omap_hsmmc_request_done(host
, cmd
->mrq
);
932 * DMA clean up for command errors
934 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host
*host
, int errno
)
938 host
->data
->error
= errno
;
940 spin_lock(&host
->irq_lock
);
941 dma_ch
= host
->dma_ch
;
943 spin_unlock(&host
->irq_lock
);
945 if (host
->use_dma
&& dma_ch
!= -1) {
946 dma_unmap_sg(mmc_dev(host
->mmc
), host
->data
->sg
, host
->dma_len
,
947 omap_hsmmc_get_dma_dir(host
, host
->data
));
948 omap_free_dma(dma_ch
);
954 * Readable error output
956 #ifdef CONFIG_MMC_DEBUG
957 static void omap_hsmmc_report_irq(struct omap_hsmmc_host
*host
, u32 status
)
959 /* --- means reserved bit without definition at documentation */
960 static const char *omap_hsmmc_status_bits
[] = {
961 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
962 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
963 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
964 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
970 len
= sprintf(buf
, "MMC IRQ 0x%x :", status
);
973 for (i
= 0; i
< ARRAY_SIZE(omap_hsmmc_status_bits
); i
++)
974 if (status
& (1 << i
)) {
975 len
= sprintf(buf
, " %s", omap_hsmmc_status_bits
[i
]);
979 dev_dbg(mmc_dev(host
->mmc
), "%s\n", res
);
981 #endif /* CONFIG_MMC_DEBUG */
984 * MMC controller internal state machines reset
986 * Used to reset command or data internal state machines, using respectively
987 * SRC or SRD bit of SYSCTL register
988 * Can be called from interrupt context
990 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host
*host
,
994 unsigned long limit
= (loops_per_jiffy
*
995 msecs_to_jiffies(MMC_TIMEOUT_MS
));
997 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
998 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | bit
);
1001 * OMAP4 ES2 and greater has an updated reset logic.
1002 * Monitor a 0->1 transition first
1004 if (mmc_slot(host
).features
& HSMMC_HAS_UPDATED_RESET
) {
1005 while ((!(OMAP_HSMMC_READ(host
, SYSCTL
) & bit
))
1011 while ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & bit
) &&
1015 if (OMAP_HSMMC_READ(host
->base
, SYSCTL
) & bit
)
1016 dev_err(mmc_dev(host
->mmc
),
1017 "Timeout waiting on controller reset in %s\n",
1021 static void omap_hsmmc_do_irq(struct omap_hsmmc_host
*host
, int status
)
1023 struct mmc_data
*data
;
1024 int end_cmd
= 0, end_trans
= 0;
1026 if (!host
->req_in_progress
) {
1028 OMAP_HSMMC_WRITE(host
->base
, STAT
, status
);
1029 /* Flush posted write */
1030 status
= OMAP_HSMMC_READ(host
->base
, STAT
);
1031 } while (status
& INT_EN_MASK
);
1036 dev_dbg(mmc_dev(host
->mmc
), "IRQ Status is %x\n", status
);
1039 #ifdef CONFIG_MMC_DEBUG
1040 omap_hsmmc_report_irq(host
, status
);
1042 if ((status
& CMD_TIMEOUT
) ||
1043 (status
& CMD_CRC
)) {
1045 if (status
& CMD_TIMEOUT
) {
1046 omap_hsmmc_reset_controller_fsm(host
,
1048 host
->cmd
->error
= -ETIMEDOUT
;
1050 host
->cmd
->error
= -EILSEQ
;
1054 if (host
->data
|| host
->response_busy
) {
1056 omap_hsmmc_dma_cleanup(host
,
1058 host
->response_busy
= 0;
1059 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1062 if ((status
& DATA_TIMEOUT
) ||
1063 (status
& DATA_CRC
)) {
1064 if (host
->data
|| host
->response_busy
) {
1065 int err
= (status
& DATA_TIMEOUT
) ?
1066 -ETIMEDOUT
: -EILSEQ
;
1069 omap_hsmmc_dma_cleanup(host
, err
);
1071 host
->mrq
->cmd
->error
= err
;
1072 host
->response_busy
= 0;
1073 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1077 if (status
& CARD_ERR
) {
1078 dev_dbg(mmc_dev(host
->mmc
),
1079 "Ignoring card err CMD%d\n", host
->cmd
->opcode
);
1087 OMAP_HSMMC_WRITE(host
->base
, STAT
, status
);
1089 if (end_cmd
|| ((status
& CC
) && host
->cmd
))
1090 omap_hsmmc_cmd_done(host
, host
->cmd
);
1091 if ((end_trans
|| (status
& TC
)) && host
->mrq
)
1092 omap_hsmmc_xfer_done(host
, data
);
1096 * MMC controller IRQ handler
1098 static irqreturn_t
omap_hsmmc_irq(int irq
, void *dev_id
)
1100 struct omap_hsmmc_host
*host
= dev_id
;
1103 status
= OMAP_HSMMC_READ(host
->base
, STAT
);
1105 omap_hsmmc_do_irq(host
, status
);
1106 /* Flush posted write */
1107 status
= OMAP_HSMMC_READ(host
->base
, STAT
);
1108 } while (status
& INT_EN_MASK
);
1113 static void set_sd_bus_power(struct omap_hsmmc_host
*host
)
1117 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1118 OMAP_HSMMC_READ(host
->base
, HCTL
) | SDBP
);
1119 for (i
= 0; i
< loops_per_jiffy
; i
++) {
1120 if (OMAP_HSMMC_READ(host
->base
, HCTL
) & SDBP
)
1127 * Switch MMC interface voltage ... only relevant for MMC1.
1129 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1130 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1131 * Some chips, like eMMC ones, use internal transceivers.
1133 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host
*host
, int vdd
)
1138 /* Disable the clocks */
1139 clk_disable(host
->fclk
);
1140 clk_disable(host
->iclk
);
1141 if (host
->got_dbclk
)
1142 clk_disable(host
->dbclk
);
1144 /* Turn the power off */
1145 ret
= mmc_slot(host
).set_power(host
->dev
, host
->slot_id
, 0, 0);
1147 /* Turn the power ON with given VDD 1.8 or 3.0v */
1149 ret
= mmc_slot(host
).set_power(host
->dev
, host
->slot_id
, 1,
1151 clk_enable(host
->iclk
);
1152 clk_enable(host
->fclk
);
1153 if (host
->got_dbclk
)
1154 clk_enable(host
->dbclk
);
1159 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1160 OMAP_HSMMC_READ(host
->base
, HCTL
) & SDVSCLR
);
1161 reg_val
= OMAP_HSMMC_READ(host
->base
, HCTL
);
1164 * If a MMC dual voltage card is detected, the set_ios fn calls
1165 * this fn with VDD bit set for 1.8V. Upon card removal from the
1166 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1168 * Cope with a bit of slop in the range ... per data sheets:
1169 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1170 * but recommended values are 1.71V to 1.89V
1171 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1172 * but recommended values are 2.7V to 3.3V
1174 * Board setup code shouldn't permit anything very out-of-range.
1175 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1176 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1178 if ((1 << vdd
) <= MMC_VDD_23_24
)
1183 OMAP_HSMMC_WRITE(host
->base
, HCTL
, reg_val
);
1184 set_sd_bus_power(host
);
1188 dev_dbg(mmc_dev(host
->mmc
), "Unable to switch operating voltage\n");
1192 /* Protect the card while the cover is open */
1193 static void omap_hsmmc_protect_card(struct omap_hsmmc_host
*host
)
1195 if (!mmc_slot(host
).get_cover_state
)
1198 host
->reqs_blocked
= 0;
1199 if (mmc_slot(host
).get_cover_state(host
->dev
, host
->slot_id
)) {
1200 if (host
->protect_card
) {
1201 printk(KERN_INFO
"%s: cover is closed, "
1202 "card is now accessible\n",
1203 mmc_hostname(host
->mmc
));
1204 host
->protect_card
= 0;
1207 if (!host
->protect_card
) {
1208 printk(KERN_INFO
"%s: cover is open, "
1209 "card is now inaccessible\n",
1210 mmc_hostname(host
->mmc
));
1211 host
->protect_card
= 1;
1217 * Work Item to notify the core about card insertion/removal
1219 static void omap_hsmmc_detect(struct work_struct
*work
)
1221 struct omap_hsmmc_host
*host
=
1222 container_of(work
, struct omap_hsmmc_host
, mmc_carddetect_work
);
1223 struct omap_mmc_slot_data
*slot
= &mmc_slot(host
);
1226 if (host
->suspended
)
1229 sysfs_notify(&host
->mmc
->class_dev
.kobj
, NULL
, "cover_switch");
1231 if (slot
->card_detect
)
1232 carddetect
= slot
->card_detect(host
->dev
, host
->slot_id
);
1234 omap_hsmmc_protect_card(host
);
1235 carddetect
= -ENOSYS
;
1239 mmc_detect_change(host
->mmc
, (HZ
* 200) / 1000);
1241 mmc_detect_change(host
->mmc
, (HZ
* 50) / 1000);
1245 * ISR for handling card insertion and removal
1247 static irqreturn_t
omap_hsmmc_cd_handler(int irq
, void *dev_id
)
1249 struct omap_hsmmc_host
*host
= (struct omap_hsmmc_host
*)dev_id
;
1251 if (host
->suspended
)
1253 schedule_work(&host
->mmc_carddetect_work
);
1258 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host
*host
,
1259 struct mmc_data
*data
)
1263 if (data
->flags
& MMC_DATA_WRITE
)
1264 sync_dev
= host
->dma_line_tx
;
1266 sync_dev
= host
->dma_line_rx
;
1270 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host
*host
,
1271 struct mmc_data
*data
,
1272 struct scatterlist
*sgl
)
1274 int blksz
, nblk
, dma_ch
;
1276 dma_ch
= host
->dma_ch
;
1277 if (data
->flags
& MMC_DATA_WRITE
) {
1278 omap_set_dma_dest_params(dma_ch
, 0, OMAP_DMA_AMODE_CONSTANT
,
1279 (host
->mapbase
+ OMAP_HSMMC_DATA
), 0, 0);
1280 omap_set_dma_src_params(dma_ch
, 0, OMAP_DMA_AMODE_POST_INC
,
1281 sg_dma_address(sgl
), 0, 0);
1283 omap_set_dma_src_params(dma_ch
, 0, OMAP_DMA_AMODE_CONSTANT
,
1284 (host
->mapbase
+ OMAP_HSMMC_DATA
), 0, 0);
1285 omap_set_dma_dest_params(dma_ch
, 0, OMAP_DMA_AMODE_POST_INC
,
1286 sg_dma_address(sgl
), 0, 0);
1289 blksz
= host
->data
->blksz
;
1290 nblk
= sg_dma_len(sgl
) / blksz
;
1292 omap_set_dma_transfer_params(dma_ch
, OMAP_DMA_DATA_TYPE_S32
,
1293 blksz
/ 4, nblk
, OMAP_DMA_SYNC_FRAME
,
1294 omap_hsmmc_get_dma_sync_dev(host
, data
),
1295 !(data
->flags
& MMC_DATA_WRITE
));
1297 omap_start_dma(dma_ch
);
1301 * DMA call back function
1303 static void omap_hsmmc_dma_cb(int lch
, u16 ch_status
, void *cb_data
)
1305 struct omap_hsmmc_host
*host
= cb_data
;
1306 struct mmc_data
*data
= host
->mrq
->data
;
1307 int dma_ch
, req_in_progress
;
1309 if (!(ch_status
& OMAP_DMA_BLOCK_IRQ
)) {
1310 dev_warn(mmc_dev(host
->mmc
), "unexpected dma status %x\n",
1315 spin_lock(&host
->irq_lock
);
1316 if (host
->dma_ch
< 0) {
1317 spin_unlock(&host
->irq_lock
);
1322 if (host
->dma_sg_idx
< host
->dma_len
) {
1323 /* Fire up the next transfer. */
1324 omap_hsmmc_config_dma_params(host
, data
,
1325 data
->sg
+ host
->dma_sg_idx
);
1326 spin_unlock(&host
->irq_lock
);
1330 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, host
->dma_len
,
1331 omap_hsmmc_get_dma_dir(host
, data
));
1333 req_in_progress
= host
->req_in_progress
;
1334 dma_ch
= host
->dma_ch
;
1336 spin_unlock(&host
->irq_lock
);
1338 omap_free_dma(dma_ch
);
1340 /* If DMA has finished after TC, complete the request */
1341 if (!req_in_progress
) {
1342 struct mmc_request
*mrq
= host
->mrq
;
1345 mmc_request_done(host
->mmc
, mrq
);
1350 * Routine to configure and start DMA for the MMC card
1352 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host
*host
,
1353 struct mmc_request
*req
)
1355 int dma_ch
= 0, ret
= 0, i
;
1356 struct mmc_data
*data
= req
->data
;
1358 /* Sanity check: all the SG entries must be aligned by block size. */
1359 for (i
= 0; i
< data
->sg_len
; i
++) {
1360 struct scatterlist
*sgl
;
1363 if (sgl
->length
% data
->blksz
)
1366 if ((data
->blksz
% 4) != 0)
1367 /* REVISIT: The MMC buffer increments only when MSB is written.
1368 * Return error for blksz which is non multiple of four.
1372 BUG_ON(host
->dma_ch
!= -1);
1374 ret
= omap_request_dma(omap_hsmmc_get_dma_sync_dev(host
, data
),
1375 "MMC/SD", omap_hsmmc_dma_cb
, host
, &dma_ch
);
1377 dev_err(mmc_dev(host
->mmc
),
1378 "%s: omap_request_dma() failed with %d\n",
1379 mmc_hostname(host
->mmc
), ret
);
1383 host
->dma_len
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
,
1384 data
->sg_len
, omap_hsmmc_get_dma_dir(host
, data
));
1385 host
->dma_ch
= dma_ch
;
1386 host
->dma_sg_idx
= 0;
1388 omap_hsmmc_config_dma_params(host
, data
, data
->sg
);
1393 static void set_data_timeout(struct omap_hsmmc_host
*host
,
1394 unsigned int timeout_ns
,
1395 unsigned int timeout_clks
)
1397 unsigned int timeout
, cycle_ns
;
1398 uint32_t reg
, clkd
, dto
= 0;
1400 reg
= OMAP_HSMMC_READ(host
->base
, SYSCTL
);
1401 clkd
= (reg
& CLKD_MASK
) >> CLKD_SHIFT
;
1405 cycle_ns
= 1000000000 / (clk_get_rate(host
->fclk
) / clkd
);
1406 timeout
= timeout_ns
/ cycle_ns
;
1407 timeout
+= timeout_clks
;
1409 while ((timeout
& 0x80000000) == 0) {
1426 reg
|= dto
<< DTO_SHIFT
;
1427 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
, reg
);
1431 * Configure block length for MMC/SD cards and initiate the transfer.
1434 omap_hsmmc_prepare_data(struct omap_hsmmc_host
*host
, struct mmc_request
*req
)
1437 host
->data
= req
->data
;
1439 if (req
->data
== NULL
) {
1440 OMAP_HSMMC_WRITE(host
->base
, BLK
, 0);
1442 * Set an arbitrary 100ms data timeout for commands with
1445 if (req
->cmd
->flags
& MMC_RSP_BUSY
)
1446 set_data_timeout(host
, 100000000U, 0);
1450 OMAP_HSMMC_WRITE(host
->base
, BLK
, (req
->data
->blksz
)
1451 | (req
->data
->blocks
<< 16));
1452 set_data_timeout(host
, req
->data
->timeout_ns
, req
->data
->timeout_clks
);
1454 if (host
->use_dma
) {
1455 ret
= omap_hsmmc_start_dma_transfer(host
, req
);
1457 dev_dbg(mmc_dev(host
->mmc
), "MMC start dma failure\n");
1465 * Request function. for read/write operation
1467 static void omap_hsmmc_request(struct mmc_host
*mmc
, struct mmc_request
*req
)
1469 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1472 BUG_ON(host
->req_in_progress
);
1473 BUG_ON(host
->dma_ch
!= -1);
1474 if (host
->protect_card
) {
1475 if (host
->reqs_blocked
< 3) {
1477 * Ensure the controller is left in a consistent
1478 * state by resetting the command and data state
1481 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1482 omap_hsmmc_reset_controller_fsm(host
, SRC
);
1483 host
->reqs_blocked
+= 1;
1485 req
->cmd
->error
= -EBADF
;
1487 req
->data
->error
= -EBADF
;
1488 req
->cmd
->retries
= 0;
1489 mmc_request_done(mmc
, req
);
1491 } else if (host
->reqs_blocked
)
1492 host
->reqs_blocked
= 0;
1493 WARN_ON(host
->mrq
!= NULL
);
1495 err
= omap_hsmmc_prepare_data(host
, req
);
1497 req
->cmd
->error
= err
;
1499 req
->data
->error
= err
;
1501 mmc_request_done(mmc
, req
);
1505 omap_hsmmc_start_command(host
, req
->cmd
, req
->data
);
1508 /* Routine to configure clock values. Exposed API to core */
1509 static void omap_hsmmc_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1511 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1513 unsigned long regval
;
1514 unsigned long timeout
;
1516 int do_send_init_stream
= 0;
1518 mmc_host_enable(host
->mmc
);
1520 if (ios
->power_mode
!= host
->power_mode
) {
1521 switch (ios
->power_mode
) {
1523 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
,
1528 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
,
1530 host
->vdd
= ios
->vdd
;
1533 do_send_init_stream
= 1;
1536 host
->power_mode
= ios
->power_mode
;
1539 /* FIXME: set registers based only on changes to ios */
1541 con
= OMAP_HSMMC_READ(host
->base
, CON
);
1542 switch (mmc
->ios
.bus_width
) {
1543 case MMC_BUS_WIDTH_8
:
1544 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| DW8
);
1546 case MMC_BUS_WIDTH_4
:
1547 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
1548 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1549 OMAP_HSMMC_READ(host
->base
, HCTL
) | FOUR_BIT
);
1551 case MMC_BUS_WIDTH_1
:
1552 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
1553 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1554 OMAP_HSMMC_READ(host
->base
, HCTL
) & ~FOUR_BIT
);
1558 if (host
->id
== OMAP_MMC1_DEVID
) {
1559 /* Only MMC1 can interface at 3V without some flavor
1560 * of external transceiver; but they all handle 1.8V.
1562 if ((OMAP_HSMMC_READ(host
->base
, HCTL
) & SDVSDET
) &&
1563 (ios
->vdd
== DUAL_VOLT_OCR_BIT
)) {
1565 * The mmc_select_voltage fn of the core does
1566 * not seem to set the power_mode to
1567 * MMC_POWER_UP upon recalculating the voltage.
1570 if (omap_hsmmc_switch_opcond(host
, ios
->vdd
) != 0)
1571 dev_dbg(mmc_dev(host
->mmc
),
1572 "Switch operation failed\n");
1577 dsor
= OMAP_MMC_MASTER_CLOCK
/ ios
->clock
;
1581 if (OMAP_MMC_MASTER_CLOCK
/ dsor
> ios
->clock
)
1587 omap_hsmmc_stop_clock(host
);
1588 regval
= OMAP_HSMMC_READ(host
->base
, SYSCTL
);
1589 regval
= regval
& ~(CLKD_MASK
);
1590 regval
= regval
| (dsor
<< 6) | (DTO
<< 16);
1591 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
, regval
);
1592 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
1593 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | ICE
);
1595 /* Wait till the ICS bit is set */
1596 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
1597 while ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ICS
) != ICS
1598 && time_before(jiffies
, timeout
))
1601 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
1602 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | CEN
);
1604 if (do_send_init_stream
)
1605 send_init_stream(host
);
1607 con
= OMAP_HSMMC_READ(host
->base
, CON
);
1608 if (ios
->bus_mode
== MMC_BUSMODE_OPENDRAIN
)
1609 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| OD
);
1611 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~OD
);
1613 if (host
->power_mode
== MMC_POWER_OFF
)
1614 mmc_host_disable(host
->mmc
);
1616 mmc_host_lazy_disable(host
->mmc
);
1619 static int omap_hsmmc_get_cd(struct mmc_host
*mmc
)
1621 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1623 if (!mmc_slot(host
).card_detect
)
1625 return mmc_slot(host
).card_detect(host
->dev
, host
->slot_id
);
1628 static int omap_hsmmc_get_ro(struct mmc_host
*mmc
)
1630 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1632 if (!mmc_slot(host
).get_ro
)
1634 return mmc_slot(host
).get_ro(host
->dev
, 0);
1637 static void omap_hsmmc_init_card(struct mmc_host
*mmc
, struct mmc_card
*card
)
1639 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1641 if (mmc_slot(host
).init_card
)
1642 mmc_slot(host
).init_card(card
);
1645 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host
*host
)
1647 u32 hctl
, capa
, value
;
1649 /* Only MMC1 supports 3.0V */
1650 if (host
->id
== OMAP_MMC1_DEVID
) {
1658 value
= OMAP_HSMMC_READ(host
->base
, HCTL
) & ~SDVS_MASK
;
1659 OMAP_HSMMC_WRITE(host
->base
, HCTL
, value
| hctl
);
1661 value
= OMAP_HSMMC_READ(host
->base
, CAPA
);
1662 OMAP_HSMMC_WRITE(host
->base
, CAPA
, value
| capa
);
1664 /* Set the controller to AUTO IDLE mode */
1665 value
= OMAP_HSMMC_READ(host
->base
, SYSCONFIG
);
1666 OMAP_HSMMC_WRITE(host
->base
, SYSCONFIG
, value
| AUTOIDLE
);
1668 /* Set SD bus power bit */
1669 set_sd_bus_power(host
);
1673 * Dynamic power saving handling, FSM:
1674 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1676 * |______________________|______________________|
1678 * ENABLED: mmc host is fully functional
1679 * DISABLED: fclk is off
1680 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1681 * REGSLEEP: fclk is off, voltage regulator is asleep
1682 * OFF: fclk is off, voltage regulator is off
1684 * Transition handlers return the timeout for the next state transition
1685 * or negative error.
1688 enum {ENABLED
= 0, DISABLED
, CARDSLEEP
, REGSLEEP
, OFF
};
1690 /* Handler for [ENABLED -> DISABLED] transition */
1691 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host
*host
)
1693 omap_hsmmc_context_save(host
);
1694 clk_disable(host
->fclk
);
1695 host
->dpm_state
= DISABLED
;
1697 dev_dbg(mmc_dev(host
->mmc
), "ENABLED -> DISABLED\n");
1699 if (host
->power_mode
== MMC_POWER_OFF
)
1702 return OMAP_MMC_SLEEP_TIMEOUT
;
1705 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1706 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host
*host
)
1710 if (!mmc_try_claim_host(host
->mmc
))
1713 clk_enable(host
->fclk
);
1714 omap_hsmmc_context_restore(host
);
1715 if (mmc_card_can_sleep(host
->mmc
)) {
1716 err
= mmc_card_sleep(host
->mmc
);
1718 clk_disable(host
->fclk
);
1719 mmc_release_host(host
->mmc
);
1722 new_state
= CARDSLEEP
;
1724 new_state
= REGSLEEP
;
1726 if (mmc_slot(host
).set_sleep
)
1727 mmc_slot(host
).set_sleep(host
->dev
, host
->slot_id
, 1, 0,
1728 new_state
== CARDSLEEP
);
1729 /* FIXME: turn off bus power and perhaps interrupts too */
1730 clk_disable(host
->fclk
);
1731 host
->dpm_state
= new_state
;
1733 mmc_release_host(host
->mmc
);
1735 dev_dbg(mmc_dev(host
->mmc
), "DISABLED -> %s\n",
1736 host
->dpm_state
== CARDSLEEP
? "CARDSLEEP" : "REGSLEEP");
1738 if (mmc_slot(host
).no_off
)
1741 if ((host
->mmc
->caps
& MMC_CAP_NONREMOVABLE
) ||
1742 mmc_slot(host
).card_detect
||
1743 (mmc_slot(host
).get_cover_state
&&
1744 mmc_slot(host
).get_cover_state(host
->dev
, host
->slot_id
)))
1745 return OMAP_MMC_OFF_TIMEOUT
;
1750 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1751 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host
*host
)
1753 if (!mmc_try_claim_host(host
->mmc
))
1756 if (mmc_slot(host
).no_off
)
1759 if (!((host
->mmc
->caps
& MMC_CAP_NONREMOVABLE
) ||
1760 mmc_slot(host
).card_detect
||
1761 (mmc_slot(host
).get_cover_state
&&
1762 mmc_slot(host
).get_cover_state(host
->dev
, host
->slot_id
)))) {
1763 mmc_release_host(host
->mmc
);
1767 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
, 0, 0);
1769 host
->power_mode
= MMC_POWER_OFF
;
1771 dev_dbg(mmc_dev(host
->mmc
), "%s -> OFF\n",
1772 host
->dpm_state
== CARDSLEEP
? "CARDSLEEP" : "REGSLEEP");
1774 host
->dpm_state
= OFF
;
1776 mmc_release_host(host
->mmc
);
1781 /* Handler for [DISABLED -> ENABLED] transition */
1782 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host
*host
)
1786 err
= clk_enable(host
->fclk
);
1790 omap_hsmmc_context_restore(host
);
1791 host
->dpm_state
= ENABLED
;
1793 dev_dbg(mmc_dev(host
->mmc
), "DISABLED -> ENABLED\n");
1798 /* Handler for [SLEEP -> ENABLED] transition */
1799 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host
*host
)
1801 if (!mmc_try_claim_host(host
->mmc
))
1804 clk_enable(host
->fclk
);
1805 omap_hsmmc_context_restore(host
);
1806 if (mmc_slot(host
).set_sleep
)
1807 mmc_slot(host
).set_sleep(host
->dev
, host
->slot_id
, 0,
1808 host
->vdd
, host
->dpm_state
== CARDSLEEP
);
1809 if (mmc_card_can_sleep(host
->mmc
))
1810 mmc_card_awake(host
->mmc
);
1812 dev_dbg(mmc_dev(host
->mmc
), "%s -> ENABLED\n",
1813 host
->dpm_state
== CARDSLEEP
? "CARDSLEEP" : "REGSLEEP");
1815 host
->dpm_state
= ENABLED
;
1817 mmc_release_host(host
->mmc
);
1822 /* Handler for [OFF -> ENABLED] transition */
1823 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host
*host
)
1825 clk_enable(host
->fclk
);
1827 omap_hsmmc_context_restore(host
);
1828 omap_hsmmc_conf_bus_power(host
);
1829 mmc_power_restore_host(host
->mmc
);
1831 host
->dpm_state
= ENABLED
;
1833 dev_dbg(mmc_dev(host
->mmc
), "OFF -> ENABLED\n");
1839 * Bring MMC host to ENABLED from any other PM state.
1841 static int omap_hsmmc_enable(struct mmc_host
*mmc
)
1843 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1845 switch (host
->dpm_state
) {
1847 return omap_hsmmc_disabled_to_enabled(host
);
1850 return omap_hsmmc_sleep_to_enabled(host
);
1852 return omap_hsmmc_off_to_enabled(host
);
1854 dev_dbg(mmc_dev(host
->mmc
), "UNKNOWN state\n");
1860 * Bring MMC host in PM state (one level deeper).
1862 static int omap_hsmmc_disable(struct mmc_host
*mmc
, int lazy
)
1864 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1866 switch (host
->dpm_state
) {
1870 delay
= omap_hsmmc_enabled_to_disabled(host
);
1871 if (lazy
|| delay
< 0)
1876 return omap_hsmmc_disabled_to_sleep(host
);
1879 return omap_hsmmc_sleep_to_off(host
);
1881 dev_dbg(mmc_dev(host
->mmc
), "UNKNOWN state\n");
1886 static int omap_hsmmc_enable_fclk(struct mmc_host
*mmc
)
1888 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1891 err
= clk_enable(host
->fclk
);
1894 dev_dbg(mmc_dev(host
->mmc
), "mmc_fclk: enabled\n");
1895 omap_hsmmc_context_restore(host
);
1899 static int omap_hsmmc_disable_fclk(struct mmc_host
*mmc
, int lazy
)
1901 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1903 omap_hsmmc_context_save(host
);
1904 clk_disable(host
->fclk
);
1905 dev_dbg(mmc_dev(host
->mmc
), "mmc_fclk: disabled\n");
1909 static const struct mmc_host_ops omap_hsmmc_ops
= {
1910 .enable
= omap_hsmmc_enable_fclk
,
1911 .disable
= omap_hsmmc_disable_fclk
,
1912 .request
= omap_hsmmc_request
,
1913 .set_ios
= omap_hsmmc_set_ios
,
1914 .get_cd
= omap_hsmmc_get_cd
,
1915 .get_ro
= omap_hsmmc_get_ro
,
1916 .init_card
= omap_hsmmc_init_card
,
1917 /* NYET -- enable_sdio_irq */
1920 static const struct mmc_host_ops omap_hsmmc_ps_ops
= {
1921 .enable
= omap_hsmmc_enable
,
1922 .disable
= omap_hsmmc_disable
,
1923 .request
= omap_hsmmc_request
,
1924 .set_ios
= omap_hsmmc_set_ios
,
1925 .get_cd
= omap_hsmmc_get_cd
,
1926 .get_ro
= omap_hsmmc_get_ro
,
1927 .init_card
= omap_hsmmc_init_card
,
1928 /* NYET -- enable_sdio_irq */
1931 #ifdef CONFIG_DEBUG_FS
1933 static int omap_hsmmc_regs_show(struct seq_file
*s
, void *data
)
1935 struct mmc_host
*mmc
= s
->private;
1936 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1937 int context_loss
= 0;
1939 if (host
->pdata
->get_context_loss_count
)
1940 context_loss
= host
->pdata
->get_context_loss_count(host
->dev
);
1942 seq_printf(s
, "mmc%d:\n"
1945 " nesting_cnt:\t%d\n"
1946 " ctx_loss:\t%d:%d\n"
1948 mmc
->index
, mmc
->enabled
? 1 : 0,
1949 host
->dpm_state
, mmc
->nesting_cnt
,
1950 host
->context_loss
, context_loss
);
1952 if (host
->suspended
|| host
->dpm_state
== OFF
) {
1953 seq_printf(s
, "host suspended, can't read registers\n");
1957 if (clk_enable(host
->fclk
) != 0) {
1958 seq_printf(s
, "can't read the regs\n");
1962 seq_printf(s
, "SYSCONFIG:\t0x%08x\n",
1963 OMAP_HSMMC_READ(host
->base
, SYSCONFIG
));
1964 seq_printf(s
, "CON:\t\t0x%08x\n",
1965 OMAP_HSMMC_READ(host
->base
, CON
));
1966 seq_printf(s
, "HCTL:\t\t0x%08x\n",
1967 OMAP_HSMMC_READ(host
->base
, HCTL
));
1968 seq_printf(s
, "SYSCTL:\t\t0x%08x\n",
1969 OMAP_HSMMC_READ(host
->base
, SYSCTL
));
1970 seq_printf(s
, "IE:\t\t0x%08x\n",
1971 OMAP_HSMMC_READ(host
->base
, IE
));
1972 seq_printf(s
, "ISE:\t\t0x%08x\n",
1973 OMAP_HSMMC_READ(host
->base
, ISE
));
1974 seq_printf(s
, "CAPA:\t\t0x%08x\n",
1975 OMAP_HSMMC_READ(host
->base
, CAPA
));
1977 clk_disable(host
->fclk
);
1982 static int omap_hsmmc_regs_open(struct inode
*inode
, struct file
*file
)
1984 return single_open(file
, omap_hsmmc_regs_show
, inode
->i_private
);
1987 static const struct file_operations mmc_regs_fops
= {
1988 .open
= omap_hsmmc_regs_open
,
1990 .llseek
= seq_lseek
,
1991 .release
= single_release
,
1994 static void omap_hsmmc_debugfs(struct mmc_host
*mmc
)
1996 if (mmc
->debugfs_root
)
1997 debugfs_create_file("regs", S_IRUSR
, mmc
->debugfs_root
,
1998 mmc
, &mmc_regs_fops
);
2003 static void omap_hsmmc_debugfs(struct mmc_host
*mmc
)
2009 static int __init
omap_hsmmc_probe(struct platform_device
*pdev
)
2011 struct omap_mmc_platform_data
*pdata
= pdev
->dev
.platform_data
;
2012 struct mmc_host
*mmc
;
2013 struct omap_hsmmc_host
*host
= NULL
;
2014 struct resource
*res
;
2017 if (pdata
== NULL
) {
2018 dev_err(&pdev
->dev
, "Platform Data is missing\n");
2022 if (pdata
->nr_slots
== 0) {
2023 dev_err(&pdev
->dev
, "No Slots\n");
2027 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2028 irq
= platform_get_irq(pdev
, 0);
2029 if (res
== NULL
|| irq
< 0)
2032 res
->start
+= pdata
->reg_offset
;
2033 res
->end
+= pdata
->reg_offset
;
2034 res
= request_mem_region(res
->start
, res
->end
- res
->start
+ 1,
2039 ret
= omap_hsmmc_gpio_init(pdata
);
2043 mmc
= mmc_alloc_host(sizeof(struct omap_hsmmc_host
), &pdev
->dev
);
2049 host
= mmc_priv(mmc
);
2051 host
->pdata
= pdata
;
2052 host
->dev
= &pdev
->dev
;
2054 host
->dev
->dma_mask
= &pdata
->dma_mask
;
2057 host
->id
= pdev
->id
;
2059 host
->mapbase
= res
->start
;
2060 host
->base
= ioremap(host
->mapbase
, SZ_4K
);
2061 host
->power_mode
= MMC_POWER_OFF
;
2063 platform_set_drvdata(pdev
, host
);
2064 INIT_WORK(&host
->mmc_carddetect_work
, omap_hsmmc_detect
);
2066 if (mmc_slot(host
).power_saving
)
2067 mmc
->ops
= &omap_hsmmc_ps_ops
;
2069 mmc
->ops
= &omap_hsmmc_ops
;
2072 * If regulator_disable can only put vcc_aux to sleep then there is
2075 if (mmc_slot(host
).vcc_aux_disable_is_sleep
)
2076 mmc_slot(host
).no_off
= 1;
2078 mmc
->f_min
= 400000;
2079 mmc
->f_max
= 52000000;
2081 spin_lock_init(&host
->irq_lock
);
2083 host
->iclk
= clk_get(&pdev
->dev
, "ick");
2084 if (IS_ERR(host
->iclk
)) {
2085 ret
= PTR_ERR(host
->iclk
);
2089 host
->fclk
= clk_get(&pdev
->dev
, "fck");
2090 if (IS_ERR(host
->fclk
)) {
2091 ret
= PTR_ERR(host
->fclk
);
2093 clk_put(host
->iclk
);
2097 omap_hsmmc_context_save(host
);
2099 mmc
->caps
|= MMC_CAP_DISABLE
;
2100 mmc_set_disable_delay(mmc
, OMAP_MMC_DISABLED_TIMEOUT
);
2101 /* we start off in DISABLED state */
2102 host
->dpm_state
= DISABLED
;
2104 if (mmc_host_enable(host
->mmc
) != 0) {
2105 clk_put(host
->iclk
);
2106 clk_put(host
->fclk
);
2110 if (clk_enable(host
->iclk
) != 0) {
2111 mmc_host_disable(host
->mmc
);
2112 clk_put(host
->iclk
);
2113 clk_put(host
->fclk
);
2117 if (cpu_is_omap2430()) {
2118 host
->dbclk
= clk_get(&pdev
->dev
, "mmchsdb_fck");
2120 * MMC can still work without debounce clock.
2122 if (IS_ERR(host
->dbclk
))
2123 dev_warn(mmc_dev(host
->mmc
),
2124 "Failed to get debounce clock\n");
2126 host
->got_dbclk
= 1;
2128 if (host
->got_dbclk
)
2129 if (clk_enable(host
->dbclk
) != 0)
2130 dev_dbg(mmc_dev(host
->mmc
), "Enabling debounce"
2134 /* Since we do only SG emulation, we can have as many segs
2136 mmc
->max_segs
= 1024;
2138 mmc
->max_blk_size
= 512; /* Block Length at max can be 1024 */
2139 mmc
->max_blk_count
= 0xFFFF; /* No. of Blocks is 16 bits */
2140 mmc
->max_req_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
2141 mmc
->max_seg_size
= mmc
->max_req_size
;
2143 mmc
->caps
|= MMC_CAP_MMC_HIGHSPEED
| MMC_CAP_SD_HIGHSPEED
|
2144 MMC_CAP_WAIT_WHILE_BUSY
| MMC_CAP_ERASE
;
2146 mmc
->caps
|= mmc_slot(host
).caps
;
2147 if (mmc
->caps
& MMC_CAP_8_BIT_DATA
)
2148 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
2150 if (mmc_slot(host
).nonremovable
)
2151 mmc
->caps
|= MMC_CAP_NONREMOVABLE
;
2153 omap_hsmmc_conf_bus_power(host
);
2155 /* Select DMA lines */
2157 case OMAP_MMC1_DEVID
:
2158 host
->dma_line_tx
= OMAP24XX_DMA_MMC1_TX
;
2159 host
->dma_line_rx
= OMAP24XX_DMA_MMC1_RX
;
2161 case OMAP_MMC2_DEVID
:
2162 host
->dma_line_tx
= OMAP24XX_DMA_MMC2_TX
;
2163 host
->dma_line_rx
= OMAP24XX_DMA_MMC2_RX
;
2165 case OMAP_MMC3_DEVID
:
2166 host
->dma_line_tx
= OMAP34XX_DMA_MMC3_TX
;
2167 host
->dma_line_rx
= OMAP34XX_DMA_MMC3_RX
;
2169 case OMAP_MMC4_DEVID
:
2170 host
->dma_line_tx
= OMAP44XX_DMA_MMC4_TX
;
2171 host
->dma_line_rx
= OMAP44XX_DMA_MMC4_RX
;
2173 case OMAP_MMC5_DEVID
:
2174 host
->dma_line_tx
= OMAP44XX_DMA_MMC5_TX
;
2175 host
->dma_line_rx
= OMAP44XX_DMA_MMC5_RX
;
2178 dev_err(mmc_dev(host
->mmc
), "Invalid MMC id\n");
2182 /* Request IRQ for MMC operations */
2183 ret
= request_irq(host
->irq
, omap_hsmmc_irq
, IRQF_DISABLED
,
2184 mmc_hostname(mmc
), host
);
2186 dev_dbg(mmc_dev(host
->mmc
), "Unable to grab HSMMC IRQ\n");
2190 if (pdata
->init
!= NULL
) {
2191 if (pdata
->init(&pdev
->dev
) != 0) {
2192 dev_dbg(mmc_dev(host
->mmc
),
2193 "Unable to configure MMC IRQs\n");
2194 goto err_irq_cd_init
;
2198 if (omap_hsmmc_have_reg() && !mmc_slot(host
).set_power
) {
2199 ret
= omap_hsmmc_reg_get(host
);
2205 mmc
->ocr_avail
= mmc_slot(host
).ocr_mask
;
2207 /* Request IRQ for card detect */
2208 if ((mmc_slot(host
).card_detect_irq
)) {
2209 ret
= request_irq(mmc_slot(host
).card_detect_irq
,
2210 omap_hsmmc_cd_handler
,
2211 IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
2213 mmc_hostname(mmc
), host
);
2215 dev_dbg(mmc_dev(host
->mmc
),
2216 "Unable to grab MMC CD IRQ\n");
2219 pdata
->suspend
= omap_hsmmc_suspend_cdirq
;
2220 pdata
->resume
= omap_hsmmc_resume_cdirq
;
2223 omap_hsmmc_disable_irq(host
);
2225 mmc_host_lazy_disable(host
->mmc
);
2227 omap_hsmmc_protect_card(host
);
2231 if (mmc_slot(host
).name
!= NULL
) {
2232 ret
= device_create_file(&mmc
->class_dev
, &dev_attr_slot_name
);
2236 if (mmc_slot(host
).card_detect_irq
&& mmc_slot(host
).get_cover_state
) {
2237 ret
= device_create_file(&mmc
->class_dev
,
2238 &dev_attr_cover_switch
);
2243 omap_hsmmc_debugfs(mmc
);
2248 mmc_remove_host(mmc
);
2249 free_irq(mmc_slot(host
).card_detect_irq
, host
);
2252 omap_hsmmc_reg_put(host
);
2254 if (host
->pdata
->cleanup
)
2255 host
->pdata
->cleanup(&pdev
->dev
);
2257 free_irq(host
->irq
, host
);
2259 mmc_host_disable(host
->mmc
);
2260 clk_disable(host
->iclk
);
2261 clk_put(host
->fclk
);
2262 clk_put(host
->iclk
);
2263 if (host
->got_dbclk
) {
2264 clk_disable(host
->dbclk
);
2265 clk_put(host
->dbclk
);
2268 iounmap(host
->base
);
2269 platform_set_drvdata(pdev
, NULL
);
2272 omap_hsmmc_gpio_free(pdata
);
2274 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
2278 static int omap_hsmmc_remove(struct platform_device
*pdev
)
2280 struct omap_hsmmc_host
*host
= platform_get_drvdata(pdev
);
2281 struct resource
*res
;
2284 mmc_host_enable(host
->mmc
);
2285 mmc_remove_host(host
->mmc
);
2287 omap_hsmmc_reg_put(host
);
2288 if (host
->pdata
->cleanup
)
2289 host
->pdata
->cleanup(&pdev
->dev
);
2290 free_irq(host
->irq
, host
);
2291 if (mmc_slot(host
).card_detect_irq
)
2292 free_irq(mmc_slot(host
).card_detect_irq
, host
);
2293 flush_scheduled_work();
2295 mmc_host_disable(host
->mmc
);
2296 clk_disable(host
->iclk
);
2297 clk_put(host
->fclk
);
2298 clk_put(host
->iclk
);
2299 if (host
->got_dbclk
) {
2300 clk_disable(host
->dbclk
);
2301 clk_put(host
->dbclk
);
2304 mmc_free_host(host
->mmc
);
2305 iounmap(host
->base
);
2306 omap_hsmmc_gpio_free(pdev
->dev
.platform_data
);
2309 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2311 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
2312 platform_set_drvdata(pdev
, NULL
);
2318 static int omap_hsmmc_suspend(struct device
*dev
)
2321 struct platform_device
*pdev
= to_platform_device(dev
);
2322 struct omap_hsmmc_host
*host
= platform_get_drvdata(pdev
);
2324 if (host
&& host
->suspended
)
2328 host
->suspended
= 1;
2329 if (host
->pdata
->suspend
) {
2330 ret
= host
->pdata
->suspend(&pdev
->dev
,
2333 dev_dbg(mmc_dev(host
->mmc
),
2334 "Unable to handle MMC board"
2335 " level suspend\n");
2336 host
->suspended
= 0;
2340 cancel_work_sync(&host
->mmc_carddetect_work
);
2341 ret
= mmc_suspend_host(host
->mmc
);
2342 mmc_host_enable(host
->mmc
);
2344 omap_hsmmc_disable_irq(host
);
2345 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
2346 OMAP_HSMMC_READ(host
->base
, HCTL
) & ~SDBP
);
2347 mmc_host_disable(host
->mmc
);
2348 clk_disable(host
->iclk
);
2349 if (host
->got_dbclk
)
2350 clk_disable(host
->dbclk
);
2352 host
->suspended
= 0;
2353 if (host
->pdata
->resume
) {
2354 ret
= host
->pdata
->resume(&pdev
->dev
,
2357 dev_dbg(mmc_dev(host
->mmc
),
2358 "Unmask interrupt failed\n");
2360 mmc_host_disable(host
->mmc
);
2367 /* Routine to resume the MMC device */
2368 static int omap_hsmmc_resume(struct device
*dev
)
2371 struct platform_device
*pdev
= to_platform_device(dev
);
2372 struct omap_hsmmc_host
*host
= platform_get_drvdata(pdev
);
2374 if (host
&& !host
->suspended
)
2378 ret
= clk_enable(host
->iclk
);
2382 if (mmc_host_enable(host
->mmc
) != 0) {
2383 clk_disable(host
->iclk
);
2387 if (host
->got_dbclk
)
2388 clk_enable(host
->dbclk
);
2390 omap_hsmmc_conf_bus_power(host
);
2392 if (host
->pdata
->resume
) {
2393 ret
= host
->pdata
->resume(&pdev
->dev
, host
->slot_id
);
2395 dev_dbg(mmc_dev(host
->mmc
),
2396 "Unmask interrupt failed\n");
2399 omap_hsmmc_protect_card(host
);
2401 /* Notify the core to resume the host */
2402 ret
= mmc_resume_host(host
->mmc
);
2404 host
->suspended
= 0;
2406 mmc_host_lazy_disable(host
->mmc
);
2412 dev_dbg(mmc_dev(host
->mmc
),
2413 "Failed to enable MMC clocks during resume\n");
2418 #define omap_hsmmc_suspend NULL
2419 #define omap_hsmmc_resume NULL
2422 static struct dev_pm_ops omap_hsmmc_dev_pm_ops
= {
2423 .suspend
= omap_hsmmc_suspend
,
2424 .resume
= omap_hsmmc_resume
,
2427 static struct platform_driver omap_hsmmc_driver
= {
2428 .remove
= omap_hsmmc_remove
,
2430 .name
= DRIVER_NAME
,
2431 .owner
= THIS_MODULE
,
2432 .pm
= &omap_hsmmc_dev_pm_ops
,
2436 static int __init
omap_hsmmc_init(void)
2438 /* Register the MMC driver */
2439 return platform_driver_probe(&omap_hsmmc_driver
, omap_hsmmc_probe
);
2442 static void __exit
omap_hsmmc_cleanup(void)
2444 /* Unregister MMC driver */
2445 platform_driver_unregister(&omap_hsmmc_driver
);
2448 module_init(omap_hsmmc_init
);
2449 module_exit(omap_hsmmc_cleanup
);
2451 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2452 MODULE_LICENSE("GPL");
2453 MODULE_ALIAS("platform:" DRIVER_NAME
);
2454 MODULE_AUTHOR("Texas Instruments Inc");