2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/timer.h>
29 #include <linux/clk.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_device.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/core.h>
35 #include <linux/mmc/mmc.h>
37 #include <linux/semaphore.h>
38 #include <linux/gpio.h>
39 #include <linux/regulator/consumer.h>
40 #include <linux/pm_runtime.h>
41 #include <mach/hardware.h>
42 #include <plat/board.h>
46 /* OMAP HSMMC Host Controller Registers */
47 #define OMAP_HSMMC_SYSCONFIG 0x0010
48 #define OMAP_HSMMC_SYSSTATUS 0x0014
49 #define OMAP_HSMMC_CON 0x002C
50 #define OMAP_HSMMC_BLK 0x0104
51 #define OMAP_HSMMC_ARG 0x0108
52 #define OMAP_HSMMC_CMD 0x010C
53 #define OMAP_HSMMC_RSP10 0x0110
54 #define OMAP_HSMMC_RSP32 0x0114
55 #define OMAP_HSMMC_RSP54 0x0118
56 #define OMAP_HSMMC_RSP76 0x011C
57 #define OMAP_HSMMC_DATA 0x0120
58 #define OMAP_HSMMC_HCTL 0x0128
59 #define OMAP_HSMMC_SYSCTL 0x012C
60 #define OMAP_HSMMC_STAT 0x0130
61 #define OMAP_HSMMC_IE 0x0134
62 #define OMAP_HSMMC_ISE 0x0138
63 #define OMAP_HSMMC_CAPA 0x0140
65 #define VS18 (1 << 26)
66 #define VS30 (1 << 25)
67 #define SDVS18 (0x5 << 9)
68 #define SDVS30 (0x6 << 9)
69 #define SDVS33 (0x7 << 9)
70 #define SDVS_MASK 0x00000E00
71 #define SDVSCLR 0xFFFFF1FF
72 #define SDVSDET 0x00000400
79 #define CLKD_MASK 0x0000FFC0
81 #define DTO_MASK 0x000F0000
83 #define INT_EN_MASK 0x307F0033
84 #define BWR_ENABLE (1 << 4)
85 #define BRR_ENABLE (1 << 5)
86 #define DTO_ENABLE (1 << 20)
87 #define INIT_STREAM (1 << 1)
88 #define DP_SELECT (1 << 21)
93 #define FOUR_BIT (1 << 1)
100 #define CMD_TIMEOUT (1 << 16)
101 #define DATA_TIMEOUT (1 << 20)
102 #define CMD_CRC (1 << 17)
103 #define DATA_CRC (1 << 21)
104 #define CARD_ERR (1 << 28)
105 #define STAT_CLEAR 0xFFFFFFFF
106 #define INIT_STREAM_CMD 0x00000000
107 #define DUAL_VOLT_OCR_BIT 7
108 #define SRC (1 << 25)
109 #define SRD (1 << 26)
110 #define SOFTRESET (1 << 1)
111 #define RESETDONE (1 << 0)
113 #define MMC_AUTOSUSPEND_DELAY 100
114 #define MMC_TIMEOUT_MS 20
115 #define OMAP_MMC_MIN_CLOCK 400000
116 #define OMAP_MMC_MAX_CLOCK 52000000
117 #define DRIVER_NAME "omap_hsmmc"
120 * One controller can have multiple slots, like on some omap boards using
121 * omap.c controller driver. Luckily this is not currently done on any known
122 * omap_hsmmc.c device.
124 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
127 * MMC Host controller read/write API's
129 #define OMAP_HSMMC_READ(base, reg) \
130 __raw_readl((base) + OMAP_HSMMC_##reg)
132 #define OMAP_HSMMC_WRITE(base, reg, val) \
133 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
135 struct omap_hsmmc_next
{
136 unsigned int dma_len
;
140 struct omap_hsmmc_host
{
142 struct mmc_host
*mmc
;
143 struct mmc_request
*mrq
;
144 struct mmc_command
*cmd
;
145 struct mmc_data
*data
;
149 * vcc == configured supply
150 * vcc_aux == optional
151 * - MMC1, supply for DAT4..DAT7
152 * - MMC2/MMC2, external level shifter voltage supply, for
153 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
155 struct regulator
*vcc
;
156 struct regulator
*vcc_aux
;
158 resource_size_t mapbase
;
159 spinlock_t irq_lock
; /* Prevent races with irq handler */
160 unsigned int dma_len
;
161 unsigned int dma_sg_idx
;
162 unsigned char bus_mode
;
163 unsigned char power_mode
;
169 struct dma_chan
*tx_chan
;
170 struct dma_chan
*rx_chan
;
179 struct omap_hsmmc_next next_data
;
181 struct omap_mmc_platform_data
*pdata
;
184 static int omap_hsmmc_card_detect(struct device
*dev
, int slot
)
186 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
188 /* NOTE: assumes card detect signal is active-low */
189 return !gpio_get_value_cansleep(mmc
->slots
[0].switch_pin
);
192 static int omap_hsmmc_get_wp(struct device
*dev
, int slot
)
194 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
196 /* NOTE: assumes write protect signal is active-high */
197 return gpio_get_value_cansleep(mmc
->slots
[0].gpio_wp
);
200 static int omap_hsmmc_get_cover_state(struct device
*dev
, int slot
)
202 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
204 /* NOTE: assumes card detect signal is active-low */
205 return !gpio_get_value_cansleep(mmc
->slots
[0].switch_pin
);
210 static int omap_hsmmc_suspend_cdirq(struct device
*dev
, int slot
)
212 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
214 disable_irq(mmc
->slots
[0].card_detect_irq
);
218 static int omap_hsmmc_resume_cdirq(struct device
*dev
, int slot
)
220 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
222 enable_irq(mmc
->slots
[0].card_detect_irq
);
228 #define omap_hsmmc_suspend_cdirq NULL
229 #define omap_hsmmc_resume_cdirq NULL
233 #ifdef CONFIG_REGULATOR
235 static int omap_hsmmc_set_power(struct device
*dev
, int slot
, int power_on
,
238 struct omap_hsmmc_host
*host
=
239 platform_get_drvdata(to_platform_device(dev
));
243 * If we don't see a Vcc regulator, assume it's a fixed
244 * voltage always-on regulator.
249 * With DT, never turn OFF the regulator. This is because
250 * the pbias cell programming support is still missing when
251 * booting with Device tree
253 if (dev
->of_node
&& !vdd
)
256 if (mmc_slot(host
).before_set_reg
)
257 mmc_slot(host
).before_set_reg(dev
, slot
, power_on
, vdd
);
260 * Assume Vcc regulator is used only to power the card ... OMAP
261 * VDDS is used to power the pins, optionally with a transceiver to
262 * support cards using voltages other than VDDS (1.8V nominal). When a
263 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
265 * In some cases this regulator won't support enable/disable;
266 * e.g. it's a fixed rail for a WLAN chip.
268 * In other cases vcc_aux switches interface power. Example, for
269 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
270 * chips/cards need an interface voltage rail too.
273 ret
= mmc_regulator_set_ocr(host
->mmc
, host
->vcc
, vdd
);
274 /* Enable interface voltage rail, if needed */
275 if (ret
== 0 && host
->vcc_aux
) {
276 ret
= regulator_enable(host
->vcc_aux
);
278 ret
= mmc_regulator_set_ocr(host
->mmc
,
282 /* Shut down the rail */
284 ret
= regulator_disable(host
->vcc_aux
);
286 /* Then proceed to shut down the local regulator */
287 ret
= mmc_regulator_set_ocr(host
->mmc
,
292 if (mmc_slot(host
).after_set_reg
)
293 mmc_slot(host
).after_set_reg(dev
, slot
, power_on
, vdd
);
298 static int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host
)
300 struct regulator
*reg
;
303 mmc_slot(host
).set_power
= omap_hsmmc_set_power
;
305 reg
= regulator_get(host
->dev
, "vmmc");
307 dev_dbg(host
->dev
, "vmmc regulator missing\n");
310 ocr_value
= mmc_regulator_get_ocrmask(reg
);
311 if (!mmc_slot(host
).ocr_mask
) {
312 mmc_slot(host
).ocr_mask
= ocr_value
;
314 if (!(mmc_slot(host
).ocr_mask
& ocr_value
)) {
315 dev_err(host
->dev
, "ocrmask %x is not supported\n",
316 mmc_slot(host
).ocr_mask
);
317 mmc_slot(host
).ocr_mask
= 0;
322 /* Allow an aux regulator */
323 reg
= regulator_get(host
->dev
, "vmmc_aux");
324 host
->vcc_aux
= IS_ERR(reg
) ? NULL
: reg
;
326 /* For eMMC do not power off when not in sleep state */
327 if (mmc_slot(host
).no_regulator_off_init
)
330 * UGLY HACK: workaround regulator framework bugs.
331 * When the bootloader leaves a supply active, it's
332 * initialized with zero usecount ... and we can't
333 * disable it without first enabling it. Until the
334 * framework is fixed, we need a workaround like this
335 * (which is safe for MMC, but not in general).
337 if (regulator_is_enabled(host
->vcc
) > 0 ||
338 (host
->vcc_aux
&& regulator_is_enabled(host
->vcc_aux
))) {
339 int vdd
= ffs(mmc_slot(host
).ocr_mask
) - 1;
341 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
,
343 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
,
351 static void omap_hsmmc_reg_put(struct omap_hsmmc_host
*host
)
353 regulator_put(host
->vcc
);
354 regulator_put(host
->vcc_aux
);
355 mmc_slot(host
).set_power
= NULL
;
358 static inline int omap_hsmmc_have_reg(void)
365 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host
)
370 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host
*host
)
374 static inline int omap_hsmmc_have_reg(void)
381 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data
*pdata
)
385 if (gpio_is_valid(pdata
->slots
[0].switch_pin
)) {
386 if (pdata
->slots
[0].cover
)
387 pdata
->slots
[0].get_cover_state
=
388 omap_hsmmc_get_cover_state
;
390 pdata
->slots
[0].card_detect
= omap_hsmmc_card_detect
;
391 pdata
->slots
[0].card_detect_irq
=
392 gpio_to_irq(pdata
->slots
[0].switch_pin
);
393 ret
= gpio_request(pdata
->slots
[0].switch_pin
, "mmc_cd");
396 ret
= gpio_direction_input(pdata
->slots
[0].switch_pin
);
400 pdata
->slots
[0].switch_pin
= -EINVAL
;
402 if (gpio_is_valid(pdata
->slots
[0].gpio_wp
)) {
403 pdata
->slots
[0].get_ro
= omap_hsmmc_get_wp
;
404 ret
= gpio_request(pdata
->slots
[0].gpio_wp
, "mmc_wp");
407 ret
= gpio_direction_input(pdata
->slots
[0].gpio_wp
);
411 pdata
->slots
[0].gpio_wp
= -EINVAL
;
416 gpio_free(pdata
->slots
[0].gpio_wp
);
418 if (gpio_is_valid(pdata
->slots
[0].switch_pin
))
420 gpio_free(pdata
->slots
[0].switch_pin
);
424 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data
*pdata
)
426 if (gpio_is_valid(pdata
->slots
[0].gpio_wp
))
427 gpio_free(pdata
->slots
[0].gpio_wp
);
428 if (gpio_is_valid(pdata
->slots
[0].switch_pin
))
429 gpio_free(pdata
->slots
[0].switch_pin
);
433 * Start clock to the card
435 static void omap_hsmmc_start_clock(struct omap_hsmmc_host
*host
)
437 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
438 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | CEN
);
442 * Stop clock to the card
444 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host
*host
)
446 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
447 OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ~CEN
);
448 if ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & CEN
) != 0x0)
449 dev_dbg(mmc_dev(host
->mmc
), "MMC Clock is not stoped\n");
452 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host
*host
,
453 struct mmc_command
*cmd
)
455 unsigned int irq_mask
;
458 irq_mask
= INT_EN_MASK
& ~(BRR_ENABLE
| BWR_ENABLE
);
460 irq_mask
= INT_EN_MASK
;
462 /* Disable timeout for erases */
463 if (cmd
->opcode
== MMC_ERASE
)
464 irq_mask
&= ~DTO_ENABLE
;
466 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
467 OMAP_HSMMC_WRITE(host
->base
, ISE
, irq_mask
);
468 OMAP_HSMMC_WRITE(host
->base
, IE
, irq_mask
);
471 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host
*host
)
473 OMAP_HSMMC_WRITE(host
->base
, ISE
, 0);
474 OMAP_HSMMC_WRITE(host
->base
, IE
, 0);
475 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
478 /* Calculate divisor for the given clock frequency */
479 static u16
calc_divisor(struct omap_hsmmc_host
*host
, struct mmc_ios
*ios
)
484 dsor
= DIV_ROUND_UP(clk_get_rate(host
->fclk
), ios
->clock
);
492 static void omap_hsmmc_set_clock(struct omap_hsmmc_host
*host
)
494 struct mmc_ios
*ios
= &host
->mmc
->ios
;
495 unsigned long regval
;
496 unsigned long timeout
;
498 dev_dbg(mmc_dev(host
->mmc
), "Set clock to %uHz\n", ios
->clock
);
500 omap_hsmmc_stop_clock(host
);
502 regval
= OMAP_HSMMC_READ(host
->base
, SYSCTL
);
503 regval
= regval
& ~(CLKD_MASK
| DTO_MASK
);
504 regval
= regval
| (calc_divisor(host
, ios
) << 6) | (DTO
<< 16);
505 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
, regval
);
506 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
507 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | ICE
);
509 /* Wait till the ICS bit is set */
510 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
511 while ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ICS
) != ICS
512 && time_before(jiffies
, timeout
))
515 omap_hsmmc_start_clock(host
);
518 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host
*host
)
520 struct mmc_ios
*ios
= &host
->mmc
->ios
;
523 con
= OMAP_HSMMC_READ(host
->base
, CON
);
524 if (ios
->timing
== MMC_TIMING_UHS_DDR50
)
525 con
|= DDR
; /* configure in DDR mode */
528 switch (ios
->bus_width
) {
529 case MMC_BUS_WIDTH_8
:
530 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| DW8
);
532 case MMC_BUS_WIDTH_4
:
533 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
534 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
535 OMAP_HSMMC_READ(host
->base
, HCTL
) | FOUR_BIT
);
537 case MMC_BUS_WIDTH_1
:
538 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
539 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
540 OMAP_HSMMC_READ(host
->base
, HCTL
) & ~FOUR_BIT
);
545 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host
*host
)
547 struct mmc_ios
*ios
= &host
->mmc
->ios
;
550 con
= OMAP_HSMMC_READ(host
->base
, CON
);
551 if (ios
->bus_mode
== MMC_BUSMODE_OPENDRAIN
)
552 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| OD
);
554 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~OD
);
560 * Restore the MMC host context, if it was lost as result of a
561 * power state change.
563 static int omap_hsmmc_context_restore(struct omap_hsmmc_host
*host
)
565 struct mmc_ios
*ios
= &host
->mmc
->ios
;
566 struct omap_mmc_platform_data
*pdata
= host
->pdata
;
567 int context_loss
= 0;
569 unsigned long timeout
;
571 if (pdata
->get_context_loss_count
) {
572 context_loss
= pdata
->get_context_loss_count(host
->dev
);
573 if (context_loss
< 0)
577 dev_dbg(mmc_dev(host
->mmc
), "context was %slost\n",
578 context_loss
== host
->context_loss
? "not " : "");
579 if (host
->context_loss
== context_loss
)
582 /* Wait for hardware reset */
583 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
584 while ((OMAP_HSMMC_READ(host
->base
, SYSSTATUS
) & RESETDONE
) != RESETDONE
585 && time_before(jiffies
, timeout
))
588 /* Do software reset */
589 OMAP_HSMMC_WRITE(host
->base
, SYSCONFIG
, SOFTRESET
);
590 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
591 while ((OMAP_HSMMC_READ(host
->base
, SYSSTATUS
) & RESETDONE
) != RESETDONE
592 && time_before(jiffies
, timeout
))
595 OMAP_HSMMC_WRITE(host
->base
, SYSCONFIG
,
596 OMAP_HSMMC_READ(host
->base
, SYSCONFIG
) | AUTOIDLE
);
598 if (host
->pdata
->controller_flags
& OMAP_HSMMC_SUPPORTS_DUAL_VOLT
) {
599 if (host
->power_mode
!= MMC_POWER_OFF
&&
600 (1 << ios
->vdd
) <= MMC_VDD_23_24
)
610 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
611 OMAP_HSMMC_READ(host
->base
, HCTL
) | hctl
);
613 OMAP_HSMMC_WRITE(host
->base
, CAPA
,
614 OMAP_HSMMC_READ(host
->base
, CAPA
) | capa
);
616 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
617 OMAP_HSMMC_READ(host
->base
, HCTL
) | SDBP
);
619 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
620 while ((OMAP_HSMMC_READ(host
->base
, HCTL
) & SDBP
) != SDBP
621 && time_before(jiffies
, timeout
))
624 omap_hsmmc_disable_irq(host
);
626 /* Do not initialize card-specific things if the power is off */
627 if (host
->power_mode
== MMC_POWER_OFF
)
630 omap_hsmmc_set_bus_width(host
);
632 omap_hsmmc_set_clock(host
);
634 omap_hsmmc_set_bus_mode(host
);
637 host
->context_loss
= context_loss
;
639 dev_dbg(mmc_dev(host
->mmc
), "context is restored\n");
644 * Save the MMC host context (store the number of power state changes so far).
646 static void omap_hsmmc_context_save(struct omap_hsmmc_host
*host
)
648 struct omap_mmc_platform_data
*pdata
= host
->pdata
;
651 if (pdata
->get_context_loss_count
) {
652 context_loss
= pdata
->get_context_loss_count(host
->dev
);
653 if (context_loss
< 0)
655 host
->context_loss
= context_loss
;
661 static int omap_hsmmc_context_restore(struct omap_hsmmc_host
*host
)
666 static void omap_hsmmc_context_save(struct omap_hsmmc_host
*host
)
673 * Send init stream sequence to card
674 * before sending IDLE command
676 static void send_init_stream(struct omap_hsmmc_host
*host
)
679 unsigned long timeout
;
681 if (host
->protect_card
)
684 disable_irq(host
->irq
);
686 OMAP_HSMMC_WRITE(host
->base
, IE
, INT_EN_MASK
);
687 OMAP_HSMMC_WRITE(host
->base
, CON
,
688 OMAP_HSMMC_READ(host
->base
, CON
) | INIT_STREAM
);
689 OMAP_HSMMC_WRITE(host
->base
, CMD
, INIT_STREAM_CMD
);
691 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
692 while ((reg
!= CC
) && time_before(jiffies
, timeout
))
693 reg
= OMAP_HSMMC_READ(host
->base
, STAT
) & CC
;
695 OMAP_HSMMC_WRITE(host
->base
, CON
,
696 OMAP_HSMMC_READ(host
->base
, CON
) & ~INIT_STREAM
);
698 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
699 OMAP_HSMMC_READ(host
->base
, STAT
);
701 enable_irq(host
->irq
);
705 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host
*host
)
709 if (mmc_slot(host
).get_cover_state
)
710 r
= mmc_slot(host
).get_cover_state(host
->dev
, host
->slot_id
);
715 omap_hsmmc_show_cover_switch(struct device
*dev
, struct device_attribute
*attr
,
718 struct mmc_host
*mmc
= container_of(dev
, struct mmc_host
, class_dev
);
719 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
721 return sprintf(buf
, "%s\n",
722 omap_hsmmc_cover_is_closed(host
) ? "closed" : "open");
725 static DEVICE_ATTR(cover_switch
, S_IRUGO
, omap_hsmmc_show_cover_switch
, NULL
);
728 omap_hsmmc_show_slot_name(struct device
*dev
, struct device_attribute
*attr
,
731 struct mmc_host
*mmc
= container_of(dev
, struct mmc_host
, class_dev
);
732 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
734 return sprintf(buf
, "%s\n", mmc_slot(host
).name
);
737 static DEVICE_ATTR(slot_name
, S_IRUGO
, omap_hsmmc_show_slot_name
, NULL
);
740 * Configure the response type and send the cmd.
743 omap_hsmmc_start_command(struct omap_hsmmc_host
*host
, struct mmc_command
*cmd
,
744 struct mmc_data
*data
)
746 int cmdreg
= 0, resptype
= 0, cmdtype
= 0;
748 dev_dbg(mmc_dev(host
->mmc
), "%s: CMD%d, argument 0x%08x\n",
749 mmc_hostname(host
->mmc
), cmd
->opcode
, cmd
->arg
);
752 omap_hsmmc_enable_irq(host
, cmd
);
754 host
->response_busy
= 0;
755 if (cmd
->flags
& MMC_RSP_PRESENT
) {
756 if (cmd
->flags
& MMC_RSP_136
)
758 else if (cmd
->flags
& MMC_RSP_BUSY
) {
760 host
->response_busy
= 1;
766 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
767 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
768 * a val of 0x3, rest 0x0.
770 if (cmd
== host
->mrq
->stop
)
773 cmdreg
= (cmd
->opcode
<< 24) | (resptype
<< 16) | (cmdtype
<< 22);
776 cmdreg
|= DP_SELECT
| MSBS
| BCE
;
777 if (data
->flags
& MMC_DATA_READ
)
786 host
->req_in_progress
= 1;
788 OMAP_HSMMC_WRITE(host
->base
, ARG
, cmd
->arg
);
789 OMAP_HSMMC_WRITE(host
->base
, CMD
, cmdreg
);
793 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host
*host
, struct mmc_data
*data
)
795 if (data
->flags
& MMC_DATA_WRITE
)
796 return DMA_TO_DEVICE
;
798 return DMA_FROM_DEVICE
;
801 static struct dma_chan
*omap_hsmmc_get_dma_chan(struct omap_hsmmc_host
*host
,
802 struct mmc_data
*data
)
804 return data
->flags
& MMC_DATA_WRITE
? host
->tx_chan
: host
->rx_chan
;
807 static void omap_hsmmc_request_done(struct omap_hsmmc_host
*host
, struct mmc_request
*mrq
)
812 spin_lock_irqsave(&host
->irq_lock
, flags
);
813 host
->req_in_progress
= 0;
814 dma_ch
= host
->dma_ch
;
815 spin_unlock_irqrestore(&host
->irq_lock
, flags
);
817 omap_hsmmc_disable_irq(host
);
818 /* Do not complete the request if DMA is still in progress */
819 if (mrq
->data
&& host
->use_dma
&& dma_ch
!= -1)
822 mmc_request_done(host
->mmc
, mrq
);
826 * Notify the transfer complete to MMC core
829 omap_hsmmc_xfer_done(struct omap_hsmmc_host
*host
, struct mmc_data
*data
)
832 struct mmc_request
*mrq
= host
->mrq
;
834 /* TC before CC from CMD6 - don't know why, but it happens */
835 if (host
->cmd
&& host
->cmd
->opcode
== 6 &&
836 host
->response_busy
) {
837 host
->response_busy
= 0;
841 omap_hsmmc_request_done(host
, mrq
);
848 data
->bytes_xfered
+= data
->blocks
* (data
->blksz
);
850 data
->bytes_xfered
= 0;
853 omap_hsmmc_request_done(host
, data
->mrq
);
856 omap_hsmmc_start_command(host
, data
->stop
, NULL
);
860 * Notify the core about command completion
863 omap_hsmmc_cmd_done(struct omap_hsmmc_host
*host
, struct mmc_command
*cmd
)
867 if (cmd
->flags
& MMC_RSP_PRESENT
) {
868 if (cmd
->flags
& MMC_RSP_136
) {
869 /* response type 2 */
870 cmd
->resp
[3] = OMAP_HSMMC_READ(host
->base
, RSP10
);
871 cmd
->resp
[2] = OMAP_HSMMC_READ(host
->base
, RSP32
);
872 cmd
->resp
[1] = OMAP_HSMMC_READ(host
->base
, RSP54
);
873 cmd
->resp
[0] = OMAP_HSMMC_READ(host
->base
, RSP76
);
875 /* response types 1, 1b, 3, 4, 5, 6 */
876 cmd
->resp
[0] = OMAP_HSMMC_READ(host
->base
, RSP10
);
879 if ((host
->data
== NULL
&& !host
->response_busy
) || cmd
->error
)
880 omap_hsmmc_request_done(host
, cmd
->mrq
);
884 * DMA clean up for command errors
886 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host
*host
, int errno
)
891 host
->data
->error
= errno
;
893 spin_lock_irqsave(&host
->irq_lock
, flags
);
894 dma_ch
= host
->dma_ch
;
896 spin_unlock_irqrestore(&host
->irq_lock
, flags
);
898 if (host
->use_dma
&& dma_ch
!= -1) {
899 struct dma_chan
*chan
= omap_hsmmc_get_dma_chan(host
, host
->data
);
901 dmaengine_terminate_all(chan
);
902 dma_unmap_sg(chan
->device
->dev
,
903 host
->data
->sg
, host
->data
->sg_len
,
904 omap_hsmmc_get_dma_dir(host
, host
->data
));
906 host
->data
->host_cookie
= 0;
912 * Readable error output
914 #ifdef CONFIG_MMC_DEBUG
915 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host
*host
, u32 status
)
917 /* --- means reserved bit without definition at documentation */
918 static const char *omap_hsmmc_status_bits
[] = {
919 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
920 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
921 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
922 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
928 len
= sprintf(buf
, "MMC IRQ 0x%x :", status
);
931 for (i
= 0; i
< ARRAY_SIZE(omap_hsmmc_status_bits
); i
++)
932 if (status
& (1 << i
)) {
933 len
= sprintf(buf
, " %s", omap_hsmmc_status_bits
[i
]);
937 dev_dbg(mmc_dev(host
->mmc
), "%s\n", res
);
940 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host
*host
,
944 #endif /* CONFIG_MMC_DEBUG */
947 * MMC controller internal state machines reset
949 * Used to reset command or data internal state machines, using respectively
950 * SRC or SRD bit of SYSCTL register
951 * Can be called from interrupt context
953 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host
*host
,
957 unsigned long limit
= (loops_per_jiffy
*
958 msecs_to_jiffies(MMC_TIMEOUT_MS
));
960 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
961 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | bit
);
964 * OMAP4 ES2 and greater has an updated reset logic.
965 * Monitor a 0->1 transition first
967 if (mmc_slot(host
).features
& HSMMC_HAS_UPDATED_RESET
) {
968 while ((!(OMAP_HSMMC_READ(host
->base
, SYSCTL
) & bit
))
974 while ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & bit
) &&
978 if (OMAP_HSMMC_READ(host
->base
, SYSCTL
) & bit
)
979 dev_err(mmc_dev(host
->mmc
),
980 "Timeout waiting on controller reset in %s\n",
984 static void omap_hsmmc_do_irq(struct omap_hsmmc_host
*host
, int status
)
986 struct mmc_data
*data
;
987 int end_cmd
= 0, end_trans
= 0;
989 if (!host
->req_in_progress
) {
991 OMAP_HSMMC_WRITE(host
->base
, STAT
, status
);
992 /* Flush posted write */
993 status
= OMAP_HSMMC_READ(host
->base
, STAT
);
994 } while (status
& INT_EN_MASK
);
999 dev_dbg(mmc_dev(host
->mmc
), "IRQ Status is %x\n", status
);
1002 omap_hsmmc_dbg_report_irq(host
, status
);
1003 if ((status
& CMD_TIMEOUT
) ||
1004 (status
& CMD_CRC
)) {
1006 if (status
& CMD_TIMEOUT
) {
1007 omap_hsmmc_reset_controller_fsm(host
,
1009 host
->cmd
->error
= -ETIMEDOUT
;
1011 host
->cmd
->error
= -EILSEQ
;
1015 if (host
->data
|| host
->response_busy
) {
1017 omap_hsmmc_dma_cleanup(host
,
1019 host
->response_busy
= 0;
1020 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1023 if ((status
& DATA_TIMEOUT
) ||
1024 (status
& DATA_CRC
)) {
1025 if (host
->data
|| host
->response_busy
) {
1026 int err
= (status
& DATA_TIMEOUT
) ?
1027 -ETIMEDOUT
: -EILSEQ
;
1030 omap_hsmmc_dma_cleanup(host
, err
);
1032 host
->mrq
->cmd
->error
= err
;
1033 host
->response_busy
= 0;
1034 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1038 if (status
& CARD_ERR
) {
1039 dev_dbg(mmc_dev(host
->mmc
),
1040 "Ignoring card err CMD%d\n", host
->cmd
->opcode
);
1048 OMAP_HSMMC_WRITE(host
->base
, STAT
, status
);
1050 if (end_cmd
|| ((status
& CC
) && host
->cmd
))
1051 omap_hsmmc_cmd_done(host
, host
->cmd
);
1052 if ((end_trans
|| (status
& TC
)) && host
->mrq
)
1053 omap_hsmmc_xfer_done(host
, data
);
1057 * MMC controller IRQ handler
1059 static irqreturn_t
omap_hsmmc_irq(int irq
, void *dev_id
)
1061 struct omap_hsmmc_host
*host
= dev_id
;
1064 status
= OMAP_HSMMC_READ(host
->base
, STAT
);
1066 omap_hsmmc_do_irq(host
, status
);
1067 /* Flush posted write */
1068 status
= OMAP_HSMMC_READ(host
->base
, STAT
);
1069 } while (status
& INT_EN_MASK
);
1074 static void set_sd_bus_power(struct omap_hsmmc_host
*host
)
1078 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1079 OMAP_HSMMC_READ(host
->base
, HCTL
) | SDBP
);
1080 for (i
= 0; i
< loops_per_jiffy
; i
++) {
1081 if (OMAP_HSMMC_READ(host
->base
, HCTL
) & SDBP
)
1088 * Switch MMC interface voltage ... only relevant for MMC1.
1090 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1091 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1092 * Some chips, like eMMC ones, use internal transceivers.
1094 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host
*host
, int vdd
)
1099 /* Disable the clocks */
1100 pm_runtime_put_sync(host
->dev
);
1102 clk_disable(host
->dbclk
);
1104 /* Turn the power off */
1105 ret
= mmc_slot(host
).set_power(host
->dev
, host
->slot_id
, 0, 0);
1107 /* Turn the power ON with given VDD 1.8 or 3.0v */
1109 ret
= mmc_slot(host
).set_power(host
->dev
, host
->slot_id
, 1,
1111 pm_runtime_get_sync(host
->dev
);
1113 clk_enable(host
->dbclk
);
1118 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1119 OMAP_HSMMC_READ(host
->base
, HCTL
) & SDVSCLR
);
1120 reg_val
= OMAP_HSMMC_READ(host
->base
, HCTL
);
1123 * If a MMC dual voltage card is detected, the set_ios fn calls
1124 * this fn with VDD bit set for 1.8V. Upon card removal from the
1125 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1127 * Cope with a bit of slop in the range ... per data sheets:
1128 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1129 * but recommended values are 1.71V to 1.89V
1130 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1131 * but recommended values are 2.7V to 3.3V
1133 * Board setup code shouldn't permit anything very out-of-range.
1134 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1135 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1137 if ((1 << vdd
) <= MMC_VDD_23_24
)
1142 OMAP_HSMMC_WRITE(host
->base
, HCTL
, reg_val
);
1143 set_sd_bus_power(host
);
1147 dev_dbg(mmc_dev(host
->mmc
), "Unable to switch operating voltage\n");
1151 /* Protect the card while the cover is open */
1152 static void omap_hsmmc_protect_card(struct omap_hsmmc_host
*host
)
1154 if (!mmc_slot(host
).get_cover_state
)
1157 host
->reqs_blocked
= 0;
1158 if (mmc_slot(host
).get_cover_state(host
->dev
, host
->slot_id
)) {
1159 if (host
->protect_card
) {
1160 dev_info(host
->dev
, "%s: cover is closed, "
1161 "card is now accessible\n",
1162 mmc_hostname(host
->mmc
));
1163 host
->protect_card
= 0;
1166 if (!host
->protect_card
) {
1167 dev_info(host
->dev
, "%s: cover is open, "
1168 "card is now inaccessible\n",
1169 mmc_hostname(host
->mmc
));
1170 host
->protect_card
= 1;
1176 * irq handler to notify the core about card insertion/removal
1178 static irqreturn_t
omap_hsmmc_detect(int irq
, void *dev_id
)
1180 struct omap_hsmmc_host
*host
= dev_id
;
1181 struct omap_mmc_slot_data
*slot
= &mmc_slot(host
);
1184 if (host
->suspended
)
1187 sysfs_notify(&host
->mmc
->class_dev
.kobj
, NULL
, "cover_switch");
1189 if (slot
->card_detect
)
1190 carddetect
= slot
->card_detect(host
->dev
, host
->slot_id
);
1192 omap_hsmmc_protect_card(host
);
1193 carddetect
= -ENOSYS
;
1197 mmc_detect_change(host
->mmc
, (HZ
* 200) / 1000);
1199 mmc_detect_change(host
->mmc
, (HZ
* 50) / 1000);
1203 static void omap_hsmmc_dma_callback(void *param
)
1205 struct omap_hsmmc_host
*host
= param
;
1206 struct dma_chan
*chan
;
1207 struct mmc_data
*data
;
1208 int req_in_progress
;
1210 spin_lock_irq(&host
->irq_lock
);
1211 if (host
->dma_ch
< 0) {
1212 spin_unlock_irq(&host
->irq_lock
);
1216 data
= host
->mrq
->data
;
1217 chan
= omap_hsmmc_get_dma_chan(host
, data
);
1218 if (!data
->host_cookie
)
1219 dma_unmap_sg(chan
->device
->dev
,
1220 data
->sg
, data
->sg_len
,
1221 omap_hsmmc_get_dma_dir(host
, data
));
1223 req_in_progress
= host
->req_in_progress
;
1225 spin_unlock_irq(&host
->irq_lock
);
1227 /* If DMA has finished after TC, complete the request */
1228 if (!req_in_progress
) {
1229 struct mmc_request
*mrq
= host
->mrq
;
1232 mmc_request_done(host
->mmc
, mrq
);
1236 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host
*host
,
1237 struct mmc_data
*data
,
1238 struct omap_hsmmc_next
*next
,
1239 struct dma_chan
*chan
)
1243 if (!next
&& data
->host_cookie
&&
1244 data
->host_cookie
!= host
->next_data
.cookie
) {
1245 dev_warn(host
->dev
, "[%s] invalid cookie: data->host_cookie %d"
1246 " host->next_data.cookie %d\n",
1247 __func__
, data
->host_cookie
, host
->next_data
.cookie
);
1248 data
->host_cookie
= 0;
1251 /* Check if next job is already prepared */
1253 (!next
&& data
->host_cookie
!= host
->next_data
.cookie
)) {
1254 dma_len
= dma_map_sg(chan
->device
->dev
, data
->sg
, data
->sg_len
,
1255 omap_hsmmc_get_dma_dir(host
, data
));
1258 dma_len
= host
->next_data
.dma_len
;
1259 host
->next_data
.dma_len
= 0;
1267 next
->dma_len
= dma_len
;
1268 data
->host_cookie
= ++next
->cookie
< 0 ? 1 : next
->cookie
;
1270 host
->dma_len
= dma_len
;
1276 * Routine to configure and start DMA for the MMC card
1278 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host
*host
,
1279 struct mmc_request
*req
)
1281 struct dma_slave_config cfg
;
1282 struct dma_async_tx_descriptor
*tx
;
1284 struct mmc_data
*data
= req
->data
;
1285 struct dma_chan
*chan
;
1287 /* Sanity check: all the SG entries must be aligned by block size. */
1288 for (i
= 0; i
< data
->sg_len
; i
++) {
1289 struct scatterlist
*sgl
;
1292 if (sgl
->length
% data
->blksz
)
1295 if ((data
->blksz
% 4) != 0)
1296 /* REVISIT: The MMC buffer increments only when MSB is written.
1297 * Return error for blksz which is non multiple of four.
1301 BUG_ON(host
->dma_ch
!= -1);
1303 chan
= omap_hsmmc_get_dma_chan(host
, data
);
1305 cfg
.src_addr
= host
->mapbase
+ OMAP_HSMMC_DATA
;
1306 cfg
.dst_addr
= host
->mapbase
+ OMAP_HSMMC_DATA
;
1307 cfg
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1308 cfg
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1309 cfg
.src_maxburst
= data
->blksz
/ 4;
1310 cfg
.dst_maxburst
= data
->blksz
/ 4;
1312 ret
= dmaengine_slave_config(chan
, &cfg
);
1316 ret
= omap_hsmmc_pre_dma_transfer(host
, data
, NULL
, chan
);
1320 tx
= dmaengine_prep_slave_sg(chan
, data
->sg
, data
->sg_len
,
1321 data
->flags
& MMC_DATA_WRITE
? DMA_MEM_TO_DEV
: DMA_DEV_TO_MEM
,
1322 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1324 dev_err(mmc_dev(host
->mmc
), "prep_slave_sg() failed\n");
1325 /* FIXME: cleanup */
1329 tx
->callback
= omap_hsmmc_dma_callback
;
1330 tx
->callback_param
= host
;
1333 dmaengine_submit(tx
);
1337 dma_async_issue_pending(chan
);
1342 static void set_data_timeout(struct omap_hsmmc_host
*host
,
1343 unsigned int timeout_ns
,
1344 unsigned int timeout_clks
)
1346 unsigned int timeout
, cycle_ns
;
1347 uint32_t reg
, clkd
, dto
= 0;
1349 reg
= OMAP_HSMMC_READ(host
->base
, SYSCTL
);
1350 clkd
= (reg
& CLKD_MASK
) >> CLKD_SHIFT
;
1354 cycle_ns
= 1000000000 / (clk_get_rate(host
->fclk
) / clkd
);
1355 timeout
= timeout_ns
/ cycle_ns
;
1356 timeout
+= timeout_clks
;
1358 while ((timeout
& 0x80000000) == 0) {
1375 reg
|= dto
<< DTO_SHIFT
;
1376 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
, reg
);
1380 * Configure block length for MMC/SD cards and initiate the transfer.
1383 omap_hsmmc_prepare_data(struct omap_hsmmc_host
*host
, struct mmc_request
*req
)
1386 host
->data
= req
->data
;
1388 if (req
->data
== NULL
) {
1389 OMAP_HSMMC_WRITE(host
->base
, BLK
, 0);
1391 * Set an arbitrary 100ms data timeout for commands with
1394 if (req
->cmd
->flags
& MMC_RSP_BUSY
)
1395 set_data_timeout(host
, 100000000U, 0);
1399 OMAP_HSMMC_WRITE(host
->base
, BLK
, (req
->data
->blksz
)
1400 | (req
->data
->blocks
<< 16));
1401 set_data_timeout(host
, req
->data
->timeout_ns
, req
->data
->timeout_clks
);
1403 if (host
->use_dma
) {
1404 ret
= omap_hsmmc_start_dma_transfer(host
, req
);
1406 dev_dbg(mmc_dev(host
->mmc
), "MMC start dma failure\n");
1413 static void omap_hsmmc_post_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
1416 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1417 struct mmc_data
*data
= mrq
->data
;
1419 if (host
->use_dma
&& data
->host_cookie
) {
1420 struct dma_chan
*c
= omap_hsmmc_get_dma_chan(host
, data
);
1422 dma_unmap_sg(c
->device
->dev
, data
->sg
, data
->sg_len
,
1423 omap_hsmmc_get_dma_dir(host
, data
));
1424 data
->host_cookie
= 0;
1428 static void omap_hsmmc_pre_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
1431 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1433 if (mrq
->data
->host_cookie
) {
1434 mrq
->data
->host_cookie
= 0;
1438 if (host
->use_dma
) {
1439 struct dma_chan
*c
= omap_hsmmc_get_dma_chan(host
, mrq
->data
);
1441 if (omap_hsmmc_pre_dma_transfer(host
, mrq
->data
,
1442 &host
->next_data
, c
))
1443 mrq
->data
->host_cookie
= 0;
1448 * Request function. for read/write operation
1450 static void omap_hsmmc_request(struct mmc_host
*mmc
, struct mmc_request
*req
)
1452 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1455 BUG_ON(host
->req_in_progress
);
1456 BUG_ON(host
->dma_ch
!= -1);
1457 if (host
->protect_card
) {
1458 if (host
->reqs_blocked
< 3) {
1460 * Ensure the controller is left in a consistent
1461 * state by resetting the command and data state
1464 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1465 omap_hsmmc_reset_controller_fsm(host
, SRC
);
1466 host
->reqs_blocked
+= 1;
1468 req
->cmd
->error
= -EBADF
;
1470 req
->data
->error
= -EBADF
;
1471 req
->cmd
->retries
= 0;
1472 mmc_request_done(mmc
, req
);
1474 } else if (host
->reqs_blocked
)
1475 host
->reqs_blocked
= 0;
1476 WARN_ON(host
->mrq
!= NULL
);
1478 err
= omap_hsmmc_prepare_data(host
, req
);
1480 req
->cmd
->error
= err
;
1482 req
->data
->error
= err
;
1484 mmc_request_done(mmc
, req
);
1488 omap_hsmmc_start_command(host
, req
->cmd
, req
->data
);
1491 /* Routine to configure clock values. Exposed API to core */
1492 static void omap_hsmmc_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1494 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1495 int do_send_init_stream
= 0;
1497 pm_runtime_get_sync(host
->dev
);
1499 if (ios
->power_mode
!= host
->power_mode
) {
1500 switch (ios
->power_mode
) {
1502 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
,
1507 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
,
1509 host
->vdd
= ios
->vdd
;
1512 do_send_init_stream
= 1;
1515 host
->power_mode
= ios
->power_mode
;
1518 /* FIXME: set registers based only on changes to ios */
1520 omap_hsmmc_set_bus_width(host
);
1522 if (host
->pdata
->controller_flags
& OMAP_HSMMC_SUPPORTS_DUAL_VOLT
) {
1523 /* Only MMC1 can interface at 3V without some flavor
1524 * of external transceiver; but they all handle 1.8V.
1526 if ((OMAP_HSMMC_READ(host
->base
, HCTL
) & SDVSDET
) &&
1527 (ios
->vdd
== DUAL_VOLT_OCR_BIT
) &&
1529 * With pbias cell programming missing, this
1530 * can't be allowed when booting with device
1533 !host
->dev
->of_node
) {
1535 * The mmc_select_voltage fn of the core does
1536 * not seem to set the power_mode to
1537 * MMC_POWER_UP upon recalculating the voltage.
1540 if (omap_hsmmc_switch_opcond(host
, ios
->vdd
) != 0)
1541 dev_dbg(mmc_dev(host
->mmc
),
1542 "Switch operation failed\n");
1546 omap_hsmmc_set_clock(host
);
1548 if (do_send_init_stream
)
1549 send_init_stream(host
);
1551 omap_hsmmc_set_bus_mode(host
);
1553 pm_runtime_put_autosuspend(host
->dev
);
1556 static int omap_hsmmc_get_cd(struct mmc_host
*mmc
)
1558 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1560 if (!mmc_slot(host
).card_detect
)
1562 return mmc_slot(host
).card_detect(host
->dev
, host
->slot_id
);
1565 static int omap_hsmmc_get_ro(struct mmc_host
*mmc
)
1567 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1569 if (!mmc_slot(host
).get_ro
)
1571 return mmc_slot(host
).get_ro(host
->dev
, 0);
1574 static void omap_hsmmc_init_card(struct mmc_host
*mmc
, struct mmc_card
*card
)
1576 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1578 if (mmc_slot(host
).init_card
)
1579 mmc_slot(host
).init_card(card
);
1582 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host
*host
)
1584 u32 hctl
, capa
, value
;
1586 /* Only MMC1 supports 3.0V */
1587 if (host
->pdata
->controller_flags
& OMAP_HSMMC_SUPPORTS_DUAL_VOLT
) {
1595 value
= OMAP_HSMMC_READ(host
->base
, HCTL
) & ~SDVS_MASK
;
1596 OMAP_HSMMC_WRITE(host
->base
, HCTL
, value
| hctl
);
1598 value
= OMAP_HSMMC_READ(host
->base
, CAPA
);
1599 OMAP_HSMMC_WRITE(host
->base
, CAPA
, value
| capa
);
1601 /* Set the controller to AUTO IDLE mode */
1602 value
= OMAP_HSMMC_READ(host
->base
, SYSCONFIG
);
1603 OMAP_HSMMC_WRITE(host
->base
, SYSCONFIG
, value
| AUTOIDLE
);
1605 /* Set SD bus power bit */
1606 set_sd_bus_power(host
);
1609 static int omap_hsmmc_enable_fclk(struct mmc_host
*mmc
)
1611 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1613 pm_runtime_get_sync(host
->dev
);
1618 static int omap_hsmmc_disable_fclk(struct mmc_host
*mmc
)
1620 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1622 pm_runtime_mark_last_busy(host
->dev
);
1623 pm_runtime_put_autosuspend(host
->dev
);
1628 static const struct mmc_host_ops omap_hsmmc_ops
= {
1629 .enable
= omap_hsmmc_enable_fclk
,
1630 .disable
= omap_hsmmc_disable_fclk
,
1631 .post_req
= omap_hsmmc_post_req
,
1632 .pre_req
= omap_hsmmc_pre_req
,
1633 .request
= omap_hsmmc_request
,
1634 .set_ios
= omap_hsmmc_set_ios
,
1635 .get_cd
= omap_hsmmc_get_cd
,
1636 .get_ro
= omap_hsmmc_get_ro
,
1637 .init_card
= omap_hsmmc_init_card
,
1638 /* NYET -- enable_sdio_irq */
1641 #ifdef CONFIG_DEBUG_FS
1643 static int omap_hsmmc_regs_show(struct seq_file
*s
, void *data
)
1645 struct mmc_host
*mmc
= s
->private;
1646 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1647 int context_loss
= 0;
1649 if (host
->pdata
->get_context_loss_count
)
1650 context_loss
= host
->pdata
->get_context_loss_count(host
->dev
);
1652 seq_printf(s
, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1653 mmc
->index
, host
->context_loss
, context_loss
);
1655 if (host
->suspended
) {
1656 seq_printf(s
, "host suspended, can't read registers\n");
1660 pm_runtime_get_sync(host
->dev
);
1662 seq_printf(s
, "SYSCONFIG:\t0x%08x\n",
1663 OMAP_HSMMC_READ(host
->base
, SYSCONFIG
));
1664 seq_printf(s
, "CON:\t\t0x%08x\n",
1665 OMAP_HSMMC_READ(host
->base
, CON
));
1666 seq_printf(s
, "HCTL:\t\t0x%08x\n",
1667 OMAP_HSMMC_READ(host
->base
, HCTL
));
1668 seq_printf(s
, "SYSCTL:\t\t0x%08x\n",
1669 OMAP_HSMMC_READ(host
->base
, SYSCTL
));
1670 seq_printf(s
, "IE:\t\t0x%08x\n",
1671 OMAP_HSMMC_READ(host
->base
, IE
));
1672 seq_printf(s
, "ISE:\t\t0x%08x\n",
1673 OMAP_HSMMC_READ(host
->base
, ISE
));
1674 seq_printf(s
, "CAPA:\t\t0x%08x\n",
1675 OMAP_HSMMC_READ(host
->base
, CAPA
));
1677 pm_runtime_mark_last_busy(host
->dev
);
1678 pm_runtime_put_autosuspend(host
->dev
);
1683 static int omap_hsmmc_regs_open(struct inode
*inode
, struct file
*file
)
1685 return single_open(file
, omap_hsmmc_regs_show
, inode
->i_private
);
1688 static const struct file_operations mmc_regs_fops
= {
1689 .open
= omap_hsmmc_regs_open
,
1691 .llseek
= seq_lseek
,
1692 .release
= single_release
,
1695 static void omap_hsmmc_debugfs(struct mmc_host
*mmc
)
1697 if (mmc
->debugfs_root
)
1698 debugfs_create_file("regs", S_IRUSR
, mmc
->debugfs_root
,
1699 mmc
, &mmc_regs_fops
);
1704 static void omap_hsmmc_debugfs(struct mmc_host
*mmc
)
1711 static u16 omap4_reg_offset
= 0x100;
1713 static const struct of_device_id omap_mmc_of_match
[] = {
1715 .compatible
= "ti,omap2-hsmmc",
1718 .compatible
= "ti,omap3-hsmmc",
1721 .compatible
= "ti,omap4-hsmmc",
1722 .data
= &omap4_reg_offset
,
1726 MODULE_DEVICE_TABLE(of
, omap_mmc_of_match
);
1728 static struct omap_mmc_platform_data
*of_get_hsmmc_pdata(struct device
*dev
)
1730 struct omap_mmc_platform_data
*pdata
;
1731 struct device_node
*np
= dev
->of_node
;
1734 pdata
= devm_kzalloc(dev
, sizeof(*pdata
), GFP_KERNEL
);
1736 return NULL
; /* out of memory */
1738 if (of_find_property(np
, "ti,dual-volt", NULL
))
1739 pdata
->controller_flags
|= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
;
1741 /* This driver only supports 1 slot */
1742 pdata
->nr_slots
= 1;
1743 pdata
->slots
[0].switch_pin
= of_get_named_gpio(np
, "cd-gpios", 0);
1744 pdata
->slots
[0].gpio_wp
= of_get_named_gpio(np
, "wp-gpios", 0);
1746 if (of_find_property(np
, "ti,non-removable", NULL
)) {
1747 pdata
->slots
[0].nonremovable
= true;
1748 pdata
->slots
[0].no_regulator_off_init
= true;
1750 of_property_read_u32(np
, "bus-width", &bus_width
);
1752 pdata
->slots
[0].caps
|= MMC_CAP_4_BIT_DATA
;
1753 else if (bus_width
== 8)
1754 pdata
->slots
[0].caps
|= MMC_CAP_8_BIT_DATA
;
1756 if (of_find_property(np
, "ti,needs-special-reset", NULL
))
1757 pdata
->slots
[0].features
|= HSMMC_HAS_UPDATED_RESET
;
1762 static inline struct omap_mmc_platform_data
1763 *of_get_hsmmc_pdata(struct device
*dev
)
1769 extern bool omap_dma_filter_fn(struct dma_chan
*chan
, void *param
);
1771 static int __devinit
omap_hsmmc_probe(struct platform_device
*pdev
)
1773 struct omap_mmc_platform_data
*pdata
= pdev
->dev
.platform_data
;
1774 struct mmc_host
*mmc
;
1775 struct omap_hsmmc_host
*host
= NULL
;
1776 struct resource
*res
;
1778 const struct of_device_id
*match
;
1779 dma_cap_mask_t mask
;
1780 unsigned tx_req
, rx_req
;
1782 match
= of_match_device(of_match_ptr(omap_mmc_of_match
), &pdev
->dev
);
1784 pdata
= of_get_hsmmc_pdata(&pdev
->dev
);
1786 u16
*offsetp
= match
->data
;
1787 pdata
->reg_offset
= *offsetp
;
1791 if (pdata
== NULL
) {
1792 dev_err(&pdev
->dev
, "Platform Data is missing\n");
1796 if (pdata
->nr_slots
== 0) {
1797 dev_err(&pdev
->dev
, "No Slots\n");
1801 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1802 irq
= platform_get_irq(pdev
, 0);
1803 if (res
== NULL
|| irq
< 0)
1806 res
= request_mem_region(res
->start
, resource_size(res
), pdev
->name
);
1810 ret
= omap_hsmmc_gpio_init(pdata
);
1814 mmc
= mmc_alloc_host(sizeof(struct omap_hsmmc_host
), &pdev
->dev
);
1820 host
= mmc_priv(mmc
);
1822 host
->pdata
= pdata
;
1823 host
->dev
= &pdev
->dev
;
1828 host
->mapbase
= res
->start
+ pdata
->reg_offset
;
1829 host
->base
= ioremap(host
->mapbase
, SZ_4K
);
1830 host
->power_mode
= MMC_POWER_OFF
;
1831 host
->next_data
.cookie
= 1;
1833 platform_set_drvdata(pdev
, host
);
1835 mmc
->ops
= &omap_hsmmc_ops
;
1838 * If regulator_disable can only put vcc_aux to sleep then there is
1841 if (mmc_slot(host
).vcc_aux_disable_is_sleep
)
1842 mmc_slot(host
).no_off
= 1;
1844 mmc
->f_min
= OMAP_MMC_MIN_CLOCK
;
1846 if (pdata
->max_freq
> 0)
1847 mmc
->f_max
= pdata
->max_freq
;
1849 mmc
->f_max
= OMAP_MMC_MAX_CLOCK
;
1851 spin_lock_init(&host
->irq_lock
);
1853 host
->fclk
= clk_get(&pdev
->dev
, "fck");
1854 if (IS_ERR(host
->fclk
)) {
1855 ret
= PTR_ERR(host
->fclk
);
1860 if (host
->pdata
->controller_flags
& OMAP_HSMMC_BROKEN_MULTIBLOCK_READ
) {
1861 dev_info(&pdev
->dev
, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1862 mmc
->caps2
|= MMC_CAP2_NO_MULTI_READ
;
1865 pm_runtime_enable(host
->dev
);
1866 pm_runtime_get_sync(host
->dev
);
1867 pm_runtime_set_autosuspend_delay(host
->dev
, MMC_AUTOSUSPEND_DELAY
);
1868 pm_runtime_use_autosuspend(host
->dev
);
1870 omap_hsmmc_context_save(host
);
1872 host
->dbclk
= clk_get(&pdev
->dev
, "mmchsdb_fck");
1874 * MMC can still work without debounce clock.
1876 if (IS_ERR(host
->dbclk
)) {
1877 dev_warn(mmc_dev(host
->mmc
), "Failed to get debounce clk\n");
1879 } else if (clk_enable(host
->dbclk
) != 0) {
1880 dev_warn(mmc_dev(host
->mmc
), "Failed to enable debounce clk\n");
1881 clk_put(host
->dbclk
);
1885 /* Since we do only SG emulation, we can have as many segs
1887 mmc
->max_segs
= 1024;
1889 mmc
->max_blk_size
= 512; /* Block Length at max can be 1024 */
1890 mmc
->max_blk_count
= 0xFFFF; /* No. of Blocks is 16 bits */
1891 mmc
->max_req_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
1892 mmc
->max_seg_size
= mmc
->max_req_size
;
1894 mmc
->caps
|= MMC_CAP_MMC_HIGHSPEED
| MMC_CAP_SD_HIGHSPEED
|
1895 MMC_CAP_WAIT_WHILE_BUSY
| MMC_CAP_ERASE
;
1897 mmc
->caps
|= mmc_slot(host
).caps
;
1898 if (mmc
->caps
& MMC_CAP_8_BIT_DATA
)
1899 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
1901 if (mmc_slot(host
).nonremovable
)
1902 mmc
->caps
|= MMC_CAP_NONREMOVABLE
;
1904 mmc
->pm_caps
= mmc_slot(host
).pm_caps
;
1906 omap_hsmmc_conf_bus_power(host
);
1908 res
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
, "tx");
1910 dev_err(mmc_dev(host
->mmc
), "cannot get DMA TX channel\n");
1913 tx_req
= res
->start
;
1915 res
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
, "rx");
1917 dev_err(mmc_dev(host
->mmc
), "cannot get DMA RX channel\n");
1920 rx_req
= res
->start
;
1923 dma_cap_set(DMA_SLAVE
, mask
);
1925 host
->rx_chan
= dma_request_channel(mask
, omap_dma_filter_fn
, &rx_req
);
1926 if (!host
->rx_chan
) {
1927 dev_err(mmc_dev(host
->mmc
), "unable to obtain RX DMA engine channel %u\n", rx_req
);
1931 host
->tx_chan
= dma_request_channel(mask
, omap_dma_filter_fn
, &tx_req
);
1932 if (!host
->tx_chan
) {
1933 dev_err(mmc_dev(host
->mmc
), "unable to obtain TX DMA engine channel %u\n", tx_req
);
1937 /* Request IRQ for MMC operations */
1938 ret
= request_irq(host
->irq
, omap_hsmmc_irq
, 0,
1939 mmc_hostname(mmc
), host
);
1941 dev_dbg(mmc_dev(host
->mmc
), "Unable to grab HSMMC IRQ\n");
1945 if (pdata
->init
!= NULL
) {
1946 if (pdata
->init(&pdev
->dev
) != 0) {
1947 dev_dbg(mmc_dev(host
->mmc
),
1948 "Unable to configure MMC IRQs\n");
1949 goto err_irq_cd_init
;
1953 if (omap_hsmmc_have_reg() && !mmc_slot(host
).set_power
) {
1954 ret
= omap_hsmmc_reg_get(host
);
1960 mmc
->ocr_avail
= mmc_slot(host
).ocr_mask
;
1962 /* Request IRQ for card detect */
1963 if ((mmc_slot(host
).card_detect_irq
)) {
1964 ret
= request_threaded_irq(mmc_slot(host
).card_detect_irq
,
1967 IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
| IRQF_ONESHOT
,
1968 mmc_hostname(mmc
), host
);
1970 dev_dbg(mmc_dev(host
->mmc
),
1971 "Unable to grab MMC CD IRQ\n");
1974 pdata
->suspend
= omap_hsmmc_suspend_cdirq
;
1975 pdata
->resume
= omap_hsmmc_resume_cdirq
;
1978 omap_hsmmc_disable_irq(host
);
1980 omap_hsmmc_protect_card(host
);
1984 if (mmc_slot(host
).name
!= NULL
) {
1985 ret
= device_create_file(&mmc
->class_dev
, &dev_attr_slot_name
);
1989 if (mmc_slot(host
).card_detect_irq
&& mmc_slot(host
).get_cover_state
) {
1990 ret
= device_create_file(&mmc
->class_dev
,
1991 &dev_attr_cover_switch
);
1996 omap_hsmmc_debugfs(mmc
);
1997 pm_runtime_mark_last_busy(host
->dev
);
1998 pm_runtime_put_autosuspend(host
->dev
);
2003 mmc_remove_host(mmc
);
2004 free_irq(mmc_slot(host
).card_detect_irq
, host
);
2007 omap_hsmmc_reg_put(host
);
2009 if (host
->pdata
->cleanup
)
2010 host
->pdata
->cleanup(&pdev
->dev
);
2012 free_irq(host
->irq
, host
);
2015 dma_release_channel(host
->tx_chan
);
2017 dma_release_channel(host
->rx_chan
);
2018 pm_runtime_put_sync(host
->dev
);
2019 pm_runtime_disable(host
->dev
);
2020 clk_put(host
->fclk
);
2022 clk_disable(host
->dbclk
);
2023 clk_put(host
->dbclk
);
2026 iounmap(host
->base
);
2027 platform_set_drvdata(pdev
, NULL
);
2030 omap_hsmmc_gpio_free(pdata
);
2032 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2034 release_mem_region(res
->start
, resource_size(res
));
2038 static int __devexit
omap_hsmmc_remove(struct platform_device
*pdev
)
2040 struct omap_hsmmc_host
*host
= platform_get_drvdata(pdev
);
2041 struct resource
*res
;
2043 pm_runtime_get_sync(host
->dev
);
2044 mmc_remove_host(host
->mmc
);
2046 omap_hsmmc_reg_put(host
);
2047 if (host
->pdata
->cleanup
)
2048 host
->pdata
->cleanup(&pdev
->dev
);
2049 free_irq(host
->irq
, host
);
2050 if (mmc_slot(host
).card_detect_irq
)
2051 free_irq(mmc_slot(host
).card_detect_irq
, host
);
2054 dma_release_channel(host
->tx_chan
);
2056 dma_release_channel(host
->rx_chan
);
2058 pm_runtime_put_sync(host
->dev
);
2059 pm_runtime_disable(host
->dev
);
2060 clk_put(host
->fclk
);
2062 clk_disable(host
->dbclk
);
2063 clk_put(host
->dbclk
);
2066 mmc_free_host(host
->mmc
);
2067 iounmap(host
->base
);
2068 omap_hsmmc_gpio_free(pdev
->dev
.platform_data
);
2070 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2072 release_mem_region(res
->start
, resource_size(res
));
2073 platform_set_drvdata(pdev
, NULL
);
2079 static int omap_hsmmc_suspend(struct device
*dev
)
2082 struct omap_hsmmc_host
*host
= dev_get_drvdata(dev
);
2087 if (host
&& host
->suspended
)
2090 pm_runtime_get_sync(host
->dev
);
2091 host
->suspended
= 1;
2092 if (host
->pdata
->suspend
) {
2093 ret
= host
->pdata
->suspend(dev
, host
->slot_id
);
2095 dev_dbg(dev
, "Unable to handle MMC board"
2096 " level suspend\n");
2097 host
->suspended
= 0;
2101 ret
= mmc_suspend_host(host
->mmc
);
2104 host
->suspended
= 0;
2105 if (host
->pdata
->resume
) {
2106 ret
= host
->pdata
->resume(dev
, host
->slot_id
);
2108 dev_dbg(dev
, "Unmask interrupt failed\n");
2113 if (!(host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
)) {
2114 omap_hsmmc_disable_irq(host
);
2115 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
2116 OMAP_HSMMC_READ(host
->base
, HCTL
) & ~SDBP
);
2120 clk_disable(host
->dbclk
);
2122 pm_runtime_put_sync(host
->dev
);
2126 /* Routine to resume the MMC device */
2127 static int omap_hsmmc_resume(struct device
*dev
)
2130 struct omap_hsmmc_host
*host
= dev_get_drvdata(dev
);
2135 if (host
&& !host
->suspended
)
2138 pm_runtime_get_sync(host
->dev
);
2141 clk_enable(host
->dbclk
);
2143 if (!(host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
))
2144 omap_hsmmc_conf_bus_power(host
);
2146 if (host
->pdata
->resume
) {
2147 ret
= host
->pdata
->resume(dev
, host
->slot_id
);
2149 dev_dbg(dev
, "Unmask interrupt failed\n");
2152 omap_hsmmc_protect_card(host
);
2154 /* Notify the core to resume the host */
2155 ret
= mmc_resume_host(host
->mmc
);
2157 host
->suspended
= 0;
2159 pm_runtime_mark_last_busy(host
->dev
);
2160 pm_runtime_put_autosuspend(host
->dev
);
2167 #define omap_hsmmc_suspend NULL
2168 #define omap_hsmmc_resume NULL
2171 static int omap_hsmmc_runtime_suspend(struct device
*dev
)
2173 struct omap_hsmmc_host
*host
;
2175 host
= platform_get_drvdata(to_platform_device(dev
));
2176 omap_hsmmc_context_save(host
);
2177 dev_dbg(dev
, "disabled\n");
2182 static int omap_hsmmc_runtime_resume(struct device
*dev
)
2184 struct omap_hsmmc_host
*host
;
2186 host
= platform_get_drvdata(to_platform_device(dev
));
2187 omap_hsmmc_context_restore(host
);
2188 dev_dbg(dev
, "enabled\n");
2193 static struct dev_pm_ops omap_hsmmc_dev_pm_ops
= {
2194 .suspend
= omap_hsmmc_suspend
,
2195 .resume
= omap_hsmmc_resume
,
2196 .runtime_suspend
= omap_hsmmc_runtime_suspend
,
2197 .runtime_resume
= omap_hsmmc_runtime_resume
,
2200 static struct platform_driver omap_hsmmc_driver
= {
2201 .probe
= omap_hsmmc_probe
,
2202 .remove
= __devexit_p(omap_hsmmc_remove
),
2204 .name
= DRIVER_NAME
,
2205 .owner
= THIS_MODULE
,
2206 .pm
= &omap_hsmmc_dev_pm_ops
,
2207 .of_match_table
= of_match_ptr(omap_mmc_of_match
),
2211 module_platform_driver(omap_hsmmc_driver
);
2212 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2213 MODULE_LICENSE("GPL");
2214 MODULE_ALIAS("platform:" DRIVER_NAME
);
2215 MODULE_AUTHOR("Texas Instruments Inc");