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[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / mmc / host / dw_mmc.h
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #ifndef _DW_MMC_H_
15 #define _DW_MMC_H_
16
17 #include <linux/scatterlist.h>
18 #include <linux/mmc/core.h>
19 #include <linux/dmaengine.h>
20 #include <linux/reset.h>
21 #include <linux/interrupt.h>
22 #include <linux/pm_qos.h>
23
24 enum dw_mci_state {
25 STATE_IDLE = 0,
26 STATE_SENDING_CMD,
27 STATE_SENDING_DATA,
28 STATE_DATA_BUSY,
29 STATE_SENDING_STOP,
30 STATE_DATA_ERROR,
31 STATE_SENDING_CMD11,
32 STATE_WAITING_CMD11_DONE,
33 };
34
35 enum {
36 EVENT_CMD_COMPLETE = 0,
37 EVENT_XFER_COMPLETE,
38 EVENT_DATA_COMPLETE,
39 EVENT_DATA_ERROR,
40 };
41
42 enum dw_mci_cookie {
43 COOKIE_UNMAPPED,
44 COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */
45 COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */
46 };
47
48 struct mmc_data;
49
50 enum {
51 TRANS_MODE_PIO = 0,
52 TRANS_MODE_IDMAC,
53 TRANS_MODE_EDMAC
54 };
55
56 struct dw_mci_dma_slave {
57 struct dma_chan *ch;
58 enum dma_transfer_direction direction;
59 };
60
61 /**
62 * struct dw_mci - MMC controller state shared between all slots
63 * @lock: Spinlock protecting the queue and associated data.
64 * @irq_lock: Spinlock protecting the INTMASK setting.
65 * @regs: Pointer to MMIO registers.
66 * @fifo_reg: Pointer to MMIO registers for data FIFO
67 * @sg: Scatterlist entry currently being processed by PIO code, if any.
68 * @sg_miter: PIO mapping scatterlist iterator.
69 * @cur_slot: The slot which is currently using the controller.
70 * @mrq: The request currently being processed on @cur_slot,
71 * or NULL if the controller is idle.
72 * @cmd: The command currently being sent to the card, or NULL.
73 * @data: The data currently being transferred, or NULL if no data
74 * transfer is in progress.
75 * @stop_abort: The command currently prepared for stoping transfer.
76 * @prev_blksz: The former transfer blksz record.
77 * @timing: Record of current ios timing.
78 * @use_dma: Whether DMA channel is initialized or not.
79 * @using_dma: Whether DMA is in use for the current transfer.
80 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
81 * @sg_dma: Bus address of DMA buffer.
82 * @sg_cpu: Virtual address of DMA buffer.
83 * @dma_ops: Pointer to platform-specific DMA callbacks.
84 * @cmd_status: Snapshot of SR taken upon completion of the current
85 * @ring_size: Buffer size for idma descriptors.
86 * command. Only valid when EVENT_CMD_COMPLETE is pending.
87 * @dms: structure of slave-dma private data.
88 * @phy_regs: physical address of controller's register map
89 * @data_status: Snapshot of SR taken upon completion of the current
90 * data transfer. Only valid when EVENT_DATA_COMPLETE or
91 * EVENT_DATA_ERROR is pending.
92 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
93 * to be sent.
94 * @dir_status: Direction of current transfer.
95 * @tasklet: Tasklet running the request state machine.
96 * @pending_events: Bitmask of events flagged by the interrupt handler
97 * to be processed by the tasklet.
98 * @completed_events: Bitmask of events which the state machine has
99 * processed.
100 * @state: Tasklet state.
101 * @queue: List of slots waiting for access to the controller.
102 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
103 * rate and timeout calculations.
104 * @current_speed: Configured rate of the controller.
105 * @num_slots: Number of slots available.
106 * @fifoth_val: The value of FIFOTH register.
107 * @verid: Denote Version ID.
108 * @dev: Device associated with the MMC controller.
109 * @pdata: Platform data associated with the MMC controller.
110 * @drv_data: Driver specific data for identified variant of the controller
111 * @priv: Implementation defined private data.
112 * @biu_clk: Pointer to bus interface unit clock instance.
113 * @ciu_clk: Pointer to card interface unit clock instance.
114 * @slot: Slots sharing this MMC controller.
115 * @fifo_depth: depth of FIFO.
116 * @data_addr_override: override fifo reg offset with this value.
117 * @wm_aligned: force fifo watermark equal with data length in PIO mode.
118 * Set as true if alignment is needed.
119 * @data_shift: log2 of FIFO item size.
120 * @part_buf_start: Start index in part_buf.
121 * @part_buf_count: Bytes of partial data in part_buf.
122 * @part_buf: Simple buffer for partial fifo reads/writes.
123 * @push_data: Pointer to FIFO push function.
124 * @pull_data: Pointer to FIFO pull function.
125 * @vqmmc_enabled: Status of vqmmc, should be true or false.
126 * @irq_flags: The flags to be passed to request_irq.
127 * @irq: The irq value to be passed to request_irq.
128 * @sdio_id0: Number of slot0 in the SDIO interrupt registers.
129 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
130 * @cto_timer: Timer for broken command transfer over scheme.
131 * @dto_timer: Timer for broken data transfer over scheme.
132 *
133 * Locking
134 * =======
135 *
136 * @lock is a softirq-safe spinlock protecting @queue as well as
137 * at the same time while holding @lock.
138 *
139 * @irq_lock is an irq-safe spinlock protecting the INTMASK register
140 * to allow the interrupt handler to modify it directly. Held for only long
141 * enough to read-modify-write INTMASK and no other locks are grabbed when
142 * holding this one.
143 *
144 * The @mrq field of struct dw_mci_slot is also protected by @lock,
145 * and must always be written at the same time as the slot is added to
146 * @queue.
147 *
148 * @pending_events and @completed_events are accessed using atomic bit
149 * operations, so they don't need any locking.
150 *
151 * None of the fields touched by the interrupt handler need any
152 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
153 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
154 * interrupts must be disabled and @data_status updated with a
155 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
156 * CMDRDY interrupt must be disabled and @cmd_status updated with a
157 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
158 * bytes_xfered field of @data must be written. This is ensured by
159 * using barriers.
160 */
161 struct dw_mci {
162 spinlock_t lock;
163 spinlock_t irq_lock;
164 void __iomem *regs;
165 void __iomem *fifo_reg;
166 u32 data_addr_override;
167 bool wm_aligned;
168
169 struct scatterlist *sg;
170 struct sg_mapping_iter sg_miter;
171
172 struct mmc_request *mrq;
173 struct mmc_command *cmd;
174 struct mmc_data *data;
175 struct mmc_command stop_abort;
176 unsigned int prev_blksz;
177 unsigned char timing;
178 struct workqueue_struct *card_workqueue;
179 struct workqueue_struct *sd_card_det_workqueue;
180
181 /* DMA interface members */
182 int use_dma;
183 int using_dma;
184 int dma_64bit_address;
185
186 dma_addr_t sg_dma;
187 void *sg_cpu;
188 const struct dw_mci_dma_ops *dma_ops;
189 /* For idmac */
190 unsigned int ring_size;
191
192 /* For edmac */
193 struct dw_mci_dma_slave *dms;
194 /* Registers's physical base address */
195 resource_size_t phy_regs;
196
197 unsigned int desc_sz;
198 struct pm_qos_request pm_qos_lock;
199 struct delayed_work qos_work;
200 bool qos_cntrl;
201 u32 cmd_status;
202 u32 data_status;
203 u32 stop_cmdr;
204 u32 dir_status;
205 struct tasklet_struct tasklet;
206 u32 tasklet_state;
207 struct work_struct card_work;
208 struct work_struct card_det_work;
209 unsigned long pending_events;
210 unsigned long completed_events;
211 enum dw_mci_state state;
212 struct list_head queue;
213
214 u32 bus_hz;
215 u32 current_speed;
216 u32 num_slots;
217 u32 fifoth_val;
218 u32 cd_rd_thr;
219 u16 verid;
220 u16 data_offset;
221 struct device *dev;
222 struct dw_mci_board *pdata;
223 const struct dw_mci_drv_data *drv_data;
224 void *priv;
225 struct clk *biu_clk;
226 struct clk *ciu_clk;
227 atomic_t biu_clk_cnt;
228 atomic_t ciu_clk_cnt;
229 atomic_t biu_en_win;
230 atomic_t ciu_en_win;
231 struct dw_mci_slot *slot;
232
233 /* FIFO push and pull */
234 int fifo_depth;
235 int data_shift;
236 u8 part_buf_start;
237 u8 part_buf_count;
238 union {
239 u16 part_buf16;
240 u32 part_buf32;
241 u64 part_buf;
242 };
243 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
244 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
245
246 /* Workaround flags */
247 u32 quirks;
248
249 /* S/W reset timer */
250 struct timer_list timer;
251 bool vqmmc_enabled;
252 unsigned long irq_flags; /* IRQ flags */
253 int irq;
254
255 /* Save request status */
256 #define DW_MMC_REQ_IDLE 0
257 #define DW_MMC_REQ_BUSY 1
258 unsigned int req_state;
259 struct dw_mci_debug_info *debug_info; /* debug info */
260
261 /* HWACG q-active ctrl check */
262 unsigned int qactive_check;
263
264 /* Support system power mode */
265 int idle_ip_index;
266
267 /* For argos */
268 unsigned int transferred_cnt;
269
270 /* Sfr dump */
271 struct dw_mci_sfr_ram_dump *sfr_dump;
272
273 /* S/W Timeout check */
274 bool sw_timeout_chk;
275
276 /* Card Clock In */
277 u32 cclk_in;
278
279 int sdio_id0;
280
281 struct timer_list cmd11_timer;
282 struct timer_list cto_timer;
283 struct timer_list dto_timer;
284 };
285
286 /* DMA ops for Internal/External DMAC interface */
287 struct dw_mci_dma_ops {
288 /* DMA Ops */
289 int (*init)(struct dw_mci *host);
290 int (*start)(struct dw_mci *host, unsigned int sg_len);
291 void (*complete)(void *host);
292 void (*stop)(struct dw_mci *host);
293 void (*reset)(struct dw_mci *host);
294 void (*cleanup)(struct dw_mci *host);
295 void (*exit)(struct dw_mci *host);
296 };
297
298 /* IP Quirks/flags. */
299 /* High Speed Capable - Supports HS cards (up to 50MHz) */
300 #define DW_MCI_QUIRK_HIGHSPEED BIT(0)
301 /* Unreliable card detection */
302 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(1)
303 /* No write protect */
304 #define DW_MCI_QUIRK_NO_WRITE_PROTECT BIT(2)
305 /* No detect end bit during read */
306 #define DW_MCI_QUIRK_NO_DETECT_EBIT BIT(3)
307 /* Use fixed IO voltage */
308 #define DW_MMC_QUIRK_FIXED_VOLTAGE BIT(4)
309 /* Card init W/A HWACG ctrl */
310 #define DW_MCI_QUIRK_HWACG_CTRL BIT(5)
311 /* Enables ultra low power mode */
312 #define DW_MCI_QUIRK_ENABLE_ULP BIT(6)
313 /* Use the security management unit */
314 #define DW_MCI_QUIRK_USE_SMU BIT(7)
315 /* Spread Spectrum Clock Cntrl */
316 #define DW_MCI_QUIRK_USE_SSC BIT(8)
317 /* Timer for broken data transfer over scheme */
318 #define DW_MCI_QUIRK_BROKEN_DTO BIT(9)
319
320 /* Slot level quirks */
321 /* This slot has no write protect */
322 #define DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT BIT(0)
323 enum dw_mci_cd_types {
324 DW_MCI_CD_INTERNAL = 1, /* use mmc internal CD line */
325 DW_MCI_CD_EXTERNAL, /* use external callback */
326 DW_MCI_CD_GPIO, /* use external gpio pin for CD line */
327 DW_MCI_CD_NONE, /* no CD line, use polling to detect card */
328 DW_MCI_CD_PERMANENT, /* no CD line, card permanently wired to host */
329 };
330 struct dma_pdata;
331
332 /* Board platform data */
333 struct dw_mci_board {
334 u32 num_slots;
335
336 u32 quirks; /* Workaround / Quirk flags */
337 unsigned int bus_hz; /* Clock speed at the cclk_in pad */
338
339 u32 caps; /* Capabilities */
340 u32 caps2; /* More capabilities */
341 u32 pm_caps; /* PM capabilities */
342 /*
343 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
344 * but note that this may not be reliable after a bootloader has used
345 * it.
346 */
347 unsigned int fifo_depth;
348
349 /* delay in mS before detecting cards after interrupt */
350 u32 detect_delay_ms;
351 u8 clk_smpl;
352 bool is_fine_tuned;
353 bool tuned;
354 bool extra_tuning;
355 bool only_once_tune;
356
357 /* INT QOS khz */
358 unsigned int qos_dvfs_level;
359 unsigned char io_mode;
360
361 /* SSC RATE */
362 unsigned int ssc_rate;
363
364 enum dw_mci_cd_types cd_type;
365 struct reset_control *rstc;
366 struct dw_mci_dma_ops *dma_ops;
367 struct dma_pdata *data;
368 struct block_settings *blk_settings;
369 unsigned int sw_timeout;
370
371 /* DATA_TIMEOUT[31:11] of TMOUT */
372 u32 data_timeout;
373 u32 hto_timeout;
374 bool use_gate_clock;
375 bool use_biu_gate_clock;
376 bool use_gpio_invert;
377 bool enable_cclk_on_suspend;
378 bool on_suspend;
379
380 /* Broke DRTO */
381 bool sw_drto;
382
383 /* Number of descriptors */
384 unsigned int desc_sz;
385 };
386
387 #ifdef CONFIG_MMC_DW_IDMAC
388 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
389 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
390 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
391 SDMMC_IDMAC_INT_TI)
392
393 #if defined(CONFIG_MMC_DW_EXYNOS_FMP)
394 struct idmac_desc_64addr {
395 u32 des0; /* Control Descriptor */
396 #define IDMAC_DES0_DIC BIT(1)
397 #define IDMAC_DES0_LD BIT(2)
398 #define IDMAC_DES0_FD BIT(3)
399 #define IDMAC_DES0_CH BIT(4)
400 #define IDMAC_DES0_ER BIT(5)
401 #define IDMAC_DES0_CES BIT(30)
402 #define IDMAC_DES0_OWN BIT(31)
403 u32 des1; /* Reserved */
404 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
405 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
406 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
407 u32 des2; /*Buffer sizes */
408 u32 des3; /* Reserved */
409 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1 */
410 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1 */
411 u32 des6; /* Lower 32-bits of Next Descriptor Address */
412 u32 des7; /* Upper 32-bits of Next Descriptor Address */
413 u32 des8; /* File IV 0 */
414 u32 des9; /* File IV 1 */
415 u32 des10; /* File IV 2 */
416 u32 des11; /* File IV 3 */
417 u32 des12; /* File EncKey 0 */
418 u32 des13; /* File EncKey 1 */
419 u32 des14; /* File EncKey 2 */
420 u32 des15; /* File EncKey 3 */
421 u32 des16; /* File EncKey 4 */
422 u32 des17; /* File EncKey 5 */
423 u32 des18; /* File EncKey 6 */
424 u32 des19; /* File EncKey 7 */
425 u32 des20; /* File TwKey 0 */
426 u32 des21; /* File TwKey 1 */
427 u32 des22; /* File TwKey 2 */
428 u32 des23; /* File TwKey 3 */
429 u32 des24; /* File TwKey 4 */
430 u32 des25; /* File TwKey 5 */
431 u32 des26; /* File TwKey 6 */
432 u32 des27; /* File TwKey 7 */
433 u32 des28; /* Disk IV 0 */
434 u32 des29; /* Disk IV 1 */
435 u32 des30; /* Disk IV 2 */
436 u32 des31; /* Disk IV 3 */
437 #if defined(CONFIG_EXYNOS_FMP_DUAL_FILE_ENCRYPTION)
438 u32 des32; /* File2 EncKey 0 */
439 u32 des33; /* File2 EncKey 1 */
440 u32 des34; /* File2 EncKey 2 */
441 u32 des35; /* File2 EncKey 3 */
442 u32 des36; /* File2 EncKey 4 */
443 u32 des37; /* File2 EncKey 5 */
444 u32 des38; /* File2 EncKey 6 */
445 u32 des39; /* File2 EncKey 7 */
446 u32 des40; /* File TwKey 0 */
447 u32 des41; /* File TwKey 1 */
448 u32 des42; /* File TwKey 2 */
449 u32 des43; /* File TwKey 3 */
450 u32 des44; /* File TwKey 4 */
451 u32 des45; /* File TwKey 5 */
452 u32 des46; /* File TwKey 6 */
453 u32 des47; /* File TwKey 7 */
454 u32 des48; /* Reserved */
455 u32 des49; /* Reserved */
456 u32 des50; /* Reserved */
457 u32 des51; /* Reserved */
458 u32 des52; /* Reserved */
459 u32 des53; /* Reserved */
460 u32 des54; /* Reserved */
461 u32 des55; /* Reserved */
462 u32 des56; /* Reserved */
463 u32 des57; /* Reserved */
464 u32 des58; /* Reserved */
465 u32 des59; /* Reserved */
466 u32 des60; /* Reserved */
467 u32 des61; /* Reserved */
468 u32 des62; /* Reserved */
469 u32 des63; /* Reserved */
470 #endif /* CONFIG_EXYNOS_FMP_DUAL_FILE_ENCRYPTION */
471 #define IDMAC_64ADDR_SET_DESC_CLEAR(d) \
472 do { \
473 (d)->des1 = 0; \
474 (d)->des2 = 0; \
475 (d)->des3 = 0; \
476 } while (0)
477 #define IDMAC_64ADDR_SET_DESC_ADDR(d, a) \
478 do { \
479 (d)->des6 = ((u32)(a) & 0xffffffff); \
480 (d)->des7 = ((u32)((a) >> 32)); \
481 } while (0)
482 };
483 #else
484 struct idmac_desc_64addr {
485 u32 des0; /* Control Descriptor */
486 #define IDMAC_OWN_CLR64(x) \
487 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
488
489 u32 des1; /* Reserved */
490
491 u32 des2; /*Buffer sizes */
492 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
493 ((d)->des2 = ((d)->des2 & 0x03ffe000) | ((s) & 0x1fff))
494
495 u32 des3; /* Reserved */
496
497 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1 */
498 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1 */
499
500 u32 des6; /* Lower 32-bits of Next Descriptor Address */
501 u32 des7; /* Upper 32-bits of Next Descriptor Address */
502 #define IDMAC_64ADDR_SET_DESC_CLEAR(d) \
503 do { \
504 (d)->des1 = 0; \
505 (d)->des2 = 0; \
506 (d)->des3 = 0; \
507 } while (0)
508 #define IDMAC_64ADDR_SET_DESC_ADDR(d, a) \
509 do { \
510 (d)->des6 = ((u32)(a) & 0xffffffff); \
511 (d)->des7 = ((u32)((a) >> 32)); \
512 } while (0)
513 };
514 #endif
515
516 struct idmac_desc {
517 u32 des0; /* Control Descriptor */
518 #define IDMAC_DES0_DIC BIT(1)
519 #define IDMAC_DES0_LD BIT(2)
520 #define IDMAC_DES0_FD BIT(3)
521 #define IDMAC_DES0_CH BIT(4)
522 #define IDMAC_DES0_ER BIT(5)
523 #define IDMAC_DES0_CES BIT(30)
524 #define IDMAC_DES0_OWN BIT(31)
525
526 u32 des1; /* Buffer sizes */
527 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
528 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
529
530 u32 des2; /* buffer 1 physical address */
531
532 u32 des3; /* buffer 2 physical address */
533 #define IDMAC_SET_DESC_ADDR(d, a) \
534 do { \
535 (d)->des3 = (u32)(a); \
536 } while (0)
537 };
538 #endif /* CONFIG_MMC_DW_IDMAC */
539
540 /* FMP bypass/encrypt mode */
541 #define CLEAR 0
542 #define AES_CBC 1
543 #define AES_XTS 2
544
545 #define DW_MMC_MAX_TRANSFER_SIZE 4096
546 #define DW_MMC_SECTOR_SIZE 512
547 #define MMC_DW_IDMAC_MULTIPLIER 8
548
549 #define DW_MMC_240A 0x240a
550 #define DW_MMC_260A 0x260a
551 #define DW_MMC_280A 0x280a
552
553 #define SDMMC_CTRL 0x000
554 #define SDMMC_PWREN 0x004
555 #define SDMMC_CLKDIV 0x008
556 #define SDMMC_CLKSRC 0x00c
557 #define SDMMC_CLKENA 0x010
558 #define SDMMC_TMOUT 0x014
559 #define SDMMC_CTYPE 0x018
560 #define SDMMC_BLKSIZ 0x01c
561 #define SDMMC_BYTCNT 0x020
562 #define SDMMC_INTMASK 0x024
563 #define SDMMC_CMDARG 0x028
564 #define SDMMC_CMD 0x02c
565 #define SDMMC_RESP0 0x030
566 #define SDMMC_RESP1 0x034
567 #define SDMMC_RESP2 0x038
568 #define SDMMC_RESP3 0x03c
569 #define SDMMC_MINTSTS 0x040
570 #define SDMMC_RINTSTS 0x044
571 #define SDMMC_STATUS 0x048
572 #define SDMMC_FIFOTH 0x04c
573 #define SDMMC_CDETECT 0x050
574 #define SDMMC_WRTPRT 0x054
575 #define SDMMC_GPIO 0x058
576 #define SDMMC_TCBCNT 0x05c
577 #define SDMMC_TBBCNT 0x060
578 #define SDMMC_DEBNCE 0x064
579 #define SDMMC_USRID 0x068
580 #define SDMMC_VERID 0x06c
581 #define SDMMC_HCON 0x070
582 #define SDMMC_UHS_REG 0x074
583 #define SDMMC_RST_N 0x078
584 #define SDMMC_BMOD 0x080
585 #define SDMMC_PLDMND 0x084
586 #define SDMMC_DBADDR 0x088
587 #define SDMMC_IDSTS 0x08c
588 #define SDMMC_IDINTEN 0x090
589 #define SDMMC_DSCADDR 0x094
590 #define SDMMC_BUFADDR 0x098
591 #define SDMMC_RESP_TAT 0x0AC
592 #define SDMMC_CDTHRCTL 0x100
593 #define SDMMC_UHS_REG_EXT 0x108
594 #define SDMMC_ENABLE_SHIFT 0x110
595 #define SDMMC_DATA(x) (x)
596
597 /*
598 * Data offset is difference according to Version
599 * Lower than 2.40a : data register offest is 0x100
600 */
601 #define DATA_OFFSET 0x100
602 #define DATA_240A_OFFSET 0x200
603
604 /* shift bit field */
605 #define _SBF(f, v) ((v) << (f))
606
607 /* Control register defines */
608 #define SDMMC_CTRL_USE_IDMAC BIT(25)
609 #define SDMMC_CTRL_CEATA_INT_EN BIT(11)
610 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
611 #define SDMMC_CTRL_SEND_CCSD BIT(9)
612 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
613 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
614 #define SDMMC_CTRL_READ_WAIT BIT(6)
615 #define SDMMC_CTRL_DMA_ENABLE BIT(5)
616 #define SDMMC_CTRL_INT_ENABLE BIT(4)
617 #define SDMMC_CTRL_DMA_RESET BIT(2)
618 #define SDMMC_CTRL_FIFO_RESET BIT(1)
619 #define SDMMC_CTRL_RESET BIT(0)
620 /* Clock Enable register defines */
621 #define SDMMC_CLKEN_LOW_PWR BIT(16)
622 #define SDMMC_CLKEN_ENABLE BIT(0)
623 /* time-out register defines */
624 #define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
625 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
626 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
627 #define SDMMC_TMOUT_RESP_MSK 0xFF
628 /* card-type register defines */
629 #define SDMMC_CTYPE_8BIT BIT(16)
630 #define SDMMC_CTYPE_4BIT BIT(0)
631 #define SDMMC_CTYPE_1BIT 0
632 /* Interrupt status & mask register defines */
633 #define SDMMC_INT_SDIO(n) BIT(16 + (n))
634 #define SDMMC_INT_EBE BIT(15)
635 #define SDMMC_INT_ACD BIT(14)
636 #define SDMMC_INT_SBE BIT(13)
637 #define SDMMC_INT_HLE BIT(12)
638 #define SDMMC_INT_FRUN BIT(11)
639 #define SDMMC_INT_HTO BIT(10)
640 #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
641 #define SDMMC_INT_DRTO BIT(9)
642 #define SDMMC_INT_RTO BIT(8)
643 #define SDMMC_INT_DCRC BIT(7)
644 #define SDMMC_INT_RCRC BIT(6)
645 #define SDMMC_INT_RXDR BIT(5)
646 #define SDMMC_INT_TXDR BIT(4)
647 #define SDMMC_INT_DATA_OVER BIT(3)
648 #define SDMMC_INT_CMD_DONE BIT(2)
649 #define SDMMC_INT_RESP_ERR BIT(1)
650 #define SDMMC_INT_CD BIT(0)
651 #define SDMMC_INT_ERROR 0xbfc2
652 /* Command register defines */
653 #define SDMMC_CMD_START BIT(31)
654 #define SDMMC_CMD_USE_HOLD_REG BIT(29)
655 #define SDMMC_CMD_VOLT_SWITCH BIT(28)
656 #define SDMMC_CMD_CCS_EXP BIT(23)
657 #define SDMMC_CMD_CEATA_RD BIT(22)
658 #define SDMMC_CMD_UPD_CLK BIT(21)
659 #define SDMMC_CMD_INIT BIT(15)
660 #define SDMMC_CMD_STOP BIT(14)
661 #define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
662 #define SDMMC_CMD_SEND_STOP BIT(12)
663 #define SDMMC_CMD_STRM_MODE BIT(11)
664 #define SDMMC_CMD_DAT_WR BIT(10)
665 #define SDMMC_CMD_DAT_EXP BIT(9)
666 #define SDMMC_CMD_RESP_CRC BIT(8)
667 #define SDMMC_CMD_RESP_LONG BIT(7)
668 #define SDMMC_CMD_RESP_EXP BIT(6)
669 #define SDMMC_CMD_INDX(n) ((n) & 0x1F)
670 /* Status register defines */
671 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
672 #define SDMMC_STATUS_DMA_REQ BIT(31)
673 #define SDMMC_STATUS_BUSY BIT(9)
674 /* FIFOTH register defines */
675 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
676 ((r) & 0xFFF) << 16 | \
677 ((t) & 0xFFF))
678 #define SDMMC_FIFOTH_DMA_MULTI_TRANS_SIZE 28
679 #define SDMMC_FIFOTH_RX_WMARK 16
680
681 /* HCON register defines */
682 #define DMA_INTERFACE_IDMA (0x0)
683 #define DMA_INTERFACE_DWDMA (0x1)
684 #define DMA_INTERFACE_GDMA (0x2)
685 #define DMA_INTERFACE_NODMA (0x3)
686 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
687 #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
688 #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
689 #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
690 /* Internal DMAC interrupt defines */
691 #define SDMMC_IDMAC_INT_AI BIT(9)
692 #define SDMMC_IDMAC_INT_NI BIT(8)
693 #define SDMMC_IDMAC_INT_CES BIT(5)
694 #define SDMMC_IDMAC_INT_DU BIT(4)
695 #define SDMMC_IDMAC_INT_FBE BIT(2)
696 #define SDMMC_IDMAC_INT_RI BIT(1)
697 #define SDMMC_IDMAC_INT_TI BIT(0)
698 /* Internal DMAC bus mode bits */
699 #define SDMMC_IDMAC_ENABLE BIT(7)
700 #define SDMMC_IDMAC_FB BIT(1)
701 #define SDMMC_IDMAC_SWRESET BIT(0)
702 /* H/W reset */
703 #define SDMMC_RST_HWACTIVE 0x1
704 /* Version ID register define */
705 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
706 /* Card read threshold */
707 #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
708 #define SDMMC_CARD_WR_THR_EN BIT(2)
709 #define SDMMC_CARD_RD_THR_EN BIT(0)
710 /* UHS-1 register defines */
711 #define SDMMC_UHS_18V BIT(0)
712 /* All ctrl reset bits */
713 #define SDMMC_CTRL_ALL_RESET_FLAGS \
714 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
715
716 /* FIFO register access macros. These should not change the data endian-ness
717 * as they are written to memory to be dealt with by the upper layers */
718 #define mci_fifo_readw(__reg) __raw_readw(__reg)
719 #define mci_fifo_readl(__reg) __raw_readl(__reg)
720 #ifdef CONFIG_MMC_DW_FORCE_32BIT_SFR_RW
721 #define mci_fifo_readq(__reg) ({\
722 u64 __ret = 0;\
723 u32 *ptr = (u32 *)&__ret;\
724 *ptr++ = __raw_readl(__reg);\
725 *ptr = __raw_readl(__reg + 0x4);\
726 __ret;\
727 })
728 #define mci_fifo_writeq(__reg, value) ({\
729 u32 *ptr = (u32 *)&(value);\
730 __raw_writel(*ptr++, __reg);\
731 __raw_writel(*ptr, __reg + 0x4);\
732 })
733 #else
734 #define mci_fifo_readq(__reg) __raw_readq(__reg)
735 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
736 #endif /* CONFIG_MMC_DW_FORCE_32BIT_SFR_RW */
737
738 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
739 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
740
741 /* Register access macros */
742 #define mci_readl(dev, reg) \
743 readl_relaxed((dev)->regs + SDMMC_##reg)
744 #define mci_writel(dev, reg, value) \
745 writel_relaxed((value), (dev)->regs + SDMMC_##reg)
746
747 /* timeout */
748 #define dw_mci_set_timeout(host, value) mci_writel(host, TMOUT, value)
749
750 /* 16-bit FIFO access macros */
751 #define mci_readw(dev, reg) \
752 readw_relaxed((dev)->regs + SDMMC_##reg)
753 #define mci_writew(dev, reg, value) \
754 writew_relaxed((value), (dev)->regs + SDMMC_##reg)
755
756 /* 64-bit FIFO access macros */
757 #ifdef readq
758 #ifdef CONFIG_MMC_DW_FORCE_32BIT_SFR_RW
759 #define mci_readq(dev, reg) ({\
760 u64 __ret = 0;\
761 u32 *ptr = (u32 *)&__ret;\
762 *ptr++ = __raw_readl((dev)->regs + SDMMC_##reg);\
763 *ptr = __raw_readl((dev)->regs + SDMMC_##reg + 0x4);\
764 __ret;\
765 })
766 #define mci_writeq(dev, reg, value) ({\
767 u32 *ptr = (u32 *)&(value);\
768 __raw_writel(*ptr++, (dev)->regs + SDMMC_##reg);\
769 __raw_writel(*ptr, (dev)->regs + SDMMC_##reg + 0x4);\
770 })
771 #else
772 #define mci_readq(dev, reg) \
773 readq_relaxed((dev)->regs + SDMMC_##reg)
774 #define mci_writeq(dev, reg, value) \
775 writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
776 #endif /* CONFIG_MMC_DW_FORCE_32BIT_SFR_RW */
777 #else
778 /*
779 * Dummy readq implementation for architectures that don't define it.
780 *
781 * We would assume that none of these architectures would configure
782 * the IP block with a 64bit FIFO width, so this code will never be
783 * executed on those machines. Defining these macros here keeps the
784 * rest of the code free from ifdefs.
785 */
786 #define mci_readq(dev, reg) \
787 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
788 #define mci_writeq(dev, reg, value) \
789 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
790
791 #define __raw_writeq(__value, __reg) \
792 (*(volatile u64 __force *)(__reg) = (__value))
793 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
794 #endif
795
796 /*
797 * platform-dependent miscellaneous control
798 *
799 * Input arguments for platform-dependent control may be different
800 * for each one, respectively. If we would add functions like them
801 * whenever we need to do that, this common header file(dw_mmc.h)
802 * will be modified so frequently.
803 * The following enumeration type is to minimize an amount of changes
804 * of common files.
805 */
806
807 enum dw_mci_misc_control {
808 CTRL_RESTORE_CLKSEL = 0,
809 CTRL_REQUEST_EXT_IRQ,
810 CTRL_CHECK_CD,
811 };
812
813 #define SDMMC_DATA_TMOUT_SHIFT 11
814 #define SDMMC_RESP_TMOUT 0xFF
815 #define SDMMC_DATA_TMOUT_CRT 8
816 #define SDMMC_DATA_TMOUT_EXT 0x1
817 #define SDMMC_DATA_TMOUT_EXT_SHIFT 8
818 #define SDMMC_DATA_TMOUT_MAX_CNT 0x1FFFFF
819 #define SDMMC_DATA_TMOUT_MAX_EXT_CNT 0xFFFFFF
820 #define SDMMC_HTO_TMOUT_SHIFT 8
821
822 extern u32 dw_mci_calc_timeout(struct dw_mci *host);
823 extern int dw_mci_probe(struct dw_mci *host);
824 extern void dw_mci_remove(struct dw_mci *host);
825 #ifdef CONFIG_PM
826 extern int dw_mci_runtime_suspend(struct device *device);
827 extern int dw_mci_runtime_resume(struct device *device);
828 #endif
829
830 /**
831 * struct dw_mci_slot - MMC slot state
832 * @mmc: The mmc_host representing this slot.
833 * @host: The MMC controller this slot is using.
834 * @ctype: Card type for this slot.
835 * @mrq: mmc_request currently being processed or waiting to be
836 * processed, or NULL when the slot is idle.
837 * @queue_node: List node for placing this node in the @queue list of
838 * &struct dw_mci.
839 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
840 * @__clk_old: The last clock value that was requested from core.
841 * Keeping track of this helps us to avoid spamming the console.
842 * @flags: Random state bits associated with the slot.
843 * @id: Number of this slot.
844 * @sdio_id: Number of this slot in the SDIO interrupt registers.
845 * @last_detect_state: Most recently observed card detect state.
846 */
847 struct dw_mci_slot {
848 struct mmc_host *mmc;
849 struct dw_mci *host;
850
851 int quirks;
852 u32 ctype;
853
854 struct mmc_request *mrq;
855 struct list_head queue_node;
856
857 unsigned int clock;
858 unsigned int __clk_old;
859
860 unsigned long flags;
861 #define DW_MMC_CARD_PRESENT 0
862 #define DW_MMC_CARD_NEED_INIT 1
863 #define DW_MMC_CARD_NO_LOW_PWR 2
864 #define DW_MMC_CARD_NO_USE_HOLD 3
865 #define DW_MMC_CARD_NEEDS_POLL 4
866 int id;
867 int sdio_id;
868 int last_detect_state;
869 };
870
871 /**
872 * struct dw_mci_debug_data - DwMMC debugging infomation
873 * @host_count: a number of all hosts
874 * @info_count: a number of set of debugging information
875 * @info_index: index of debugging information for each host
876 * @host: pointer of each dw_mci structure
877 * @debug_info: debugging information structure
878 */
879
880 struct dw_mci_cmd_log {
881 u64 send_time;
882 u64 done_time;
883 u8 cmd;
884 u32 arg;
885 u8 data_size;
886 /* no data CMD = CD, data CMD = DTO */
887 /*
888 * 0b1000 0000 : new_cmd with without send_cmd
889 * 0b0000 1000 : error occurs
890 * 0b0000 0100 : data_done : DTO(Data Transfer Over)
891 * 0b0000 0010 : resp : CD(Command Done)
892 * 0b0000 0001 : send_cmd : set 1 only start_command
893 */
894 u8 seq_status; /* 0bxxxx xxxx : error data_done resp send */
895 #define DW_MCI_FLAG_SEND_CMD BIT(0)
896 #define DW_MCI_FLAG_CD BIT(1)
897 #define DW_MCI_FLAG_DTO BIT(2)
898 #define DW_MCI_FLAG_ERROR BIT(3)
899 #define DW_MCI_FLAG_NEW_CMD_ERR BIT(7)
900
901 u16 rint_sts; /* RINTSTS value in case of error */
902 u8 status_count; /* TBD : It can be changed */
903 };
904
905 enum dw_mci_req_log_state {
906 STATE_REQ_START = 0,
907 STATE_REQ_CMD_PROCESS,
908 STATE_REQ_DATA_PROCESS,
909 STATE_REQ_END,
910 };
911
912 struct dw_mci_req_log {
913 u64 timestamp;
914 u32 info0;
915 u32 info1;
916 u32 info2;
917 u32 info3;
918 u32 pending_events;
919 u32 completed_events;
920 enum dw_mci_state state;
921 enum dw_mci_state state_cmd;
922 enum dw_mci_state state_dat;
923 enum dw_mci_req_log_state log_state;
924 };
925
926 #define DWMCI_LOG_MAX 0x80
927 #define DWMCI_REQ_LOG_MAX 0x40
928 struct dw_mci_debug_info {
929 struct dw_mci_cmd_log cmd_log[DWMCI_LOG_MAX];
930 atomic_t cmd_log_count;
931 struct dw_mci_req_log req_log[DWMCI_REQ_LOG_MAX];
932 atomic_t req_log_count;
933 unsigned char en_logging;
934 #define DW_MCI_DEBUG_ON_CMD BIT(0)
935 #define DW_MCI_DEBUG_ON_REQ BIT(1)
936 };
937
938 #define DWMCI_DBG_NUM_HOST 3
939
940 #define DWMCI_DBG_NUM_INFO 3 /* configurable */
941 #define DWMCI_DBG_MASK_INFO (BIT(0) | BIT(1) | BIT(2)) /* configurable */
942 #define DWMCI_DBG_BIT_HOST(x) BIT(x)
943
944 struct dw_mci_debug_data {
945 unsigned char host_count;
946 unsigned char info_count;
947 unsigned char info_index[DWMCI_DBG_NUM_HOST];
948 struct dw_mci *host[DWMCI_DBG_NUM_HOST];
949 struct dw_mci_debug_info debug_info[DWMCI_DBG_NUM_INFO];
950 };
951
952 struct dw_mci_tuning_data {
953 const u8 *blk_pattern;
954 unsigned int blksz;
955 };
956
957 /**
958 * dw_mci driver data - dw-mshc implementation specific driver data.
959 * @caps: mmc subsystem specified capabilities of the controller(s).
960 * @num_caps: number of capabilities specified by @caps.
961 * @init: early implementation specific initialization.
962 * @set_ios: handle bus specific extensions.
963 * @parse_dt: parse implementation specific device tree properties.
964 * @execute_tuning: implementation specific tuning procedure.
965 *
966 * Provide controller implementation specific extensions. The usage of this
967 * data structure is fully optional and usage of each member in this structure
968 * is optional as well.
969 */
970 struct dw_mci_drv_data {
971 unsigned long *caps;
972 u32 num_caps;
973 int (*init)(struct dw_mci *host);
974 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
975 int (*parse_dt)(struct dw_mci *host);
976 int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode,
977 struct dw_mci_tuning_data *tuning_data);
978 int (*prepare_hs400_tuning)(struct dw_mci *host, struct mmc_ios *ios);
979 int (*switch_voltage)(struct mmc_host *mmc, struct mmc_ios *ios);
980 void (*hwacg_control)(struct dw_mci *host, u32 flag);
981 int (*misc_control)(struct dw_mci *host, enum dw_mci_misc_control control, void *priv);
982 int (*crypto_engine_cfg)(struct dw_mci *host,
983 void *desc,
984 struct mmc_data *data,
985 struct page *page, int sector_offset, bool cmdq_enabled);
986 int (*crypto_engine_clear)(struct dw_mci *host, void *desc, bool cmdq_enabled);
987 int (*access_control_get_dev)(struct dw_mci *host);
988 int (*access_control_sec_cfg)(struct dw_mci *host);
989 int (*access_control_init)(struct dw_mci *host);
990 int (*access_control_abort)(struct dw_mci *host);
991 int (*access_control_resume)(struct dw_mci *host);
992 void (*ssclk_control)(struct dw_mci *host, int enable);
993 };
994
995 struct dw_mci_sfr_ram_dump {
996 u32 contrl;
997 u32 pwren;
998 u32 clkdiv;
999 u32 clkena;
1000 u32 clksrc;
1001 u32 tmout;
1002 u32 ctype;
1003 u32 blksiz;
1004 u32 bytcnt;
1005 u32 intmask;
1006 u32 cmdarg;
1007 u32 cmd;
1008 u32 mintsts;
1009 u32 rintsts;
1010 u32 status;
1011 u32 fifoth;
1012 u32 tcbcnt;
1013 u32 tbbcnt;
1014 u32 debnce;
1015 u32 uhs_reg;
1016 u32 bmod;
1017 u32 pldmnd;
1018 u32 dbaddrl;
1019 u32 dbaddru;
1020 u32 dscaddrl;
1021 u32 dscaddru;
1022 u32 bufaddru;
1023 u32 dbaddr;
1024 u32 dscaddr;
1025 u32 bufaddr;
1026 u32 clksel;
1027 u32 idsts64;
1028 u32 idinten64;
1029 u32 force_clk_stop;
1030 u32 cdthrctl;
1031 u32 hs400_rdqs_en;
1032 u32 hs400_acync_fifo_ctrl;
1033 u32 hs400_dline_ctrl;
1034 u32 fmp_emmcp_base;
1035 u32 mpsecurity;
1036 u32 mpstat;
1037 u32 mpsbegin;
1038 u32 mpsend;
1039 u32 mpsctrl;
1040 u32 cmd_status;
1041 u32 data_status;
1042 unsigned long pending_events;
1043 unsigned long completed_events;
1044 u32 host_state;
1045 u32 cmd_index;
1046 u32 fifo_count;
1047 u32 data_busy;
1048 u32 data_3_state;
1049 u32 fifo_tx_watermark;
1050 u32 fifo_rx_watermark;
1051 };
1052 #endif /* _DW_MMC_H_ */