projects / GitHub / LineageOS / android_kernel_motorola_exynos9610.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
mmc: dw_mmc: Fix the CTO timeout calculation
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / mmc / host / dw_mmc.c
1 /*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/iopoll.h>
23 #include <linux/ioport.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/delay.h>
31 #include <linux/irq.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/mmc.h>
35 #include <linux/mmc/sd.h>
36 #include <linux/mmc/sdio.h>
37 #include <linux/bitops.h>
38 #include <linux/regulator/consumer.h>
39 #include <linux/of.h>
40 #include <linux/of_gpio.h>
41 #include <linux/mmc/slot-gpio.h>
42
43 #include "dw_mmc.h"
44
45 /* Common flag combinations */
46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
47 SDMMC_INT_HTO | SDMMC_INT_SBE | \
48 SDMMC_INT_EBE | SDMMC_INT_HLE)
49 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
51 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
52 DW_MCI_CMD_ERROR_FLAGS)
53 #define DW_MCI_SEND_STATUS 1
54 #define DW_MCI_RECV_STATUS 2
55 #define DW_MCI_DMA_THRESHOLD 16
56
57 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
58 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
59
60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
65 #define DESC_RING_BUF_SZ PAGE_SIZE
66
67 struct idmac_desc_64addr {
68 u32 des0; /* Control Descriptor */
69 #define IDMAC_OWN_CLR64(x) \
70 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
71
72 u32 des1; /* Reserved */
73
74 u32 des2; /*Buffer sizes */
75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
78
79 u32 des3; /* Reserved */
80
81 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
82 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
83
84 u32 des6; /* Lower 32-bits of Next Descriptor Address */
85 u32 des7; /* Upper 32-bits of Next Descriptor Address */
86 };
87
88 struct idmac_desc {
89 __le32 des0; /* Control Descriptor */
90 #define IDMAC_DES0_DIC BIT(1)
91 #define IDMAC_DES0_LD BIT(2)
92 #define IDMAC_DES0_FD BIT(3)
93 #define IDMAC_DES0_CH BIT(4)
94 #define IDMAC_DES0_ER BIT(5)
95 #define IDMAC_DES0_CES BIT(30)
96 #define IDMAC_DES0_OWN BIT(31)
97
98 __le32 des1; /* Buffer sizes */
99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
101
102 __le32 des2; /* buffer 1 physical address */
103
104 __le32 des3; /* buffer 2 physical address */
105 };
106
107 /* Each descriptor can transfer up to 4KB of data in chained mode */
108 #define DW_MCI_DESC_DATA_LENGTH 0x1000
109
110 #if defined(CONFIG_DEBUG_FS)
111 static int dw_mci_req_show(struct seq_file *s, void *v)
112 {
113 struct dw_mci_slot *slot = s->private;
114 struct mmc_request *mrq;
115 struct mmc_command *cmd;
116 struct mmc_command *stop;
117 struct mmc_data *data;
118
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot->host->lock);
121 mrq = slot->mrq;
122
123 if (mrq) {
124 cmd = mrq->cmd;
125 data = mrq->data;
126 stop = mrq->stop;
127
128 if (cmd)
129 seq_printf(s,
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd->opcode, cmd->arg, cmd->flags,
132 cmd->resp[0], cmd->resp[1], cmd->resp[2],
133 cmd->resp[2], cmd->error);
134 if (data)
135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
136 data->bytes_xfered, data->blocks,
137 data->blksz, data->flags, data->error);
138 if (stop)
139 seq_printf(s,
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop->opcode, stop->arg, stop->flags,
142 stop->resp[0], stop->resp[1], stop->resp[2],
143 stop->resp[2], stop->error);
144 }
145
146 spin_unlock_bh(&slot->host->lock);
147
148 return 0;
149 }
150
151 static int dw_mci_req_open(struct inode *inode, struct file *file)
152 {
153 return single_open(file, dw_mci_req_show, inode->i_private);
154 }
155
156 static const struct file_operations dw_mci_req_fops = {
157 .owner = THIS_MODULE,
158 .open = dw_mci_req_open,
159 .read = seq_read,
160 .llseek = seq_lseek,
161 .release = single_release,
162 };
163
164 static int dw_mci_regs_show(struct seq_file *s, void *v)
165 {
166 struct dw_mci *host = s->private;
167
168 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
169 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
170 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
171 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
172 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
173 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
174
175 return 0;
176 }
177
178 static int dw_mci_regs_open(struct inode *inode, struct file *file)
179 {
180 return single_open(file, dw_mci_regs_show, inode->i_private);
181 }
182
183 static const struct file_operations dw_mci_regs_fops = {
184 .owner = THIS_MODULE,
185 .open = dw_mci_regs_open,
186 .read = seq_read,
187 .llseek = seq_lseek,
188 .release = single_release,
189 };
190
191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
192 {
193 struct mmc_host *mmc = slot->mmc;
194 struct dw_mci *host = slot->host;
195 struct dentry *root;
196 struct dentry *node;
197
198 root = mmc->debugfs_root;
199 if (!root)
200 return;
201
202 node = debugfs_create_file("regs", S_IRUSR, root, host,
203 &dw_mci_regs_fops);
204 if (!node)
205 goto err;
206
207 node = debugfs_create_file("req", S_IRUSR, root, slot,
208 &dw_mci_req_fops);
209 if (!node)
210 goto err;
211
212 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
213 if (!node)
214 goto err;
215
216 node = debugfs_create_x32("pending_events", S_IRUSR, root,
217 (u32 *)&host->pending_events);
218 if (!node)
219 goto err;
220
221 node = debugfs_create_x32("completed_events", S_IRUSR, root,
222 (u32 *)&host->completed_events);
223 if (!node)
224 goto err;
225
226 return;
227
228 err:
229 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
230 }
231 #endif /* defined(CONFIG_DEBUG_FS) */
232
233 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
234 {
235 u32 ctrl;
236
237 ctrl = mci_readl(host, CTRL);
238 ctrl |= reset;
239 mci_writel(host, CTRL, ctrl);
240
241 /* wait till resets clear */
242 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
243 !(ctrl & reset),
244 1, 500 * USEC_PER_MSEC)) {
245 dev_err(host->dev,
246 "Timeout resetting block (ctrl reset %#x)\n",
247 ctrl & reset);
248 return false;
249 }
250
251 return true;
252 }
253
254 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
255 {
256 u32 status;
257
258 /*
259 * Databook says that before issuing a new data transfer command
260 * we need to check to see if the card is busy. Data transfer commands
261 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
262 *
263 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
264 * expected.
265 */
266 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
267 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
268 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
269 status,
270 !(status & SDMMC_STATUS_BUSY),
271 10, 500 * USEC_PER_MSEC))
272 dev_err(host->dev, "Busy; trying anyway\n");
273 }
274 }
275
276 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
277 {
278 struct dw_mci *host = slot->host;
279 unsigned int cmd_status = 0;
280
281 mci_writel(host, CMDARG, arg);
282 wmb(); /* drain writebuffer */
283 dw_mci_wait_while_busy(host, cmd);
284 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
285
286 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
287 !(cmd_status & SDMMC_CMD_START),
288 1, 500 * USEC_PER_MSEC))
289 dev_err(&slot->mmc->class_dev,
290 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
291 cmd, arg, cmd_status);
292 }
293
294 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
295 {
296 struct dw_mci_slot *slot = mmc_priv(mmc);
297 struct dw_mci *host = slot->host;
298 u32 cmdr;
299
300 cmd->error = -EINPROGRESS;
301 cmdr = cmd->opcode;
302
303 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
304 cmd->opcode == MMC_GO_IDLE_STATE ||
305 cmd->opcode == MMC_GO_INACTIVE_STATE ||
306 (cmd->opcode == SD_IO_RW_DIRECT &&
307 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
308 cmdr |= SDMMC_CMD_STOP;
309 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
310 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
311
312 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
313 u32 clk_en_a;
314
315 /* Special bit makes CMD11 not die */
316 cmdr |= SDMMC_CMD_VOLT_SWITCH;
317
318 /* Change state to continue to handle CMD11 weirdness */
319 WARN_ON(slot->host->state != STATE_SENDING_CMD);
320 slot->host->state = STATE_SENDING_CMD11;
321
322 /*
323 * We need to disable low power mode (automatic clock stop)
324 * while doing voltage switch so we don't confuse the card,
325 * since stopping the clock is a specific part of the UHS
326 * voltage change dance.
327 *
328 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
329 * unconditionally turned back on in dw_mci_setup_bus() if it's
330 * ever called with a non-zero clock. That shouldn't happen
331 * until the voltage change is all done.
332 */
333 clk_en_a = mci_readl(host, CLKENA);
334 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
335 mci_writel(host, CLKENA, clk_en_a);
336 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
337 SDMMC_CMD_PRV_DAT_WAIT, 0);
338 }
339
340 if (cmd->flags & MMC_RSP_PRESENT) {
341 /* We expect a response, so set this bit */
342 cmdr |= SDMMC_CMD_RESP_EXP;
343 if (cmd->flags & MMC_RSP_136)
344 cmdr |= SDMMC_CMD_RESP_LONG;
345 }
346
347 if (cmd->flags & MMC_RSP_CRC)
348 cmdr |= SDMMC_CMD_RESP_CRC;
349
350 if (cmd->data) {
351 cmdr |= SDMMC_CMD_DAT_EXP;
352 if (cmd->data->flags & MMC_DATA_WRITE)
353 cmdr |= SDMMC_CMD_DAT_WR;
354 }
355
356 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
357 cmdr |= SDMMC_CMD_USE_HOLD_REG;
358
359 return cmdr;
360 }
361
362 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
363 {
364 struct mmc_command *stop;
365 u32 cmdr;
366
367 if (!cmd->data)
368 return 0;
369
370 stop = &host->stop_abort;
371 cmdr = cmd->opcode;
372 memset(stop, 0, sizeof(struct mmc_command));
373
374 if (cmdr == MMC_READ_SINGLE_BLOCK ||
375 cmdr == MMC_READ_MULTIPLE_BLOCK ||
376 cmdr == MMC_WRITE_BLOCK ||
377 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
378 cmdr == MMC_SEND_TUNING_BLOCK ||
379 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
380 stop->opcode = MMC_STOP_TRANSMISSION;
381 stop->arg = 0;
382 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
383 } else if (cmdr == SD_IO_RW_EXTENDED) {
384 stop->opcode = SD_IO_RW_DIRECT;
385 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
386 ((cmd->arg >> 28) & 0x7);
387 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
388 } else {
389 return 0;
390 }
391
392 cmdr = stop->opcode | SDMMC_CMD_STOP |
393 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
394
395 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
396 cmdr |= SDMMC_CMD_USE_HOLD_REG;
397
398 return cmdr;
399 }
400
401 static inline void dw_mci_set_cto(struct dw_mci *host)
402 {
403 unsigned int cto_clks;
404 unsigned int cto_div;
405 unsigned int cto_ms;
406
407 cto_clks = mci_readl(host, TMOUT) & 0xff;
408 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
409 if (cto_div == 0)
410 cto_div = 1;
411 cto_ms = DIV_ROUND_UP(MSEC_PER_SEC * cto_clks * cto_div, host->bus_hz);
412
413 /* add a bit spare time */
414 cto_ms += 10;
415
416 mod_timer(&host->cto_timer,
417 jiffies + msecs_to_jiffies(cto_ms) + 1);
418 }
419
420 static void dw_mci_start_command(struct dw_mci *host,
421 struct mmc_command *cmd, u32 cmd_flags)
422 {
423 host->cmd = cmd;
424 dev_vdbg(host->dev,
425 "start command: ARGR=0x%08x CMDR=0x%08x\n",
426 cmd->arg, cmd_flags);
427
428 mci_writel(host, CMDARG, cmd->arg);
429 wmb(); /* drain writebuffer */
430 dw_mci_wait_while_busy(host, cmd_flags);
431
432 /* response expected command only */
433 if (cmd_flags & SDMMC_CMD_RESP_EXP)
434 dw_mci_set_cto(host);
435
436 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
437 }
438
439 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
440 {
441 struct mmc_command *stop = &host->stop_abort;
442
443 dw_mci_start_command(host, stop, host->stop_cmdr);
444 }
445
446 /* DMA interface functions */
447 static void dw_mci_stop_dma(struct dw_mci *host)
448 {
449 if (host->using_dma) {
450 host->dma_ops->stop(host);
451 host->dma_ops->cleanup(host);
452 }
453
454 /* Data transfer was stopped by the interrupt handler */
455 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
456 }
457
458 static void dw_mci_dma_cleanup(struct dw_mci *host)
459 {
460 struct mmc_data *data = host->data;
461
462 if (data && data->host_cookie == COOKIE_MAPPED) {
463 dma_unmap_sg(host->dev,
464 data->sg,
465 data->sg_len,
466 mmc_get_dma_dir(data));
467 data->host_cookie = COOKIE_UNMAPPED;
468 }
469 }
470
471 static void dw_mci_idmac_reset(struct dw_mci *host)
472 {
473 u32 bmod = mci_readl(host, BMOD);
474 /* Software reset of DMA */
475 bmod |= SDMMC_IDMAC_SWRESET;
476 mci_writel(host, BMOD, bmod);
477 }
478
479 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
480 {
481 u32 temp;
482
483 /* Disable and reset the IDMAC interface */
484 temp = mci_readl(host, CTRL);
485 temp &= ~SDMMC_CTRL_USE_IDMAC;
486 temp |= SDMMC_CTRL_DMA_RESET;
487 mci_writel(host, CTRL, temp);
488
489 /* Stop the IDMAC running */
490 temp = mci_readl(host, BMOD);
491 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
492 temp |= SDMMC_IDMAC_SWRESET;
493 mci_writel(host, BMOD, temp);
494 }
495
496 static void dw_mci_dmac_complete_dma(void *arg)
497 {
498 struct dw_mci *host = arg;
499 struct mmc_data *data = host->data;
500
501 dev_vdbg(host->dev, "DMA complete\n");
502
503 if ((host->use_dma == TRANS_MODE_EDMAC) &&
504 data && (data->flags & MMC_DATA_READ))
505 /* Invalidate cache after read */
506 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
507 data->sg,
508 data->sg_len,
509 DMA_FROM_DEVICE);
510
511 host->dma_ops->cleanup(host);
512
513 /*
514 * If the card was removed, data will be NULL. No point in trying to
515 * send the stop command or waiting for NBUSY in this case.
516 */
517 if (data) {
518 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
519 tasklet_schedule(&host->tasklet);
520 }
521 }
522
523 static int dw_mci_idmac_init(struct dw_mci *host)
524 {
525 int i;
526
527 if (host->dma_64bit_address == 1) {
528 struct idmac_desc_64addr *p;
529 /* Number of descriptors in the ring buffer */
530 host->ring_size =
531 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
532
533 /* Forward link the descriptor list */
534 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
535 i++, p++) {
536 p->des6 = (host->sg_dma +
537 (sizeof(struct idmac_desc_64addr) *
538 (i + 1))) & 0xffffffff;
539
540 p->des7 = (u64)(host->sg_dma +
541 (sizeof(struct idmac_desc_64addr) *
542 (i + 1))) >> 32;
543 /* Initialize reserved and buffer size fields to "0" */
544 p->des1 = 0;
545 p->des2 = 0;
546 p->des3 = 0;
547 }
548
549 /* Set the last descriptor as the end-of-ring descriptor */
550 p->des6 = host->sg_dma & 0xffffffff;
551 p->des7 = (u64)host->sg_dma >> 32;
552 p->des0 = IDMAC_DES0_ER;
553
554 } else {
555 struct idmac_desc *p;
556 /* Number of descriptors in the ring buffer */
557 host->ring_size =
558 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
559
560 /* Forward link the descriptor list */
561 for (i = 0, p = host->sg_cpu;
562 i < host->ring_size - 1;
563 i++, p++) {
564 p->des3 = cpu_to_le32(host->sg_dma +
565 (sizeof(struct idmac_desc) * (i + 1)));
566 p->des1 = 0;
567 }
568
569 /* Set the last descriptor as the end-of-ring descriptor */
570 p->des3 = cpu_to_le32(host->sg_dma);
571 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
572 }
573
574 dw_mci_idmac_reset(host);
575
576 if (host->dma_64bit_address == 1) {
577 /* Mask out interrupts - get Tx & Rx complete only */
578 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
579 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
580 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
581
582 /* Set the descriptor base address */
583 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
584 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
585
586 } else {
587 /* Mask out interrupts - get Tx & Rx complete only */
588 mci_writel(host, IDSTS, IDMAC_INT_CLR);
589 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
590 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
591
592 /* Set the descriptor base address */
593 mci_writel(host, DBADDR, host->sg_dma);
594 }
595
596 return 0;
597 }
598
599 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
600 struct mmc_data *data,
601 unsigned int sg_len)
602 {
603 unsigned int desc_len;
604 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
605 u32 val;
606 int i;
607
608 desc_first = desc_last = desc = host->sg_cpu;
609
610 for (i = 0; i < sg_len; i++) {
611 unsigned int length = sg_dma_len(&data->sg[i]);
612
613 u64 mem_addr = sg_dma_address(&data->sg[i]);
614
615 for ( ; length ; desc++) {
616 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
617 length : DW_MCI_DESC_DATA_LENGTH;
618
619 length -= desc_len;
620
621 /*
622 * Wait for the former clear OWN bit operation
623 * of IDMAC to make sure that this descriptor
624 * isn't still owned by IDMAC as IDMAC's write
625 * ops and CPU's read ops are asynchronous.
626 */
627 if (readl_poll_timeout_atomic(&desc->des0, val,
628 !(val & IDMAC_DES0_OWN),
629 10, 100 * USEC_PER_MSEC))
630 goto err_own_bit;
631
632 /*
633 * Set the OWN bit and disable interrupts
634 * for this descriptor
635 */
636 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
637 IDMAC_DES0_CH;
638
639 /* Buffer length */
640 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
641
642 /* Physical address to DMA to/from */
643 desc->des4 = mem_addr & 0xffffffff;
644 desc->des5 = mem_addr >> 32;
645
646 /* Update physical address for the next desc */
647 mem_addr += desc_len;
648
649 /* Save pointer to the last descriptor */
650 desc_last = desc;
651 }
652 }
653
654 /* Set first descriptor */
655 desc_first->des0 |= IDMAC_DES0_FD;
656
657 /* Set last descriptor */
658 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
659 desc_last->des0 |= IDMAC_DES0_LD;
660
661 return 0;
662 err_own_bit:
663 /* restore the descriptor chain as it's polluted */
664 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
665 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
666 dw_mci_idmac_init(host);
667 return -EINVAL;
668 }
669
670
671 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
672 struct mmc_data *data,
673 unsigned int sg_len)
674 {
675 unsigned int desc_len;
676 struct idmac_desc *desc_first, *desc_last, *desc;
677 u32 val;
678 int i;
679
680 desc_first = desc_last = desc = host->sg_cpu;
681
682 for (i = 0; i < sg_len; i++) {
683 unsigned int length = sg_dma_len(&data->sg[i]);
684
685 u32 mem_addr = sg_dma_address(&data->sg[i]);
686
687 for ( ; length ; desc++) {
688 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
689 length : DW_MCI_DESC_DATA_LENGTH;
690
691 length -= desc_len;
692
693 /*
694 * Wait for the former clear OWN bit operation
695 * of IDMAC to make sure that this descriptor
696 * isn't still owned by IDMAC as IDMAC's write
697 * ops and CPU's read ops are asynchronous.
698 */
699 if (readl_poll_timeout_atomic(&desc->des0, val,
700 IDMAC_OWN_CLR64(val),
701 10,
702 100 * USEC_PER_MSEC))
703 goto err_own_bit;
704
705 /*
706 * Set the OWN bit and disable interrupts
707 * for this descriptor
708 */
709 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
710 IDMAC_DES0_DIC |
711 IDMAC_DES0_CH);
712
713 /* Buffer length */
714 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
715
716 /* Physical address to DMA to/from */
717 desc->des2 = cpu_to_le32(mem_addr);
718
719 /* Update physical address for the next desc */
720 mem_addr += desc_len;
721
722 /* Save pointer to the last descriptor */
723 desc_last = desc;
724 }
725 }
726
727 /* Set first descriptor */
728 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
729
730 /* Set last descriptor */
731 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
732 IDMAC_DES0_DIC));
733 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
734
735 return 0;
736 err_own_bit:
737 /* restore the descriptor chain as it's polluted */
738 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
739 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
740 dw_mci_idmac_init(host);
741 return -EINVAL;
742 }
743
744 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
745 {
746 u32 temp;
747 int ret;
748
749 if (host->dma_64bit_address == 1)
750 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
751 else
752 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
753
754 if (ret)
755 goto out;
756
757 /* drain writebuffer */
758 wmb();
759
760 /* Make sure to reset DMA in case we did PIO before this */
761 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
762 dw_mci_idmac_reset(host);
763
764 /* Select IDMAC interface */
765 temp = mci_readl(host, CTRL);
766 temp |= SDMMC_CTRL_USE_IDMAC;
767 mci_writel(host, CTRL, temp);
768
769 /* drain writebuffer */
770 wmb();
771
772 /* Enable the IDMAC */
773 temp = mci_readl(host, BMOD);
774 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
775 mci_writel(host, BMOD, temp);
776
777 /* Start it running */
778 mci_writel(host, PLDMND, 1);
779
780 out:
781 return ret;
782 }
783
784 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
785 .init = dw_mci_idmac_init,
786 .start = dw_mci_idmac_start_dma,
787 .stop = dw_mci_idmac_stop_dma,
788 .complete = dw_mci_dmac_complete_dma,
789 .cleanup = dw_mci_dma_cleanup,
790 };
791
792 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
793 {
794 dmaengine_terminate_async(host->dms->ch);
795 }
796
797 static int dw_mci_edmac_start_dma(struct dw_mci *host,
798 unsigned int sg_len)
799 {
800 struct dma_slave_config cfg;
801 struct dma_async_tx_descriptor *desc = NULL;
802 struct scatterlist *sgl = host->data->sg;
803 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
804 u32 sg_elems = host->data->sg_len;
805 u32 fifoth_val;
806 u32 fifo_offset = host->fifo_reg - host->regs;
807 int ret = 0;
808
809 /* Set external dma config: burst size, burst width */
810 cfg.dst_addr = host->phy_regs + fifo_offset;
811 cfg.src_addr = cfg.dst_addr;
812 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
813 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
814
815 /* Match burst msize with external dma config */
816 fifoth_val = mci_readl(host, FIFOTH);
817 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
818 cfg.src_maxburst = cfg.dst_maxburst;
819
820 if (host->data->flags & MMC_DATA_WRITE)
821 cfg.direction = DMA_MEM_TO_DEV;
822 else
823 cfg.direction = DMA_DEV_TO_MEM;
824
825 ret = dmaengine_slave_config(host->dms->ch, &cfg);
826 if (ret) {
827 dev_err(host->dev, "Failed to config edmac.\n");
828 return -EBUSY;
829 }
830
831 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
832 sg_len, cfg.direction,
833 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
834 if (!desc) {
835 dev_err(host->dev, "Can't prepare slave sg.\n");
836 return -EBUSY;
837 }
838
839 /* Set dw_mci_dmac_complete_dma as callback */
840 desc->callback = dw_mci_dmac_complete_dma;
841 desc->callback_param = (void *)host;
842 dmaengine_submit(desc);
843
844 /* Flush cache before write */
845 if (host->data->flags & MMC_DATA_WRITE)
846 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
847 sg_elems, DMA_TO_DEVICE);
848
849 dma_async_issue_pending(host->dms->ch);
850
851 return 0;
852 }
853
854 static int dw_mci_edmac_init(struct dw_mci *host)
855 {
856 /* Request external dma channel */
857 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
858 if (!host->dms)
859 return -ENOMEM;
860
861 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
862 if (!host->dms->ch) {
863 dev_err(host->dev, "Failed to get external DMA channel.\n");
864 kfree(host->dms);
865 host->dms = NULL;
866 return -ENXIO;
867 }
868
869 return 0;
870 }
871
872 static void dw_mci_edmac_exit(struct dw_mci *host)
873 {
874 if (host->dms) {
875 if (host->dms->ch) {
876 dma_release_channel(host->dms->ch);
877 host->dms->ch = NULL;
878 }
879 kfree(host->dms);
880 host->dms = NULL;
881 }
882 }
883
884 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
885 .init = dw_mci_edmac_init,
886 .exit = dw_mci_edmac_exit,
887 .start = dw_mci_edmac_start_dma,
888 .stop = dw_mci_edmac_stop_dma,
889 .complete = dw_mci_dmac_complete_dma,
890 .cleanup = dw_mci_dma_cleanup,
891 };
892
893 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
894 struct mmc_data *data,
895 int cookie)
896 {
897 struct scatterlist *sg;
898 unsigned int i, sg_len;
899
900 if (data->host_cookie == COOKIE_PRE_MAPPED)
901 return data->sg_len;
902
903 /*
904 * We don't do DMA on "complex" transfers, i.e. with
905 * non-word-aligned buffers or lengths. Also, we don't bother
906 * with all the DMA setup overhead for short transfers.
907 */
908 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
909 return -EINVAL;
910
911 if (data->blksz & 3)
912 return -EINVAL;
913
914 for_each_sg(data->sg, sg, data->sg_len, i) {
915 if (sg->offset & 3 || sg->length & 3)
916 return -EINVAL;
917 }
918
919 sg_len = dma_map_sg(host->dev,
920 data->sg,
921 data->sg_len,
922 mmc_get_dma_dir(data));
923 if (sg_len == 0)
924 return -EINVAL;
925
926 data->host_cookie = cookie;
927
928 return sg_len;
929 }
930
931 static void dw_mci_pre_req(struct mmc_host *mmc,
932 struct mmc_request *mrq)
933 {
934 struct dw_mci_slot *slot = mmc_priv(mmc);
935 struct mmc_data *data = mrq->data;
936
937 if (!slot->host->use_dma || !data)
938 return;
939
940 /* This data might be unmapped at this time */
941 data->host_cookie = COOKIE_UNMAPPED;
942
943 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
944 COOKIE_PRE_MAPPED) < 0)
945 data->host_cookie = COOKIE_UNMAPPED;
946 }
947
948 static void dw_mci_post_req(struct mmc_host *mmc,
949 struct mmc_request *mrq,
950 int err)
951 {
952 struct dw_mci_slot *slot = mmc_priv(mmc);
953 struct mmc_data *data = mrq->data;
954
955 if (!slot->host->use_dma || !data)
956 return;
957
958 if (data->host_cookie != COOKIE_UNMAPPED)
959 dma_unmap_sg(slot->host->dev,
960 data->sg,
961 data->sg_len,
962 mmc_get_dma_dir(data));
963 data->host_cookie = COOKIE_UNMAPPED;
964 }
965
966 static int dw_mci_get_cd(struct mmc_host *mmc)
967 {
968 int present;
969 struct dw_mci_slot *slot = mmc_priv(mmc);
970 struct dw_mci *host = slot->host;
971 int gpio_cd = mmc_gpio_get_cd(mmc);
972
973 /* Use platform get_cd function, else try onboard card detect */
974 if (((mmc->caps & MMC_CAP_NEEDS_POLL)
975 || !mmc_card_is_removable(mmc))) {
976 present = 1;
977
978 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
979 if (mmc->caps & MMC_CAP_NEEDS_POLL) {
980 dev_info(&mmc->class_dev,
981 "card is polling.\n");
982 } else {
983 dev_info(&mmc->class_dev,
984 "card is non-removable.\n");
985 }
986 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
987 }
988
989 return present;
990 } else if (gpio_cd >= 0)
991 present = gpio_cd;
992 else
993 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
994 == 0 ? 1 : 0;
995
996 spin_lock_bh(&host->lock);
997 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
998 dev_dbg(&mmc->class_dev, "card is present\n");
999 else if (!present &&
1000 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1001 dev_dbg(&mmc->class_dev, "card is not present\n");
1002 spin_unlock_bh(&host->lock);
1003
1004 return present;
1005 }
1006
1007 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
1008 {
1009 unsigned int blksz = data->blksz;
1010 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
1011 u32 fifo_width = 1 << host->data_shift;
1012 u32 blksz_depth = blksz / fifo_width, fifoth_val;
1013 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
1014 int idx = ARRAY_SIZE(mszs) - 1;
1015
1016 /* pio should ship this scenario */
1017 if (!host->use_dma)
1018 return;
1019
1020 tx_wmark = (host->fifo_depth) / 2;
1021 tx_wmark_invers = host->fifo_depth - tx_wmark;
1022
1023 /*
1024 * MSIZE is '1',
1025 * if blksz is not a multiple of the FIFO width
1026 */
1027 if (blksz % fifo_width)
1028 goto done;
1029
1030 do {
1031 if (!((blksz_depth % mszs[idx]) ||
1032 (tx_wmark_invers % mszs[idx]))) {
1033 msize = idx;
1034 rx_wmark = mszs[idx] - 1;
1035 break;
1036 }
1037 } while (--idx > 0);
1038 /*
1039 * If idx is '0', it won't be tried
1040 * Thus, initial values are uesed
1041 */
1042 done:
1043 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1044 mci_writel(host, FIFOTH, fifoth_val);
1045 }
1046
1047 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1048 {
1049 unsigned int blksz = data->blksz;
1050 u32 blksz_depth, fifo_depth;
1051 u16 thld_size;
1052 u8 enable;
1053
1054 /*
1055 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1056 * in the FIFO region, so we really shouldn't access it).
1057 */
1058 if (host->verid < DW_MMC_240A ||
1059 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1060 return;
1061
1062 /*
1063 * Card write Threshold is introduced since 2.80a
1064 * It's used when HS400 mode is enabled.
1065 */
1066 if (data->flags & MMC_DATA_WRITE &&
1067 !(host->timing != MMC_TIMING_MMC_HS400))
1068 return;
1069
1070 if (data->flags & MMC_DATA_WRITE)
1071 enable = SDMMC_CARD_WR_THR_EN;
1072 else
1073 enable = SDMMC_CARD_RD_THR_EN;
1074
1075 if (host->timing != MMC_TIMING_MMC_HS200 &&
1076 host->timing != MMC_TIMING_UHS_SDR104)
1077 goto disable;
1078
1079 blksz_depth = blksz / (1 << host->data_shift);
1080 fifo_depth = host->fifo_depth;
1081
1082 if (blksz_depth > fifo_depth)
1083 goto disable;
1084
1085 /*
1086 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1087 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1088 * Currently just choose blksz.
1089 */
1090 thld_size = blksz;
1091 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1092 return;
1093
1094 disable:
1095 mci_writel(host, CDTHRCTL, 0);
1096 }
1097
1098 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1099 {
1100 unsigned long irqflags;
1101 int sg_len;
1102 u32 temp;
1103
1104 host->using_dma = 0;
1105
1106 /* If we don't have a channel, we can't do DMA */
1107 if (!host->use_dma)
1108 return -ENODEV;
1109
1110 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1111 if (sg_len < 0) {
1112 host->dma_ops->stop(host);
1113 return sg_len;
1114 }
1115
1116 host->using_dma = 1;
1117
1118 if (host->use_dma == TRANS_MODE_IDMAC)
1119 dev_vdbg(host->dev,
1120 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1121 (unsigned long)host->sg_cpu,
1122 (unsigned long)host->sg_dma,
1123 sg_len);
1124
1125 /*
1126 * Decide the MSIZE and RX/TX Watermark.
1127 * If current block size is same with previous size,
1128 * no need to update fifoth.
1129 */
1130 if (host->prev_blksz != data->blksz)
1131 dw_mci_adjust_fifoth(host, data);
1132
1133 /* Enable the DMA interface */
1134 temp = mci_readl(host, CTRL);
1135 temp |= SDMMC_CTRL_DMA_ENABLE;
1136 mci_writel(host, CTRL, temp);
1137
1138 /* Disable RX/TX IRQs, let DMA handle it */
1139 spin_lock_irqsave(&host->irq_lock, irqflags);
1140 temp = mci_readl(host, INTMASK);
1141 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1142 mci_writel(host, INTMASK, temp);
1143 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1144
1145 if (host->dma_ops->start(host, sg_len)) {
1146 host->dma_ops->stop(host);
1147 /* We can't do DMA, try PIO for this one */
1148 dev_dbg(host->dev,
1149 "%s: fall back to PIO mode for current transfer\n",
1150 __func__);
1151 return -ENODEV;
1152 }
1153
1154 return 0;
1155 }
1156
1157 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1158 {
1159 unsigned long irqflags;
1160 int flags = SG_MITER_ATOMIC;
1161 u32 temp;
1162
1163 data->error = -EINPROGRESS;
1164
1165 WARN_ON(host->data);
1166 host->sg = NULL;
1167 host->data = data;
1168
1169 if (data->flags & MMC_DATA_READ)
1170 host->dir_status = DW_MCI_RECV_STATUS;
1171 else
1172 host->dir_status = DW_MCI_SEND_STATUS;
1173
1174 dw_mci_ctrl_thld(host, data);
1175
1176 if (dw_mci_submit_data_dma(host, data)) {
1177 if (host->data->flags & MMC_DATA_READ)
1178 flags |= SG_MITER_TO_SG;
1179 else
1180 flags |= SG_MITER_FROM_SG;
1181
1182 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1183 host->sg = data->sg;
1184 host->part_buf_start = 0;
1185 host->part_buf_count = 0;
1186
1187 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1188
1189 spin_lock_irqsave(&host->irq_lock, irqflags);
1190 temp = mci_readl(host, INTMASK);
1191 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1192 mci_writel(host, INTMASK, temp);
1193 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1194
1195 temp = mci_readl(host, CTRL);
1196 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1197 mci_writel(host, CTRL, temp);
1198
1199 /*
1200 * Use the initial fifoth_val for PIO mode. If wm_algined
1201 * is set, we set watermark same as data size.
1202 * If next issued data may be transfered by DMA mode,
1203 * prev_blksz should be invalidated.
1204 */
1205 if (host->wm_aligned)
1206 dw_mci_adjust_fifoth(host, data);
1207 else
1208 mci_writel(host, FIFOTH, host->fifoth_val);
1209 host->prev_blksz = 0;
1210 } else {
1211 /*
1212 * Keep the current block size.
1213 * It will be used to decide whether to update
1214 * fifoth register next time.
1215 */
1216 host->prev_blksz = data->blksz;
1217 }
1218 }
1219
1220 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1221 {
1222 struct dw_mci *host = slot->host;
1223 unsigned int clock = slot->clock;
1224 u32 div;
1225 u32 clk_en_a;
1226 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1227
1228 /* We must continue to set bit 28 in CMD until the change is complete */
1229 if (host->state == STATE_WAITING_CMD11_DONE)
1230 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1231
1232 if (!clock) {
1233 mci_writel(host, CLKENA, 0);
1234 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1235 } else if (clock != host->current_speed || force_clkinit) {
1236 div = host->bus_hz / clock;
1237 if (host->bus_hz % clock && host->bus_hz > clock)
1238 /*
1239 * move the + 1 after the divide to prevent
1240 * over-clocking the card.
1241 */
1242 div += 1;
1243
1244 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1245
1246 if ((clock != slot->__clk_old &&
1247 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1248 force_clkinit) {
1249 /* Silent the verbose log if calling from PM context */
1250 if (!force_clkinit)
1251 dev_info(&slot->mmc->class_dev,
1252 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1253 slot->id, host->bus_hz, clock,
1254 div ? ((host->bus_hz / div) >> 1) :
1255 host->bus_hz, div);
1256
1257 /*
1258 * If card is polling, display the message only
1259 * one time at boot time.
1260 */
1261 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1262 slot->mmc->f_min == clock)
1263 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1264 }
1265
1266 /* disable clock */
1267 mci_writel(host, CLKENA, 0);
1268 mci_writel(host, CLKSRC, 0);
1269
1270 /* inform CIU */
1271 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1272
1273 /* set clock to desired speed */
1274 mci_writel(host, CLKDIV, div);
1275
1276 /* inform CIU */
1277 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1278
1279 /* enable clock; only low power if no SDIO */
1280 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1281 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1282 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1283 mci_writel(host, CLKENA, clk_en_a);
1284
1285 /* inform CIU */
1286 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1287
1288 /* keep the last clock value that was requested from core */
1289 slot->__clk_old = clock;
1290 }
1291
1292 host->current_speed = clock;
1293
1294 /* Set the current slot bus width */
1295 mci_writel(host, CTYPE, (slot->ctype << slot->id));
1296 }
1297
1298 static void __dw_mci_start_request(struct dw_mci *host,
1299 struct dw_mci_slot *slot,
1300 struct mmc_command *cmd)
1301 {
1302 struct mmc_request *mrq;
1303 struct mmc_data *data;
1304 u32 cmdflags;
1305
1306 mrq = slot->mrq;
1307
1308 host->mrq = mrq;
1309
1310 host->pending_events = 0;
1311 host->completed_events = 0;
1312 host->cmd_status = 0;
1313 host->data_status = 0;
1314 host->dir_status = 0;
1315
1316 data = cmd->data;
1317 if (data) {
1318 mci_writel(host, TMOUT, 0xFFFFFFFF);
1319 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1320 mci_writel(host, BLKSIZ, data->blksz);
1321 }
1322
1323 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1324
1325 /* this is the first command, send the initialization clock */
1326 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1327 cmdflags |= SDMMC_CMD_INIT;
1328
1329 if (data) {
1330 dw_mci_submit_data(host, data);
1331 wmb(); /* drain writebuffer */
1332 }
1333
1334 dw_mci_start_command(host, cmd, cmdflags);
1335
1336 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1337 unsigned long irqflags;
1338
1339 /*
1340 * Databook says to fail after 2ms w/ no response, but evidence
1341 * shows that sometimes the cmd11 interrupt takes over 130ms.
1342 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1343 * is just about to roll over.
1344 *
1345 * We do this whole thing under spinlock and only if the
1346 * command hasn't already completed (indicating the the irq
1347 * already ran so we don't want the timeout).
1348 */
1349 spin_lock_irqsave(&host->irq_lock, irqflags);
1350 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1351 mod_timer(&host->cmd11_timer,
1352 jiffies + msecs_to_jiffies(500) + 1);
1353 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1354 }
1355
1356 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1357 }
1358
1359 static void dw_mci_start_request(struct dw_mci *host,
1360 struct dw_mci_slot *slot)
1361 {
1362 struct mmc_request *mrq = slot->mrq;
1363 struct mmc_command *cmd;
1364
1365 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1366 __dw_mci_start_request(host, slot, cmd);
1367 }
1368
1369 /* must be called with host->lock held */
1370 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1371 struct mmc_request *mrq)
1372 {
1373 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1374 host->state);
1375
1376 slot->mrq = mrq;
1377
1378 if (host->state == STATE_WAITING_CMD11_DONE) {
1379 dev_warn(&slot->mmc->class_dev,
1380 "Voltage change didn't complete\n");
1381 /*
1382 * this case isn't expected to happen, so we can
1383 * either crash here or just try to continue on
1384 * in the closest possible state
1385 */
1386 host->state = STATE_IDLE;
1387 }
1388
1389 if (host->state == STATE_IDLE) {
1390 host->state = STATE_SENDING_CMD;
1391 dw_mci_start_request(host, slot);
1392 } else {
1393 list_add_tail(&slot->queue_node, &host->queue);
1394 }
1395 }
1396
1397 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1398 {
1399 struct dw_mci_slot *slot = mmc_priv(mmc);
1400 struct dw_mci *host = slot->host;
1401
1402 WARN_ON(slot->mrq);
1403
1404 /*
1405 * The check for card presence and queueing of the request must be
1406 * atomic, otherwise the card could be removed in between and the
1407 * request wouldn't fail until another card was inserted.
1408 */
1409
1410 if (!dw_mci_get_cd(mmc)) {
1411 mrq->cmd->error = -ENOMEDIUM;
1412 mmc_request_done(mmc, mrq);
1413 return;
1414 }
1415
1416 spin_lock_bh(&host->lock);
1417
1418 dw_mci_queue_request(host, slot, mrq);
1419
1420 spin_unlock_bh(&host->lock);
1421 }
1422
1423 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1424 {
1425 struct dw_mci_slot *slot = mmc_priv(mmc);
1426 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1427 u32 regs;
1428 int ret;
1429
1430 switch (ios->bus_width) {
1431 case MMC_BUS_WIDTH_4:
1432 slot->ctype = SDMMC_CTYPE_4BIT;
1433 break;
1434 case MMC_BUS_WIDTH_8:
1435 slot->ctype = SDMMC_CTYPE_8BIT;
1436 break;
1437 default:
1438 /* set default 1 bit mode */
1439 slot->ctype = SDMMC_CTYPE_1BIT;
1440 }
1441
1442 regs = mci_readl(slot->host, UHS_REG);
1443
1444 /* DDR mode set */
1445 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1446 ios->timing == MMC_TIMING_UHS_DDR50 ||
1447 ios->timing == MMC_TIMING_MMC_HS400)
1448 regs |= ((0x1 << slot->id) << 16);
1449 else
1450 regs &= ~((0x1 << slot->id) << 16);
1451
1452 mci_writel(slot->host, UHS_REG, regs);
1453 slot->host->timing = ios->timing;
1454
1455 /*
1456 * Use mirror of ios->clock to prevent race with mmc
1457 * core ios update when finding the minimum.
1458 */
1459 slot->clock = ios->clock;
1460
1461 if (drv_data && drv_data->set_ios)
1462 drv_data->set_ios(slot->host, ios);
1463
1464 switch (ios->power_mode) {
1465 case MMC_POWER_UP:
1466 if (!IS_ERR(mmc->supply.vmmc)) {
1467 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1468 ios->vdd);
1469 if (ret) {
1470 dev_err(slot->host->dev,
1471 "failed to enable vmmc regulator\n");
1472 /*return, if failed turn on vmmc*/
1473 return;
1474 }
1475 }
1476 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1477 regs = mci_readl(slot->host, PWREN);
1478 regs |= (1 << slot->id);
1479 mci_writel(slot->host, PWREN, regs);
1480 break;
1481 case MMC_POWER_ON:
1482 if (!slot->host->vqmmc_enabled) {
1483 if (!IS_ERR(mmc->supply.vqmmc)) {
1484 ret = regulator_enable(mmc->supply.vqmmc);
1485 if (ret < 0)
1486 dev_err(slot->host->dev,
1487 "failed to enable vqmmc\n");
1488 else
1489 slot->host->vqmmc_enabled = true;
1490
1491 } else {
1492 /* Keep track so we don't reset again */
1493 slot->host->vqmmc_enabled = true;
1494 }
1495
1496 /* Reset our state machine after powering on */
1497 dw_mci_ctrl_reset(slot->host,
1498 SDMMC_CTRL_ALL_RESET_FLAGS);
1499 }
1500
1501 /* Adjust clock / bus width after power is up */
1502 dw_mci_setup_bus(slot, false);
1503
1504 break;
1505 case MMC_POWER_OFF:
1506 /* Turn clock off before power goes down */
1507 dw_mci_setup_bus(slot, false);
1508
1509 if (!IS_ERR(mmc->supply.vmmc))
1510 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1511
1512 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1513 regulator_disable(mmc->supply.vqmmc);
1514 slot->host->vqmmc_enabled = false;
1515
1516 regs = mci_readl(slot->host, PWREN);
1517 regs &= ~(1 << slot->id);
1518 mci_writel(slot->host, PWREN, regs);
1519 break;
1520 default:
1521 break;
1522 }
1523
1524 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1525 slot->host->state = STATE_IDLE;
1526 }
1527
1528 static int dw_mci_card_busy(struct mmc_host *mmc)
1529 {
1530 struct dw_mci_slot *slot = mmc_priv(mmc);
1531 u32 status;
1532
1533 /*
1534 * Check the busy bit which is low when DAT[3:0]
1535 * (the data lines) are 0000
1536 */
1537 status = mci_readl(slot->host, STATUS);
1538
1539 return !!(status & SDMMC_STATUS_BUSY);
1540 }
1541
1542 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1543 {
1544 struct dw_mci_slot *slot = mmc_priv(mmc);
1545 struct dw_mci *host = slot->host;
1546 const struct dw_mci_drv_data *drv_data = host->drv_data;
1547 u32 uhs;
1548 u32 v18 = SDMMC_UHS_18V << slot->id;
1549 int ret;
1550
1551 if (drv_data && drv_data->switch_voltage)
1552 return drv_data->switch_voltage(mmc, ios);
1553
1554 /*
1555 * Program the voltage. Note that some instances of dw_mmc may use
1556 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1557 * does no harm but you need to set the regulator directly. Try both.
1558 */
1559 uhs = mci_readl(host, UHS_REG);
1560 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1561 uhs &= ~v18;
1562 else
1563 uhs |= v18;
1564
1565 if (!IS_ERR(mmc->supply.vqmmc)) {
1566 ret = mmc_regulator_set_vqmmc(mmc, ios);
1567
1568 if (ret) {
1569 dev_dbg(&mmc->class_dev,
1570 "Regulator set error %d - %s V\n",
1571 ret, uhs & v18 ? "1.8" : "3.3");
1572 return ret;
1573 }
1574 }
1575 mci_writel(host, UHS_REG, uhs);
1576
1577 return 0;
1578 }
1579
1580 static int dw_mci_get_ro(struct mmc_host *mmc)
1581 {
1582 int read_only;
1583 struct dw_mci_slot *slot = mmc_priv(mmc);
1584 int gpio_ro = mmc_gpio_get_ro(mmc);
1585
1586 /* Use platform get_ro function, else try on board write protect */
1587 if (gpio_ro >= 0)
1588 read_only = gpio_ro;
1589 else
1590 read_only =
1591 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1592
1593 dev_dbg(&mmc->class_dev, "card is %s\n",
1594 read_only ? "read-only" : "read-write");
1595
1596 return read_only;
1597 }
1598
1599 static void dw_mci_hw_reset(struct mmc_host *mmc)
1600 {
1601 struct dw_mci_slot *slot = mmc_priv(mmc);
1602 struct dw_mci *host = slot->host;
1603 int reset;
1604
1605 if (host->use_dma == TRANS_MODE_IDMAC)
1606 dw_mci_idmac_reset(host);
1607
1608 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1609 SDMMC_CTRL_FIFO_RESET))
1610 return;
1611
1612 /*
1613 * According to eMMC spec, card reset procedure:
1614 * tRstW >= 1us: RST_n pulse width
1615 * tRSCA >= 200us: RST_n to Command time
1616 * tRSTH >= 1us: RST_n high period
1617 */
1618 reset = mci_readl(host, RST_N);
1619 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1620 mci_writel(host, RST_N, reset);
1621 usleep_range(1, 2);
1622 reset |= SDMMC_RST_HWACTIVE << slot->id;
1623 mci_writel(host, RST_N, reset);
1624 usleep_range(200, 300);
1625 }
1626
1627 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1628 {
1629 struct dw_mci_slot *slot = mmc_priv(mmc);
1630 struct dw_mci *host = slot->host;
1631
1632 /*
1633 * Low power mode will stop the card clock when idle. According to the
1634 * description of the CLKENA register we should disable low power mode
1635 * for SDIO cards if we need SDIO interrupts to work.
1636 */
1637 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1638 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1639 u32 clk_en_a_old;
1640 u32 clk_en_a;
1641
1642 clk_en_a_old = mci_readl(host, CLKENA);
1643
1644 if (card->type == MMC_TYPE_SDIO ||
1645 card->type == MMC_TYPE_SD_COMBO) {
1646 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1647 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1648 } else {
1649 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1650 clk_en_a = clk_en_a_old | clken_low_pwr;
1651 }
1652
1653 if (clk_en_a != clk_en_a_old) {
1654 mci_writel(host, CLKENA, clk_en_a);
1655 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1656 SDMMC_CMD_PRV_DAT_WAIT, 0);
1657 }
1658 }
1659 }
1660
1661 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1662 {
1663 struct dw_mci *host = slot->host;
1664 unsigned long irqflags;
1665 u32 int_mask;
1666
1667 spin_lock_irqsave(&host->irq_lock, irqflags);
1668
1669 /* Enable/disable Slot Specific SDIO interrupt */
1670 int_mask = mci_readl(host, INTMASK);
1671 if (enb)
1672 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1673 else
1674 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1675 mci_writel(host, INTMASK, int_mask);
1676
1677 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1678 }
1679
1680 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1681 {
1682 struct dw_mci_slot *slot = mmc_priv(mmc);
1683 struct dw_mci *host = slot->host;
1684
1685 __dw_mci_enable_sdio_irq(slot, enb);
1686
1687 /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1688 if (enb)
1689 pm_runtime_get_noresume(host->dev);
1690 else
1691 pm_runtime_put_noidle(host->dev);
1692 }
1693
1694 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1695 {
1696 struct dw_mci_slot *slot = mmc_priv(mmc);
1697
1698 __dw_mci_enable_sdio_irq(slot, 1);
1699 }
1700
1701 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1702 {
1703 struct dw_mci_slot *slot = mmc_priv(mmc);
1704 struct dw_mci *host = slot->host;
1705 const struct dw_mci_drv_data *drv_data = host->drv_data;
1706 int err = -EINVAL;
1707
1708 if (drv_data && drv_data->execute_tuning)
1709 err = drv_data->execute_tuning(slot, opcode);
1710 return err;
1711 }
1712
1713 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1714 struct mmc_ios *ios)
1715 {
1716 struct dw_mci_slot *slot = mmc_priv(mmc);
1717 struct dw_mci *host = slot->host;
1718 const struct dw_mci_drv_data *drv_data = host->drv_data;
1719
1720 if (drv_data && drv_data->prepare_hs400_tuning)
1721 return drv_data->prepare_hs400_tuning(host, ios);
1722
1723 return 0;
1724 }
1725
1726 static bool dw_mci_reset(struct dw_mci *host)
1727 {
1728 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1729 bool ret = false;
1730 u32 status = 0;
1731
1732 /*
1733 * Resetting generates a block interrupt, hence setting
1734 * the scatter-gather pointer to NULL.
1735 */
1736 if (host->sg) {
1737 sg_miter_stop(&host->sg_miter);
1738 host->sg = NULL;
1739 }
1740
1741 if (host->use_dma)
1742 flags |= SDMMC_CTRL_DMA_RESET;
1743
1744 if (dw_mci_ctrl_reset(host, flags)) {
1745 /*
1746 * In all cases we clear the RAWINTS
1747 * register to clear any interrupts.
1748 */
1749 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1750
1751 if (!host->use_dma) {
1752 ret = true;
1753 goto ciu_out;
1754 }
1755
1756 /* Wait for dma_req to be cleared */
1757 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1758 status,
1759 !(status & SDMMC_STATUS_DMA_REQ),
1760 1, 500 * USEC_PER_MSEC)) {
1761 dev_err(host->dev,
1762 "%s: Timeout waiting for dma_req to be cleared\n",
1763 __func__);
1764 goto ciu_out;
1765 }
1766
1767 /* when using DMA next we reset the fifo again */
1768 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1769 goto ciu_out;
1770 } else {
1771 /* if the controller reset bit did clear, then set clock regs */
1772 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1773 dev_err(host->dev,
1774 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1775 __func__);
1776 goto ciu_out;
1777 }
1778 }
1779
1780 if (host->use_dma == TRANS_MODE_IDMAC)
1781 /* It is also recommended that we reset and reprogram idmac */
1782 dw_mci_idmac_reset(host);
1783
1784 ret = true;
1785
1786 ciu_out:
1787 /* After a CTRL reset we need to have CIU set clock registers */
1788 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1789
1790 return ret;
1791 }
1792
1793 static const struct mmc_host_ops dw_mci_ops = {
1794 .request = dw_mci_request,
1795 .pre_req = dw_mci_pre_req,
1796 .post_req = dw_mci_post_req,
1797 .set_ios = dw_mci_set_ios,
1798 .get_ro = dw_mci_get_ro,
1799 .get_cd = dw_mci_get_cd,
1800 .hw_reset = dw_mci_hw_reset,
1801 .enable_sdio_irq = dw_mci_enable_sdio_irq,
1802 .ack_sdio_irq = dw_mci_ack_sdio_irq,
1803 .execute_tuning = dw_mci_execute_tuning,
1804 .card_busy = dw_mci_card_busy,
1805 .start_signal_voltage_switch = dw_mci_switch_voltage,
1806 .init_card = dw_mci_init_card,
1807 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
1808 };
1809
1810 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1811 __releases(&host->lock)
1812 __acquires(&host->lock)
1813 {
1814 struct dw_mci_slot *slot;
1815 struct mmc_host *prev_mmc = host->slot->mmc;
1816
1817 WARN_ON(host->cmd || host->data);
1818
1819 host->slot->mrq = NULL;
1820 host->mrq = NULL;
1821 if (!list_empty(&host->queue)) {
1822 slot = list_entry(host->queue.next,
1823 struct dw_mci_slot, queue_node);
1824 list_del(&slot->queue_node);
1825 dev_vdbg(host->dev, "list not empty: %s is next\n",
1826 mmc_hostname(slot->mmc));
1827 host->state = STATE_SENDING_CMD;
1828 dw_mci_start_request(host, slot);
1829 } else {
1830 dev_vdbg(host->dev, "list empty\n");
1831
1832 if (host->state == STATE_SENDING_CMD11)
1833 host->state = STATE_WAITING_CMD11_DONE;
1834 else
1835 host->state = STATE_IDLE;
1836 }
1837
1838 spin_unlock(&host->lock);
1839 mmc_request_done(prev_mmc, mrq);
1840 spin_lock(&host->lock);
1841 }
1842
1843 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1844 {
1845 u32 status = host->cmd_status;
1846
1847 host->cmd_status = 0;
1848
1849 /* Read the response from the card (up to 16 bytes) */
1850 if (cmd->flags & MMC_RSP_PRESENT) {
1851 if (cmd->flags & MMC_RSP_136) {
1852 cmd->resp[3] = mci_readl(host, RESP0);
1853 cmd->resp[2] = mci_readl(host, RESP1);
1854 cmd->resp[1] = mci_readl(host, RESP2);
1855 cmd->resp[0] = mci_readl(host, RESP3);
1856 } else {
1857 cmd->resp[0] = mci_readl(host, RESP0);
1858 cmd->resp[1] = 0;
1859 cmd->resp[2] = 0;
1860 cmd->resp[3] = 0;
1861 }
1862 }
1863
1864 if (status & SDMMC_INT_RTO)
1865 cmd->error = -ETIMEDOUT;
1866 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1867 cmd->error = -EILSEQ;
1868 else if (status & SDMMC_INT_RESP_ERR)
1869 cmd->error = -EIO;
1870 else
1871 cmd->error = 0;
1872
1873 return cmd->error;
1874 }
1875
1876 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1877 {
1878 u32 status = host->data_status;
1879
1880 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1881 if (status & SDMMC_INT_DRTO) {
1882 data->error = -ETIMEDOUT;
1883 } else if (status & SDMMC_INT_DCRC) {
1884 data->error = -EILSEQ;
1885 } else if (status & SDMMC_INT_EBE) {
1886 if (host->dir_status ==
1887 DW_MCI_SEND_STATUS) {
1888 /*
1889 * No data CRC status was returned.
1890 * The number of bytes transferred
1891 * will be exaggerated in PIO mode.
1892 */
1893 data->bytes_xfered = 0;
1894 data->error = -ETIMEDOUT;
1895 } else if (host->dir_status ==
1896 DW_MCI_RECV_STATUS) {
1897 data->error = -EILSEQ;
1898 }
1899 } else {
1900 /* SDMMC_INT_SBE is included */
1901 data->error = -EILSEQ;
1902 }
1903
1904 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1905
1906 /*
1907 * After an error, there may be data lingering
1908 * in the FIFO
1909 */
1910 dw_mci_reset(host);
1911 } else {
1912 data->bytes_xfered = data->blocks * data->blksz;
1913 data->error = 0;
1914 }
1915
1916 return data->error;
1917 }
1918
1919 static void dw_mci_set_drto(struct dw_mci *host)
1920 {
1921 unsigned int drto_clks;
1922 unsigned int drto_ms;
1923
1924 drto_clks = mci_readl(host, TMOUT) >> 8;
1925 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1926
1927 /* add a bit spare time */
1928 drto_ms += 10;
1929
1930 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1931 }
1932
1933 static void dw_mci_tasklet_func(unsigned long priv)
1934 {
1935 struct dw_mci *host = (struct dw_mci *)priv;
1936 struct mmc_data *data;
1937 struct mmc_command *cmd;
1938 struct mmc_request *mrq;
1939 enum dw_mci_state state;
1940 enum dw_mci_state prev_state;
1941 unsigned int err;
1942
1943 spin_lock(&host->lock);
1944
1945 state = host->state;
1946 data = host->data;
1947 mrq = host->mrq;
1948
1949 do {
1950 prev_state = state;
1951
1952 switch (state) {
1953 case STATE_IDLE:
1954 case STATE_WAITING_CMD11_DONE:
1955 break;
1956
1957 case STATE_SENDING_CMD11:
1958 case STATE_SENDING_CMD:
1959 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1960 &host->pending_events))
1961 break;
1962
1963 cmd = host->cmd;
1964 host->cmd = NULL;
1965 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1966 err = dw_mci_command_complete(host, cmd);
1967 if (cmd == mrq->sbc && !err) {
1968 prev_state = state = STATE_SENDING_CMD;
1969 __dw_mci_start_request(host, host->slot,
1970 mrq->cmd);
1971 goto unlock;
1972 }
1973
1974 if (cmd->data && err) {
1975 /*
1976 * During UHS tuning sequence, sending the stop
1977 * command after the response CRC error would
1978 * throw the system into a confused state
1979 * causing all future tuning phases to report
1980 * failure.
1981 *
1982 * In such case controller will move into a data
1983 * transfer state after a response error or
1984 * response CRC error. Let's let that finish
1985 * before trying to send a stop, so we'll go to
1986 * STATE_SENDING_DATA.
1987 *
1988 * Although letting the data transfer take place
1989 * will waste a bit of time (we already know
1990 * the command was bad), it can't cause any
1991 * errors since it's possible it would have
1992 * taken place anyway if this tasklet got
1993 * delayed. Allowing the transfer to take place
1994 * avoids races and keeps things simple.
1995 */
1996 if ((err != -ETIMEDOUT) &&
1997 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1998 state = STATE_SENDING_DATA;
1999 continue;
2000 }
2001
2002 dw_mci_stop_dma(host);
2003 send_stop_abort(host, data);
2004 state = STATE_SENDING_STOP;
2005 break;
2006 }
2007
2008 if (!cmd->data || err) {
2009 dw_mci_request_end(host, mrq);
2010 goto unlock;
2011 }
2012
2013 prev_state = state = STATE_SENDING_DATA;
2014 /* fall through */
2015
2016 case STATE_SENDING_DATA:
2017 /*
2018 * We could get a data error and never a transfer
2019 * complete so we'd better check for it here.
2020 *
2021 * Note that we don't really care if we also got a
2022 * transfer complete; stopping the DMA and sending an
2023 * abort won't hurt.
2024 */
2025 if (test_and_clear_bit(EVENT_DATA_ERROR,
2026 &host->pending_events)) {
2027 dw_mci_stop_dma(host);
2028 if (!(host->data_status & (SDMMC_INT_DRTO |
2029 SDMMC_INT_EBE)))
2030 send_stop_abort(host, data);
2031 state = STATE_DATA_ERROR;
2032 break;
2033 }
2034
2035 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2036 &host->pending_events)) {
2037 /*
2038 * If all data-related interrupts don't come
2039 * within the given time in reading data state.
2040 */
2041 if (host->dir_status == DW_MCI_RECV_STATUS)
2042 dw_mci_set_drto(host);
2043 break;
2044 }
2045
2046 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2047
2048 /*
2049 * Handle an EVENT_DATA_ERROR that might have shown up
2050 * before the transfer completed. This might not have
2051 * been caught by the check above because the interrupt
2052 * could have gone off between the previous check and
2053 * the check for transfer complete.
2054 *
2055 * Technically this ought not be needed assuming we
2056 * get a DATA_COMPLETE eventually (we'll notice the
2057 * error and end the request), but it shouldn't hurt.
2058 *
2059 * This has the advantage of sending the stop command.
2060 */
2061 if (test_and_clear_bit(EVENT_DATA_ERROR,
2062 &host->pending_events)) {
2063 dw_mci_stop_dma(host);
2064 if (!(host->data_status & (SDMMC_INT_DRTO |
2065 SDMMC_INT_EBE)))
2066 send_stop_abort(host, data);
2067 state = STATE_DATA_ERROR;
2068 break;
2069 }
2070 prev_state = state = STATE_DATA_BUSY;
2071
2072 /* fall through */
2073
2074 case STATE_DATA_BUSY:
2075 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2076 &host->pending_events)) {
2077 /*
2078 * If data error interrupt comes but data over
2079 * interrupt doesn't come within the given time.
2080 * in reading data state.
2081 */
2082 if (host->dir_status == DW_MCI_RECV_STATUS)
2083 dw_mci_set_drto(host);
2084 break;
2085 }
2086
2087 host->data = NULL;
2088 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2089 err = dw_mci_data_complete(host, data);
2090
2091 if (!err) {
2092 if (!data->stop || mrq->sbc) {
2093 if (mrq->sbc && data->stop)
2094 data->stop->error = 0;
2095 dw_mci_request_end(host, mrq);
2096 goto unlock;
2097 }
2098
2099 /* stop command for open-ended transfer*/
2100 if (data->stop)
2101 send_stop_abort(host, data);
2102 } else {
2103 /*
2104 * If we don't have a command complete now we'll
2105 * never get one since we just reset everything;
2106 * better end the request.
2107 *
2108 * If we do have a command complete we'll fall
2109 * through to the SENDING_STOP command and
2110 * everything will be peachy keen.
2111 */
2112 if (!test_bit(EVENT_CMD_COMPLETE,
2113 &host->pending_events)) {
2114 host->cmd = NULL;
2115 dw_mci_request_end(host, mrq);
2116 goto unlock;
2117 }
2118 }
2119
2120 /*
2121 * If err has non-zero,
2122 * stop-abort command has been already issued.
2123 */
2124 prev_state = state = STATE_SENDING_STOP;
2125
2126 /* fall through */
2127
2128 case STATE_SENDING_STOP:
2129 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2130 &host->pending_events))
2131 break;
2132
2133 /* CMD error in data command */
2134 if (mrq->cmd->error && mrq->data)
2135 dw_mci_reset(host);
2136
2137 host->cmd = NULL;
2138 host->data = NULL;
2139
2140 if (!mrq->sbc && mrq->stop)
2141 dw_mci_command_complete(host, mrq->stop);
2142 else
2143 host->cmd_status = 0;
2144
2145 dw_mci_request_end(host, mrq);
2146 goto unlock;
2147
2148 case STATE_DATA_ERROR:
2149 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2150 &host->pending_events))
2151 break;
2152
2153 state = STATE_DATA_BUSY;
2154 break;
2155 }
2156 } while (state != prev_state);
2157
2158 host->state = state;
2159 unlock:
2160 spin_unlock(&host->lock);
2161
2162 }
2163
2164 /* push final bytes to part_buf, only use during push */
2165 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2166 {
2167 memcpy((void *)&host->part_buf, buf, cnt);
2168 host->part_buf_count = cnt;
2169 }
2170
2171 /* append bytes to part_buf, only use during push */
2172 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2173 {
2174 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2175 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2176 host->part_buf_count += cnt;
2177 return cnt;
2178 }
2179
2180 /* pull first bytes from part_buf, only use during pull */
2181 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2182 {
2183 cnt = min_t(int, cnt, host->part_buf_count);
2184 if (cnt) {
2185 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2186 cnt);
2187 host->part_buf_count -= cnt;
2188 host->part_buf_start += cnt;
2189 }
2190 return cnt;
2191 }
2192
2193 /* pull final bytes from the part_buf, assuming it's just been filled */
2194 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2195 {
2196 memcpy(buf, &host->part_buf, cnt);
2197 host->part_buf_start = cnt;
2198 host->part_buf_count = (1 << host->data_shift) - cnt;
2199 }
2200
2201 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2202 {
2203 struct mmc_data *data = host->data;
2204 int init_cnt = cnt;
2205
2206 /* try and push anything in the part_buf */
2207 if (unlikely(host->part_buf_count)) {
2208 int len = dw_mci_push_part_bytes(host, buf, cnt);
2209
2210 buf += len;
2211 cnt -= len;
2212 if (host->part_buf_count == 2) {
2213 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2214 host->part_buf_count = 0;
2215 }
2216 }
2217 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2218 if (unlikely((unsigned long)buf & 0x1)) {
2219 while (cnt >= 2) {
2220 u16 aligned_buf[64];
2221 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2222 int items = len >> 1;
2223 int i;
2224 /* memcpy from input buffer into aligned buffer */
2225 memcpy(aligned_buf, buf, len);
2226 buf += len;
2227 cnt -= len;
2228 /* push data from aligned buffer into fifo */
2229 for (i = 0; i < items; ++i)
2230 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2231 }
2232 } else
2233 #endif
2234 {
2235 u16 *pdata = buf;
2236
2237 for (; cnt >= 2; cnt -= 2)
2238 mci_fifo_writew(host->fifo_reg, *pdata++);
2239 buf = pdata;
2240 }
2241 /* put anything remaining in the part_buf */
2242 if (cnt) {
2243 dw_mci_set_part_bytes(host, buf, cnt);
2244 /* Push data if we have reached the expected data length */
2245 if ((data->bytes_xfered + init_cnt) ==
2246 (data->blksz * data->blocks))
2247 mci_fifo_writew(host->fifo_reg, host->part_buf16);
2248 }
2249 }
2250
2251 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2252 {
2253 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2254 if (unlikely((unsigned long)buf & 0x1)) {
2255 while (cnt >= 2) {
2256 /* pull data from fifo into aligned buffer */
2257 u16 aligned_buf[64];
2258 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2259 int items = len >> 1;
2260 int i;
2261
2262 for (i = 0; i < items; ++i)
2263 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2264 /* memcpy from aligned buffer into output buffer */
2265 memcpy(buf, aligned_buf, len);
2266 buf += len;
2267 cnt -= len;
2268 }
2269 } else
2270 #endif
2271 {
2272 u16 *pdata = buf;
2273
2274 for (; cnt >= 2; cnt -= 2)
2275 *pdata++ = mci_fifo_readw(host->fifo_reg);
2276 buf = pdata;
2277 }
2278 if (cnt) {
2279 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2280 dw_mci_pull_final_bytes(host, buf, cnt);
2281 }
2282 }
2283
2284 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2285 {
2286 struct mmc_data *data = host->data;
2287 int init_cnt = cnt;
2288
2289 /* try and push anything in the part_buf */
2290 if (unlikely(host->part_buf_count)) {
2291 int len = dw_mci_push_part_bytes(host, buf, cnt);
2292
2293 buf += len;
2294 cnt -= len;
2295 if (host->part_buf_count == 4) {
2296 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2297 host->part_buf_count = 0;
2298 }
2299 }
2300 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2301 if (unlikely((unsigned long)buf & 0x3)) {
2302 while (cnt >= 4) {
2303 u32 aligned_buf[32];
2304 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2305 int items = len >> 2;
2306 int i;
2307 /* memcpy from input buffer into aligned buffer */
2308 memcpy(aligned_buf, buf, len);
2309 buf += len;
2310 cnt -= len;
2311 /* push data from aligned buffer into fifo */
2312 for (i = 0; i < items; ++i)
2313 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2314 }
2315 } else
2316 #endif
2317 {
2318 u32 *pdata = buf;
2319
2320 for (; cnt >= 4; cnt -= 4)
2321 mci_fifo_writel(host->fifo_reg, *pdata++);
2322 buf = pdata;
2323 }
2324 /* put anything remaining in the part_buf */
2325 if (cnt) {
2326 dw_mci_set_part_bytes(host, buf, cnt);
2327 /* Push data if we have reached the expected data length */
2328 if ((data->bytes_xfered + init_cnt) ==
2329 (data->blksz * data->blocks))
2330 mci_fifo_writel(host->fifo_reg, host->part_buf32);
2331 }
2332 }
2333
2334 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2335 {
2336 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2337 if (unlikely((unsigned long)buf & 0x3)) {
2338 while (cnt >= 4) {
2339 /* pull data from fifo into aligned buffer */
2340 u32 aligned_buf[32];
2341 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2342 int items = len >> 2;
2343 int i;
2344
2345 for (i = 0; i < items; ++i)
2346 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2347 /* memcpy from aligned buffer into output buffer */
2348 memcpy(buf, aligned_buf, len);
2349 buf += len;
2350 cnt -= len;
2351 }
2352 } else
2353 #endif
2354 {
2355 u32 *pdata = buf;
2356
2357 for (; cnt >= 4; cnt -= 4)
2358 *pdata++ = mci_fifo_readl(host->fifo_reg);
2359 buf = pdata;
2360 }
2361 if (cnt) {
2362 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2363 dw_mci_pull_final_bytes(host, buf, cnt);
2364 }
2365 }
2366
2367 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2368 {
2369 struct mmc_data *data = host->data;
2370 int init_cnt = cnt;
2371
2372 /* try and push anything in the part_buf */
2373 if (unlikely(host->part_buf_count)) {
2374 int len = dw_mci_push_part_bytes(host, buf, cnt);
2375
2376 buf += len;
2377 cnt -= len;
2378
2379 if (host->part_buf_count == 8) {
2380 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2381 host->part_buf_count = 0;
2382 }
2383 }
2384 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2385 if (unlikely((unsigned long)buf & 0x7)) {
2386 while (cnt >= 8) {
2387 u64 aligned_buf[16];
2388 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2389 int items = len >> 3;
2390 int i;
2391 /* memcpy from input buffer into aligned buffer */
2392 memcpy(aligned_buf, buf, len);
2393 buf += len;
2394 cnt -= len;
2395 /* push data from aligned buffer into fifo */
2396 for (i = 0; i < items; ++i)
2397 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2398 }
2399 } else
2400 #endif
2401 {
2402 u64 *pdata = buf;
2403
2404 for (; cnt >= 8; cnt -= 8)
2405 mci_fifo_writeq(host->fifo_reg, *pdata++);
2406 buf = pdata;
2407 }
2408 /* put anything remaining in the part_buf */
2409 if (cnt) {
2410 dw_mci_set_part_bytes(host, buf, cnt);
2411 /* Push data if we have reached the expected data length */
2412 if ((data->bytes_xfered + init_cnt) ==
2413 (data->blksz * data->blocks))
2414 mci_fifo_writeq(host->fifo_reg, host->part_buf);
2415 }
2416 }
2417
2418 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2419 {
2420 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2421 if (unlikely((unsigned long)buf & 0x7)) {
2422 while (cnt >= 8) {
2423 /* pull data from fifo into aligned buffer */
2424 u64 aligned_buf[16];
2425 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2426 int items = len >> 3;
2427 int i;
2428
2429 for (i = 0; i < items; ++i)
2430 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2431
2432 /* memcpy from aligned buffer into output buffer */
2433 memcpy(buf, aligned_buf, len);
2434 buf += len;
2435 cnt -= len;
2436 }
2437 } else
2438 #endif
2439 {
2440 u64 *pdata = buf;
2441
2442 for (; cnt >= 8; cnt -= 8)
2443 *pdata++ = mci_fifo_readq(host->fifo_reg);
2444 buf = pdata;
2445 }
2446 if (cnt) {
2447 host->part_buf = mci_fifo_readq(host->fifo_reg);
2448 dw_mci_pull_final_bytes(host, buf, cnt);
2449 }
2450 }
2451
2452 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2453 {
2454 int len;
2455
2456 /* get remaining partial bytes */
2457 len = dw_mci_pull_part_bytes(host, buf, cnt);
2458 if (unlikely(len == cnt))
2459 return;
2460 buf += len;
2461 cnt -= len;
2462
2463 /* get the rest of the data */
2464 host->pull_data(host, buf, cnt);
2465 }
2466
2467 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2468 {
2469 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2470 void *buf;
2471 unsigned int offset;
2472 struct mmc_data *data = host->data;
2473 int shift = host->data_shift;
2474 u32 status;
2475 unsigned int len;
2476 unsigned int remain, fcnt;
2477
2478 do {
2479 if (!sg_miter_next(sg_miter))
2480 goto done;
2481
2482 host->sg = sg_miter->piter.sg;
2483 buf = sg_miter->addr;
2484 remain = sg_miter->length;
2485 offset = 0;
2486
2487 do {
2488 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2489 << shift) + host->part_buf_count;
2490 len = min(remain, fcnt);
2491 if (!len)
2492 break;
2493 dw_mci_pull_data(host, (void *)(buf + offset), len);
2494 data->bytes_xfered += len;
2495 offset += len;
2496 remain -= len;
2497 } while (remain);
2498
2499 sg_miter->consumed = offset;
2500 status = mci_readl(host, MINTSTS);
2501 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2502 /* if the RXDR is ready read again */
2503 } while ((status & SDMMC_INT_RXDR) ||
2504 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2505
2506 if (!remain) {
2507 if (!sg_miter_next(sg_miter))
2508 goto done;
2509 sg_miter->consumed = 0;
2510 }
2511 sg_miter_stop(sg_miter);
2512 return;
2513
2514 done:
2515 sg_miter_stop(sg_miter);
2516 host->sg = NULL;
2517 smp_wmb(); /* drain writebuffer */
2518 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2519 }
2520
2521 static void dw_mci_write_data_pio(struct dw_mci *host)
2522 {
2523 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2524 void *buf;
2525 unsigned int offset;
2526 struct mmc_data *data = host->data;
2527 int shift = host->data_shift;
2528 u32 status;
2529 unsigned int len;
2530 unsigned int fifo_depth = host->fifo_depth;
2531 unsigned int remain, fcnt;
2532
2533 do {
2534 if (!sg_miter_next(sg_miter))
2535 goto done;
2536
2537 host->sg = sg_miter->piter.sg;
2538 buf = sg_miter->addr;
2539 remain = sg_miter->length;
2540 offset = 0;
2541
2542 do {
2543 fcnt = ((fifo_depth -
2544 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2545 << shift) - host->part_buf_count;
2546 len = min(remain, fcnt);
2547 if (!len)
2548 break;
2549 host->push_data(host, (void *)(buf + offset), len);
2550 data->bytes_xfered += len;
2551 offset += len;
2552 remain -= len;
2553 } while (remain);
2554
2555 sg_miter->consumed = offset;
2556 status = mci_readl(host, MINTSTS);
2557 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2558 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2559
2560 if (!remain) {
2561 if (!sg_miter_next(sg_miter))
2562 goto done;
2563 sg_miter->consumed = 0;
2564 }
2565 sg_miter_stop(sg_miter);
2566 return;
2567
2568 done:
2569 sg_miter_stop(sg_miter);
2570 host->sg = NULL;
2571 smp_wmb(); /* drain writebuffer */
2572 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2573 }
2574
2575 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2576 {
2577 del_timer(&host->cto_timer);
2578
2579 if (!host->cmd_status)
2580 host->cmd_status = status;
2581
2582 smp_wmb(); /* drain writebuffer */
2583
2584 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2585 tasklet_schedule(&host->tasklet);
2586 }
2587
2588 static void dw_mci_handle_cd(struct dw_mci *host)
2589 {
2590 struct dw_mci_slot *slot = host->slot;
2591
2592 if (slot->mmc->ops->card_event)
2593 slot->mmc->ops->card_event(slot->mmc);
2594 mmc_detect_change(slot->mmc,
2595 msecs_to_jiffies(host->pdata->detect_delay_ms));
2596 }
2597
2598 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2599 {
2600 struct dw_mci *host = dev_id;
2601 u32 pending;
2602 struct dw_mci_slot *slot = host->slot;
2603
2604 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2605
2606 if (pending) {
2607 /* Check volt switch first, since it can look like an error */
2608 if ((host->state == STATE_SENDING_CMD11) &&
2609 (pending & SDMMC_INT_VOLT_SWITCH)) {
2610 unsigned long irqflags;
2611
2612 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2613 pending &= ~SDMMC_INT_VOLT_SWITCH;
2614
2615 /*
2616 * Hold the lock; we know cmd11_timer can't be kicked
2617 * off after the lock is released, so safe to delete.
2618 */
2619 spin_lock_irqsave(&host->irq_lock, irqflags);
2620 dw_mci_cmd_interrupt(host, pending);
2621 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2622
2623 del_timer(&host->cmd11_timer);
2624 }
2625
2626 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2627 del_timer(&host->cto_timer);
2628 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2629 host->cmd_status = pending;
2630 smp_wmb(); /* drain writebuffer */
2631 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2632 }
2633
2634 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2635 /* if there is an error report DATA_ERROR */
2636 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2637 host->data_status = pending;
2638 smp_wmb(); /* drain writebuffer */
2639 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2640 tasklet_schedule(&host->tasklet);
2641 }
2642
2643 if (pending & SDMMC_INT_DATA_OVER) {
2644 del_timer(&host->dto_timer);
2645
2646 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2647 if (!host->data_status)
2648 host->data_status = pending;
2649 smp_wmb(); /* drain writebuffer */
2650 if (host->dir_status == DW_MCI_RECV_STATUS) {
2651 if (host->sg != NULL)
2652 dw_mci_read_data_pio(host, true);
2653 }
2654 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2655 tasklet_schedule(&host->tasklet);
2656 }
2657
2658 if (pending & SDMMC_INT_RXDR) {
2659 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2660 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2661 dw_mci_read_data_pio(host, false);
2662 }
2663
2664 if (pending & SDMMC_INT_TXDR) {
2665 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2666 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2667 dw_mci_write_data_pio(host);
2668 }
2669
2670 if (pending & SDMMC_INT_CMD_DONE) {
2671 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2672 dw_mci_cmd_interrupt(host, pending);
2673 }
2674
2675 if (pending & SDMMC_INT_CD) {
2676 mci_writel(host, RINTSTS, SDMMC_INT_CD);
2677 dw_mci_handle_cd(host);
2678 }
2679
2680 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2681 mci_writel(host, RINTSTS,
2682 SDMMC_INT_SDIO(slot->sdio_id));
2683 __dw_mci_enable_sdio_irq(slot, 0);
2684 sdio_signal_irq(slot->mmc);
2685 }
2686
2687 }
2688
2689 if (host->use_dma != TRANS_MODE_IDMAC)
2690 return IRQ_HANDLED;
2691
2692 /* Handle IDMA interrupts */
2693 if (host->dma_64bit_address == 1) {
2694 pending = mci_readl(host, IDSTS64);
2695 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2696 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2697 SDMMC_IDMAC_INT_RI);
2698 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2699 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2700 host->dma_ops->complete((void *)host);
2701 }
2702 } else {
2703 pending = mci_readl(host, IDSTS);
2704 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2705 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2706 SDMMC_IDMAC_INT_RI);
2707 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2708 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2709 host->dma_ops->complete((void *)host);
2710 }
2711 }
2712
2713 return IRQ_HANDLED;
2714 }
2715
2716 static int dw_mci_init_slot(struct dw_mci *host)
2717 {
2718 struct mmc_host *mmc;
2719 struct dw_mci_slot *slot;
2720 const struct dw_mci_drv_data *drv_data = host->drv_data;
2721 int ctrl_id, ret;
2722 u32 freq[2];
2723
2724 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2725 if (!mmc)
2726 return -ENOMEM;
2727
2728 slot = mmc_priv(mmc);
2729 slot->id = 0;
2730 slot->sdio_id = host->sdio_id0 + slot->id;
2731 slot->mmc = mmc;
2732 slot->host = host;
2733 host->slot = slot;
2734
2735 mmc->ops = &dw_mci_ops;
2736 if (device_property_read_u32_array(host->dev, "clock-freq-min-max",
2737 freq, 2)) {
2738 mmc->f_min = DW_MCI_FREQ_MIN;
2739 mmc->f_max = DW_MCI_FREQ_MAX;
2740 } else {
2741 dev_info(host->dev,
2742 "'clock-freq-min-max' property was deprecated.\n");
2743 mmc->f_min = freq[0];
2744 mmc->f_max = freq[1];
2745 }
2746
2747 /*if there are external regulators, get them*/
2748 ret = mmc_regulator_get_supply(mmc);
2749 if (ret == -EPROBE_DEFER)
2750 goto err_host_allocated;
2751
2752 if (!mmc->ocr_avail)
2753 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2754
2755 if (host->pdata->caps)
2756 mmc->caps = host->pdata->caps;
2757
2758 /*
2759 * Support MMC_CAP_ERASE by default.
2760 * It needs to use trim/discard/erase commands.
2761 */
2762 mmc->caps |= MMC_CAP_ERASE;
2763
2764 if (host->pdata->pm_caps)
2765 mmc->pm_caps = host->pdata->pm_caps;
2766
2767 if (host->dev->of_node) {
2768 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2769 if (ctrl_id < 0)
2770 ctrl_id = 0;
2771 } else {
2772 ctrl_id = to_platform_device(host->dev)->id;
2773 }
2774 if (drv_data && drv_data->caps)
2775 mmc->caps |= drv_data->caps[ctrl_id];
2776
2777 if (host->pdata->caps2)
2778 mmc->caps2 = host->pdata->caps2;
2779
2780 ret = mmc_of_parse(mmc);
2781 if (ret)
2782 goto err_host_allocated;
2783
2784 /* Process SDIO IRQs through the sdio_irq_work. */
2785 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2786 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2787
2788 /* Useful defaults if platform data is unset. */
2789 if (host->use_dma == TRANS_MODE_IDMAC) {
2790 mmc->max_segs = host->ring_size;
2791 mmc->max_blk_size = 65535;
2792 mmc->max_seg_size = 0x1000;
2793 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2794 mmc->max_blk_count = mmc->max_req_size / 512;
2795 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2796 mmc->max_segs = 64;
2797 mmc->max_blk_size = 65535;
2798 mmc->max_blk_count = 65535;
2799 mmc->max_req_size =
2800 mmc->max_blk_size * mmc->max_blk_count;
2801 mmc->max_seg_size = mmc->max_req_size;
2802 } else {
2803 /* TRANS_MODE_PIO */
2804 mmc->max_segs = 64;
2805 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2806 mmc->max_blk_count = 512;
2807 mmc->max_req_size = mmc->max_blk_size *
2808 mmc->max_blk_count;
2809 mmc->max_seg_size = mmc->max_req_size;
2810 }
2811
2812 dw_mci_get_cd(mmc);
2813
2814 ret = mmc_add_host(mmc);
2815 if (ret)
2816 goto err_host_allocated;
2817
2818 #if defined(CONFIG_DEBUG_FS)
2819 dw_mci_init_debugfs(slot);
2820 #endif
2821
2822 return 0;
2823
2824 err_host_allocated:
2825 mmc_free_host(mmc);
2826 return ret;
2827 }
2828
2829 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
2830 {
2831 /* Debugfs stuff is cleaned up by mmc core */
2832 mmc_remove_host(slot->mmc);
2833 slot->host->slot = NULL;
2834 mmc_free_host(slot->mmc);
2835 }
2836
2837 static void dw_mci_init_dma(struct dw_mci *host)
2838 {
2839 int addr_config;
2840 struct device *dev = host->dev;
2841
2842 /*
2843 * Check tansfer mode from HCON[17:16]
2844 * Clear the ambiguous description of dw_mmc databook:
2845 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2846 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2847 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2848 * 2b'11: Non DW DMA Interface -> pio only
2849 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2850 * simpler request/acknowledge handshake mechanism and both of them
2851 * are regarded as external dma master for dw_mmc.
2852 */
2853 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2854 if (host->use_dma == DMA_INTERFACE_IDMA) {
2855 host->use_dma = TRANS_MODE_IDMAC;
2856 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2857 host->use_dma == DMA_INTERFACE_GDMA) {
2858 host->use_dma = TRANS_MODE_EDMAC;
2859 } else {
2860 goto no_dma;
2861 }
2862
2863 /* Determine which DMA interface to use */
2864 if (host->use_dma == TRANS_MODE_IDMAC) {
2865 /*
2866 * Check ADDR_CONFIG bit in HCON to find
2867 * IDMAC address bus width
2868 */
2869 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2870
2871 if (addr_config == 1) {
2872 /* host supports IDMAC in 64-bit address mode */
2873 host->dma_64bit_address = 1;
2874 dev_info(host->dev,
2875 "IDMAC supports 64-bit address mode.\n");
2876 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2877 dma_set_coherent_mask(host->dev,
2878 DMA_BIT_MASK(64));
2879 } else {
2880 /* host supports IDMAC in 32-bit address mode */
2881 host->dma_64bit_address = 0;
2882 dev_info(host->dev,
2883 "IDMAC supports 32-bit address mode.\n");
2884 }
2885
2886 /* Alloc memory for sg translation */
2887 host->sg_cpu = dmam_alloc_coherent(host->dev,
2888 DESC_RING_BUF_SZ,
2889 &host->sg_dma, GFP_KERNEL);
2890 if (!host->sg_cpu) {
2891 dev_err(host->dev,
2892 "%s: could not alloc DMA memory\n",
2893 __func__);
2894 goto no_dma;
2895 }
2896
2897 host->dma_ops = &dw_mci_idmac_ops;
2898 dev_info(host->dev, "Using internal DMA controller.\n");
2899 } else {
2900 /* TRANS_MODE_EDMAC: check dma bindings again */
2901 if ((device_property_read_string_array(dev, "dma-names",
2902 NULL, 0) < 0) ||
2903 !device_property_present(dev, "dmas")) {
2904 goto no_dma;
2905 }
2906 host->dma_ops = &dw_mci_edmac_ops;
2907 dev_info(host->dev, "Using external DMA controller.\n");
2908 }
2909
2910 if (host->dma_ops->init && host->dma_ops->start &&
2911 host->dma_ops->stop && host->dma_ops->cleanup) {
2912 if (host->dma_ops->init(host)) {
2913 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2914 __func__);
2915 goto no_dma;
2916 }
2917 } else {
2918 dev_err(host->dev, "DMA initialization not found.\n");
2919 goto no_dma;
2920 }
2921
2922 return;
2923
2924 no_dma:
2925 dev_info(host->dev, "Using PIO mode.\n");
2926 host->use_dma = TRANS_MODE_PIO;
2927 }
2928
2929 static void dw_mci_cmd11_timer(unsigned long arg)
2930 {
2931 struct dw_mci *host = (struct dw_mci *)arg;
2932
2933 if (host->state != STATE_SENDING_CMD11) {
2934 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2935 return;
2936 }
2937
2938 host->cmd_status = SDMMC_INT_RTO;
2939 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2940 tasklet_schedule(&host->tasklet);
2941 }
2942
2943 static void dw_mci_cto_timer(unsigned long arg)
2944 {
2945 struct dw_mci *host = (struct dw_mci *)arg;
2946
2947 switch (host->state) {
2948 case STATE_SENDING_CMD11:
2949 case STATE_SENDING_CMD:
2950 case STATE_SENDING_STOP:
2951 /*
2952 * If CMD_DONE interrupt does NOT come in sending command
2953 * state, we should notify the driver to terminate current
2954 * transfer and report a command timeout to the core.
2955 */
2956 host->cmd_status = SDMMC_INT_RTO;
2957 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2958 tasklet_schedule(&host->tasklet);
2959 break;
2960 default:
2961 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
2962 host->state);
2963 break;
2964 }
2965 }
2966
2967 static void dw_mci_dto_timer(unsigned long arg)
2968 {
2969 struct dw_mci *host = (struct dw_mci *)arg;
2970
2971 switch (host->state) {
2972 case STATE_SENDING_DATA:
2973 case STATE_DATA_BUSY:
2974 /*
2975 * If DTO interrupt does NOT come in sending data state,
2976 * we should notify the driver to terminate current transfer
2977 * and report a data timeout to the core.
2978 */
2979 host->data_status = SDMMC_INT_DRTO;
2980 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2981 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2982 tasklet_schedule(&host->tasklet);
2983 break;
2984 default:
2985 break;
2986 }
2987 }
2988
2989 #ifdef CONFIG_OF
2990 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2991 {
2992 struct dw_mci_board *pdata;
2993 struct device *dev = host->dev;
2994 const struct dw_mci_drv_data *drv_data = host->drv_data;
2995 int ret;
2996 u32 clock_frequency;
2997
2998 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2999 if (!pdata)
3000 return ERR_PTR(-ENOMEM);
3001
3002 /* find reset controller when exist */
3003 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
3004 if (IS_ERR(pdata->rstc)) {
3005 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
3006 return ERR_PTR(-EPROBE_DEFER);
3007 }
3008
3009 /* find out number of slots supported */
3010 if (!device_property_read_u32(dev, "num-slots", &pdata->num_slots))
3011 dev_info(dev, "'num-slots' was deprecated.\n");
3012
3013 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
3014 dev_info(dev,
3015 "fifo-depth property not found, using value of FIFOTH register as default\n");
3016
3017 device_property_read_u32(dev, "card-detect-delay",
3018 &pdata->detect_delay_ms);
3019
3020 device_property_read_u32(dev, "data-addr", &host->data_addr_override);
3021
3022 if (device_property_present(dev, "fifo-watermark-aligned"))
3023 host->wm_aligned = true;
3024
3025 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3026 pdata->bus_hz = clock_frequency;
3027
3028 if (drv_data && drv_data->parse_dt) {
3029 ret = drv_data->parse_dt(host);
3030 if (ret)
3031 return ERR_PTR(ret);
3032 }
3033
3034 return pdata;
3035 }
3036
3037 #else /* CONFIG_OF */
3038 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3039 {
3040 return ERR_PTR(-EINVAL);
3041 }
3042 #endif /* CONFIG_OF */
3043
3044 static void dw_mci_enable_cd(struct dw_mci *host)
3045 {
3046 unsigned long irqflags;
3047 u32 temp;
3048
3049 /*
3050 * No need for CD if all slots have a non-error GPIO
3051 * as well as broken card detection is found.
3052 */
3053 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3054 return;
3055
3056 if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
3057 spin_lock_irqsave(&host->irq_lock, irqflags);
3058 temp = mci_readl(host, INTMASK);
3059 temp |= SDMMC_INT_CD;
3060 mci_writel(host, INTMASK, temp);
3061 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3062 }
3063 }
3064
3065 int dw_mci_probe(struct dw_mci *host)
3066 {
3067 const struct dw_mci_drv_data *drv_data = host->drv_data;
3068 int width, i, ret = 0;
3069 u32 fifo_size;
3070
3071 if (!host->pdata) {
3072 host->pdata = dw_mci_parse_dt(host);
3073 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3074 return -EPROBE_DEFER;
3075 } else if (IS_ERR(host->pdata)) {
3076 dev_err(host->dev, "platform data not available\n");
3077 return -EINVAL;
3078 }
3079 }
3080
3081 host->biu_clk = devm_clk_get(host->dev, "biu");
3082 if (IS_ERR(host->biu_clk)) {
3083 dev_dbg(host->dev, "biu clock not available\n");
3084 } else {
3085 ret = clk_prepare_enable(host->biu_clk);
3086 if (ret) {
3087 dev_err(host->dev, "failed to enable biu clock\n");
3088 return ret;
3089 }
3090 }
3091
3092 host->ciu_clk = devm_clk_get(host->dev, "ciu");
3093 if (IS_ERR(host->ciu_clk)) {
3094 dev_dbg(host->dev, "ciu clock not available\n");
3095 host->bus_hz = host->pdata->bus_hz;
3096 } else {
3097 ret = clk_prepare_enable(host->ciu_clk);
3098 if (ret) {
3099 dev_err(host->dev, "failed to enable ciu clock\n");
3100 goto err_clk_biu;
3101 }
3102
3103 if (host->pdata->bus_hz) {
3104 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3105 if (ret)
3106 dev_warn(host->dev,
3107 "Unable to set bus rate to %uHz\n",
3108 host->pdata->bus_hz);
3109 }
3110 host->bus_hz = clk_get_rate(host->ciu_clk);
3111 }
3112
3113 if (!host->bus_hz) {
3114 dev_err(host->dev,
3115 "Platform data must supply bus speed\n");
3116 ret = -ENODEV;
3117 goto err_clk_ciu;
3118 }
3119
3120 if (!IS_ERR(host->pdata->rstc)) {
3121 reset_control_assert(host->pdata->rstc);
3122 usleep_range(10, 50);
3123 reset_control_deassert(host->pdata->rstc);
3124 }
3125
3126 if (drv_data && drv_data->init) {
3127 ret = drv_data->init(host);
3128 if (ret) {
3129 dev_err(host->dev,
3130 "implementation specific init failed\n");
3131 goto err_clk_ciu;
3132 }
3133 }
3134
3135 setup_timer(&host->cmd11_timer,
3136 dw_mci_cmd11_timer, (unsigned long)host);
3137
3138 setup_timer(&host->cto_timer,
3139 dw_mci_cto_timer, (unsigned long)host);
3140
3141 setup_timer(&host->dto_timer,
3142 dw_mci_dto_timer, (unsigned long)host);
3143
3144 spin_lock_init(&host->lock);
3145 spin_lock_init(&host->irq_lock);
3146 INIT_LIST_HEAD(&host->queue);
3147
3148 /*
3149 * Get the host data width - this assumes that HCON has been set with
3150 * the correct values.
3151 */
3152 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3153 if (!i) {
3154 host->push_data = dw_mci_push_data16;
3155 host->pull_data = dw_mci_pull_data16;
3156 width = 16;
3157 host->data_shift = 1;
3158 } else if (i == 2) {
3159 host->push_data = dw_mci_push_data64;
3160 host->pull_data = dw_mci_pull_data64;
3161 width = 64;
3162 host->data_shift = 3;
3163 } else {
3164 /* Check for a reserved value, and warn if it is */
3165 WARN((i != 1),
3166 "HCON reports a reserved host data width!\n"
3167 "Defaulting to 32-bit access.\n");
3168 host->push_data = dw_mci_push_data32;
3169 host->pull_data = dw_mci_pull_data32;
3170 width = 32;
3171 host->data_shift = 2;
3172 }
3173
3174 /* Reset all blocks */
3175 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3176 ret = -ENODEV;
3177 goto err_clk_ciu;
3178 }
3179
3180 host->dma_ops = host->pdata->dma_ops;
3181 dw_mci_init_dma(host);
3182
3183 /* Clear the interrupts for the host controller */
3184 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3185 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3186
3187 /* Put in max timeout */
3188 mci_writel(host, TMOUT, 0xFFFFFFFF);
3189
3190 /*
3191 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3192 * Tx Mark = fifo_size / 2 DMA Size = 8
3193 */
3194 if (!host->pdata->fifo_depth) {
3195 /*
3196 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3197 * have been overwritten by the bootloader, just like we're
3198 * about to do, so if you know the value for your hardware, you
3199 * should put it in the platform data.
3200 */
3201 fifo_size = mci_readl(host, FIFOTH);
3202 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3203 } else {
3204 fifo_size = host->pdata->fifo_depth;
3205 }
3206 host->fifo_depth = fifo_size;
3207 host->fifoth_val =
3208 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3209 mci_writel(host, FIFOTH, host->fifoth_val);
3210
3211 /* disable clock to CIU */
3212 mci_writel(host, CLKENA, 0);
3213 mci_writel(host, CLKSRC, 0);
3214
3215 /*
3216 * In 2.40a spec, Data offset is changed.
3217 * Need to check the version-id and set data-offset for DATA register.
3218 */
3219 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3220 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3221
3222 if (host->data_addr_override)
3223 host->fifo_reg = host->regs + host->data_addr_override;
3224 else if (host->verid < DW_MMC_240A)
3225 host->fifo_reg = host->regs + DATA_OFFSET;
3226 else
3227 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3228
3229 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3230 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3231 host->irq_flags, "dw-mci", host);
3232 if (ret)
3233 goto err_dmaunmap;
3234
3235 /*
3236 * Enable interrupts for command done, data over, data empty,
3237 * receive ready and error such as transmit, receive timeout, crc error
3238 */
3239 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3240 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3241 DW_MCI_ERROR_FLAGS);
3242 /* Enable mci interrupt */
3243 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3244
3245 dev_info(host->dev,
3246 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3247 host->irq, width, fifo_size);
3248
3249 /* We need at least one slot to succeed */
3250 ret = dw_mci_init_slot(host);
3251 if (ret) {
3252 dev_dbg(host->dev, "slot %d init failed\n", i);
3253 goto err_dmaunmap;
3254 }
3255
3256 /* Now that slots are all setup, we can enable card detect */
3257 dw_mci_enable_cd(host);
3258
3259 return 0;
3260
3261 err_dmaunmap:
3262 if (host->use_dma && host->dma_ops->exit)
3263 host->dma_ops->exit(host);
3264
3265 if (!IS_ERR(host->pdata->rstc))
3266 reset_control_assert(host->pdata->rstc);
3267
3268 err_clk_ciu:
3269 clk_disable_unprepare(host->ciu_clk);
3270
3271 err_clk_biu:
3272 clk_disable_unprepare(host->biu_clk);
3273
3274 return ret;
3275 }
3276 EXPORT_SYMBOL(dw_mci_probe);
3277
3278 void dw_mci_remove(struct dw_mci *host)
3279 {
3280 dev_dbg(host->dev, "remove slot\n");
3281 if (host->slot)
3282 dw_mci_cleanup_slot(host->slot);
3283
3284 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3285 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3286
3287 /* disable clock to CIU */
3288 mci_writel(host, CLKENA, 0);
3289 mci_writel(host, CLKSRC, 0);
3290
3291 if (host->use_dma && host->dma_ops->exit)
3292 host->dma_ops->exit(host);
3293
3294 if (!IS_ERR(host->pdata->rstc))
3295 reset_control_assert(host->pdata->rstc);
3296
3297 clk_disable_unprepare(host->ciu_clk);
3298 clk_disable_unprepare(host->biu_clk);
3299 }
3300 EXPORT_SYMBOL(dw_mci_remove);
3301
3302
3303
3304 #ifdef CONFIG_PM
3305 int dw_mci_runtime_suspend(struct device *dev)
3306 {
3307 struct dw_mci *host = dev_get_drvdata(dev);
3308
3309 if (host->use_dma && host->dma_ops->exit)
3310 host->dma_ops->exit(host);
3311
3312 clk_disable_unprepare(host->ciu_clk);
3313
3314 if (host->slot &&
3315 (mmc_can_gpio_cd(host->slot->mmc) ||
3316 !mmc_card_is_removable(host->slot->mmc)))
3317 clk_disable_unprepare(host->biu_clk);
3318
3319 return 0;
3320 }
3321 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3322
3323 int dw_mci_runtime_resume(struct device *dev)
3324 {
3325 int ret = 0;
3326 struct dw_mci *host = dev_get_drvdata(dev);
3327
3328 if (host->slot &&
3329 (mmc_can_gpio_cd(host->slot->mmc) ||
3330 !mmc_card_is_removable(host->slot->mmc))) {
3331 ret = clk_prepare_enable(host->biu_clk);
3332 if (ret)
3333 return ret;
3334 }
3335
3336 ret = clk_prepare_enable(host->ciu_clk);
3337 if (ret)
3338 goto err;
3339
3340 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3341 clk_disable_unprepare(host->ciu_clk);
3342 ret = -ENODEV;
3343 goto err;
3344 }
3345
3346 if (host->use_dma && host->dma_ops->init)
3347 host->dma_ops->init(host);
3348
3349 /*
3350 * Restore the initial value at FIFOTH register
3351 * And Invalidate the prev_blksz with zero
3352 */
3353 mci_writel(host, FIFOTH, host->fifoth_val);
3354 host->prev_blksz = 0;
3355
3356 /* Put in max timeout */
3357 mci_writel(host, TMOUT, 0xFFFFFFFF);
3358
3359 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3360 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3361 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3362 DW_MCI_ERROR_FLAGS);
3363 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3364
3365
3366 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3367 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
3368
3369 /* Force setup bus to guarantee available clock output */
3370 dw_mci_setup_bus(host->slot, true);
3371
3372 /* Now that slots are all setup, we can enable card detect */
3373 dw_mci_enable_cd(host);
3374
3375 return 0;
3376
3377 err:
3378 if (host->slot &&
3379 (mmc_can_gpio_cd(host->slot->mmc) ||
3380 !mmc_card_is_removable(host->slot->mmc)))
3381 clk_disable_unprepare(host->biu_clk);
3382
3383 return ret;
3384 }
3385 EXPORT_SYMBOL(dw_mci_runtime_resume);
3386 #endif /* CONFIG_PM */
3387
3388 static int __init dw_mci_init(void)
3389 {
3390 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3391 return 0;
3392 }
3393
3394 static void __exit dw_mci_exit(void)
3395 {
3396 }
3397
3398 module_init(dw_mci_init);
3399 module_exit(dw_mci_exit);
3400
3401 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3402 MODULE_AUTHOR("NXP Semiconductor VietNam");
3403 MODULE_AUTHOR("Imagination Technologies Ltd");
3404 MODULE_LICENSE("GPL v2");