2 * Copyright 2007, Google Inc.
3 * Copyright 2012, Intel Inc.
5 * based on omap.c driver, which was
6 * Copyright (C) 2004 Nokia Corporation
7 * Written by Tuukka Tikkanen and Juha Yrjölä <juha.yrjola@nokia.com>
8 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
9 * Other hacks (DMA, SD, etc) by David Brownell
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/major.h>
20 #include <linux/types.h>
21 #include <linux/pci.h>
22 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
26 #include <linux/errno.h>
27 #include <linux/hdreg.h>
28 #include <linux/kdev_t.h>
29 #include <linux/blkdev.h>
30 #include <linux/mutex.h>
31 #include <linux/scatterlist.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/card.h>
37 #include <linux/moduleparam.h>
38 #include <linux/init.h>
39 #include <linux/ioport.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/delay.h>
42 #include <linux/spinlock.h>
43 #include <linux/timer.h>
44 #include <linux/clk.h>
45 #include <linux/scatterlist.h>
50 #include <asm/types.h>
52 #include <linux/uaccess.h>
54 #define DRIVER_NAME "goldfish_mmc"
56 #define BUFFER_SIZE 16384
58 #define GOLDFISH_MMC_READ(host, addr) (readl(host->reg_base + addr))
59 #define GOLDFISH_MMC_WRITE(host, addr, x) (writel(x, host->reg_base + addr))
63 MMC_INT_STATUS
= 0x00,
64 /* set this to enable IRQ */
65 MMC_INT_ENABLE
= 0x04,
66 /* set this to specify buffer address */
67 MMC_SET_BUFFER
= 0x08,
69 /* MMC command number */
75 /* MMC response (or R2 bits 0 - 31) */
78 /* MMC R2 response bits 32 - 63 */
81 /* MMC R2 response bits 64 - 95 */
84 /* MMC R2 response bits 96 - 127 */
87 MMC_BLOCK_LENGTH
= 0x24,
88 MMC_BLOCK_COUNT
= 0x28,
93 /* MMC_INT_STATUS bits */
95 MMC_STAT_END_OF_CMD
= 1U << 0,
96 MMC_STAT_END_OF_DATA
= 1U << 1,
97 MMC_STAT_STATE_CHANGE
= 1U << 2,
98 MMC_STAT_CMD_TIMEOUT
= 1U << 3,
101 MMC_STATE_INSERTED
= 1U << 0,
102 MMC_STATE_READ_ONLY
= 1U << 1,
108 #define OMAP_MMC_CMDTYPE_BC 0
109 #define OMAP_MMC_CMDTYPE_BCR 1
110 #define OMAP_MMC_CMDTYPE_AC 2
111 #define OMAP_MMC_CMDTYPE_ADTC 3
114 struct goldfish_mmc_host
{
115 struct mmc_request
*mrq
;
116 struct mmc_command
*cmd
;
117 struct mmc_data
*data
;
118 struct mmc_host
*mmc
;
120 unsigned char id
; /* 16xx chips have 2 MMC blocks */
122 unsigned int phys_base
;
124 unsigned char bus_mode
;
125 unsigned char hw_bus_mode
;
129 unsigned dma_in_use
:1;
131 void __iomem
*reg_base
;
135 goldfish_mmc_cover_is_open(struct goldfish_mmc_host
*host
)
141 goldfish_mmc_show_cover_switch(struct device
*dev
,
142 struct device_attribute
*attr
, char *buf
)
144 struct goldfish_mmc_host
*host
= dev_get_drvdata(dev
);
146 return sprintf(buf
, "%s\n", goldfish_mmc_cover_is_open(host
) ? "open" :
150 static DEVICE_ATTR(cover_switch
, S_IRUGO
, goldfish_mmc_show_cover_switch
, NULL
);
153 goldfish_mmc_start_command(struct goldfish_mmc_host
*host
, struct mmc_command
*cmd
)
164 /* Our hardware needs to know exact type */
165 switch (mmc_resp_type(cmd
)) {
170 /* resp 1, 1b, 6, 7 */
180 dev_err(mmc_dev(host
->mmc
),
181 "Invalid response type: %04x\n", mmc_resp_type(cmd
));
185 if (mmc_cmd_type(cmd
) == MMC_CMD_ADTC
)
186 cmdtype
= OMAP_MMC_CMDTYPE_ADTC
;
187 else if (mmc_cmd_type(cmd
) == MMC_CMD_BC
)
188 cmdtype
= OMAP_MMC_CMDTYPE_BC
;
189 else if (mmc_cmd_type(cmd
) == MMC_CMD_BCR
)
190 cmdtype
= OMAP_MMC_CMDTYPE_BCR
;
192 cmdtype
= OMAP_MMC_CMDTYPE_AC
;
194 cmdreg
= cmd
->opcode
| (resptype
<< 8) | (cmdtype
<< 12);
196 if (host
->bus_mode
== MMC_BUSMODE_OPENDRAIN
)
199 if (cmd
->flags
& MMC_RSP_BUSY
)
202 if (host
->data
&& !(host
->data
->flags
& MMC_DATA_WRITE
))
205 GOLDFISH_MMC_WRITE(host
, MMC_ARG
, cmd
->arg
);
206 GOLDFISH_MMC_WRITE(host
, MMC_CMD
, cmdreg
);
209 static void goldfish_mmc_xfer_done(struct goldfish_mmc_host
*host
,
210 struct mmc_data
*data
)
212 if (host
->dma_in_use
) {
213 enum dma_data_direction dma_data_dir
;
215 dma_data_dir
= mmc_get_dma_dir(data
);
217 if (dma_data_dir
== DMA_FROM_DEVICE
) {
219 * We don't really have DMA, so we need
220 * to copy from our platform driver buffer
222 uint8_t *dest
= (uint8_t *)sg_virt(data
->sg
);
223 memcpy(dest
, host
->virt_base
, data
->sg
->length
);
225 host
->data
->bytes_xfered
+= data
->sg
->length
;
226 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, host
->sg_len
,
234 * NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
235 * dozens of requests until the card finishes writing data.
236 * It'd be cheaper to just wait till an EOFB interrupt arrives...
241 mmc_request_done(host
->mmc
, data
->mrq
);
245 goldfish_mmc_start_command(host
, data
->stop
);
248 static void goldfish_mmc_end_of_data(struct goldfish_mmc_host
*host
,
249 struct mmc_data
*data
)
251 if (!host
->dma_in_use
) {
252 goldfish_mmc_xfer_done(host
, data
);
256 goldfish_mmc_xfer_done(host
, data
);
259 static void goldfish_mmc_cmd_done(struct goldfish_mmc_host
*host
,
260 struct mmc_command
*cmd
)
263 if (cmd
->flags
& MMC_RSP_PRESENT
) {
264 if (cmd
->flags
& MMC_RSP_136
) {
265 /* response type 2 */
267 GOLDFISH_MMC_READ(host
, MMC_RESP_0
);
269 GOLDFISH_MMC_READ(host
, MMC_RESP_1
);
271 GOLDFISH_MMC_READ(host
, MMC_RESP_2
);
273 GOLDFISH_MMC_READ(host
, MMC_RESP_3
);
275 /* response types 1, 1b, 3, 4, 5, 6 */
277 GOLDFISH_MMC_READ(host
, MMC_RESP_0
);
281 if (host
->data
== NULL
|| cmd
->error
) {
283 mmc_request_done(host
->mmc
, cmd
->mrq
);
287 static irqreturn_t
goldfish_mmc_irq(int irq
, void *dev_id
)
289 struct goldfish_mmc_host
*host
= (struct goldfish_mmc_host
*)dev_id
;
292 int end_transfer
= 0;
293 int transfer_error
= 0;
294 int state_changed
= 0;
297 while ((status
= GOLDFISH_MMC_READ(host
, MMC_INT_STATUS
)) != 0) {
298 GOLDFISH_MMC_WRITE(host
, MMC_INT_STATUS
, status
);
300 if (status
& MMC_STAT_END_OF_CMD
)
303 if (status
& MMC_STAT_END_OF_DATA
)
306 if (status
& MMC_STAT_STATE_CHANGE
)
309 if (status
& MMC_STAT_CMD_TIMEOUT
) {
316 struct mmc_request
*mrq
= host
->mrq
;
317 mrq
->cmd
->error
= -ETIMEDOUT
;
319 mmc_request_done(host
->mmc
, mrq
);
323 goldfish_mmc_cmd_done(host
, host
->cmd
);
326 goldfish_mmc_xfer_done(host
, host
->data
);
327 else if (end_transfer
) {
329 goldfish_mmc_end_of_data(host
, host
->data
);
330 } else if (host
->data
!= NULL
) {
332 * WORKAROUND -- after porting this driver from 2.6 to 3.4,
333 * during device initialization, cases where host->data is
334 * non-null but end_transfer is false would occur. Doing
335 * nothing in such cases results in no further interrupts,
336 * and initialization failure.
337 * TODO -- find the real cause.
340 goldfish_mmc_end_of_data(host
, host
->data
);
344 u32 state
= GOLDFISH_MMC_READ(host
, MMC_STATE
);
345 pr_info("%s: Card detect now %d\n", __func__
,
346 (state
& MMC_STATE_INSERTED
));
347 mmc_detect_change(host
->mmc
, 0);
350 if (!end_command
&& !end_transfer
&&
351 !transfer_error
&& !state_changed
&& !cmd_timeout
) {
352 status
= GOLDFISH_MMC_READ(host
, MMC_INT_STATUS
);
353 dev_info(mmc_dev(host
->mmc
),"spurious irq 0x%04x\n", status
);
355 GOLDFISH_MMC_WRITE(host
, MMC_INT_STATUS
, status
);
356 GOLDFISH_MMC_WRITE(host
, MMC_INT_ENABLE
, 0);
363 static void goldfish_mmc_prepare_data(struct goldfish_mmc_host
*host
,
364 struct mmc_request
*req
)
366 struct mmc_data
*data
= req
->data
;
369 enum dma_data_direction dma_data_dir
;
373 GOLDFISH_MMC_WRITE(host
, MMC_BLOCK_LENGTH
, 0);
374 GOLDFISH_MMC_WRITE(host
, MMC_BLOCK_COUNT
, 0);
375 host
->dma_in_use
= 0;
379 block_size
= data
->blksz
;
381 GOLDFISH_MMC_WRITE(host
, MMC_BLOCK_COUNT
, data
->blocks
- 1);
382 GOLDFISH_MMC_WRITE(host
, MMC_BLOCK_LENGTH
, block_size
- 1);
385 * Cope with calling layer confusion; it issues "single
386 * block" writes using multi-block scatterlists.
388 sg_len
= (data
->blocks
== 1) ? 1 : data
->sg_len
;
390 dma_data_dir
= mmc_get_dma_dir(data
);
392 host
->sg_len
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
,
393 sg_len
, dma_data_dir
);
395 host
->dma_in_use
= 1;
397 if (dma_data_dir
== DMA_TO_DEVICE
) {
399 * We don't really have DMA, so we need to copy to our
400 * platform driver buffer
402 const uint8_t *src
= (uint8_t *)sg_virt(data
->sg
);
403 memcpy(host
->virt_base
, src
, data
->sg
->length
);
407 static void goldfish_mmc_request(struct mmc_host
*mmc
, struct mmc_request
*req
)
409 struct goldfish_mmc_host
*host
= mmc_priv(mmc
);
411 WARN_ON(host
->mrq
!= NULL
);
414 goldfish_mmc_prepare_data(host
, req
);
415 goldfish_mmc_start_command(host
, req
->cmd
);
418 * This is to avoid accidentally being detected as an SDIO card
419 * in mmc_attach_sdio().
421 if (req
->cmd
->opcode
== SD_IO_SEND_OP_COND
&&
422 req
->cmd
->flags
== (MMC_RSP_SPI_R4
| MMC_RSP_R4
| MMC_CMD_BCR
))
423 req
->cmd
->error
= -EINVAL
;
426 static void goldfish_mmc_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
428 struct goldfish_mmc_host
*host
= mmc_priv(mmc
);
430 host
->bus_mode
= ios
->bus_mode
;
431 host
->hw_bus_mode
= host
->bus_mode
;
434 static int goldfish_mmc_get_ro(struct mmc_host
*mmc
)
437 struct goldfish_mmc_host
*host
= mmc_priv(mmc
);
439 state
= GOLDFISH_MMC_READ(host
, MMC_STATE
);
440 return ((state
& MMC_STATE_READ_ONLY
) != 0);
443 static const struct mmc_host_ops goldfish_mmc_ops
= {
444 .request
= goldfish_mmc_request
,
445 .set_ios
= goldfish_mmc_set_ios
,
446 .get_ro
= goldfish_mmc_get_ro
,
449 static int goldfish_mmc_probe(struct platform_device
*pdev
)
451 struct mmc_host
*mmc
;
452 struct goldfish_mmc_host
*host
= NULL
;
453 struct resource
*res
;
458 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
459 irq
= platform_get_irq(pdev
, 0);
460 if (res
== NULL
|| irq
< 0)
463 mmc
= mmc_alloc_host(sizeof(struct goldfish_mmc_host
), &pdev
->dev
);
466 goto err_alloc_host_failed
;
469 host
= mmc_priv(mmc
);
472 pr_err("mmc: Mapping %lX to %lX\n", (long)res
->start
, (long)res
->end
);
473 host
->reg_base
= ioremap(res
->start
, resource_size(res
));
474 if (host
->reg_base
== NULL
) {
478 host
->virt_base
= dma_alloc_coherent(&pdev
->dev
, BUFFER_SIZE
,
479 &buf_addr
, GFP_KERNEL
);
481 if (host
->virt_base
== 0) {
483 goto dma_alloc_failed
;
485 host
->phys_base
= buf_addr
;
490 mmc
->ops
= &goldfish_mmc_ops
;
492 mmc
->f_max
= 24000000;
493 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
494 mmc
->caps
= MMC_CAP_4_BIT_DATA
;
496 /* Use scatterlist DMA to reduce per-transfer costs.
497 * NOTE max_seg_size assumption that small blocks aren't
498 * normally used (except e.g. for reading SD registers).
501 mmc
->max_blk_size
= 2048; /* MMC_BLOCK_LENGTH is 11 bits (+1) */
502 mmc
->max_blk_count
= 2048; /* MMC_BLOCK_COUNT is 11 bits (+1) */
503 mmc
->max_req_size
= BUFFER_SIZE
;
504 mmc
->max_seg_size
= mmc
->max_req_size
;
506 ret
= request_irq(host
->irq
, goldfish_mmc_irq
, 0, DRIVER_NAME
, host
);
508 dev_err(&pdev
->dev
, "Failed IRQ Adding goldfish MMC\n");
509 goto err_request_irq_failed
;
512 host
->dev
= &pdev
->dev
;
513 platform_set_drvdata(pdev
, host
);
515 ret
= device_create_file(&pdev
->dev
, &dev_attr_cover_switch
);
517 dev_warn(mmc_dev(host
->mmc
),
518 "Unable to create sysfs attributes\n");
520 GOLDFISH_MMC_WRITE(host
, MMC_SET_BUFFER
, host
->phys_base
);
521 GOLDFISH_MMC_WRITE(host
, MMC_INT_ENABLE
,
522 MMC_STAT_END_OF_CMD
| MMC_STAT_END_OF_DATA
|
523 MMC_STAT_STATE_CHANGE
| MMC_STAT_CMD_TIMEOUT
);
528 err_request_irq_failed
:
529 dma_free_coherent(&pdev
->dev
, BUFFER_SIZE
, host
->virt_base
,
532 iounmap(host
->reg_base
);
534 mmc_free_host(host
->mmc
);
535 err_alloc_host_failed
:
539 static int goldfish_mmc_remove(struct platform_device
*pdev
)
541 struct goldfish_mmc_host
*host
= platform_get_drvdata(pdev
);
543 BUG_ON(host
== NULL
);
545 mmc_remove_host(host
->mmc
);
546 free_irq(host
->irq
, host
);
547 dma_free_coherent(&pdev
->dev
, BUFFER_SIZE
, host
->virt_base
, host
->phys_base
);
548 iounmap(host
->reg_base
);
549 mmc_free_host(host
->mmc
);
553 static struct platform_driver goldfish_mmc_driver
= {
554 .probe
= goldfish_mmc_probe
,
555 .remove
= goldfish_mmc_remove
,
561 module_platform_driver(goldfish_mmc_driver
);
562 MODULE_LICENSE("GPL v2");