1 /****************************************************************************
3 * Copyright (c) 2014 - 2016 Samsung Electronics Co., Ltd. All rights reserved
5 ****************************************************************************/
8 * mx140 Infrastructure Configuration Structure.
10 * Used to pass configuration data from AP to R4 infrastructure
11 * on Maxwell Subsystem startup.
15 * - All multi-octet integers shall be stored LittleEndian.
17 * - All location fields ("*_loc") are 32 bit octet offsets w.r.t. the R4
18 * address map. They can therefore refer to DRAM memory or Mailbox registers.
20 * - "typedefs" are avoided to allow inclusion in linux source code.
27 /* It appears that due to the previous syntax "__packed struct foo" used in this
28 * header, the structures here don't actually get packed. Clang warns that
29 * that syntax is ignored. But correcting it causes a misalignment with FW.
30 * The __MXPACKED macro is used to stop packing the structures in this
31 * header until we've investigated further.
33 #define __MXPACKED /* TODO: HACK - don't actually pack! */
38 * Config structure magic number.
40 * The AP writes this value and the R4 checks it to trap endian mismatches.
42 #define MXCONF_MAGIC 0x79828486
45 * Config structure version
47 * The AP writes these values and the R4 checks them to trap config structure
50 #define MXCONF_VERSION_MAJOR 0
51 #define MXCONF_VERSION_MINOR 5 /* For fleximac moredump */
56 * Maxwell Circular Packet Buffer Configuration.
59 scsc_mifram_ref buffer_loc
; /**< Location of allocated buffer in DRAM */
60 uint32_t num_packets
; /**< Total number of packets that can be stored in the buffer */
61 uint32_t packet_size
; /**< Size of each individual packet within the buffer */
62 scsc_mifram_ref read_index_loc
; /**< Location of 32bit read index in DRAM or Mailbox */
63 scsc_mifram_ref write_index_loc
; /**< Location of 32bit write index */
67 * Maxwell Management Simplex Stream Configuration
69 * A circular buffer plus a pair of R/W signaling bits.
72 /** Circular Packet Buffer configuration */
73 struct mxcbufconf buf_conf
;
75 /** Allocated MIF Interrupt Read Bit Index */
78 /** Allocated MIF Interrupt Write Bit Index */
79 uint8_t write_bit_idx
;
83 * Maxwell Management Transport Configuration
85 * A pair of simplex streams.
88 struct mxstreamconf to_ap_stream_conf
;
89 struct mxstreamconf from_ap_stream_conf
;
93 * Maxwell Infrastructure Configuration Version
95 struct mxconfversion
{
101 * Mxlog Event Buffer Configuration.
103 * A circular buffer. Size must be a multiple of 2.
107 struct mxstreamconf stream_conf
;
112 * Maxwell Infrastructure Configuration Override (HCF block)
121 * Maxwell Infrastructure Configuration
125 * Config Magic Number
127 * Always 1st field in config.
134 * Always second field in config.
136 struct mxconfversion version
;
139 * MX Management Message Transport Configuration.
141 struct mxtransconf mx_trans_conf
;
144 * MX Management GDB Message Transport Configuration.
146 /* Cortex-R4 channel */
147 struct mxtransconf mx_trans_conf_gdb_r4
;
148 /* Cortex-M4 channel */
149 struct mxtransconf mx_trans_conf_gdb_m4
;
152 * Mxlog Event Buffer Configuration.
154 struct mxlogconf mxlogconf
;
159 * SOC HW revision override from host
161 uint32_t soc_revision
;
168 #define MXCONF_FLAGS_FM_ON (BIT(0)) /* FM already on */
176 struct mxmibref fwconfig
;
180 /* Fleximac Cortex-M3_1 piggy back as M4 channel.
181 * (Driver must initialise from-ap buffer address to 0
182 * if channel is not in use).
184 struct mxtransconf mx_trans_conf_gdb_m4_1
;
188 #endif /* MXCONF_H__ */