drivers/misc/samsung/scsc/mif_reg_S5E9630.h

   1 /****************************************************************************
   2  *
   3  * Copyright (c) 2014 - 2019 Samsung Electronics Co., Ltd. All rights reserved
   4  *
   5  ****************************************************************************/
   6
   7 #ifndef __MIF_REG_9630_H
   8 #define __MIF_REG_9630_H
   9
  10 /*********************************/
  11 /* PLATFORM register definitions */
  12 /*********************************/
  13 #define NUM_MBOX_PLAT   8
  14 #define NUM_SEMAPHORE   12
  15
  16 #define MAILBOX_WLBT_BASE       0x0000
  17 #define MAILBOX_WLBT_REG(r)     (MAILBOX_WLBT_BASE + (r))
  18 #define MCUCTRL                 0x000 /* MCU Controller Register */
  19 /* R0 [31:16]  - Int FROM R4/M4 */
  20 #define INTGR0                  0x008 /* Interrupt Generation Register 0 (r/w) */
  21 #define INTCR0                  0x00C /* Interrupt Clear Register 0 (w) */
  22 #define INTMR0                  0x010 /* Interrupt Mask Register 0 (r/w) */
  23 #define INTSR0                  0x014 /* Interrupt Status Register 0 (r) */
  24 #define INTMSR0                 0x018 /* Interrupt Mask Status Register 0 (r) */
  25 /* R1 [15:0]  - Int TO R4/M4 */
  26 #define INTGR1                  0x01c /* Interrupt Generation Register 1 */
  27 #define INTCR1                  0x020 /* Interrupt Clear Register 1 */
  28 #define INTMR1                  0x024 /* Interrupt Mask Register 1 */
  29 #define INTSR1                  0x028 /* Interrupt Status Register 1 */
  30 #define INTMSR1                 0x02c /* Interrupt Mask Status Register 1 */
  31 #define MIF_INIT                0x04c /* MIF_init */
  32 #define IS_VERSION              0x050 /* Version Information Register */
  33 #define ISSR_BASE               0x080 /* IS_Shared_Register Base address */
  34 #define ISSR(r)                 (ISSR_BASE + (4 * (r)))
  35 #define SEMAPHORE_BASE          0x180 /* IS_Shared_Register Base address */
  36 #define SEMAPHORE(r)            (SEMAPHORE_BASE + (4 * (r)))
  37 #define SEMA0CON                0x1c0
  38 #define SEMA0STATE              0x1c8
  39 #define SEMA1CON                0x1e0
  40 #define SEMA1STATE              0x1e8
  41
  42 #define WLBT_PBUS_BASE                                  0x14400000
  43
  44 // CBUS : APM_BUS
  45 // PBUS : CFG_BUS
  46
  47 /* New WLBT SFRs for MEM config */
  48 #define WLBT_PBUS_D_TZPC_SFR                    (WLBT_PBUS_BASE + 0x10000)
  49 #define WLBT_PBUS_BAAW_DBUS                     (WLBT_PBUS_BASE + 0x20000)
  50 #define WLBT_PBUS_BAAW_CBUS                     (WLBT_PBUS_BASE + 0x30000)
  51 #define WLBT_PBUS_SMAPPER                       (WLBT_PBUS_BASE + 0x40000)
  52 #define WLBT_PBUS_SYSREG                        (WLBT_PBUS_BASE + 0x50000)
  53 #define WLBT_PBUS_BOOT                          (WLBT_PBUS_BASE + 0x60000)
  54
  55 #define TZPC_PROT0STAT          0x14410200
  56 #define TZPC_PROT0SET           0x14410204
  57
  58 /* POWER */
  59
  60 #define VGPIO_TX_MONITOR        0x1700
  61 #define VGPIO_TX_MON_BIT29      BIT(29)
  62
  63 /* Exynos 9630 UM - 9.8.719 */
  64 #define WLBT_CONFIGURATION      0x3300
  65 #define LOCAL_PWR_CFG           BIT(0) /* Control power state 0: Power down 1: Power on */
  66
  67 /* Exynos 9630 UM - 9.8.720 */
  68 #define WLBT_STATUS             0x3304
  69 #define WLBT_STATUS_BIT0        BIT(0) /* Status 0 : Power down 1 : Power on */
  70
  71 /* Exynos 9630 UM - 9.8.721 */
  72 #define WLBT_STATES             0x3308 /* STATES [7:0] States index for debugging
  73                                         * 0x00 : Reset
  74                                         * 0x10 : Power up
  75                                         * 0x80 : Power down
  76                                         * */
  77
  78 /* Exynos 9630 UM - 9.8.722 */
  79 #define WLBT_OPTION             0x330C
  80 #define WLBT_OPTION_DATA        BIT(3)
  81
  82 /* Exynos 9630 UM - 9.8.723 */
  83 #define WLBT_CTRL_NS            0x3310 /* WLBT Control SFR non-secure */
  84 #define WLBT_ACTIVE_CLR         BIT(8)  /* WLBT_ACTIVE_REQ is clear internally on WAKEUP */
  85 #define WLBT_ACTIVE_EN          BIT(7)  /* Enable of WIFI_ACTIVE_REQ */
  86 #define SW_TCXO_REQ             BIT(6)  /* SW TCXO Request register, if MASK_TCXO_REQ
  87                                          *  filed value is 1, This register value control TCXO Request*/
  88 #define MASK_TCXO_REQ           BIT(5) /* 1:mask TCXO_REQ coming from CP,
  89                                          * 0:enable request source
  90                                          */
  91 #define TCXO_GATE               BIT(4) /* TCXO gate control 0: TCXO enabled 1: TCXO gated */
  92 /*#define SET_SW_MIF_REQ                BIT(13)*/ /* MIF SLEEP control by SW 1: if MASK_MIF_REQ is
  93                                          * set to HIGH, MIF enters into down state by
  94                                          * SET_SW_MIF_REQ.
  95                                          */
  96 /*#define MASK_MIF_REQ          BIT(12)*/ /* 1:mask MIF_REQ coming from WLBT, 0 : disable */
  97 /*#define RTC_OUT_EN            BIT(10)*/ /* 1:enable, 0 : disable This is enable signal on RTC
  98                                          * CLK(32KHz). This clock can be used as WLBT PMU
  99                                          * clock when WLBT is internal power-down and
 100                                          * TCXO(26MHz) is disable at WLBT side.
 101                                          */
 102
 103
 104 /*------------------------------------*/
 105
 106 //??????#define WLBT_PWRON              BIT(1)
 107 #define WLBT_RESET_SET          BIT(0)  /* WLBT reset assertion control by using
 108                                          * PMU_ALIVE_WLBT.
 109                                          * 0x1: Reset Assertion,
 110                                          * 0x0: Reset Release
 111                                          */
 112 #define WLBT_RESET_REQ_EN       BIT(7)  /* 1:enable, 0:disable  Enable of WLBT_RESET_REQ */
 113 #define WLBT_RESET_REQ_CLR      BIT(8)  /* WLBT_RESET_REQ is clear internally on WAKEUP */
 114 #define MASK_PWR_REQ            BIT(1) /* 1:mask PWR_REQ coming from WLBT, 0 : disable */
 115 #define TCXO_ENABLE_SW          BIT(1) /* 1:enable, 0 : disable This is enable signal on TCXO
 116                                          * clock of WLBT. This signal can decide whether TCXO
 117                                          * clock is active by software when WLBT is internal
 118                                          * power-down or WLBT is in reset state at WLBT side. if
 119                                          * this value is HIGH, TCXO is active regardless of
 120                                          * hardware control
 121                                          */
 122 /* from wlbt_if_S5E7920.h excite code */
 123
 124 /* PMU_ALIVE Bit Field */
 125 /* WLBT_CTRL_NS */
 126 //#define CLEANY_BYPASS_DATA_EN                         BIT(16)
 127 //#define SET_SW_MIF_REQ                                        BIT(13)
 128 //#define MASK_MIF_REQ                                  BIT(12)
 129 //#define RTC_OUT_EN                                    BIT(10)
 130 //#define MASK_WLBT_PWRDN_DONE                          BIT(9)
 131 //#define WLBT_RESET_REQ_CLR                            BIT(8)
 132 //#define       WLBT_RESET_REQ_EN                               BIT(7)
 133 //#define       WLBT_ACTIVE_CLR                                 BIT(6)
 134 //#define WLBT_ACTIVE_EN                                        BIT(5)
 135 //#define WLBT_RESET_SET                                        BIT(0)
 136 //#define WLBT_PWRON                                    BIT(1)
 137
 138 /* WLBT_CTRL_S */
 139 //#define WLBT_START                                    BIT(0)
 140
 141 /* WLBT_STAT */
 142 //#define WLBT_ACCESS_MIF                                       BIT(4)
 143 //#define WLBT_PWRDN_DONE                                       BIT(0)
 144
 145 /* WLBT_DEBUG */
 146 //#define MASK_CLKREQ_WLBT                              BIT(8)
 147 //#define EN_PWR_REQ                                    BIT(5)
 148 //#define EN_WLBT_WAKEUP_REQ                            BIT(4)
 149 //#define EN_WLBT_RESET_REQ                             BIT(3)
 150 //#define EN_WLBT_ACTIVE                                        BIT(2)
 151 //#define EN_MIF_REQ                                    BIT(0)
 152
 153 /* WLBT_BOOT_TEST_RST_CONFIG */
 154 #define WLBT_IRAM_BOOT_OFFSET                           (BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8))
 155 #define WLBT_IRAM_BOOT_TEST                             BIT(5)
 156 #define WLBT_NOREMAP_BOOT_TEST                          BIT(4)
 157 #define WLBT2AP_PERI_PROT2                              BIT(2)
 158
 159 /* WLBT_QOS */
 160 #define WLBT_AWQOS                                      (BIT(19) | BIT(18) | BIT(17) | BIT(16))
 161 #define WLBT_ARQOS                                      (BIT(11) | BIT(10) | BIT(9) | BIT(8))
 162 #define WLBT_QOS_OVERRIDE                               BIT(0)
 163
 164 /*------------------------------------*/
 165
 166 /* Exynos 9630 UM - 9.8.724 */
 167 #define WLBT_CTRL_S             0x3314 /* WLBT Control SFR secure */
 168 #define WLBT_START              BIT(3) /* CP control enable 0: Disable 1: Enable */
 169
 170 /* Exynos 9630 UM - 9.8.725 */
 171 #define WLBT_OUT 0x3320
 172 #define SWEEPER_BYPASS          BIT(13) /* SWEEPER bypass mode control(WLBT2AP path) If
 173                                          * this bit is set to 1, SWEEPER is bypass mode.
 174                                          */
 175 #define SWEEPER_PND_CLR_REQ     BIT(7) /* SWEEPER_CLEAN Request. SWPPER is the IP
 176                                         * that can clean up hung transaction in the Long hop
 177                                         * async Bus Interface, when <SUBSYS> get hung
 178                                         * state. 0: Normal 1: SWEEPER CLEAN Requested
 179                                         */
 180
 181 /* Exynos 9630 UM - 9.8.726 */
 182 #define WLBT_IN                 0x3324
 183 #define BUS_READY               BIT(4) /* BUS ready indication signal when reset released. 0:
 184                                         * Normal 1: BUS ready state */
 185 #define PWRDOWN_IND             BIT(2) /* PWRDOWN state indication 0: Normal 1: In the
 186                                         * power down state */
 187 #define SWEEPER_PND_CLR_ACK     BIT(0) /* SWEEPER_CLEAN ACK signal. SWPPER is the IP
 188                                         * that can clean up hung transaction in the Long hop
 189                                         * async Bus Interface, when <SUBSYS> get hung
 190                                         * state. 0: Normal 1: SWEEPER CLEAN
 191                                         * Acknowledged */
 192 /* Exynos 9630 UM - 9.8.728 */
 193 #define WLBT_INT_EN             0x3344
 194 #define PWR_REQ_F               BIT(3)
 195 #define TCXO_REQ_F              BIT(5)
 196
 197 /* Exynos 9630 UM - 9.8.10 */
 198 #define WLBT_STAT               0x0058
 199 #define WLBT_PWRDN_DONE         BIT(0) /* Check WLBT power-down status.*/
 200 #define WLBT_ACCESS_MIF         BIT(4) /* Check whether WLBT accesses MIF domain */
 201
 202 /* Exynos 9630 UM - 9.8.11 */
 203 #define WLBT_DEBUG              0x005C /* MIF sleep, wakeup debugging control */
 204 /* need to find where have they moved */
 205 //#define EN_MIF_REQ            BIT(0) /* Control MIF_REQ through GPIO_ALIVE. */
 206 //#define EN_WLBT_ACTIVE        BIT(2) /* Control WLBT_ACTIVE through GPIO_ALIVE. */
 207 //#define EN_WLBT_RESET_REQ     BIT(3) /* Control WLBT_RESET_REQ through GPIO_ALIVE. */
 208 #define MASK_CLKREQ_WLBT        BIT(8) /* When this field is set to HIGH, ALIVE ignores
 209                                         * CLKREQ from WLBT.
 210                                         */
 211
 212 #define RESET_SEQUENCER_STATUS  0x0504
 213 #define RESET_STATUS_MASK       (BIT(10)|BIT(9)|BIT(8))
 214 #define RESET_STATUS            (5 << 8)
 215
 216 #define PMU_SHARED_PWR_REQ_WLBT_CONTROL_STATUS 0x8008
 217 #define CTRL_STATUS_MASK 0x1
 218
 219 #define CLEANY_BUS_WLBT_CONFIGURATION 0x3b20
 220 #define CLEANY_CFG_MASK 0x1
 221
 222 #define CLEANY_BUS_WLBT_STATUS  0x3B24
 223 #define CLEANY_STATUS_MASK      (BIT(17)|BIT(16))
 224
 225 /* Exynos 9630 UM - 9.8.763 */
 226 #define SYSTEM_OUT              0x3A20
 227 #define PWRRGTON_CON            BIT(9) /* XPWRRTON_CON control 0: Disable 1: Enable */
 228
 229 /* Exynos 9630 UM - 9.8.812 */
 230 #define TCXO_BUF_CTRL           0x3C10
 231 #define TCXO_BUF_BIAS_EN_WLBT   BIT(2)
 232 #define TCXO_BUF_EN_WLBT        BIT(3)
 233
 234 /* New WLBT SFRs for MEM config */
 235
 236 /* end address is exclusive so the ENDx register should be set to the first
 237  * address that is not accessible through that BAAW.
 238  *
 239  * Another very important point to note here is we are using BAAW0 to expose
 240  * 16MB region, so other BAAWs can be used for other purposes
 241  */
 242 #define WLBT_DBUS_BAAW_0_START          0x80000000 // Start of DRAM for WLBT R7
 243 #define WLBT_DBUS_BAAW_0_END            WLBT_DBUS_BAAW_4_START // 16 MB
 244 #define WLBT_DBUS_BAAW_1_START          0x80400000
 245 #define WLBT_DBUS_BAAW_1_END            WLBT_DBUS_BAAW_2_START
 246 #define WLBT_DBUS_BAAW_2_START          0x80800000
 247 #define WLBT_DBUS_BAAW_2_END            WLBT_DBUS_BAAW_3_START
 248 #define WLBT_DBUS_BAAW_3_START          0x80C00000
 249 #define WLBT_DBUS_BAAW_3_END            WLBT_DBUS_BAAW_4_START
 250 #define WLBT_DBUS_BAAW_4_START          0x81000000
 251 #define WLBT_DBUS_BAAW_4_END            0x813FFFFF
 252
 253 #define WLBT_BAAW_CON_INIT_DONE         (1 << 31)
 254 #define WLBT_BAAW_CON_EN_WRITE          (1 << 1)
 255 #define WLBT_BAAW_CON_EN_READ           (1 << 0)
 256 #define WLBT_BAAW_ACCESS_CTRL           (WLBT_BAAW_CON_INIT_DONE | WLBT_BAAW_CON_EN_WRITE | WLBT_BAAW_CON_EN_READ)
 257
 258 /* ref Confluence Maxwell450+Memory+Map */
 259 #define WLBT_CBUS_BAAW_0_START          0xA0000000              // CP2WLBT MBOX
 260 #define WLBT_CBUS_BAAW_0_END            0xA000FFFF
 261
 262 #define WLBT_CBUS_BAAW_1_START          0xA0010000              // GNSS,APM,AP,ABOX,CHUB2WLBT MBOX
 263 #define WLBT_CBUS_BAAW_1_END            0xA005FFFF
 264
 265 #define WLBT_CBUS_BAAW_2_START          0xA0060000              // CMGP SFR GPIO_CMGP_BASE
 266 #define WLBT_CBUS_BAAW_2_END            0xA009FFFF
 267
 268 #define WLBT_CBUS_BAAW_3_START          0xA00A0000              // CMGP SFR SYSREG_CMGP2WLBT_BASE
 269 #define WLBT_CBUS_BAAW_3_END            0xA00CFFFF
 270
 271 #define WLBT_CBUS_BAAW_4_START          0xA00D0000              // CMGP SFR USI_CMG00_BASE
 272 #define WLBT_CBUS_BAAW_4_END            0xA015FFFF
 273
 274 #define WLBT_CBUS_BAAW_5_START          0xA0160000              // CHUB SFR CHUB_USICHUB0_BASE
 275 #define WLBT_CBUS_BAAW_5_END            0xA01BFFFF
 276
 277 #define WLBT_CBUS_BAAW_6_START          0xA01C0000              // CHUB SFR CHUB_BASE
 278 #define WLBT_CBUS_BAAW_6_END            0xA01EFFFF
 279
 280 #define WLBT_PBUS_MBOX_CP2WLBT_BASE     0x10F50000
 281 #define WLBT_PBUS_MBOX_GNSS2WLBT_BASE   0x10FA0000
 282 #define WLBT_PBUS_MBOX_SHUB2WLBT_BASE   0x119A0000
 283 #define WLBT_PBUS_USI_CMG00_BASE        0x11500000
 284 #define WLBT_PBUS_SYSREG_CMGP2WLBT_BASE 0x11490000
 285 #define WLBT_PBUS_GPIO_CMGP_BASE        0x11430000
 286 #define WLBT_PBUS_CHUB_USICHUB0_BASE    0x11B70000
 287 #define WLBT_PBUS_CHUB_BASE             0x11A00000
 288
 289
 290
 291 /* CHIP_VERSION_ID SFR (remap block) 0x14450410
 292  */
 293 #define CHIP_VERSION_ID_OFFSET          0x410
 294 #define CHIP_VERSION_ID_VER_MASK        0xFFFFFFFF      /* [00:31] Version ID */
 295 #define CHIP_VERSION_ID_IP_PMU          0x0000F000      /* [12:15] PMU ROM Rev */
 296 #define CHIP_VERSION_ID_IP_MINOR        0x000F0000      /* [16:19] Minor Rev */
 297 #define CHIP_VERSION_ID_IP_MAJOR        0x00F00000      /* [20:23] Major Rev */
 298 #define CHIP_VERSION_ID_IP_PMU_SHIFT    12
 299 #define CHIP_VERSION_ID_IP_MINOR_SHIFT  16
 300 #define CHIP_VERSION_ID_IP_MAJOR_SHIFT  20
 301
 302 /* Power down registers */
 303 #define RESET_AHEAD_WLBT_SYS_PWR_REG 0x1360     /* Control power state in LOWPWR mode 1 - on, 0 - down*/
 304 #define CLEANY_BUS_WLBT_SYS_PWR_REG  0x1364     /* Control power state in LOWPWR mode 1 - on, 0 - down*/
 305 #define LOGIC_RESET_WLBT_SYS_PWR_REG 0x1368     /* Control power state in LOWPWR mode 1 - on, 0 - down*/
 306 #define TCXO_GATE_WLBT_SYS_PWR_REG   0x136C     /* Control power state in LOWPWR mode 1 - on, 0 */
 307 #define WLBT_DISABLE_ISO_SYS_PWR_REG 0x1370     /* Control power state in LOWPWR mode 1 - on, 0 */
 308 #define WLBT_RESET_ISO_SYS_PWR_REG   0x1374     /* Control power state in LOWPWR mode 1 - on, 0 */
 309
 310 #define CENTRAL_SEQ_WLBT_CONFIGURATION 0x0180  /* bit 16. Decides whether system-level low-power mode
 311                                                 * is used HIGH: System-level Low-Power mode
 312                                                 * disabled. LOW: System-level Low-Power mode
 313                                                 * enabled. When system enters low-power mode,
 314                                                 * this field is automatically cleared to HIGH.
 315                                                 */
 316
 317 //#define CENTRAL_SEQ_WLBT_STATUS 0x0184        /* 23:16  Check statemachine status */
 318 //#define STATES                  0xff0000
 319
 320 #define SYS_PWR_CFG             BIT(0)
 321 #define SYS_PWR_CFG_2           (BIT(0) | BIT(1))
 322 #define SYS_PWR_CFG_16          BIT(16)
 323
 324 /* TZASC (TrustZone Address Space Controller) configuration for Katmai onwards */
 325 #define EXYNOS_SET_CONN_TZPC    0
 326 #define SMC_CMD_CONN_IF         (0x82000710)
 327 #endif /* __MIF_REG_9630_H */