drivers/misc/samsung/scsc/mif_reg_S5E7872.h

   1 /****************************************************************************
   2  *
   3  * Copyright (c) 2014 - 2016 Samsung Electronics Co., Ltd. All rights reserved
   4  *
   5  ****************************************************************************/
   6
   7 #ifndef __MIF_REG_7872_H
   8 #define __MIF_REG_7872_H
   9
  10 /*********************************/
  11 /* PLATFORM register definitions */
  12 /*********************************/
  13 #define NUM_MBOX_PLAT   8
  14 #define NUM_SEMAPHORE   12
  15
  16 #define MAILBOX_WLBT_BASE       0x0000
  17 #define MAILBOX_WLBT_REG(r)     (MAILBOX_WLBT_BASE + (r))
  18 #define MCUCTRL                 0x000 /* MCU Controller Register */
  19 /* R0 [31:16]  - Int FROM R4/M4 */
  20 #define INTGR0                  0x008 /* Interrupt Generation Register 0 (r/w) */
  21 #define INTCR0                  0x00C /* Interrupt Clear Register 0 (w) */
  22 #define INTMR0                  0x010 /* Interrupt Mask Register 0 (r/w) */
  23 #define INTSR0                  0x014 /* Interrupt Status Register 0 (r) */
  24 #define INTMSR0                 0x018 /* Interrupt Mask Status Register 0 (r) */
  25 /* R1 [15:0]  - Int TO R4/M4 */
  26 #define INTGR1                  0x01c /* Interrupt Generation Register 1 */
  27 #define INTCR1                  0x020 /* Interrupt Clear Register 1 */
  28 #define INTMR1                  0x024 /* Interrupt Mask Register 1 */
  29 #define INTSR1                  0x028 /* Interrupt Status Register 1 */
  30 #define INTMSR1                 0x02c /* Interrupt Mask Status Register 1 */
  31 #define MIF_INIT                0x04c /* MIF_init */
  32 #define IS_VERSION              0x050 /* Version Information Register */
  33 #define ISSR_BASE               0x080 /* IS_Shared_Register Base address */
  34 #define ISSR(r)                 (ISSR_BASE + (4 * (r)))
  35 #define SEMAPHORE_BASE          0x180 /* IS_Shared_Register Base address */
  36 #define SEMAPHORE(r)            (SEMAPHORE_BASE + (4 * (r)))
  37 #define SEMA0CON                0x1c0
  38 #define SEMA0STATE              0x1c8
  39 #define SEMA1CON                0x1e0
  40 #define SEMA1STATE              0x1e8
  41
  42
  43 /* POWER */
  44 /* Page 594 datasheet */
  45 /* Base Address - 0x11C8_0000 */
  46 #define WIFI_CTRL_NS            0x0140 /* WIFI Control SFR non-secure */
  47 #define WIFI_PWRON              BIT(1)
  48 #define WIFI_RESET_SET          BIT(2)
  49 #define WIFI_ACTIVE_EN          BIT(5) /* Enable of WIFI_ACTIVE_REQ */
  50 #define WIFI_ACTIVE_CLR         BIT(6) /* WIFI_ACTIVE_REQ is clear internally on WAKEUP */
  51 #define WIFI_RESET_REQ_EN       BIT(7) /* 1:enable, 0:disable  Enable of WIFI_RESET_REQ */
  52 #define WIFI_RESET_REQ_CLR      BIT(8) /* WIFI_RESET_REQ is clear internally on WAKEUP */
  53 #define MASK_WIFI_PWRDN_DONE    BIT(9) /* 1:mask, 0 : pass RTC clock out enable to WIFI
  54                                         * This mask WIFI_PWRDN_DONE come in from WIFI.
  55                                         * If MASK_WIFI_PWRDN_DONE = 1, WIFI enter to DOWN
  56                                         * state without checking WIFI_PWRDN_DONE*/
  57 #define RTC_OUT_EN              BIT(10) /* 1:enable, 0 : disable This is enable signal on RTC
  58                                          * CLK(32KHz). This clock can be used as WIFI PMU
  59                                          * clock when WIFI is internal power-down and
  60                                          * TCXO(26MHz) is disable at WIFI side.*/
  61 #define TCXO_ENABLE_SW          BIT(11) /* 1:enable, 0 : disable This is enable signal on TCXO
  62                                          * clock of WIFI. This signal can decide whether TCXO
  63                                          * clock is active by software when WIFI is internal
  64                                          * power-down or WIFI is in reset state at WIFI side. if
  65                                          * this value is HIGH, TCXO is active regardless of
  66                                          * hardware control */
  67 #define MASK_MIF_REQ            BIT(12) /* 1:mask MIF_REQ comming from WIFI, 0 : disable */
  68 #define SET_SW_MIF_REQ          BIT(13) /* MIF SLEEP control by SW 1: if MASK_MIF_REQ is
  69                                            set to HIGH, MIF enters into down state by
  70                                            SET_SW_MIF_REQ. */
  71 #define SWEEPER_BYPASS_DATA_EN  BIT(16) /* CLEANY bypass mode control(WIFI2AP MEM path)
  72                                            If this bit is set to 1, CLEANY in MIF block starts
  73                                            operation. If this bit is set to 0, CLEANY is bypass
  74                                            mode.*/
  75 #define SFR_SERIALIZER_DUR_DATA2REQ (BIT(20) | BIT(21)) /* Duration between DATA and REQUEST on
  76                                                            SFR_SERIALIZER */
  77
  78
  79 #define WIFI_CTRL_S             0x0144 /* WIFI Control SFR secure */
  80 #define WIFI_START              BIT(3) /* WIFI Reset release control  If WIFI_START = 1,
  81                                         * WIFI exit from DOWN state and go to UP state.
  82                                         * If this field is set to high (WIFI_START = 1)
  83                                         * WIFI state can go to UP state. This signal can be
  84                                         * auto-clear by DIRECTWR at UP */
  85
  86 #define WIFI_STAT               0x0148
  87 #define WIFI_PWRDN_DONE         BIT(0) /* Check WIFI power-down status.*/
  88 #define WIFI_ACCESS_MIF         BIT(4) /* Check whether WIFI accesses MIF doman */
  89
  90 #define WIFI_DEBUG              0x014c /* MIF sleep, wakeup debugging control */
  91 #define EN_MIF_REQ              BIT(0) /* Control MIF_REQ through GPIO_ALIVE. */
  92 #define EN_WIFI_ACTIVE          BIT(2) /* Control WIFI_ACTIVE through GPIO_ALIVE. */
  93 #define EN_MIF_RESET_REQ        BIT(3) /* Control WIFI_RESET_REQ through GPIO_ALIVE. */
  94 #define MASK_CLKREQ_WIFI        BIT(8) /* When this field is set to HIGH, ALIVE ignores
  95                                         * CLKREQ from WIFI.*/
  96
  97 /* TODO: Might be 0x10480000 */
  98 #define PMU_ALIVE_BASE          0x0000
  99 #define PMU_ALIVE_REG(r)        (PMU_ALIVE_BASE + (r))
 100 #define WIFI2AP_MEM_CONFIG0     0x7300 /* MEM_SIZE SECTION_0 */
 101 #define WIFI2AP_MEM_CONFIG1     0x7304 /* BASE ADDRESS SECTION 0*/
 102 #define WIFI2AP_MEM_CONFIG2     0x7300 /* MEM_SIZE SECTION_0 */
 103 #define WIFI2AP_MEM_CONFIG3     0x7304 /* BASE ADDRESS SECTION 1*/
 104 #define WIFI2AP_MEM_CONFIG4     0x7300 /* MEM_SIZE SECTION_1 */
 105 #define WIFI2AP_MEM_CONFIG5     0x7304 /* BASE ADDRESS SECTION 0*/
 106 #define WIFI2AP_MIF_ACCESS_WIN0 0x7318 /* ACCESS_CONTROL SFR*/
 107 #define WIFI2AP_MIF_ACCESS_WIN1 0x731c /* ACCESS_CONTROL SFR*/
 108 #define WIFI2AP_PERI0_ACCESS_WIN0 0x7320 /* ACCESS WINDOW PERI */
 109 #define WIFI2AP_PERI0_ACCESS_WIN1 0x7324 /* ACCESS WINDOW PERI */
 110 #define WIFI2AP_PERI0_ACCESS_WIN2 0x7328 /* ACCESS WINDOW PERI */
 111 #define WIFI2AP_PERI0_ACCESS_WIN3 0x732c /* ACCESS WINDOW PERI */
 112 #define WLBT_BOOT_TEST_RST_CFG  0x7330  /* WLBT_IRAM_BOOT_OFFSET */
 113                                         /* WLBT_IRAM_BOOT_TEST */
 114                                         /* WLBT2AP_PERI_PROT2 */
 115
 116 /* Power down registers */
 117 #define RESET_AHEAD_WIFI_PWR_REG 0x1360         /* Control power state in LOWPWR mode 1 - on, 0 - down*/
 118 #define CLEANY_BUS_WIFI_SYS_PWR_REG 0x1364      /* Control power state in LOWPWR mode 1 - on, 0 - down*/
 119 #define LOGIC_RESET_WIFI_SYS_PWR_REG 0x1368     /* Control power state in LOWPWR mode 1 - on, 0 - down*/
 120 #define TCXO_GATE_WIFI_SYS_PWR_REG 0x136c       /* Control power state in LOWPWR mode 1 - on, 0 */
 121 #define WIFI_DISABLE_ISO_SYS_PWR_REG 0x1370     /* Control power state in LOWPWR mode 1 - on, 0 */
 122 #define WIFI_RESET_ISO_SYS_PWR_REG 0x1374       /* Control power state in LOWPWR mode 1 - on, 0 */
 123
 124 #define CENTRAL_SEQ_WIFI_CONFIGURATION 0x0380 /* bit 16. Decides whether system-level low-power mode
 125                                                 * is used HIGH: System-level Low-Power mode
 126                                                 * disabled. LOW: System-level Low-Power mode
 127                                                 * enabled. When system enters low-power mode,
 128                                                 * this field is automatically cleared to HIGH. */
 129
 130 #define CENTRAL_SEQ_WIFI_STATUS 0x0384        /* 23:16  Check statemachine status */
 131 #define STATES                  0xff0000
 132
 133 #define SYS_PWR_CFG             BIT(0)
 134 #define SYS_PWR_CFG_2           (BIT(0) | BIT(1))
 135 #define SYS_PWR_CFG_16          BIT(16)
 136
 137
 138 /* CMU registers to request PLL for USB Clock */
 139 #define USBPLL_CON0 0x0200
 140 #define AP2WIFI_USBPLL_REQ      BIT(0)  /* 1: Request PLL, 0: Release PLL */
 141
 142 #define USBPLL_CON1 0x0204
 143 #define AP2WLBT_USBPLL_WPLL_SEL BIT(0)  /* 1: WLBT, 0: AP */
 144 #define AP2WLBT_USBPLL_WPLL_EN  BIT(1)  /* 1: Enable, 0: Disable */
 145
 146 /* TZASC configuration for Katmai onward */
 147 #define WLBT_TZASC                      0
 148 #define EXYNOS_SMC_WLBT_TZASC_CMD       0x82000710
 149 #endif /* __MIF_REG_7872_H */