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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / xhci_test / mtk-test.c
1 #include <linux/init.h>
2 #include <linux/irq.h>
3 #include <linux/log2.h>
4 #include <linux/module.h>
5 #include <linux/moduleparam.h>
6 #include <linux/slab.h>
7
8 #include <linux/kernel.h> /* printk() */
9 #include <linux/fs.h> /* everything... */
10 #include <linux/errno.h> /* error codes */
11 #include <linux/types.h> /* size_t */
12 #include <linux/proc_fs.h>
13 #include <linux/fcntl.h> /* O_ACCMODE */
14 #include <linux/seq_file.h>
15 #include <linux/cdev.h>
16 //#include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/random.h>
19 #include <linux/scatterlist.h>
20 #include <asm/unaligned.h>
21 #include <linux/usb/ch9.h>
22 #include <asm/uaccess.h>
23 #include "mtk-test.h"
24 #include "xhci.h"
25 #include "mtk-usb-hcd.h"
26 //#include <linux/usb/hcd.h>
27 #include "mtk-test-lib.h"
28 #include "mtk-protocol.h"
29 //#include "xhci-hub.c"
30 #include <linux/dma-mapping.h>
31 #include "xhci-mtk-scheduler.h"
32 #include <linux/mu3phy/mtk-phy.h>
33 #include "xhci-mtk-power.h"
34 #include <linux/dmapool.h>
35
36 #include <linux/kthread.h>
37 #include <linux/kobject.h>
38 #include <linux/miscdevice.h>
39
40
41 #include "xhci.h"
42 //extern u32 mtktest_xhci_port_state_to_neutral(u32 state);
43
44 struct file_operations xhci_mtk_test_fops_host;
45
46 static struct miscdevice mu3h_test_uevent_device = {
47 .minor = MISC_DYNAMIC_MINOR,
48 .name = "usbif_u3h_test_uevent",
49 .fops = NULL,
50 };
51
52 /********************************************************
53 * slt.disable
54 * Send disable slot command, release current slot id
55 * args:
56 *********************************************************/
57 static int t_slot_disable_slot(int argc, char** argv);
58 /********************************************************
59 * slt.configep
60 * Config an bulk EP to let slot go to configured state
61 * args:
62 *********************************************************/
63 //static int t_slot_config_ep(int argc, char** argv);
64 static int t_slot_reset_device(int argc, char** argv);
65 /********************************************************
66 * slt.reconfig
67 * After reset device, set address command and getConfigure, setConfigure
68 * args:
69 *********************************************************/
70 /********************************************************
71 * slt.enable
72 * Attach device, send enable slot command
73 * args:
74 *********************************************************/
75 static int t_slot_enable_slot(int argc, char** argv);
76 /********************************************************
77 * slt.addslt
78 * Send address command to current slot
79 * args:
80 *********************************************************/
81 static int t_slot_address(int argc, char** argv);
82 /********************************************************
83 * slt.getdesc
84 * Do GetDescriptor control transfer
85 * args:
86 *********************************************************/
87 static int t_slot_getdescriptor(int argc, char** argv);
88 static int t_slot_forcegetdescriptor(int argc, char** argv);
89 static int t_slot_getbos(int argc, char** argv);
90 static int t_slot_setconf(int argc, char** argv);
91 static int t_slot_setu1u2(int argc, char** argv);
92 //static int t_slot_setsel(int argc, char** argv);
93 static int t_slot_getdevstatus(int argc, char** argv);
94 static int t_slt_resetport(int argc, char** argv);
95 //static int t_slot_stress_ctrl(int argc, char** argv);
96 /********************************************************
97 * slt.getdesc
98 * Wait device to desicon, disable slot
99 * args:
100 *********************************************************/
101 static int t_slot_discon(int argc, char** argv);
102 static int t_slot_evaluate_context(int argc, char** argv);
103 static int t_slt_ped(int argc, char** argv);
104 //loopback
105 static int t_loopback_loop(int argc, char** argv);
106 static int t_loopback_configep(int argc, char** argv);
107 static int t_loopback_deconfigep(int argc, char** argv);
108
109 /********************************************************
110 * pw.suspend
111 * suspend U2 device
112 * args:
113 *********************************************************/
114 static int t_power_suspend(int argc, char** argv);
115 /********************************************************
116 * pw.resume
117 * resume U2 device
118 * args:
119 *********************************************************/
120 static int t_power_resume(int argc, char** argv);
121 /********************************************************
122 * pw.wakeup
123 * When in suspend(U3) state, wait for device to wakeup
124 * After got remote wakeup signal, back to U0 state
125 * args:
126 *********************************************************/
127 static int t_power_remotewakeup(int argc, char** argv);
128 /********************************************************
129 * pw.u1u2
130 * Adjust U1/U2 timeout regs value
131 * args:
132 * 1. u?(1/2): 1=u1, 2=u2
133 * 2. value: u1(0~127, 255), u2(0~254, 255)
134 *********************************************************/
135 static int t_power_u1u2(int argc, char** argv);
136 static int t_power_suspendport(int argc, char** argv);
137 static int t_power_resumeport(int argc, char** argv);
138 static int t_power_fla(int argc, char** argv);
139 static int t_power_occ(int argc, char** argv);
140 static int t_power_u2_lpm(int argc, char** argv);
141 static int t_power_u2_swlpm(int argc, char** argv);
142 static int t_power_random_access_regs(int argc, char** argv);
143 /********************************************************
144 * ring.erfull
145 * Test event ring full error event
146 * args:
147 *********************************************************/
148 static int t_ring_er_full(int argc, char** argv);
149 /********************************************************
150 * ring.stopcmd
151 * Stop command ring
152 * args:
153 *********************************************************/
154 static int t_ring_stop_cmd(int argc, char** argv);
155 /********************************************************
156 * ring.abortcmd
157 * Abort command when executing address device command
158 * args:
159 *********************************************************/
160 static int t_ring_abort_cmd_add(int argc, char** argv);
161 static int t_ring_stop_ep(int argc, char** argv);
162 static int t_ring_random_ring_doorbell(int argc, char** argv);
163 static int t_ring_random_stop_ep(int argc, char** argv);
164 static int t_ring_enlarge(int argc, char** argv);
165 static int t_ring_shrink(int argc, char**argv);
166 static int t_ring_intr_moderation(int argc, char** argv);
167 static int t_ring_bei(int argc, char** argv);
168 static int t_ring_idt(int argc, char** argv);
169 static int t_ring_noop_transfer(int argc, char** argv);
170
171 static int t_u3auto_ctrl_loopback(int argc, char** argv);
172 static int t_u3auto_loopback(int argc, char** argv);
173 static int t_u3auto_loopback_scan(int argc, char** argv);
174 static int t_u3auto_loopback_sg(int argc, char** argv);
175 static int t_u3auto_loopback_scan_sg(int argc, char** argv);
176 static int t_u3auto_random_suspend(int argc, char** argv);
177 static int t_u3auto_random_wakeup(int argc, char**argv);
178 static int t_u3auto_randomstop_dev(int argc, char** argv);
179 static int t_u3auto_stress(int argc, char** argv);
180 static int t_u3auto_isoc_frame_id(int argc, char** argv);
181 static int t_u3auto_concurrent_remotewakeup(int argc, char** argv);
182 static int t_u3auto_concurrent_u1u2_enter(int argc, char** argv);
183 static int t_u3auto_concurrent_u1u2_exit(int argc, char** argv);
184
185 static int t_hub_configurehub(int argc, char** argv);
186 static int t_hub_configuresubhub(int argc, char** argv);
187 static int t_hub_configuredevice(int argc, char** argv);
188 static int t_hub_ixia_stress(int argc, char** argv);
189 static int t_hub_loop_stress(int argc, char** argv);
190 static int t_hub_loop(int argc, char** argv);
191 static int t_hub_reset_dev(int argc, char** argv);
192 static int t_hub_remotewakeup_dev(int argc, char** argv);
193 static int t_hub_selsuspend(int argc, char** argv);
194 static int t_hub_selresume(int argc, char** argv);
195 static int t_hub_configure_eth_device(int argc, char** argv);
196 static int t_hub_queue_intr(int argc, char** argv);
197 static int t_hub_set_u1u2(int argc, char** argv);
198 static int t_hub_force_pm(int argc, char** argv);
199
200 static int t_u3h_otg_dev_A_host(int argc,char** argv);
201 static int t_u3h_otg_dev_B_host(int argc,char** argv);
202 static int t_u3h_otg_dev_A_srp(int argc,char** argv);
203 static int t_u3h_otg_dev_A_hnp(int argc,char** argv);
204 static int t_u3h_otg_dev_A_hnp_back(int argc,char** argv);
205 static int t_u3h_otg_dev_B_hnp(int argc,char** argv);
206 static int t_u3h_otg_dev_B_hnp_back(int argc, char** argv);
207 static int t_u3h_otg_uut_A(int argc, char** argv);
208 static int t_u3h_otg_uut_B(int argc,char * * argv);
209 static int t_u3h_otg_pet_uutA(int argc, char** argv);
210 static int t_u3h_otg_pet_uutB(int argc, char** argv);
211
212 static int t_hcd_init(int argc, char** argv);
213 static int t_hcd_cleanup(int argc, char** argv);
214
215 static int t_drv_vbus(int argc, char** argv);
216 static int t_stop_vbus(int argc, char** argv);
217
218 static int t_start_host_test_mode(int argc, char** argv);
219 static int t_stop_host_test_mode(int argc, char** argv);
220
221 /********************************************************
222 * dbg.portstatus
223 * Print current port status register value
224 * args:
225 *********************************************************/
226 static int dbg_printportstatus(int argc, char** argv);
227 /********************************************************
228 * dbg.dbgslt
229 * Print current slot context content
230 * args:
231 *********************************************************/
232 static int dbg_printslotcontext(int argc, char** argv);
233 /********************************************************
234 * dbg.hccparams
235 * Print HCCPARAM values
236 * args:
237 *********************************************************/
238 static int dbg_printhccparams(int argc, char** argv);
239 /********************************************************
240 * dbg.r
241 * Print xhci related register value
242 * args:
243 * 1. address: offset
244 * 2. length
245 *********************************************************/
246 static int dbg_read_xhci(int argc, char** argv);
247 /********************************************************
248 * dbg.dr
249 * print all xhci registers
250 * args:
251 *********************************************************/
252 static int dbg_dump_regs(int argc, char** argv);
253
254 static int dbg_port_set_pls(int argc, char** argv);
255 static int dbg_port_set_ped(int argc, char** argv);
256 static int dbg_port_reset(int argc, char** argv);
257
258 static int dbg_delayms(int argc, char** argv);
259 static int dbg_u3w(int argc, char**argv);
260 static int dbg_u3r(int argc, char**argv);
261 static int dbg_u3PHY_init(int argc, char**argv);
262 static int dbg_u3_calibration(int argc, char** argv);
263 static int dbg_phy_eyescan(int argc, char** argv);
264 static int dbg_u2_testmode(int argc, char** argv);
265
266 static int dbg_u3ct_lecroy(int argc, char** argv);
267 static int dbg_u3ct_ellisys(int argc, char** argv);
268 static int dbg_u2ct(int argc, char** argv);
269
270 static int dbg_memorywrite(int argc, char** argv);
271 static int dbg_memoryread(int argc, char** argv);
272 static int dbg_sch_algorithm(int argc, char** argv);
273 static int dbg_reg_ewe(int argc, char** argv);
274
275 static int t_class_keyboard(int argc, char** argv);
276 static int t_ellysis_TD7_36(int argc, char** argv);
277
278 static int t_dev_config_ep(int argc,char * * argv);
279 static int t_dev_polling_status(int argc,char * * argv);
280 static int t_dev_query_status(int argc,char * * argv);
281 static int t_dev_remotewakeup(int argc,char * * argv);
282 static int t_dev_reset(int argc,char * * argv);
283 static int t_dev_init(int argc, char** argv);
284 static int t_dev_notification(int argc, char** argv);
285 static int t_dev_u1u2(int argc, char** argv);
286 static int t_dev_lpm(int argc, char** argv);
287
288
289 ////////////////////////////////////////////////////////////////////////////
290 // USBIF
291 //#define CLI_MAGIC 'CLI'
292 #define CLI_MAGIC 'CLI_MU3H'
293 #define IOCTL_READ _IOR(CLI_MAGIC, 0, int)
294 #define IOCTL_WRITE _IOW(CLI_MAGIC, 1, int)
295
296 #define BUF_SIZE 200
297 #define MAX_ARG_SIZE 20
298
299 #define DMA_BURST_SIZE_TEST
300
301 ////////////////////////////////////////////////////////////////////////////
302
303 int u2_initialize(int argc, char** argv);
304
305 ////////////////////////////////////////////////////////////////////////////
306
307 typedef struct
308 {
309 char name[256];
310 int (*cb_func)(int argc, char** argv);
311 } CMD_TBL_T;
312
313 CMD_TBL_T _arPCmdTbl_host[] =
314 {
315 {"hcd.init", &t_hcd_init},
316 {"hcd.cleanup", &t_hcd_cleanup},
317 {"hcd.drvvbus", &t_drv_vbus},
318 {"hcd.stopvbus", &t_stop_vbus},
319 {"hcd.starthosttestmode", &t_start_host_test_mode},
320 {"hcd.stophosttestmode", &t_stop_host_test_mode},
321 {"slt.discon", &t_slot_discon},
322 {"slt.disable", &t_slot_disable_slot},
323 {"slt.reset", &t_slot_reset_device},
324 {"slt.resetp", &t_slt_resetport},
325 {"slt.enable", &t_slot_enable_slot},
326 {"slt.addslt", &t_slot_address},
327 {"slt.getdesc", &t_slot_forcegetdescriptor},
328 {"slt.getbos", &t_slot_getbos},
329 {"slt.setconf", &t_slot_setconf},
330 {"slt.setu1u2", &t_slot_setu1u2},
331 {"slt.devstat", &t_slot_getdevstatus},
332 {"slt.evalctx", &t_slot_evaluate_context},
333 {"slt.ped", &t_slt_ped},
334 {"lb.config", &t_loopback_configep},
335 {"lb.deconfig", &t_loopback_deconfigep},
336 {"lb.loop", &t_loopback_loop},
337 {"pw.suspend", &t_power_suspend},
338 {"pw.suspendp", &t_power_suspendport},
339 {"pw.resume", &t_power_resume},
340 {"pw.resumep", &t_power_resumeport},
341 {"pw.wakeup", &t_power_remotewakeup},
342 {"pw.u1u2", &t_power_u1u2},
343 {"pw.fla", &t_power_fla},
344 {"pw.occ", &t_power_occ},
345 {"pw.lpm", &t_power_u2_lpm},
346 {"pw.swlpm", &t_power_u2_swlpm},
347 {"pw.rdnreg", &t_power_random_access_regs},
348 {"ring.erfull", &t_ring_er_full},
349 {"ring.stopcmd", &t_ring_stop_cmd},
350 {"ring.abortcmd", &t_ring_abort_cmd_add},
351 {"ring.stopep", &t_ring_stop_ep},
352 {"ring.rrd", &t_ring_random_ring_doorbell},
353 {"ring.rstp", &t_ring_random_stop_ep},
354 {"ring.enlarge", &t_ring_enlarge},
355 {"ring.shrink", &t_ring_shrink},
356 {"ring.intrmod", &t_ring_intr_moderation},
357 {"ring.bei", &t_ring_bei},
358 {"ring.idt", &t_ring_idt},
359 {"ring.noop", &t_ring_noop_transfer},
360 {"auto.lbctrl", &t_u3auto_ctrl_loopback},
361 {"auto.lb", &t_u3auto_loopback},
362 {"auto.lbscan", &t_u3auto_loopback_scan},
363 {"auto.lbsg", &t_u3auto_loopback_sg},
364 {"auto.lbsgscan", &t_u3auto_loopback_scan_sg},
365 {"auto.randomsuspend", &t_u3auto_random_suspend},
366 {"auto.randomwakeup", &t_u3auto_random_wakeup},
367 {"auto.devrandomstop", &t_u3auto_randomstop_dev},
368 {"auto.stress", &t_u3auto_stress},
369 {"auto.isofrm", &t_u3auto_isoc_frame_id},
370 {"auto.conresume", &t_u3auto_concurrent_remotewakeup},
371 {"auto.conu1u2", &t_u3auto_concurrent_u1u2_enter},
372 {"auto.conu1u2exit", &t_u3auto_concurrent_u1u2_exit},
373 {"hub.config", &t_hub_configurehub},
374 {"hub.subhub", &t_hub_configuresubhub},
375 {"hub.dev", &t_hub_configuredevice},
376 {"hub.ixia", &t_hub_ixia_stress},
377 {"hub.lbstress", &t_hub_loop_stress},
378 {"hub.loop", &t_hub_loop},
379 {"hub.reset", &t_hub_reset_dev},
380 {"hub.wakeup", &t_hub_remotewakeup_dev},
381 {"hub.selsuspend", &t_hub_selsuspend},
382 {"hub.selresume", &t_hub_selresume},
383 {"hub.deveth", &t_hub_configure_eth_device},
384 {"hub.intr", &t_hub_queue_intr},
385 {"hub.u1u2", &t_hub_set_u1u2},
386 {"hub.forcepm", &t_hub_force_pm},
387 {"otg.deva", &t_u3h_otg_dev_A_host},
388 {"otg.devb", &t_u3h_otg_dev_B_host},
389 {"otg.srp", &t_u3h_otg_dev_A_srp},
390 {"otg.hnpa", &t_u3h_otg_dev_A_hnp},
391 {"otg.hnpabackh", &t_u3h_otg_dev_A_hnp_back},
392 {"otg.hnpb", &t_u3h_otg_dev_B_hnp},
393 {"otg.hnpbbackd", &t_u3h_otg_dev_B_hnp_back},
394 //{"otg.uuta", &t_u3h_otg_uut_A},
395 //{"otg.uutb", &t_u3h_otg_uut_B},
396 {"otg.uuta", &t_u3h_otg_pet_uutA},
397 {"otg.uutb", &t_u3h_otg_pet_uutB},
398 {"dbg.portstatus", &dbg_printportstatus},
399 {"dbg.dbgslt", &dbg_printslotcontext},
400 {"dbg.hccparams", &dbg_printhccparams},
401 {"dbg.r", &dbg_read_xhci},
402 {"dbg.dr", &dbg_dump_regs},
403 {"dbg.setpls", &dbg_port_set_pls},
404 {"dbg.setped", &dbg_port_set_ped},
405 {"dbg.portreset", &dbg_port_reset},
406 {"dbg.mdelay", &dbg_delayms},
407 {"dbg.u3w", &dbg_u3w},
408 {"dbg.u3r", &dbg_u3r},
409 {"dbg.u3i", &dbg_u3PHY_init},
410 {"dbg.u3c", &dbg_u3_calibration},
411 {"dbg.u3eyescan", &dbg_phy_eyescan},
412 {"dbg.mw", &dbg_memorywrite},
413 {"dbg.mr", &dbg_memoryread},
414 {"dbg.kb", &t_ellysis_TD7_36},
415 {"dbg.sch", &dbg_sch_algorithm},
416 {"dbg.ewe", &dbg_reg_ewe},
417 {"dbg.u2t", &dbg_u2_testmode},
418 {"dbg.u3lect", &dbg_u3ct_lecroy},
419 {"dbg.u3elct", &dbg_u3ct_ellisys},
420 {"dbg.u2ct", &dbg_u2ct},
421 {"dev.reset", &t_dev_reset},
422 {"dev.pollstatus", &t_dev_polling_status},
423 {"dev.qrystatus", &t_dev_query_status},
424 {"dev.configep", &t_dev_config_ep},
425 {"dev.wakeup", &t_dev_remotewakeup},
426 {"dev.note", &t_dev_notification},
427 {"dev.u1u2", &t_dev_u1u2},
428 {"dev.lpm", &t_dev_lpm},
429 {"dev.init", &t_dev_init},
430 {NULL, NULL}
431 };
432
433 ////////////////////////////////////////////////////////////////////////////
434
435 char w_buf_host[BUF_SIZE];
436 char r_buf_host[BUF_SIZE] = "this is a test";
437
438 ////////////////////////////////////////////////////////////////////////////
439
440 int call_function_host(char *buf)
441 {
442 int i;
443 int argc;
444 char *argv[MAX_ARG_SIZE];
445
446 argc = 0;
447 do
448 {
449 argv[argc] = strsep(&buf, " ");
450 mtk_test_dbg( "[%d] %s\r\n", argc, argv[argc]);
451 argc++;
452 } while (buf);
453
454 for (i = 0; i < sizeof(_arPCmdTbl_host)/sizeof(CMD_TBL_T); i++)
455 {
456 if ((!strcmp(_arPCmdTbl_host[i].name, argv[0])) && (_arPCmdTbl_host[i].cb_func != NULL))
457 return _arPCmdTbl_host[i].cb_func(argc, argv);
458 }
459
460 return -1;
461 }
462
463 struct numsection
464 {
465 int min;
466 int max;
467 int current_value;
468 struct numsection *next;
469 };
470
471 struct numsection *init_num_sec(int min, int max){
472 struct numsection *tmp;
473 tmp = kmalloc(sizeof(struct numsection), GFP_NOIO);
474 tmp->min = min;
475 tmp->max = max;
476 tmp->current_value = min;
477 tmp->next = NULL;
478 return tmp;
479 }
480
481 void clear_num_secs(struct numsection *num_sec){
482 struct numsection *next;
483 struct numsection *cur;
484 cur = num_sec;
485 while(cur != NULL){
486 next = cur->next;
487 kfree(cur);
488 cur = next;
489 }
490 }
491
492 void add_num_sec(int min, int max, struct numsection *sec){
493 struct numsection *tmp, *cur;
494 cur = sec;
495 while(cur->next != NULL){
496 cur = cur->next;
497 }
498 tmp = kmalloc(sizeof(struct numsection), GFP_NOIO);
499 tmp->min = min;
500 tmp->max = max;
501 tmp->current_value = min;
502 tmp->next = NULL;
503 cur->next = tmp;
504 }
505
506 struct numsection *find_next_num(struct numsection *sec){
507 struct numsection *cur;
508 cur = sec;
509 cur->current_value++;
510 if(cur->current_value > cur->max){
511 cur->current_value = cur->min;
512 cur = cur->next;
513 }
514 return cur;
515 }
516
517 static int xhci_mtk_test_open(struct inode *inode, struct file *file)
518 {
519
520 mtk_test_dbg( "xhci_mtk_test open: successful\n");
521 return 0;
522 }
523
524 static int xhci_mtk_test_release(struct inode *inode, struct file *file)
525 {
526
527 mtk_test_dbg( "xhci_mtk_test release: successful\n");
528 return 0;
529 }
530
531 static ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
532 {
533
534 mtk_test_dbg( "xhci_mtk_test read: returning zero bytes\n");
535 return 0;
536 }
537
538 static ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
539 {
540
541 mtk_test_dbg( "xhci_mtk_test write: accepting zero bytes\n");
542 return 0;
543 }
544
545 static int xhci_mtk_test_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
546 {
547
548 int len = BUF_SIZE;
549
550 switch (cmd) {
551 case IOCTL_READ:
552 copy_to_user((char *) arg, r_buf_host, len);
553 mtk_test_dbg( "IOCTL_READ: %s\r\n", r_buf_host);
554 break;
555 case IOCTL_WRITE:
556 copy_from_user(w_buf_host, (char *) arg, len);
557 mtk_test_dbg( "IOCTL_WRITE: %s\r\n", w_buf_host);
558
559 //invoke function
560 return call_function_host(w_buf_host);
561 break;
562 default:
563 return -ENOTTY;
564 }
565
566 return len;
567 }
568
569 static int xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
570 {
571
572 int len = BUF_SIZE;
573
574 switch (cmd) {
575 case IOCTL_READ:
576 copy_to_user((char *) arg, r_buf_host, len);
577 mtk_test_dbg( "IOCTL_READ: %s\r\n", r_buf_host);
578 break;
579 case IOCTL_WRITE:
580 copy_from_user(w_buf_host, (char *) arg, len);
581 mtk_test_dbg( "IOCTL_WRITE: %s\r\n", w_buf_host);
582
583 //invoke function
584 return call_function_host(w_buf_host);
585 break;
586 default:
587 return -ENOTTY;
588 }
589
590 return len;
591 }
592
593
594 static void print_slot_state(int slot_state){
595 switch (slot_state) {
596 case 0:
597 mtk_test_dbg( "slot state: enabled/disabled\n");
598 break;
599 case 1:
600 mtk_test_dbg( "slot state: default\n");
601 break;
602 case 2:
603 mtk_test_dbg( "slot state: addressed\n");
604 break;
605 case 3:
606 mtk_test_dbg( "slot state: configured\n");
607 break;
608 default:
609 mtk_test_dbg( "slot state: reserved\n");
610 break;
611 }
612 }
613
614 static int t_hcd_init(int argc, char** argv){
615 return f_test_lib_init();
616 }
617
618 static int t_hcd_cleanup(int argc, char** argv){
619 return f_test_lib_cleanup();
620 }
621
622 void framecount_disabe(){
623 writel(0x01, 0xf1270944);
624 mtk_test_dbg("disable frame counter\n");
625 }
626
627 void framecount_enable(){
628 writel(0x00, 0xf1270944);
629 mtk_test_dbg("enable frame counter\n");
630 }
631 int u3auto_hcd_reset(void)
632 {
633 if(f_test_lib_init() != RET_SUCCESS)
634 return RET_FAIL;
635
636 #if 0
637 framecount_disabe();
638 #endif
639
640 if(f_enable_port(0) != RET_SUCCESS)
641 return RET_FAIL;
642 if(f_enable_slot(NULL) != RET_SUCCESS)
643 return RET_FAIL;
644
645 #if 0
646 msleep(1000);
647 framecount_enable();
648 msleep(30);
649 #endif
650
651 if(f_address_slot(false, NULL) != RET_SUCCESS)
652 return RET_FAIL;
653
654 }
655
656 static int t_slot_discon(int argc, char** argv){
657 int ret;
658
659 ret = f_disconnect_port(0);
660 if(ret != RET_SUCCESS){
661 return RET_FAIL;
662 }
663 ret = f_disable_slot();
664 if(ret != RET_SUCCESS){
665 return RET_FAIL;
666 }
667 }
668
669 static int t_slot_disable_slot(int argc, char** argv){
670 int ret;
671 struct xhci_hcd *xhci;
672 ret = 0;
673 if(my_hcd == NULL){
674 mtk_test_dbg( "[ERROR]host controller driver not initiated\n");
675 return RET_FAIL;
676 }
677 xhci = hcd_to_xhci(my_hcd);
678
679 ret = f_disable_slot();
680
681 if(ret != RET_SUCCESS){
682 return RET_FAIL;
683 }
684 return RET_SUCCESS;
685 }
686
687 static int t_slot_evaluate_context(int argc, char** argv){
688 int ret;
689 int max_exit_latency, maxp0, preping_mode, preping;
690 int besld, besl;
691
692 ret = 0;
693 max_exit_latency = 0;
694 maxp0 = 64;
695 preping_mode = 0;
696 preping = 0;
697
698 if(my_hcd == NULL){
699 mtk_test_dbg( "[ERROR]host controller driver not initiated\n");
700 return RET_FAIL;
701 }
702 if(argc > 1){
703 max_exit_latency = (int)simple_strtol(argv[1], &argv[1], 10);
704 }
705 if(argc > 2){
706 maxp0 = (int)simple_strtol(argv[2], &argv[2], 10);
707 }
708 if(argc > 3){
709 preping_mode = (int)simple_strtol(argv[3], &argv[3], 10);
710 }
711 if(argc > 4){
712 preping = (int)simple_strtol(argv[4], &argv[4], 10);
713 }
714 if(argc > 5){
715 besl = (int)simple_strtol(argv[5], &argv[5], 10);
716 }
717 if(argc > 6){
718 besld = (int)simple_strtol(argv[6], &argv[6], 10);
719 }
720 ret = f_evaluate_context(max_exit_latency, maxp0, preping_mode, preping, besl, besld);
721
722 if(ret != RET_SUCCESS){
723 return RET_FAIL;
724 }
725 return RET_SUCCESS;
726 }
727
728 static int t_slot_getbos(int argc, char** argv){
729 int ret;
730 struct usb_device *udev, *rhdev;
731 struct xhci_virt_device *virt_dev;
732 struct xhci_hcd *xhci;
733 struct urb *urb;
734 struct usb_ctrlrequest *dr;
735 void *buf;
736 short *tmp_length, total_length;
737 ret = 0;
738
739 if(g_slot_id == 0){
740 mtk_test_dbg( "[ERROR] slot ID not valid\n");
741 return RET_FAIL;
742 }
743
744 xhci = hcd_to_xhci(my_hcd);
745 rhdev = my_hcd->self.root_hub;
746 udev = rhdev->children[g_port_id-1];
747
748 //get total length in bos
749 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
750 dr->bRequestType = USB_DIR_IN;
751 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
752 dr->wValue = cpu_to_le16((USB_DT_BOS << 8) + 0);
753 dr->wIndex = cpu_to_le16(0);
754 dr->wLength = cpu_to_le16(USB_DT_BOS_SIZE);
755 buf = kmalloc(USB_DT_BOS_SIZE, GFP_KERNEL);
756 memset(buf, 0, USB_DT_BOS_SIZE);
757
758 urb = alloc_ctrl_urb(dr, buf, udev);
759 ret = f_ctrlrequest(urb,udev);
760
761 tmp_length = urb->transfer_buffer+2;
762 total_length = *tmp_length;
763 xhci_dbg(xhci, "total_length: %d\n", total_length);
764
765 kfree(dr);
766 kfree(buf);
767 usb_free_urb(urb);
768 // kfree(urb);
769
770 //get bos
771 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
772 dr->bRequestType = USB_DIR_IN;
773 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
774 dr->wValue = cpu_to_le16((USB_DT_BOS << 8) + 0);
775 dr->wIndex = cpu_to_le16(0);
776 dr->wLength = cpu_to_le16(total_length);
777 buf = kmalloc(total_length, GFP_KERNEL);
778 memset(buf, 0 , total_length);
779 urb = alloc_ctrl_urb(dr, buf, udev);
780 ret = f_ctrlrequest(urb,udev);
781 kfree(dr);
782 kfree(buf);
783 usb_free_urb(urb);
784 // kfree(urb);
785 return ret;
786 }
787
788 static int t_slot_forcegetdescriptor(int argc, char** argv){
789 int ret;
790 struct usb_device *udev, *rhdev;
791 struct xhci_virt_device *virt_dev;
792 struct xhci_hcd *xhci;
793 struct urb *urb;
794 struct usb_ctrlrequest *dr;
795 struct usb_config_descriptor *desc;
796 int i;
797 char *tmp;
798 ret = 0;
799
800 if(g_slot_id == 0){
801 mtk_test_dbg( "[ERROR] slot ID not valid\n");
802 return RET_FAIL;
803 }
804
805 xhci = hcd_to_xhci(my_hcd);
806 rhdev = my_hcd->self.root_hub;
807 udev = rhdev->children[g_port_id-1];
808
809 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
810 dr->bRequestType = USB_DIR_IN;
811 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
812 dr->wValue = cpu_to_le16((USB_DT_DEVICE << 8) + 0);
813 dr->wIndex = cpu_to_le16(0);
814 dr->wLength = cpu_to_le16(USB_DT_DEVICE_SIZE);
815 desc = kmalloc(USB_DT_DEVICE_SIZE, GFP_KERNEL);
816 memset(desc, 0, USB_DT_DEVICE_SIZE);
817
818 urb = alloc_ctrl_urb(dr, desc, udev);
819 ret = f_ctrlrequest(urb, udev);
820 if(urb->status == -EINPROGRESS){
821 //timeout, stop endpoint, set TR dequeue pointer
822 f_ring_stop_ep(g_slot_id, 0);
823 f_ring_set_tr_dequeue_pointer(g_slot_id, 0, urb);
824 }
825 kfree(dr);
826 kfree(desc);
827 usb_free_urb(urb);
828 // kfree(urb);
829
830 return ret;
831 }
832
833 static int t_slot_getdescriptor(int argc, char** argv){
834 int ret;
835 struct usb_device *udev, *rhdev;
836 struct xhci_virt_device *virt_dev;
837 struct xhci_hcd *xhci;
838 struct urb *urb;
839 struct usb_ctrlrequest *dr;
840 struct usb_config_descriptor *desc;
841 int i;
842 char *tmp;
843 ret = 0;
844
845 if(g_slot_id == 0){
846 mtk_test_dbg( "[ERROR] slot ID not valid\n");
847 return RET_FAIL;
848 }
849
850 xhci = hcd_to_xhci(my_hcd);
851 rhdev = my_hcd->self.root_hub;
852 udev = rhdev->children[g_port_id-1];
853
854 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
855 dr->bRequestType = USB_DIR_IN;
856 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
857 dr->wValue = cpu_to_le16((USB_DT_DEVICE << 8) + 0);
858 dr->wIndex = cpu_to_le16(0);
859 dr->wLength = cpu_to_le16(USB_DT_DEVICE_SIZE);
860 desc = kmalloc(USB_DT_DEVICE_SIZE, GFP_KERNEL);
861 memset(desc, 0, USB_DT_DEVICE_SIZE);
862
863 urb = alloc_ctrl_urb(dr, desc, udev);
864 ret = f_ctrlrequest(urb, udev);
865
866 kfree(dr);
867 kfree(desc);
868 usb_free_urb(urb);
869 // kfree(urb);
870
871 return ret;
872 }
873
874 static int t_slot_setconf(int argc, char** argv){
875 int ret;
876 struct usb_device *udev, *rhdev;
877 struct xhci_virt_device *virt_dev;
878 struct xhci_hcd *xhci;
879 struct urb *urb;
880 struct usb_ctrlrequest *dr;
881 int i;
882 char *tmp;
883 char isConfigMouse;
884 ret = 0;
885
886 isConfigMouse = false;
887
888 if(g_slot_id == 0){
889 mtk_test_dbg( "[ERROR] slot ID not valid\n");
890 return RET_FAIL;
891 }
892
893 if(argc > 1){
894 if(!strcmp(argv[1], "mouse")){
895 isConfigMouse = true;
896 }
897 }
898
899 xhci = hcd_to_xhci(my_hcd);
900 rhdev = my_hcd->self.root_hub;
901 udev = rhdev->children[g_port_id-1];
902
903 if(isConfigMouse){
904 //config mouse for Ellysis T7.36 test case
905 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
906 dr->bRequestType = 0x21;
907 dr->bRequest = 0x0a;
908 dr->wValue = cpu_to_le16(0);
909 dr->wIndex = cpu_to_le16(0);
910 dr->wLength = cpu_to_le16(0);
911 urb = alloc_ctrl_urb(dr, NULL, udev);
912 ret = f_ctrlrequest(urb,udev);
913 kfree(dr);
914 usb_free_urb(urb);
915 }
916 else{
917 //set configuration
918 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
919 dr->bRequestType = USB_DIR_OUT;
920 dr->bRequest = USB_REQ_SET_CONFIGURATION;
921 dr->wValue = cpu_to_le16(1);
922 dr->wIndex = cpu_to_le16(0);
923 dr->wLength = cpu_to_le16(0);
924 urb = alloc_ctrl_urb(dr, NULL, udev);
925 ret = f_ctrlrequest(urb,udev);
926 kfree(dr);
927 usb_free_urb(urb);
928 }
929 // kfree(urb);
930 return ret;
931 }
932
933 static int t_slot_setu1u2(int argc, char** argv){
934 int ret;
935 struct usb_device *udev, *rhdev;
936 struct xhci_virt_device *virt_dev;
937 struct xhci_hcd *xhci;
938 struct urb *urb;
939 struct usb_ctrlrequest *dr;
940 struct usb_config_descriptor *desc;
941 int i;
942 char *tmp;
943 ret = 0;
944
945 if(g_slot_id == 0){
946 mtk_test_dbg( "[ERROR] slot ID not valid\n");
947 return RET_FAIL;
948 }
949
950 xhci = hcd_to_xhci(my_hcd);
951 rhdev = my_hcd->self.root_hub;
952 udev = rhdev->children[g_port_id-1];
953
954 //set feature - u1 enable
955 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
956 dr->bRequestType = USB_DIR_OUT;
957 dr->bRequest = USB_REQ_SET_FEATURE;
958 dr->wValue = cpu_to_le16(USB_U1_ENABLE);
959 dr->wIndex = cpu_to_le16(0);
960 dr->wLength = cpu_to_le16(0);
961 urb = alloc_ctrl_urb(dr, NULL, udev);
962 ret = f_ctrlrequest(urb,udev);
963
964 // kfree(urb);
965 usb_free_urb(urb);
966 kfree(dr);
967
968 //set feature - u2 enable
969 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
970 dr->bRequestType = USB_DIR_OUT;
971 dr->bRequest = USB_REQ_SET_FEATURE;
972 dr->wValue = cpu_to_le16(USB_U2_ENABLE);
973 dr->wIndex = cpu_to_le16(0);
974 dr->wLength = cpu_to_le16(0);
975 urb = alloc_ctrl_urb(dr, NULL, udev);
976 ret = f_ctrlrequest(urb,udev);
977
978 kfree(dr);
979 usb_free_urb(urb);
980 // kfree(urb);
981 return ret;
982 }
983
984 static int t_slot_getdevstatus(int argc, char** argv){
985 int ret;
986 struct usb_device *udev, *rhdev;
987 struct xhci_virt_device *virt_dev;
988 struct xhci_hcd *xhci;
989 struct urb *urb;
990 struct usb_ctrlrequest *dr;
991 struct usb_config_descriptor *desc;
992 int i;
993 char *tmp;
994 ret = 0;
995
996 if(g_slot_id == 0){
997 mtk_test_dbg( "[ERROR] slot ID not valid\n");
998 return RET_FAIL;
999 }
1000
1001 xhci = hcd_to_xhci(my_hcd);
1002 rhdev = my_hcd->self.root_hub;
1003 udev = rhdev->children[g_port_id-1];
1004
1005 //get status
1006 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
1007 dr->bRequestType = USB_DIR_IN;
1008 dr->bRequest = USB_REQ_GET_STATUS;
1009 dr->wValue = cpu_to_le16(0);
1010 dr->wIndex = cpu_to_le16(0);
1011 dr->wLength = cpu_to_le16(USB_DT_STATUS_SIZE);
1012 desc = kmalloc(USB_DT_STATUS_SIZE, GFP_KERNEL);
1013 urb = alloc_ctrl_urb(dr, desc, udev);
1014 ret = f_ctrlrequest(urb,udev);
1015 kfree(dr);
1016 kfree(desc);
1017 usb_free_urb(urb);
1018 // kfree(urb);
1019 return ret;
1020 }
1021
1022 static int t_slt_resetport(int argc, char** argv){
1023 u32 __iomem *addr;
1024 int temp;
1025 int port_id;
1026 char isWarmReset;
1027 struct xhci_hcd *xhci;
1028
1029 port_id = g_port_id;
1030 isWarmReset = false;
1031
1032 if(argc > 1){
1033 if(!strcmp(argv[1], "true")){
1034 mtk_test_dbg( "Do Warm Reset\n");
1035 isWarmReset = true;
1036 }
1037 }
1038 if(argc > 2){
1039 port_id = (int)simple_strtol(argv[2], &argv[2], 10);
1040 }
1041
1042 xhci = hcd_to_xhci(my_hcd);
1043
1044 if(isWarmReset){
1045 //do warm reset
1046 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
1047 temp = xhci_readl(xhci, addr);
1048 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
1049 temp = mtktest_xhci_port_state_to_neutral(temp);
1050 temp = (temp | PORT_WR);
1051 xhci_writel(xhci, temp, addr);
1052 temp = xhci_readl(xhci, addr);
1053 xhci_dbg(xhci, "after reset port %d = 0x%x\n", port_id-1, temp);
1054
1055 }
1056 else{
1057 //hot reset port
1058 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
1059 temp = xhci_readl(xhci, addr);
1060 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
1061 temp = mtktest_xhci_port_state_to_neutral(temp);
1062 temp = (temp | PORT_RESET);
1063 xhci_writel(xhci, temp, addr);
1064 }
1065 }
1066
1067 static int t_slt_ped(int argc, char** argv){
1068 struct xhci_hcd *xhci;
1069 u32 __iomem *addr;
1070 int temp;
1071 int ret;
1072
1073 xhci = hcd_to_xhci(my_hcd);
1074 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(g_port_id-1 & 0xff);
1075 temp = xhci_readl(xhci, addr);
1076 temp |= PORT_PE;
1077 xhci_writel(xhci, temp, addr);
1078 ret = f_disconnect_port(0);
1079 if(ret != RET_SUCCESS){
1080 return RET_FAIL;
1081 }
1082 ret = f_disable_slot();
1083 if(ret != RET_SUCCESS){
1084 return RET_FAIL;
1085 }
1086 return ret;
1087 }
1088
1089 /* simply address a slot */
1090 static int t_slot_address(int argc, char** argv){
1091 int ret;
1092 char isBSR;
1093
1094 isBSR = false;
1095 if(argc > 1){
1096 if(!strcmp(argv[1], "true")){
1097 mtk_test_dbg( "test BSR=true\n");
1098 isBSR = true;
1099 }
1100 }
1101
1102 return f_address_slot(isBSR, NULL);
1103 }
1104
1105 static int t_slot_enable_slot(int argc, char** argv){
1106 char isEnablePort;
1107 isEnablePort = true;
1108 if(argc > 1){
1109 if(!strcmp(argv[1], "false")){
1110 mtk_test_dbg( "test BSR=true\n");
1111 isEnablePort = false;
1112 }
1113 }
1114 if(isEnablePort){
1115 if(f_enable_port(0) != RET_SUCCESS){
1116 return RET_FAIL;
1117 }
1118 }
1119 return f_enable_slot(NULL);
1120 }
1121
1122 static int t_slot_reset_device(int argc, char** argv){
1123 char isWarmReset;
1124 isWarmReset = false;
1125
1126 if(argc > 1){
1127 if(!strcmp(argv[1], "true")){
1128 mtk_test_dbg( "test WarmReset=true\n");
1129 isWarmReset = true;
1130 }
1131 }
1132 return f_slot_reset_device(0, isWarmReset);
1133
1134 }
1135
1136 static int t_u3auto_ctrl_loopback(int argc, char** argv){
1137 int ret,loop,length,num=0;
1138 char isFullSpeed, isReset;
1139
1140 isFullSpeed = false;
1141 ret = 0;
1142 num = 1;
1143 length = 8;
1144 isReset = false;
1145 if(argc > 1){
1146 num = (int)simple_strtol(argv[1], &argv[1], 10);
1147 }
1148 if(argc > 2){
1149 length = (int)simple_strtol(argv[2], &argv[2], 10);
1150 }
1151 if(argc > 3){
1152 if(!strcmp(argv[3], "ss")){
1153 mtk_test_dbg( "test super speed\n");
1154 isFullSpeed = false;
1155 }
1156 if(!strcmp(argv[3], "hs")){
1157 mtk_test_dbg( "test high speed\n");
1158 isFullSpeed = false;
1159 }
1160 if(!strcmp(argv[3], "fs")){
1161 mtk_test_dbg( "Test full speed\n");
1162 isFullSpeed = true;
1163 }
1164 }
1165 if(argc > 4){
1166 if(!strcmp(argv[4], "true")){
1167 mtk_test_dbg( "Reset device\n");
1168 isReset = true;
1169 }
1170 }
1171 #if 0
1172 if(u3auto_hcd_reset() != RET_SUCCESS)
1173 return RET_FAIL;
1174 #endif
1175 if(isFullSpeed && isReset){
1176 start_port_reenabled(0, DEV_SPEED_FULL);
1177
1178 ret=dev_reset(DEV_SPEED_FULL,NULL);
1179 if(ret){
1180 mtk_test_dbg( "Set device to full speed failed!!\n");
1181 return RET_FAIL;
1182 }
1183
1184 ret = f_disable_slot();
1185 if(ret){
1186 mtk_test_dbg( "disable slot failed!!\n");
1187 return RET_FAIL;
1188 }
1189
1190 ret = f_reenable_port(0);
1191 if(ret){
1192 mtk_test_dbg( "reenable port failed!!\n");
1193 return RET_FAIL;
1194 }
1195
1196 ret = f_enable_slot(NULL);
1197 if(ret){
1198 mtk_test_dbg( "enable slot failed!!\n");
1199 return RET_FAIL;
1200 }
1201
1202 ret=f_address_slot(false, NULL);
1203 if(ret){
1204 mtk_test_dbg( "address device failed!!\n");
1205 return RET_FAIL;
1206 }
1207 }
1208
1209 //num = 0, loop forever
1210 //num = 1, follow the length that user input
1211 //num != 1, loopback incremental length data
1212 int max_length = 2048;
1213 if(num == 0){
1214 for(length=1; length <= max_length;){
1215 mtk_test_dbg( "Do CTRL loopback, length %d\n", length);
1216 ret=dev_ctrl_loopback(length,NULL);
1217
1218
1219 if(ret)
1220 {
1221 mtk_test_dbg( "ctrl loop fail!!\n");
1222 mtk_test_dbg( "length : %d\n",length);
1223 break;
1224 }
1225 length = length + 1;
1226 }
1227 }
1228 else{
1229 for(loop=0;loop<num;loop++){
1230 if(num != 1){
1231 length=((((loop+1)*102400)+loop*40)%2048);
1232 }
1233
1234 if(!length){
1235 length=2048;
1236 }
1237 mtk_test_dbg( "Do CTRL loopback, length %d\n", length);
1238 ret=dev_ctrl_loopback(length,NULL);
1239
1240 if(ret)
1241 {
1242 mtk_test_dbg( "ctrl loop fail!!\n");
1243 mtk_test_dbg( "length : %d\n",length);
1244 break;
1245 }
1246
1247 }
1248 }
1249 if(ret){
1250 mtk_test_dbg( "[FAIL] Ctrl loop back test failed\n");
1251 }
1252 else{
1253 mtk_test_dbg( "[PASS] ctrl loop back [%d] round\n",num);
1254 }
1255 return ret;
1256 }
1257
1258 #define SG_SS_BULK_INTERVAL_SIZE 1
1259 #define SG_SS_BULK_MAXP_SIZE 1
1260 #define SG_SS_BULK_OUT_EP_SIZE 1
1261 #define SG_SS_BULK_IN_EP_SIZE 1
1262 #define SG_SS_BULK_SG_LEN_SIZE 4
1263 #define SG_SS_BULK_BURST_SIZE 1
1264 #define SG_SS_BULK_MULT_SIZE 1
1265
1266 #define SG_SS_INTR_INTERVAL_SIZE 1
1267 #define SG_SS_INTR_MAXP_SIZE 1
1268 #define SG_SS_INTR_OUT_EP_SIZE 1
1269 #define SG_SS_INTR_IN_EP_SIZE 1
1270 #define SG_SS_INTR_SG_LEN_SIZE 3
1271 #define SG_SS_INTR_BURST_SIZE 1
1272 #define SG_SS_INTR_MULT_SIZE 1
1273
1274 #define SG_HS_BULK_INTERVAL_SIZE 1
1275 #define SG_HS_BULK_MAXP_SIZE 1
1276 #define SG_HS_BULK_OUT_EP_SIZE 1
1277 #define SG_HS_BULK_IN_EP_SIZE 1
1278 #define SG_HS_BULK_SG_LEN_SIZE 4
1279
1280 #define SG_HS_INTR_INTERVAL_SIZE 1
1281 #define SG_HS_INTR_MAXP_SIZE 1
1282 #define SG_HS_INTR_OUT_EP_SIZE 1
1283 #define SG_HS_INTR_IN_EP_SIZE 1
1284 #define SG_HS_INTR_SG_LEN_SIZE 3
1285
1286 #define SG_FS_BULK_INTERVAL_SIZE 1
1287 #define SG_FS_BULK_MAXP_SIZE 1
1288 #define SG_FS_BULK_OUT_EP_SIZE 1
1289 #define SG_FS_BULK_IN_EP_SIZE 1
1290 #define SG_FS_BULK_SG_LEN_SIZE 4
1291
1292 #define SG_FS_INTR_INTERVAL_SIZE 1
1293 #define SG_FS_INTR_MAXP_SIZE 1
1294 #define SG_FS_INTR_OUT_EP_SIZE 1
1295 #define SG_FS_INTR_IN_EP_SIZE 1
1296 #define SG_FS_INTR_SG_LEN_SIZE 3
1297
1298 #define DF_BURST_SIZE 1 //default for hs, fs
1299 #define DF_MULT_SIZE 1 //default for hs, fs
1300
1301 static int t_u3auto_loopback_scan_sg(int argc, char** argv){
1302 int ret,length,start_add;
1303 char bdp;
1304 int gpd_buf_size,bd_buf_size;
1305 int transfer_type;
1306 int maxp;
1307 int bInterval;
1308 int sg_len;
1309 int ep_out_num, ep_in_num;
1310 int speed;
1311 int start_add_index, ep_out_index, ep_in_index, maxp_index, interval_index, sg_len_index, mult_index, burst_index;
1312 int interval_arr_size, maxp_arr_size, out_ep_arr_size, in_ep_arr_size, sg_len_arr_size, mult_arr_size, burst_arr_size;
1313 int min_length, max_length, min_start_add, max_start_add;
1314 int *arr_interval, *arr_maxp, *arr_ep_out, *arr_ep_in, *arr_sg_len, *arr_mult, *arr_burst;
1315 int mult_dev, burst, mult;
1316 int dram_offset, extension;
1317 struct numsection *sec, *cur_sec;
1318
1319 int sg_ss_bulk_interval[SG_SS_BULK_INTERVAL_SIZE] = {0};
1320 int sg_ss_bulk_maxp[SG_SS_BULK_MAXP_SIZE] = {1024};
1321 int sg_ss_bulk_out_ep[SG_SS_BULK_OUT_EP_SIZE] = {1};
1322 int sg_ss_bulk_in_ep[SG_SS_BULK_IN_EP_SIZE] = {1};
1323 int sg_ss_bulk_sg_len[SG_SS_BULK_SG_LEN_SIZE] = {512, 1024, 2048, 4096};
1324 int sg_ss_bulk_burst[SG_SS_BULK_BURST_SIZE] = {15};
1325 int sg_ss_bulk_mult[SG_SS_BULK_MULT_SIZE] = {0};
1326
1327 int sg_ss_intr_interval[SG_SS_INTR_INTERVAL_SIZE] = {1};
1328 int sg_ss_intr_maxp[SG_SS_INTR_MAXP_SIZE] = {1024};
1329 int sg_ss_intr_out_ep[SG_SS_INTR_OUT_EP_SIZE] = {1};
1330 int sg_ss_intr_in_ep[SG_SS_INTR_IN_EP_SIZE] = {1};
1331 int sg_ss_intr_sg_len[SG_SS_INTR_SG_LEN_SIZE] = {64,512,1024};
1332 int sg_ss_intr_burst[SG_SS_INTR_BURST_SIZE] = {0/*,1,2*/};
1333 int sg_ss_intr_mult[SG_SS_INTR_MULT_SIZE] = {0};
1334
1335 int sg_hs_bulk_interval[SG_HS_BULK_INTERVAL_SIZE] = {0};
1336 int sg_hs_bulk_maxp[SG_HS_BULK_MAXP_SIZE] = {512};
1337 int sg_hs_bulk_out_ep[SG_HS_BULK_OUT_EP_SIZE] = {1};
1338 int sg_hs_bulk_in_ep[SG_HS_BULK_IN_EP_SIZE] = {1};
1339 int sg_hs_bulk_sg_len[SG_HS_BULK_SG_LEN_SIZE] = {512, 1024, 2048, 4096};
1340
1341 int sg_hs_intr_interval[SG_HS_INTR_INTERVAL_SIZE] = {1};
1342 int sg_hs_intr_maxp[SG_HS_INTR_MAXP_SIZE] = {1024}; //32, 512, 1024
1343 int sg_hs_intr_out_ep[SG_HS_INTR_OUT_EP_SIZE] = {2};
1344 int sg_hs_intr_in_ep[SG_HS_INTR_IN_EP_SIZE] = {2};
1345 int sg_hs_intr_sg_len[SG_HS_INTR_SG_LEN_SIZE] = {64, 512, 1024};
1346
1347 int sg_fs_bulk_interval[SG_FS_BULK_INTERVAL_SIZE] = {0};
1348 int sg_fs_bulk_maxp[SG_FS_BULK_MAXP_SIZE] = {64};
1349 int sg_fs_bulk_out_ep[SG_FS_BULK_OUT_EP_SIZE] = {1};
1350 int sg_fs_bulk_in_ep[SG_FS_BULK_IN_EP_SIZE] = {1};
1351 int sg_fs_bulk_sg_len[SG_FS_BULK_SG_LEN_SIZE] = {64, 512, 1024, 2048};
1352
1353 int sg_fs_intr_interval[SG_FS_INTR_INTERVAL_SIZE] = {1};// 1, 127,255
1354 int sg_fs_intr_maxp[SG_FS_INTR_MAXP_SIZE] = {32}; //8, 32, 64
1355 int sg_fs_intr_out_ep[SG_FS_INTR_OUT_EP_SIZE] = {2};
1356 int sg_fs_intr_in_ep[SG_FS_INTR_IN_EP_SIZE] = {2};
1357 int sg_fs_intr_sg_len[SG_FS_INTR_SG_LEN_SIZE] = {64,512,1024};
1358
1359 int df_burst[DF_BURST_SIZE] = {0};
1360 int df_mult[DF_MULT_SIZE] = {0};
1361
1362 ret = 0;
1363 speed = DEV_SPEED_HIGH;;
1364 transfer_type = EPATT_BULK;
1365 maxp = 512;
1366 bInterval = 0;
1367 ep_out_num = 1;
1368 ep_in_num = 1;
1369 length = 65535;
1370 mult_dev = 3;
1371 mult = 0;
1372 burst = 8;
1373 dram_offset = 0;
1374 extension = 0;
1375
1376 if(argc > 1){
1377 if(!strcmp(argv[1], "ss")){
1378 mtk_test_dbg( "Test super speed\n");
1379 speed = DEV_SPEED_SUPER; //TODO: superspeed
1380 }
1381 else if(!strcmp(argv[1], "hs")){
1382 mtk_test_dbg( "Test high speed\n");
1383 speed = DEV_SPEED_HIGH;
1384 }
1385 else if(!strcmp(argv[1], "fs")){
1386 mtk_test_dbg( "Test full speed\n");
1387 speed = DEV_SPEED_FULL;
1388 }
1389 }
1390 if(argc > 2){
1391 if(!strcmp(argv[2], "bulk")){
1392 mtk_test_dbg( "Test bulk transfer\n");
1393 transfer_type = EPATT_BULK;
1394 }
1395 else if(!strcmp(argv[2], "intr")){
1396 mtk_test_dbg( "Test intr transfer\n");
1397 transfer_type = EPATT_INT;
1398 }
1399 else if(!strcmp(argv[2], "isoc")){
1400 mtk_test_dbg( "Test isoc transfer\n");
1401 transfer_type = EPATT_ISO;
1402 }
1403 }
1404
1405 if(speed == DEV_SPEED_SUPER && transfer_type == EPATT_BULK){
1406 arr_maxp = sg_ss_bulk_maxp;
1407 maxp_arr_size = SG_SS_BULK_MAXP_SIZE;
1408 arr_interval = sg_ss_bulk_interval;
1409 interval_arr_size = SG_SS_BULK_INTERVAL_SIZE;
1410 //length 1~65535
1411 sec = init_num_sec(513, 1025);
1412 add_num_sec(10240-10, 10240+10,sec);
1413 add_num_sec(65535-10,65535,sec);
1414 //start_add 0~63
1415 min_start_add = 0;
1416 max_start_add = 0;
1417 arr_ep_out = sg_ss_bulk_out_ep;
1418 out_ep_arr_size = SG_SS_BULK_OUT_EP_SIZE;
1419 arr_ep_in = sg_ss_bulk_in_ep;
1420 in_ep_arr_size = SG_SS_BULK_IN_EP_SIZE;
1421
1422 //sg_len
1423 arr_sg_len = sg_ss_bulk_sg_len;
1424 sg_len_arr_size = SG_SS_BULK_SG_LEN_SIZE;
1425
1426 arr_burst = sg_ss_bulk_burst;
1427 burst_arr_size = SG_SS_BULK_BURST_SIZE;
1428 arr_mult = sg_ss_bulk_mult;
1429 mult_arr_size = SG_SS_BULK_MULT_SIZE;
1430 }
1431
1432 if(speed == DEV_SPEED_SUPER && transfer_type == EPATT_INT){
1433 arr_maxp = sg_ss_intr_maxp;
1434 maxp_arr_size = SG_SS_INTR_MAXP_SIZE;
1435 arr_interval = sg_ss_intr_interval;
1436 interval_arr_size = SG_SS_INTR_INTERVAL_SIZE;
1437 //length 1~65535
1438 sec = init_num_sec(513, 1025);
1439 add_num_sec(10240-10, 10240+10,sec);
1440 add_num_sec(65535-10,65535,sec);
1441 //start_add 0
1442 min_start_add = 0;
1443 max_start_add = 0;
1444 arr_ep_out = sg_ss_intr_out_ep;
1445 out_ep_arr_size = SG_SS_INTR_OUT_EP_SIZE;
1446 arr_ep_in = sg_ss_intr_in_ep;
1447 in_ep_arr_size = SG_SS_INTR_IN_EP_SIZE;
1448
1449 //sg_len
1450 arr_sg_len = sg_ss_intr_sg_len;
1451 sg_len_arr_size = SG_SS_INTR_SG_LEN_SIZE;
1452
1453 arr_burst = sg_ss_intr_burst;
1454 burst_arr_size = SG_SS_INTR_BURST_SIZE;
1455 arr_mult = sg_ss_intr_mult;
1456 mult_arr_size = SG_SS_INTR_MULT_SIZE;
1457 }
1458
1459 if(speed == DEV_SPEED_HIGH && transfer_type == EPATT_BULK){
1460 arr_maxp = sg_hs_bulk_maxp;
1461 maxp_arr_size = SG_HS_BULK_MAXP_SIZE;
1462 arr_interval = sg_hs_bulk_interval;
1463 interval_arr_size = SG_HS_BULK_INTERVAL_SIZE;
1464 //length 4096~65535
1465 sec = init_num_sec(1,513);
1466 add_num_sec(10240-10,10240+10,sec);
1467 add_num_sec(65535-10,65535,sec);
1468 //start_add 0~63
1469 min_start_add = 0;
1470 max_start_add = 0;
1471 //ep_out_num 1~15
1472 arr_ep_out = sg_hs_bulk_out_ep;
1473 out_ep_arr_size = SG_HS_BULK_OUT_EP_SIZE;
1474 //ep_in_num 1~15
1475 arr_ep_in = sg_hs_bulk_in_ep;
1476 in_ep_arr_size = SG_HS_BULK_IN_EP_SIZE;
1477 //sg_len
1478 arr_sg_len = sg_hs_bulk_sg_len;
1479 sg_len_arr_size = SG_HS_BULK_SG_LEN_SIZE;
1480
1481 //burst & mult all default value
1482 arr_burst = df_burst;
1483 burst_arr_size = DF_BURST_SIZE;
1484 arr_mult = df_mult;
1485 mult_arr_size = DF_MULT_SIZE;
1486 }
1487 if(speed == DEV_SPEED_HIGH && transfer_type == EPATT_INT){
1488 arr_maxp = sg_hs_intr_maxp;
1489 maxp_arr_size = SG_HS_INTR_MAXP_SIZE;
1490 arr_interval = sg_hs_intr_interval;
1491 interval_arr_size = SG_HS_INTR_INTERVAL_SIZE;
1492 //length 1~2048
1493 sec = init_num_sec(1, 1025);
1494 add_num_sec(10240-10, 10240+10,sec);
1495 //start_add 0~63
1496 min_start_add = 0;
1497 max_start_add = 0;
1498 //ep_out_num 1,8,15
1499 arr_ep_out = sg_hs_intr_out_ep;
1500 out_ep_arr_size = SG_HS_INTR_OUT_EP_SIZE;
1501 //ep_in_num 1,8,15
1502 arr_ep_in = sg_hs_intr_in_ep;
1503 in_ep_arr_size = SG_HS_INTR_IN_EP_SIZE;
1504 //sg_len
1505 arr_sg_len = sg_hs_intr_sg_len;
1506 sg_len_arr_size = SG_HS_INTR_SG_LEN_SIZE;
1507
1508 //burst & mult all default value
1509 arr_burst = df_burst;
1510 burst_arr_size = DF_BURST_SIZE;
1511 arr_mult = df_mult;
1512 mult_arr_size = DF_MULT_SIZE;
1513 }
1514 if(speed == DEV_SPEED_FULL && transfer_type == EPATT_BULK){
1515 arr_maxp = sg_fs_bulk_maxp;
1516 maxp_arr_size = SG_FS_BULK_MAXP_SIZE;
1517 arr_interval = sg_fs_bulk_interval;
1518 interval_arr_size = SG_FS_BULK_INTERVAL_SIZE;
1519 //length 4096~10241
1520 sec = init_num_sec(513, 1025);
1521 add_num_sec(10240-10, 10240+10,sec);
1522 add_num_sec(65535-10,65535,sec);
1523 //start_add 0~63
1524 min_start_add = 0;
1525 max_start_add = 0;
1526 //ep_out_num 1~15
1527 arr_ep_out = sg_fs_bulk_out_ep;
1528 out_ep_arr_size = SG_FS_BULK_OUT_EP_SIZE;
1529 //ep_in_num 1~15
1530 arr_ep_in = sg_fs_bulk_in_ep;
1531 in_ep_arr_size = SG_FS_BULK_IN_EP_SIZE;
1532 //sg_len
1533 arr_sg_len = sg_fs_bulk_sg_len;
1534 sg_len_arr_size = SG_FS_BULK_SG_LEN_SIZE;
1535
1536 //burst & mult all default value
1537 arr_burst = df_burst;
1538 burst_arr_size = DF_BURST_SIZE;
1539 arr_mult = df_mult;
1540 mult_arr_size = DF_MULT_SIZE;
1541
1542 }
1543 if(speed == DEV_SPEED_FULL && transfer_type == EPATT_INT){
1544 arr_maxp = sg_fs_intr_maxp;
1545 maxp_arr_size = SG_FS_INTR_MAXP_SIZE;
1546 arr_interval = sg_fs_intr_interval;
1547 interval_arr_size = SG_FS_INTR_INTERVAL_SIZE;
1548 //length 1024~4097
1549 sec = init_num_sec(1, 1025);
1550 add_num_sec(2048-10, 2048+10,sec);
1551 add_num_sec(3072-10, 3072+10,sec);
1552 //start_add 0~63
1553 min_start_add = 0;
1554 max_start_add = 0;
1555 //ep_out_num 1,8,15
1556 arr_ep_out = sg_fs_intr_out_ep;
1557 out_ep_arr_size = SG_FS_INTR_OUT_EP_SIZE;
1558 //ep_in_num 1,8,15
1559 arr_ep_in = sg_fs_intr_in_ep;
1560 in_ep_arr_size = SG_FS_INTR_IN_EP_SIZE;
1561 //sg_len
1562 arr_sg_len = sg_fs_intr_sg_len;
1563 sg_len_arr_size = SG_FS_INTR_SG_LEN_SIZE;
1564
1565 //burst & mult all default value
1566 arr_burst = df_burst;
1567 burst_arr_size = DF_BURST_SIZE;
1568 arr_mult = df_mult;
1569 mult_arr_size = DF_MULT_SIZE;
1570 }
1571 #if 0
1572 if(u3auto_hcd_reset() != RET_SUCCESS)
1573 return RET_FAIL;
1574 #endif
1575 for(ep_in_index = 0; ep_in_index < in_ep_arr_size; ep_in_index++){
1576 ep_in_num = *(arr_ep_in + ep_in_index);
1577 for(ep_out_index = 0; ep_out_index < out_ep_arr_size; ep_out_index++){
1578 ep_out_num = *(arr_ep_out + ep_out_index);
1579 for(interval_index = 0; interval_index < interval_arr_size; interval_index++){
1580 bInterval = *(arr_interval + interval_index);
1581 for(maxp_index = 0; maxp_index < maxp_arr_size; maxp_index++){
1582 maxp = *(arr_maxp + maxp_index);
1583 for(mult_index = 0; mult_index < mult_arr_size; mult_index++){
1584 mult = *(arr_mult+mult_index);
1585 for(burst_index = 0; burst_index < burst_arr_size; burst_index++){
1586 burst = *(arr_burst+burst_index);
1587 mtk_test_dbg( "[TEST]*************************************\n");
1588 mtk_test_dbg( " OUT_EP: %d***************************\n", ep_out_num);
1589 mtk_test_dbg( " IN_EP: %d ***************************\n", ep_in_num);
1590 mtk_test_dbg( " MAXP: %d ***************************\n", maxp);
1591 mtk_test_dbg( " INTERVAL: %d ***************************\n", bInterval);
1592 mtk_test_dbg( " MULT: %d **************************\n", mult);
1593 mtk_test_dbg( " BURST: %d *************************\n", burst);
1594 /* ==phase 0 : device reset==*/
1595 start_port_reenabled(0, speed);
1596 ret=dev_reset(speed,NULL);
1597 if(ret){
1598 mtk_test_dbg( "device reset failed!!!!!!!!!!\n");
1599 return ret;
1600 }
1601
1602 ret = f_disable_slot();
1603 if(ret){
1604 mtk_test_dbg( "disable slot failed!!!!!!!!!!\n");
1605 return ret;
1606 }
1607
1608 ret = f_reenable_port(0);
1609 if(ret != RET_SUCCESS){
1610 mtk_test_dbg( "device reenable failed!!!!!!!!!!\n");
1611 return ret;
1612 }
1613
1614 ret = f_enable_slot(NULL);
1615 if(ret){
1616 mtk_test_dbg( "enable slot failed!!!!!!!!!!\n");
1617 return ret;
1618 }
1619
1620 ret=f_address_slot(false, NULL);
1621 if(ret){
1622 mtk_test_dbg( "address slot failed!!!!!!!!!!\n");
1623 return ret;
1624 }
1625 mtktest_mtk_xhci_scheduler_init();
1626 /* ==phase 1 : config EP==*/
1627 ret=dev_config_ep(ep_out_num,USB_RX,transfer_type,maxp,bInterval,mult_dev,burst,mult,NULL);
1628 if(ret)
1629 {
1630 mtk_test_dbg( "config dev EP fail!!\n");
1631 return ret;
1632 }
1633
1634 ret=dev_config_ep(ep_in_num,USB_TX,transfer_type,maxp,bInterval,mult_dev,burst,mult,NULL);
1635 if(ret)
1636 {
1637 mtk_test_dbg( "config dev EP fail!!\n");
1638 return ret;
1639 }
1640
1641 ret = f_config_ep(ep_out_num,EPADD_OUT,transfer_type,maxp,bInterval,burst,mult, NULL,0);
1642 if(ret)
1643 {
1644 mtk_test_dbg( "config EP fail!!\n");
1645 return ret;
1646 }
1647
1648 ret = f_config_ep(ep_in_num,EPADD_IN,transfer_type,maxp,bInterval,burst,mult, NULL,1);
1649 if(ret)
1650 {
1651 mtk_test_dbg( "config EP fail!!\n");
1652 return ret;
1653 }
1654
1655 for(start_add = min_start_add; start_add <= max_start_add; start_add++){
1656 cur_sec = sec;
1657 while(cur_sec != NULL){
1658 length = cur_sec->current_value;
1659 for(sg_len_index = 0; sg_len_index < sg_len_arr_size; sg_len_index++){
1660 sg_len = *(arr_sg_len + sg_len_index);
1661 if((length/sg_len) > 61)
1662 continue;
1663 mtk_test_dbg( " [ROUND]**************************\n");
1664 mtk_test_dbg( " START_ADD: %d*************\n", start_add);
1665 mtk_test_dbg( " LENGTH: %d *************\n", length);
1666 mtk_test_dbg( " SG_LEN: %d *************\n", sg_len);
1667 /* ==phase 2 : loopback==*/
1668 bdp=1;
1669 gpd_buf_size=length;
1670 bd_buf_size=4096;
1671
1672 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size, dram_offset, extension,NULL);
1673 if(ret)
1674 {
1675 mtk_test_dbg( "loopback request fail!!\n");
1676 f_power_suspend();
1677 return ret;
1678 }
1679
1680 // ret = f_loopback_sg_loop(
1681 // ep_out_num, ep_in_num, length, start_add, sg_len, NULL);
1682 ret = f_loopback_sg_loop_gpd(
1683 ep_out_num,ep_in_num,length,start_add,sg_len, gpd_buf_size,NULL);
1684 if(ret)
1685 {
1686 mtk_test_dbg( "loopback fail!!\n");
1687 mtk_test_dbg( "length : %d\n",length);
1688 return ret;
1689 }
1690
1691 /* ==phase 3: get device status==*/
1692 ret=dev_polling_status(NULL);
1693 if(ret)
1694 {
1695 f_power_suspend();
1696 mtk_test_dbg( "query request fail!!\n");
1697 return ret;
1698 }
1699 } //sg_num
1700 cur_sec = find_next_num(cur_sec);
1701 } //length
1702 } //start_add
1703 } //burst
1704 } //mult
1705 } //maxp
1706 } //interval
1707 } //ep_out
1708 } //ep_in
1709 return ret;
1710 }
1711
1712 #define SS_BULK_INTERVAL_SIZE 1
1713 #define SS_BULK_MAXP_SIZE 1
1714 #define SS_BULK_OUT_EP_SIZE 1
1715 #define SS_BULK_IN_EP_SIZE 1
1716 #define SS_BULK_BURST_SIZE 2
1717 #define SS_BULK_MULT_SIZE 1
1718
1719 #define SS_INTR_INTERVAL_SIZE 2
1720 #define SS_INTR_MAXP_SIZE 2
1721 #define SS_INTR_OUT_EP_SIZE 1
1722 #define SS_INTR_IN_EP_SIZE 1
1723 #define SS_INTR_BURST_SIZE 1
1724 #define SS_INTR_MULT_SIZE 1
1725
1726 #define SS_HB_INTR_INTERVAL_SIZE 1
1727 #define SS_HB_INTR_MAXP_SIZE 1
1728 #define SS_HB_INTR_OUT_EP_SIZE 1
1729 #define SS_HB_INTR_IN_EP_SIZE 1
1730 #define SS_HB_INTR_BURST_SIZE 2
1731 #define SS_HB_INTR_MULT_SIZE 1
1732
1733 #define SS_ISOC_INTERVAL_SIZE 2
1734 #define SS_ISOC_MAXP_SIZE 2
1735 #define SS_ISOC_OUT_EP_SIZE 1
1736 #define SS_ISOC_IN_EP_SIZE 1
1737 #define SS_ISOC_BURST_SIZE 1
1738 #define SS_ISOC_MULT_SIZE 1
1739
1740 #define SS_HB_ISOC_INTERVAL_SIZE 2
1741 #define SS_HB_ISOC_MAXP_SIZE 1
1742 #define SS_HB_ISOC_OUT_EP_SIZE 1
1743 #define SS_HB_ISOC_IN_EP_SIZE 1
1744 #define SS_HB_ISOC_BURST_SIZE 2
1745 #define SS_HB_ISOC_MULT_SIZE 2
1746
1747 #define HS_BULK_INTERVAL_SIZE 1
1748 #define HS_BULK_MAXP_SIZE 1
1749 #define HS_BULK_OUT_EP_SIZE 1
1750 #define HS_BULK_IN_EP_SIZE 1
1751
1752 #define HS_INTR_INTERVAL_SIZE 2
1753 #define HS_INTR_MAXP_SIZE 4
1754 #define HS_INTR_OUT_EP_SIZE 1
1755 #define HS_INTR_IN_EP_SIZE 1
1756
1757 #define HS_HB_INTR_INTERVAL_SIZE 2
1758 #define HS_HB_INTR_MAXP_SIZE 1
1759 #define HS_HB_INTR_OUT_EP_SIZE 1
1760 #define HS_HB_INTR_IN_EP_SIZE 1
1761 #define HS_HB_INTR_MULT_SIZE 2
1762
1763 #define HS_ISOC_INTERVAL_SIZE 2
1764 #define HS_ISOC_MAXP_SIZE 2
1765 #define HS_ISOC_OUT_EP_SIZE 1
1766 #define HS_ISOC_IN_EP_SIZE 1
1767
1768 #define HS_HB_ISOC_INTERVAL_SIZE 2
1769 #define HS_HB_ISOC_MAXP_SIZE 1
1770 #define HS_HB_ISOC_OUT_EP_SIZE 1
1771 #define HS_HB_ISOC_IN_EP_SIZE 1
1772 #define HS_HB_ISOC_MULT_SIZE 2
1773
1774 #define FS_BULK_INTERVAL_SIZE 1
1775 #define FS_BULK_MAXP_SIZE 3
1776 #define FS_BULK_OUT_EP_SIZE 1
1777 #define FS_BULK_IN_EP_SIZE 1
1778
1779 #define FS_INTR_INTERVAL_SIZE 2
1780 #define FS_INTR_MAXP_SIZE 4
1781 #define FS_INTR_OUT_EP_SIZE 1
1782 #define FS_INTR_IN_EP_SIZE 1
1783
1784 #define FS_ISOC_INTERVAL_SIZE 2
1785 #define FS_ISOC_MAXP_SIZE 2
1786 #define FS_ISOC_OUT_EP_SIZE 1
1787 #define FS_ISOC_IN_EP_SIZE 1
1788
1789 #define DF_BURST_SIZE 1 //default for hs, fs
1790 #define DF_MULT_SIZE 1 //default for hs, fs
1791
1792
1793 static int t_u3auto_loopback_scan(int argc, char** argv){
1794 int ret,length,start_add;
1795 char bdp;
1796 int gpd_buf_size,bd_buf_size;
1797 int transfer_type;
1798 int maxp;
1799 int bInterval;
1800 int ep_out_num, ep_in_num;
1801 int speed;
1802 int start_add_index, ep_out_index, ep_in_index, maxp_index, interval_index, burst_index, mult_index;
1803 int interval_arr_size, maxp_arr_size, out_ep_arr_size, in_ep_arr_size, burst_arr_size, mult_arr_size;
1804 int min_length, max_length, min_start_add, max_start_add;
1805 int *arr_interval, *arr_maxp, *arr_ep_out, *arr_ep_in, *arr_burst, *arr_mult;
1806 int mult_dev, mult, burst;
1807 int dram_offset, extension;
1808 struct numsection *sec, *cur_sec;
1809 char isHB;
1810 #ifdef DMA_BURST_SIZE_TEST
1811 int dma_burst_sz = 0;
1812 int dma_tmp = 0;
1813 #endif
1814
1815 int ss_bulk_interval[SS_BULK_INTERVAL_SIZE] = {0};
1816 int ss_bulk_maxp[SS_BULK_MAXP_SIZE] = {1024};
1817 int ss_bulk_out_ep[SS_BULK_OUT_EP_SIZE] = {1/*,2*/};
1818 int ss_bulk_in_ep[SS_BULK_IN_EP_SIZE] = {1/*,2*/};
1819 int ss_bulk_burst[SS_BULK_BURST_SIZE] = {0,15,/*0*/};
1820 int ss_bulk_mult[SS_BULK_MULT_SIZE] = {0};
1821
1822 int ss_intr_interval[SS_INTR_INTERVAL_SIZE] = {1, 2/*, 16*/};
1823 int ss_intr_maxp[SS_INTR_MAXP_SIZE] = {8, /*32, 128, 512, */1024};
1824 int ss_intr_out_ep[SS_INTR_OUT_EP_SIZE] = {1};
1825 int ss_intr_in_ep[SS_INTR_IN_EP_SIZE] = {1};
1826 int ss_intr_burst[SS_INTR_BURST_SIZE] = {0};
1827 int ss_intr_mult[SS_INTR_MULT_SIZE] = {0};
1828
1829 int ss_hb_intr_interval[SS_HB_INTR_INTERVAL_SIZE] = {1};
1830 int ss_hb_intr_maxp[SS_HB_INTR_MAXP_SIZE] = {1024};
1831 int ss_hb_intr_out_ep[SS_HB_INTR_OUT_EP_SIZE] = {1};
1832 int ss_hb_intr_in_ep[SS_HB_INTR_IN_EP_SIZE] = {1};
1833 int ss_hb_intr_burst[SS_HB_INTR_BURST_SIZE] = {1,2};
1834 int ss_hb_intr_mult[SS_HB_INTR_MULT_SIZE] = {0};
1835
1836 int ss_isoc_interval[SS_ISOC_INTERVAL_SIZE] = {1, 2/*, 16*/};
1837 int ss_isoc_maxp[SS_ISOC_MAXP_SIZE] = {/*64, 512, */64,1024};
1838 int ss_isoc_out_ep[SS_ISOC_OUT_EP_SIZE] = {1};
1839 int ss_isoc_in_ep[SS_ISOC_IN_EP_SIZE] = {1};
1840 int ss_isoc_burst[SS_ISOC_BURST_SIZE] = {0};
1841 int ss_isoc_mult[SS_ISOC_MULT_SIZE] = {0};
1842
1843 int ss_hb_isoc_interval[SS_HB_ISOC_INTERVAL_SIZE] = {1, 2};
1844 int ss_hb_isoc_maxp[SS_HB_ISOC_MAXP_SIZE] = {1024};
1845 int ss_hb_isoc_out_ep[SS_HB_ISOC_OUT_EP_SIZE] = {1};
1846 int ss_hb_isoc_in_ep[SS_HB_ISOC_IN_EP_SIZE] = {1};
1847 int ss_hb_isoc_burst[SS_HB_ISOC_BURST_SIZE] = {/*0,*/1,2};
1848 int ss_hb_isoc_mult[SS_HB_ISOC_MULT_SIZE] = {0,1/*,2*/};
1849
1850 int hs_bulk_interval[HS_BULK_INTERVAL_SIZE] = {0};
1851 int hs_bulk_maxp[HS_BULK_MAXP_SIZE] = {512};
1852 int hs_bulk_out_ep[HS_BULK_OUT_EP_SIZE] = {1};
1853 int hs_bulk_in_ep[HS_BULK_IN_EP_SIZE] = {1};
1854
1855 int hs_intr_interval[HS_INTR_INTERVAL_SIZE] = {1/*,7*/,2}; //0,8,15
1856 int hs_intr_maxp[HS_INTR_MAXP_SIZE] = {6, 8, 30/*,32,128,512*/,1024}; //8,16,128,512, 1024, 2048, 3072
1857 int hs_intr_out_ep[HS_INTR_OUT_EP_SIZE] = {1};
1858 int hs_intr_in_ep[HS_INTR_IN_EP_SIZE] = {1};
1859
1860 int hs_hb_intr_interval[HS_HB_INTR_INTERVAL_SIZE] = {1/*,7*/,2}; //0,8,15
1861 int hs_hb_intr_maxp[HS_HB_INTR_MAXP_SIZE] = {1024}; //8,16,128,512, 1024, 2048, 3072
1862 int hs_hb_intr_out_ep[HS_HB_INTR_OUT_EP_SIZE] = {1};
1863 int hs_hb_intr_in_ep[HS_HB_INTR_IN_EP_SIZE] = {1};
1864 int hs_hb_intr_mult[HS_HB_INTR_MULT_SIZE] = {1,2};
1865
1866 int hs_isoc_interval[HS_ISOC_INTERVAL_SIZE] = {1,2};
1867 int hs_isoc_maxp[HS_ISOC_MAXP_SIZE] = {/*8,32,*/128,/*512,*/1024};
1868 int hs_isoc_out_ep[HS_ISOC_OUT_EP_SIZE] = {1};
1869 int hs_isoc_in_ep[HS_ISOC_IN_EP_SIZE] = {1};
1870
1871 int hs_hb_isoc_interval[HS_HB_ISOC_INTERVAL_SIZE] = {1,2};
1872 int hs_hb_isoc_maxp[HS_HB_ISOC_MAXP_SIZE] = {1024};
1873 int hs_hb_isoc_out_ep[HS_HB_ISOC_OUT_EP_SIZE] = {1};
1874 int hs_hb_isoc_in_ep[HS_HB_ISOC_IN_EP_SIZE] = {1};
1875 int hs_hb_isoc_mult[HS_HB_ISOC_MULT_SIZE] = {1,2};
1876
1877 int fs_bulk_interval[FS_BULK_INTERVAL_SIZE] = {0};
1878 int fs_bulk_maxp[FS_BULK_MAXP_SIZE] = {8/*,16*/,32,64}; // 8,16,32,64
1879 int fs_bulk_out_ep[FS_BULK_OUT_EP_SIZE] = {1};
1880 int fs_bulk_in_ep[FS_BULK_IN_EP_SIZE] = {1};
1881
1882 int fs_intr_interval[FS_INTR_INTERVAL_SIZE] = {1, 2}; //1, 127 ,255
1883 int fs_intr_maxp[FS_INTR_MAXP_SIZE] = {6, 8, 30,/*32,*/64}; // 8,32,64
1884 int fs_intr_out_ep[FS_INTR_OUT_EP_SIZE] = {1};
1885 int fs_intr_in_ep[FS_INTR_IN_EP_SIZE] = {1};
1886
1887 int fs_isoc_interval[FS_ISOC_INTERVAL_SIZE] = {1, 2};
1888 int fs_isoc_maxp[FS_ISOC_MAXP_SIZE] = {/*8,32,*/128,1023};
1889 int fs_isoc_out_ep[FS_ISOC_OUT_EP_SIZE] = {1};
1890 int fs_isoc_in_ep[FS_ISOC_IN_EP_SIZE] = {1};
1891
1892 int df_burst[DF_BURST_SIZE] = {0};
1893 int df_mult[DF_MULT_SIZE] = {0};
1894
1895 ret = 0;
1896 speed = DEV_SPEED_HIGH;;
1897 transfer_type = EPATT_BULK;
1898 maxp = 512;
1899 bInterval = 0;
1900 ep_out_num = 1;
1901 ep_in_num = 1;
1902 isHB = false;
1903 length = 65535;
1904 mult_dev = 3;
1905 mult = 0;
1906 burst = 8;
1907 dram_offset = 0;
1908 extension = 0;
1909
1910 if(argc > 1){
1911 if(!strcmp(argv[1], "ss")){
1912 mtk_test_dbg( "Test super speed\n");
1913 speed = DEV_SPEED_SUPER;
1914 }
1915 else if(!strcmp(argv[1], "hs")){
1916 mtk_test_dbg( "Test high speed\n");
1917 speed = DEV_SPEED_HIGH;
1918 }
1919 else if(!strcmp(argv[1], "fs")){
1920 mtk_test_dbg( "Test full speed\n");
1921 speed = DEV_SPEED_FULL;
1922 }
1923 }
1924 if(argc > 2){
1925 if(!strcmp(argv[2], "bulk")){
1926 mtk_test_dbg( "Test bulk transfer\n");
1927 transfer_type = EPATT_BULK;
1928 }
1929 else if(!strcmp(argv[2], "intr")){
1930 mtk_test_dbg( "Test intr transfer\n");
1931 transfer_type = EPATT_INT;
1932 }
1933 else if(!strcmp(argv[2], "isoc")){
1934 mtk_test_dbg( "Test isoc transfer\n");
1935 transfer_type = EPATT_ISO;
1936 }
1937 }
1938 if(argc > 3){
1939 if(!strcmp(argv[3], "true")){
1940 mtk_test_dbg( "Test high bandwidth\n");
1941 isHB = true;
1942 }
1943 else{
1944 mtk_test_dbg( "Doesn't test high bandwidth\n");
1945 isHB = false;
1946 }
1947 }
1948 if(speed == DEV_SPEED_SUPER && transfer_type == EPATT_BULK){
1949 arr_maxp = ss_bulk_maxp;
1950 maxp_arr_size = SS_BULK_MAXP_SIZE;
1951 arr_interval = ss_bulk_interval;
1952 interval_arr_size = SS_BULK_INTERVAL_SIZE;
1953 //1~1025, 10240+-512, 65535-1024~65535
1954 #if 1
1955 sec = init_num_sec(1,1025);
1956 add_num_sec(10240-10,10240+10,sec);
1957 add_num_sec(65535-10,65535,sec);
1958 #endif
1959 // sec = init_num_sec(1025,1027);
1960 //start_add 0~63
1961 min_start_add = 0;
1962 max_start_add = 0;
1963 arr_ep_out = ss_bulk_out_ep;
1964 out_ep_arr_size = SS_BULK_OUT_EP_SIZE;
1965 arr_ep_in = ss_bulk_in_ep;
1966 in_ep_arr_size = SS_BULK_IN_EP_SIZE;
1967 arr_burst = ss_bulk_burst;
1968 burst_arr_size = SS_BULK_BURST_SIZE;
1969 arr_mult = ss_bulk_mult;
1970 mult_arr_size = SS_BULK_MULT_SIZE;
1971 }
1972 if(speed == DEV_SPEED_SUPER && transfer_type == EPATT_INT && (!isHB)){
1973 arr_maxp = ss_intr_maxp;
1974 maxp_arr_size = SS_INTR_MAXP_SIZE;
1975 arr_interval = ss_intr_interval;
1976 interval_arr_size = SS_INTR_INTERVAL_SIZE;
1977 //length 1~1025,10241-1024~10241
1978 #if 1
1979 sec = init_num_sec(1,1025);
1980 add_num_sec(2048-10,2048+10, sec);
1981 add_num_sec(3072-10,3072+10, sec);
1982 add_num_sec(10240-10,10240+10,sec);
1983 #else
1984 sec = init_num_sec(1023,1027);
1985 #endif
1986 //start_add 0
1987 min_start_add = 0;
1988 max_start_add = 0;
1989 arr_ep_out = ss_intr_out_ep;
1990 out_ep_arr_size = SS_INTR_OUT_EP_SIZE;
1991 arr_ep_in = ss_intr_in_ep;
1992 in_ep_arr_size = SS_INTR_IN_EP_SIZE;
1993 arr_burst = ss_intr_burst;
1994 burst_arr_size = SS_INTR_BURST_SIZE;
1995 arr_mult = ss_intr_mult;
1996 mult_arr_size = SS_INTR_MULT_SIZE;
1997 }
1998 if(speed == DEV_SPEED_SUPER && transfer_type == EPATT_INT && isHB){
1999 arr_maxp = ss_hb_intr_maxp;
2000 maxp_arr_size = SS_HB_INTR_MAXP_SIZE;
2001 arr_interval = ss_hb_intr_interval;
2002 interval_arr_size = SS_HB_INTR_INTERVAL_SIZE;
2003 //length 1~1025,10241-1024~10241
2004 #if 1
2005 sec = init_num_sec(1,1025);
2006 add_num_sec(2048-10,2048+10, sec);
2007 add_num_sec(3072-10,3072+10, sec);
2008 add_num_sec(10241-3,10241,sec);
2009 #else
2010 sec = init_num_sec(1023,1027);
2011 #endif
2012 //start_add 0
2013 min_start_add = 0;
2014 max_start_add = 0;
2015 arr_ep_out = ss_hb_intr_out_ep;
2016 out_ep_arr_size = SS_HB_INTR_OUT_EP_SIZE;
2017 arr_ep_in = ss_hb_intr_in_ep;
2018 in_ep_arr_size = SS_HB_INTR_IN_EP_SIZE;
2019 arr_burst = ss_hb_intr_burst;
2020 burst_arr_size = SS_HB_INTR_BURST_SIZE;
2021 arr_mult = ss_hb_intr_mult;
2022 mult_arr_size = SS_HB_INTR_MULT_SIZE;
2023 }
2024 if(speed == DEV_SPEED_SUPER && transfer_type == EPATT_ISO && (!isHB)){
2025 arr_maxp = ss_isoc_maxp;
2026 maxp_arr_size = SS_ISOC_MAXP_SIZE;
2027 arr_interval = ss_isoc_interval;
2028 interval_arr_size = SS_ISOC_INTERVAL_SIZE;
2029 //length 1~1025, 10241-1024~10241, 65535-1024~65535
2030 //sec = init_num_sec(9217, 9225);
2031 #if 1
2032 sec = init_num_sec(1,3);
2033 add_num_sec(1024-3,1024+3,sec);
2034 //sec = init_num_sec(1023,1025);
2035 add_num_sec(10241-3,10241,sec);
2036 //add_num_sec(65535-3,65535,sec);
2037 #else
2038 sec = init_num_sec(1024*48-1,1024*48+1);
2039 #endif
2040 //start_add 0
2041 min_start_add = 0;
2042 max_start_add = 0;
2043 arr_ep_out = ss_isoc_out_ep;
2044 out_ep_arr_size = SS_ISOC_OUT_EP_SIZE;
2045 arr_ep_in = ss_isoc_in_ep;
2046 in_ep_arr_size = SS_ISOC_IN_EP_SIZE;
2047 arr_burst = ss_isoc_burst;
2048 burst_arr_size = SS_ISOC_BURST_SIZE;
2049 arr_mult = ss_isoc_mult;
2050 mult_arr_size = SS_ISOC_MULT_SIZE;
2051 }
2052 if(speed == DEV_SPEED_SUPER && transfer_type == EPATT_ISO && isHB){
2053 arr_maxp = ss_hb_isoc_maxp;
2054 maxp_arr_size = SS_HB_ISOC_MAXP_SIZE;
2055 arr_interval = ss_hb_isoc_interval;
2056 interval_arr_size = SS_HB_ISOC_INTERVAL_SIZE;
2057 //length 1~1025, 10241-1024~10241, 65535-1024~65535
2058 //sec = init_num_sec(9217, 9225);
2059 #if 1
2060 sec = init_num_sec(1,3);
2061 add_num_sec(1024-3,1024+3,sec);
2062 //sec = init_num_sec(1023,1025);
2063 add_num_sec(10241-3,10240+3,sec);
2064 add_num_sec(65535-3,65535,sec);
2065 #else
2066 sec = init_num_sec(1024*48-1,1024*48+1);
2067 #endif
2068 //start_add 0
2069 min_start_add = 0;
2070 max_start_add = 0;
2071 arr_ep_out = ss_hb_isoc_out_ep;
2072 out_ep_arr_size = SS_HB_ISOC_OUT_EP_SIZE;
2073 arr_ep_in = ss_hb_isoc_in_ep;
2074 in_ep_arr_size = SS_HB_ISOC_IN_EP_SIZE;
2075 arr_burst = ss_hb_isoc_burst;
2076 burst_arr_size = SS_HB_ISOC_BURST_SIZE;
2077 arr_mult = ss_hb_isoc_mult;
2078 mult_arr_size = SS_HB_ISOC_MULT_SIZE;
2079 }
2080 if(speed == DEV_SPEED_HIGH && transfer_type == EPATT_BULK){
2081 arr_maxp = hs_bulk_maxp;
2082 maxp_arr_size = HS_BULK_MAXP_SIZE;
2083 arr_interval = hs_bulk_interval;
2084 interval_arr_size = HS_BULK_INTERVAL_SIZE;
2085 //length 1~65535
2086 sec = init_num_sec(1,513);
2087 add_num_sec(10240-10, 10240+10,sec);
2088 add_num_sec(65535-10, 65535,sec);
2089 //start_add 0~63
2090 min_start_add = 0;
2091 max_start_add = 0;
2092 //ep_out_num 1~15
2093 arr_ep_out = hs_bulk_out_ep;
2094 out_ep_arr_size = HS_BULK_OUT_EP_SIZE;
2095 //ep_in_num 1~15
2096 arr_ep_in = hs_bulk_in_ep;
2097 in_ep_arr_size = HS_BULK_IN_EP_SIZE;
2098 //burst & mult all default value
2099 arr_burst = df_burst;
2100 burst_arr_size = DF_BURST_SIZE;
2101 arr_mult = df_mult;
2102 mult_arr_size = DF_MULT_SIZE;
2103 }
2104 if(speed == DEV_SPEED_HIGH && transfer_type == EPATT_INT && (!isHB)){
2105 arr_maxp = hs_intr_maxp;
2106 maxp_arr_size = HS_INTR_MAXP_SIZE;
2107 arr_interval = hs_intr_interval;
2108 interval_arr_size = HS_INTR_INTERVAL_SIZE;
2109 //length 1~2048
2110 sec = init_num_sec(1,1025);
2111 add_num_sec(2048-3,2048+3,sec);
2112 add_num_sec(3072-3,3072+3,sec);
2113 add_num_sec(10240-3,10240+3,sec);
2114 // min_length = 1;
2115 // max_length = 5120;
2116 //start_add 0~63
2117 min_start_add = 0;
2118 max_start_add = 0;
2119 //ep_out_num 1,8,15
2120 arr_ep_out = hs_intr_out_ep;
2121 out_ep_arr_size = HS_INTR_OUT_EP_SIZE;
2122 //ep_in_num 1,8,15
2123 arr_ep_in = hs_intr_in_ep;
2124 in_ep_arr_size = HS_INTR_IN_EP_SIZE;
2125 //burst & mult all default value
2126 arr_burst = df_burst;
2127 burst_arr_size = DF_BURST_SIZE;
2128 arr_mult = df_mult;
2129 mult_arr_size = DF_MULT_SIZE;
2130 }
2131 if(speed == DEV_SPEED_HIGH && transfer_type == EPATT_INT && (isHB)){
2132 arr_maxp = hs_hb_intr_maxp;
2133 maxp_arr_size = HS_HB_INTR_MAXP_SIZE;
2134 arr_interval = hs_hb_intr_interval;
2135 interval_arr_size = HS_HB_INTR_INTERVAL_SIZE;
2136 //length 1~2048
2137 sec = init_num_sec(1,1025);
2138 add_num_sec(2048-3,2048+3,sec);
2139 add_num_sec(3072-3,3072+3,sec);
2140 add_num_sec(10240-3,10240+3,sec);
2141 // min_length = 1;
2142 // max_length = 5120;
2143 //start_add 0~63
2144 min_start_add = 0;
2145 max_start_add = 0;
2146 //ep_out_num 1,8,15
2147 arr_ep_out = hs_hb_intr_out_ep;
2148 out_ep_arr_size = HS_HB_INTR_OUT_EP_SIZE;
2149 //ep_in_num 1,8,15
2150 arr_ep_in = hs_hb_intr_in_ep;
2151 in_ep_arr_size = HS_HB_INTR_IN_EP_SIZE;
2152 //burst & mult all default value
2153 arr_burst = df_burst;
2154 burst_arr_size = DF_BURST_SIZE;
2155 arr_mult = hs_hb_intr_mult;
2156 mult_arr_size = HS_HB_INTR_MULT_SIZE;
2157 }
2158 if(speed == DEV_SPEED_HIGH && transfer_type == EPATT_ISO && (!isHB)){
2159 arr_maxp = hs_isoc_maxp;
2160 maxp_arr_size = HS_ISOC_MAXP_SIZE;
2161 arr_interval = hs_isoc_interval;
2162 interval_arr_size = HS_ISOC_INTERVAL_SIZE;
2163 //length 1~10241
2164 sec = init_num_sec(1,3);
2165 add_num_sec(1024-3,1024+3,sec);
2166 add_num_sec(2048-3,2048+3,sec);
2167 add_num_sec(3072-3,3072+3,sec);
2168 add_num_sec(10240-3,10240+3,sec);
2169 //start_add 0
2170 min_start_add = 0;
2171 max_start_add = 0;
2172
2173 arr_ep_out = hs_isoc_out_ep;
2174 out_ep_arr_size = HS_ISOC_OUT_EP_SIZE;
2175 arr_ep_in = hs_isoc_in_ep;
2176 in_ep_arr_size = HS_ISOC_IN_EP_SIZE;
2177 //burst & mult all default value
2178 arr_burst = df_burst;
2179 burst_arr_size = DF_BURST_SIZE;
2180 arr_mult = df_mult;
2181 mult_arr_size = DF_MULT_SIZE;
2182 }
2183 if(speed == DEV_SPEED_HIGH && transfer_type == EPATT_ISO && (isHB)){
2184 arr_maxp = hs_hb_isoc_maxp;
2185 maxp_arr_size = HS_HB_ISOC_MAXP_SIZE;
2186 arr_interval = hs_hb_isoc_interval;
2187 interval_arr_size = HS_HB_ISOC_INTERVAL_SIZE;
2188 //length 1~10241
2189 sec = init_num_sec(1,3);
2190 add_num_sec(1024-3,1024+3,sec);
2191 add_num_sec(2048-3,2048+3,sec);
2192 add_num_sec(3072-3,3072+3,sec);
2193 add_num_sec(10240-3,10240+3,sec);
2194 //start_add 0
2195 min_start_add = 0;
2196 max_start_add = 0;
2197
2198 arr_ep_out = hs_hb_isoc_out_ep;
2199 out_ep_arr_size = HS_HB_ISOC_OUT_EP_SIZE;
2200 arr_ep_in = hs_hb_isoc_in_ep;
2201 in_ep_arr_size = HS_HB_ISOC_IN_EP_SIZE;
2202 //burst & mult all default value
2203 arr_burst = df_burst;
2204 burst_arr_size = DF_BURST_SIZE;
2205 arr_mult = hs_hb_isoc_mult;
2206 mult_arr_size = HS_HB_ISOC_MULT_SIZE;
2207 }
2208 if(speed == DEV_SPEED_FULL && transfer_type == EPATT_BULK){
2209 arr_maxp = fs_bulk_maxp;
2210 maxp_arr_size = FS_BULK_MAXP_SIZE;
2211 arr_interval = hs_bulk_interval;
2212 interval_arr_size = FS_BULK_INTERVAL_SIZE;
2213 //length 1~10241
2214 sec = init_num_sec(1,65);
2215 add_num_sec(10240-10,10240+10,sec);
2216 add_num_sec(65535-10,65535,sec);
2217
2218 min_start_add = 0;
2219 max_start_add = 0;
2220
2221 arr_ep_out = fs_bulk_out_ep;
2222 out_ep_arr_size = FS_BULK_OUT_EP_SIZE;
2223 arr_ep_in = fs_bulk_in_ep;
2224 in_ep_arr_size = FS_BULK_IN_EP_SIZE;
2225 //burst & mult all default value
2226 arr_burst = df_burst;
2227 burst_arr_size = DF_BURST_SIZE;
2228 arr_mult = df_mult;
2229 mult_arr_size = DF_MULT_SIZE;
2230 }
2231 if(speed == DEV_SPEED_FULL && transfer_type == EPATT_INT){
2232 arr_maxp = fs_intr_maxp;
2233 maxp_arr_size = FS_INTR_MAXP_SIZE;
2234 arr_interval = fs_intr_interval;
2235 interval_arr_size = FS_INTR_INTERVAL_SIZE;
2236 //length 1~10241
2237 sec = init_num_sec(1, 65);
2238 add_num_sec(3072-3,3072+3,sec);
2239 min_start_add = 0;
2240 max_start_add = 0;
2241
2242 arr_ep_out = fs_intr_out_ep;
2243 out_ep_arr_size = FS_INTR_OUT_EP_SIZE;
2244 arr_ep_in = fs_intr_in_ep;
2245 in_ep_arr_size = FS_INTR_IN_EP_SIZE;
2246 //burst & mult all default value
2247 arr_burst = df_burst;
2248 burst_arr_size = DF_BURST_SIZE;
2249 arr_mult = df_mult;
2250 mult_arr_size = DF_MULT_SIZE;
2251 }
2252 if(speed == DEV_SPEED_FULL && transfer_type == EPATT_ISO){
2253 arr_maxp = fs_isoc_maxp;
2254 maxp_arr_size = FS_ISOC_MAXP_SIZE;
2255 arr_interval = fs_isoc_interval;
2256 interval_arr_size = FS_ISOC_INTERVAL_SIZE;
2257 sec = init_num_sec(1,3);
2258 add_num_sec(1023-3,1023+3,sec);
2259 add_num_sec(3072-3,3072+3,sec);
2260 min_start_add = 0;
2261 max_start_add = 0;
2262
2263 arr_ep_out = fs_isoc_out_ep;
2264 out_ep_arr_size = FS_ISOC_OUT_EP_SIZE;
2265 arr_ep_in = fs_isoc_in_ep;
2266 in_ep_arr_size = FS_ISOC_IN_EP_SIZE;
2267 //burst & mult all default value
2268 arr_burst = df_burst;
2269 burst_arr_size = DF_BURST_SIZE;
2270 arr_mult = df_mult;
2271 mult_arr_size = DF_MULT_SIZE;
2272 }
2273 #if 0
2274 if(u3auto_hcd_reset() != RET_SUCCESS)
2275 return RET_FAIL;
2276 #endif
2277 for(ep_in_index = 0; ep_in_index < in_ep_arr_size; ep_in_index++){
2278 ep_in_num = *(arr_ep_in + ep_in_index);
2279 for(ep_out_index = 0; ep_out_index < out_ep_arr_size; ep_out_index++){
2280 ep_out_num = *(arr_ep_out + ep_out_index);
2281 for(maxp_index = 0; maxp_index < maxp_arr_size; maxp_index++){
2282 maxp = *(arr_maxp + maxp_index);
2283 for(interval_index = 0; interval_index < interval_arr_size; interval_index++){
2284 bInterval = *(arr_interval + interval_index);
2285 for(mult_index = 0; mult_index < mult_arr_size; mult_index++){
2286 mult = *(arr_mult+mult_index);
2287 for(burst_index = 0; burst_index < burst_arr_size; burst_index++){
2288 burst = *(arr_burst+burst_index);
2289 /*
2290 printk(KERN_ERR "[TEST]*************************************\n");
2291 printk(KERN_ERR " OUT_EP: %d***************************\n", ep_out_num);
2292 printk(KERN_ERR " IN_EP: %d ***************************\n", ep_in_num);
2293 printk(KERN_ERR " MAXP: %d ***************************\n", maxp);
2294 printk(KERN_ERR " INTERVAL: %d ***************************\n", bInterval);
2295 printk(KERN_ERR " MULT: %d **************************\n", mult);
2296 printk(KERN_ERR " BURST: %d *************************\n", burst);
2297 */
2298 /* ==phase 0 : device reset==*/
2299 #if 1
2300 if(speed == DEV_SPEED_SUPER && transfer_type == EPATT_ISO && mult > 0 && burst > 1){
2301 mtk_test_dbg( " SKIP!!\n");
2302 continue;
2303 }
2304 start_port_reenabled(0, speed);
2305 ret=dev_reset(speed, NULL);
2306 if(ret){
2307 mtk_test_dbg( "device reset failed!!!!!!!!!!\n");
2308 return ret;
2309 }
2310
2311 ret = f_disable_slot();
2312 if(ret){
2313 mtk_test_dbg( "disable slot failed!!!!!!!!!!\n");
2314 return ret;
2315 }
2316
2317 ret = f_reenable_port(0);
2318 if(ret != RET_SUCCESS){
2319 mtk_test_dbg( "device reenable failed!!!!!!!!!!\n");
2320 return ret;
2321 }
2322
2323 ret = f_enable_slot(NULL);
2324 if(ret){
2325 mtk_test_dbg( "enable slot failed!!!!!!!!!!\n");
2326 return ret;
2327 }
2328
2329 ret=f_address_slot(false, NULL);
2330 if(ret){
2331 mtk_test_dbg( "address slot failed!!!!!!!!!!\n");
2332 return ret;
2333 }
2334 #endif
2335 //reset SW scheduler algorithm
2336 mtktest_mtk_xhci_scheduler_init();
2337 /* ==phase 1 : config EP==*/
2338 ret=dev_config_ep(ep_out_num,USB_RX,transfer_type,maxp,bInterval,mult_dev,burst,mult,NULL);
2339 if(ret)
2340 {
2341 mtk_test_dbg( "config dev EP fail!!\n");
2342 return ret;
2343 }
2344 ret=dev_config_ep(ep_in_num,USB_TX,transfer_type,maxp,bInterval,mult_dev,burst,mult,NULL);
2345 if(ret)
2346 {
2347 mtk_test_dbg( "config dev EP fail!!\n");
2348 return ret;
2349 }
2350 ret = f_config_ep(ep_out_num,EPADD_OUT,transfer_type,maxp,bInterval,burst,mult, NULL,0);
2351 if(ret)
2352 {
2353 mtk_test_dbg( "config EP fail!!\n");
2354 return ret;
2355 }
2356
2357 ret = f_config_ep(ep_in_num,EPADD_IN,transfer_type,maxp,bInterval,burst,mult, NULL,1);
2358 if(ret)
2359 {
2360 mtk_test_dbg( "config EP fail!!\n");
2361 return ret;
2362 }
2363
2364 for(start_add = min_start_add; start_add <= max_start_add; start_add++){
2365 cur_sec = sec;
2366 while(cur_sec != NULL){
2367 mtk_test_dbg( "[TEST]*************************************\n");
2368 mtk_test_dbg( " OUT_EP: %d***************************\n", ep_out_num);
2369 mtk_test_dbg( " IN_EP: %d ***************************\n", ep_in_num);
2370 mtk_test_dbg( " MAXP: %d ***************************\n", maxp);
2371 mtk_test_dbg( " INTERVAL: %d ***************************\n", bInterval);
2372 mtk_test_dbg( " MULT: %d **************************\n", mult);
2373 mtk_test_dbg( " BURST: %d *************************\n", burst);
2374
2375
2376 length = cur_sec->current_value;
2377 mtk_test_dbg( " [ROUND]**************************\n");
2378 mtk_test_dbg( " START_ADD: %d*************\n", start_add);
2379 mtk_test_dbg( " LENGTH: %d *************\n", length);
2380 #if 1
2381 if(speed == DEV_SPEED_HIGH && transfer_type == EPATT_ISO
2382 && (maxp == 2048 || maxp == 3072) && (length%maxp != 0)
2383 && (length % 1024 == 0)){
2384 mtk_test_dbg( " SKIP!!\n");
2385 cur_sec = find_next_num(cur_sec);
2386 continue;
2387 }
2388 #endif
2389
2390 /* ==phase 2 : loopback==*/
2391
2392 #ifdef DMA_BURST_SIZE_TEST
2393 dma_burst_sz = (dma_burst_sz + 1) % 4;
2394 dma_tmp = readl(SSUSB_XHCI_HDMA_CFG);
2395 /* clear dma r/w fields */
2396 dma_tmp &= ~0x0C0C;
2397 /* set r/w burst size */
2398 dma_tmp |= (dma_burst_sz << 2 | dma_burst_sz << 10);
2399 writel(dma_tmp, SSUSB_XHCI_HDMA_CFG);
2400 #endif
2401 mtk_test_dbg( " DMA_BURST: %d *************\n", dma_burst_sz);
2402
2403 #if 1
2404 if(speed == DEV_SPEED_SUPER && transfer_type == EPATT_ISO){
2405 if(length % maxp == 0){
2406 cur_sec = find_next_num(cur_sec);
2407 mtk_test_dbg( " SKIP!!\n");
2408 continue;
2409 }
2410 else if((burst==0) && (length/maxp>250)){
2411 cur_sec = find_next_num(cur_sec);
2412 mtk_test_dbg( " SKIP!!\n");
2413 continue;
2414 }
2415 else{
2416 bdp=1;
2417 gpd_buf_size = length;
2418 bd_buf_size = 4096;
2419 }
2420 }
2421 else if(speed == DEV_SPEED_HIGH && transfer_type == EPATT_ISO){
2422 if(length % maxp == 0){
2423 cur_sec = find_next_num(cur_sec);
2424 mtk_test_dbg( " SKIP!!\n");
2425 continue;
2426 }
2427 else if((mult == 0) && (length/maxp>250)){
2428 cur_sec = find_next_num(cur_sec);
2429 mtk_test_dbg( " SKIP!!\n");
2430 continue;
2431 }
2432 else{
2433 bdp=1;
2434 gpd_buf_size = length;
2435 bd_buf_size = 4096;
2436 }
2437 }
2438 else if(transfer_type == EPATT_ISO){
2439 if(length/maxp > 250){
2440 cur_sec = find_next_num(cur_sec);
2441 mtk_test_dbg( " SKIP!!\n");
2442 continue;
2443 }
2444 else{
2445 bdp=1;
2446 gpd_buf_size = length;
2447 bd_buf_size = 4096;
2448 }
2449 }
2450 else{
2451 bdp=1;
2452 gpd_buf_size = length;
2453 bd_buf_size = 4096;
2454 }
2455 #endif
2456 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size,dram_offset,extension,NULL);
2457 if(ret)
2458 {
2459 mtk_test_dbg( "loopback request fail!!\n");
2460 f_power_suspend();
2461 return ret;
2462 }
2463
2464 // ret = f_loopback_loop(ep_out_num, ep_in_num, length, start_add,NULL);
2465 ret = f_loopback_loop_gpd(
2466 ep_out_num, ep_in_num, length, start_add, gpd_buf_size, NULL);
2467 if(ret)
2468 {
2469 mtk_test_dbg( "loopback fail!!\n");
2470 mtk_test_dbg( "length : %d\n",length);
2471 f_power_suspend();
2472 return ret;
2473 }
2474
2475 /* ==phase 3: get device status==*/
2476 ret=dev_polling_status(NULL);
2477 if(ret)
2478 {
2479 f_power_suspend();
2480 mtk_test_dbg( "query request fail!!\n");
2481 return ret;
2482 }
2483 cur_sec = find_next_num(cur_sec);
2484 }
2485 }
2486 } //burst
2487 } //mult
2488 } //interval
2489 } //maxp
2490 } // ep_out
2491 } //ep_in
2492 clear_num_secs(sec);
2493 return ret;
2494 }
2495
2496 static int t_u3auto_loopback(int argc, char** argv){
2497 int ret,length,start_add;
2498 char bdp;
2499 int gpd_buf_size,bd_buf_size;
2500 int transfer_type;
2501 int maxp;
2502 int bInterval;
2503 int ep_out_num, ep_in_num;
2504 int speed;
2505 int mult, burst, dev_mult;
2506 int dram_offset, extension;
2507
2508 ret = 0;
2509 speed = DEV_SPEED_HIGH;;
2510 transfer_type = EPATT_BULK;
2511 maxp = 512;
2512 bInterval = 0;
2513 ep_out_num = 1;
2514 ep_in_num = 1;
2515 length = 65535;
2516 dev_mult = 1;
2517 burst = 8;
2518 mult = 0;
2519
2520 if(argc > 1){
2521 if(!strcmp(argv[1], "ss")){
2522 mtk_test_dbg( "Test super speed\n");
2523 speed = DEV_SPEED_SUPER; //TODO: superspeed
2524 }
2525 else if(!strcmp(argv[1], "hs")){
2526 mtk_test_dbg( "Test high speed\n");
2527 speed = DEV_SPEED_HIGH;
2528 }
2529 else if(!strcmp(argv[1], "fs")){
2530 mtk_test_dbg( "Test full speed\n");
2531 speed = DEV_SPEED_FULL;
2532 }
2533 }
2534 if(argc > 2){
2535 if(!strcmp(argv[2], "bulk")){
2536 mtk_test_dbg( "Test bulk transfer\n");
2537 transfer_type = EPATT_BULK;
2538 }
2539 else if(!strcmp(argv[2], "intr")){
2540 mtk_test_dbg( "Test intr transfer\n");
2541 transfer_type = EPATT_INT;
2542 }
2543 else if(!strcmp(argv[2], "isoc")){
2544 mtk_test_dbg( "Test isoc transfer\n");
2545 transfer_type = EPATT_ISO;
2546 }
2547 }
2548 if(argc > 3){
2549 maxp = (int)simple_strtol(argv[3], &argv[3], 10);
2550 mtk_test_dbg( "maxp set to %d\n", maxp);
2551 }
2552 if(argc > 4){
2553 bInterval = (int)simple_strtol(argv[4], &argv[4], 10);
2554 mtk_test_dbg( "interval set to %d\n", bInterval);
2555 }
2556 if(argc > 5){
2557 length = (int)simple_strtol(argv[5], &argv[5], 10);
2558 mtk_test_dbg( "length set to %d\n", length);
2559 }
2560 if(argc > 6){
2561 start_add = (int)simple_strtol(argv[6], &argv[6], 10);
2562 mtk_test_dbg( "start add offset set to %d\n", start_add);
2563 }
2564 if(argc > 7){
2565 ep_out_num = (int)simple_strtol(argv[7], &argv[7], 10);
2566 mtk_test_dbg( "ep out num set to %d\n", ep_out_num);
2567 }
2568 if(argc > 8){
2569 ep_in_num = (int)simple_strtol(argv[8], &argv[8], 10);
2570 mtk_test_dbg( "ep in num set to %d\n", ep_in_num);
2571 }
2572 if(argc > 9){
2573 burst = (int)simple_strtol(argv[9], &argv[9], 10);
2574 mtk_test_dbg( "burst set to %d\n", burst);
2575 }
2576 if(argc > 10){
2577 mult = (int)simple_strtol(argv[10], &argv[10], 10);
2578 mtk_test_dbg( "mult set to %d\n", mult);
2579 }
2580 #if 0
2581 if(u3auto_hcd_reset() != RET_SUCCESS)
2582 return RET_FAIL;
2583 #endif
2584 mtk_test_dbg( "/*=========loopback===========*/\n");
2585
2586 /* ==phase 0 : device reset==*/
2587 start_port_reenabled(0, speed);
2588 ret=dev_reset(speed,NULL);
2589 if(ret){
2590 mtk_test_dbg( "device reset failed!!!!!!!!!!\n");
2591 return ret;
2592 }
2593
2594 ret = f_disable_slot();
2595 if(ret){
2596 mtk_test_dbg( "disable slot failed!!!!!!!!!!\n");
2597 return ret;
2598 }
2599
2600 ret = f_reenable_port(0);
2601 if(ret != RET_SUCCESS){
2602 mtk_test_dbg( "device reenable failed!!!!!!!!!!\n");
2603 return ret;
2604 }
2605
2606 ret = f_enable_slot(NULL);
2607 if(ret){
2608 mtk_test_dbg( "enable slot failed!!!!!!!!!!\n");
2609 return ret;
2610 }
2611
2612 ret=f_address_slot(false, NULL);
2613 if(ret){
2614 mtk_test_dbg( "address slot failed!!!!!!!!!!\n");
2615 return ret;
2616 }
2617
2618 /* ==phase 1 : config EP==*/
2619 ret=dev_config_ep(ep_out_num,USB_RX,transfer_type,maxp,bInterval,dev_mult,burst,mult,NULL);
2620 if(ret)
2621 {
2622 mtk_test_dbg( "config dev EP fail!!\n");
2623 return ret;
2624 }
2625
2626 ret=dev_config_ep(ep_in_num,USB_TX,transfer_type,maxp,bInterval,dev_mult,burst,mult,NULL);
2627 if(ret)
2628 {
2629 mtk_test_dbg( "config dev EP fail!!\n");
2630 return ret;
2631 }
2632
2633 ret = f_config_ep(ep_out_num,EPADD_OUT,transfer_type,maxp,bInterval,burst,mult, NULL,0);
2634 if(ret)
2635 {
2636 mtk_test_dbg( "config EP fail!!\n");
2637 return ret;
2638 }
2639
2640 ret = f_config_ep(ep_in_num,EPADD_IN,transfer_type,maxp,bInterval,burst,mult, NULL,1);
2641 if(ret)
2642 {
2643 mtk_test_dbg( "config EP fail!!\n");
2644 return ret;
2645 }
2646
2647 /* ==phase 2 : loopback==*/
2648 bdp=1;
2649 gpd_buf_size=length;
2650 bd_buf_size=8192;
2651 //TODO: device should turn off extension length feature
2652 #if 0
2653 if(((length-10)%(bd_buf_size+6))<7){
2654 length+=12;
2655 }
2656 #endif
2657 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size,dram_offset,extension,NULL);
2658 if(ret)
2659 {
2660 mtk_test_dbg( "loopback request fail!!\n");
2661 return ret;
2662 }
2663
2664 ret = f_loopback_loop_gpd(ep_out_num, ep_in_num, length, start_add, gpd_buf_size, NULL);
2665 if(ret)
2666 {
2667 mtk_test_dbg( "loopback fail!!\n");
2668 mtk_test_dbg( "length : %d\n",length);
2669 return ret;
2670 }
2671
2672 /* ==phase 3: get device status==*/
2673 ret=dev_polling_status(NULL);
2674 if(ret)
2675 {
2676 mtk_test_dbg( "query request fail!!\n");
2677 return ret;
2678 }
2679 #if 0
2680 ret=dev_reset(speed,NULL);
2681 #endif
2682 return ret;
2683 }
2684
2685 static int t_u3auto_loopback_sg(int argc, char** argv){
2686 int ret,length,start_add;
2687 char bdp;
2688 int gpd_buf_size,bd_buf_size;
2689 int transfer_type;
2690 int maxp;
2691 int bInterval;
2692 int ep_out_num, ep_in_num;
2693 int speed;
2694 int sg_len;
2695 int mult,burst, dev_mult;
2696 int dram_offset, extension;
2697
2698 ret = 0;
2699 speed = DEV_SPEED_HIGH;
2700 transfer_type = EPATT_BULK;
2701 maxp = 512;
2702 ep_out_num = 1;
2703 ep_in_num = 1;
2704 bInterval = 0;
2705 length = 65535;
2706 mult=0;
2707 burst=8;
2708 dev_mult=1;
2709
2710 if(argc > 1){
2711 if(!strcmp(argv[1], "ss")){
2712 mtk_test_dbg( "Test super speed\n");
2713 speed = DEV_SPEED_SUPER;
2714 }
2715 else if(!strcmp(argv[1], "hs")){
2716 mtk_test_dbg( "Test high speed\n");
2717 speed = DEV_SPEED_HIGH;
2718 }
2719 else if(!strcmp(argv[1], "fs")){
2720 mtk_test_dbg( "Test full speed\n");
2721 speed = DEV_SPEED_FULL;
2722 }
2723 }
2724 if(argc > 2){
2725 if(!strcmp(argv[2], "bulk")){
2726 mtk_test_dbg( "Test bulk transfer\n");
2727 transfer_type = EPATT_BULK;
2728 }
2729 else if(!strcmp(argv[2], "intr")){
2730 mtk_test_dbg( "Test intr transfer\n");
2731 transfer_type = EPATT_INT;
2732 }
2733 else if(!strcmp(argv[2], "isoc")){
2734 mtk_test_dbg( "Test isoc transfer\n");
2735 transfer_type = EPATT_ISO;
2736 }
2737 }
2738 if(argc > 3){
2739 maxp = (int)simple_strtol(argv[3], &argv[3], 10);
2740 mtk_test_dbg( "maxp set to %d\n", maxp);
2741 }
2742 if(argc > 4){
2743 bInterval = (int)simple_strtol(argv[4], &argv[4], 10);
2744 mtk_test_dbg( "interval set to %d\n", bInterval);
2745 }
2746 if(argc > 5){
2747 length = (int)simple_strtol(argv[5], &argv[5], 10);
2748 mtk_test_dbg( "length set to %d\n", length);
2749 }
2750 if(argc > 6){
2751 start_add = (int)simple_strtol(argv[6], &argv[6], 10);
2752 mtk_test_dbg( "start add offset set to %d\n", start_add);
2753 }
2754 if(argc > 7){
2755 sg_len = (int)simple_strtol(argv[7], &argv[7], 10);
2756 mtk_test_dbg( "sg length set to %d\n", sg_len);
2757 if(sg_len == 0){
2758 mtk_test_dbg( "random sg length\n");
2759 }
2760 }
2761 if(argc > 8){
2762 ep_out_num = (int)simple_strtol(argv[8], &argv[8], 10);
2763 mtk_test_dbg( "ep out num set to %d\n", ep_out_num);
2764 }
2765 if(argc > 9){
2766 ep_in_num = (int)simple_strtol(argv[9], &argv[9], 10);
2767 mtk_test_dbg( "ep in num set to %d\n", ep_in_num);
2768 }
2769 if(argc > 10){
2770 burst = (int)simple_strtol(argv[10], &argv[10], 10);
2771 mtk_test_dbg( "burst set to %d\n", burst);
2772 }
2773 if(argc > 11){
2774 mult = (int)simple_strtol(argv[11], &argv[11], 10);
2775 mtk_test_dbg( "mult set to %d\n", mult);
2776 }
2777 #if 0
2778 if(u3auto_hcd_reset() != RET_SUCCESS)
2779 return RET_FAIL;
2780 #endif
2781 mtk_test_dbg( "/*=========loopback===========*/\n");
2782
2783 /* ==phase 0 : device reset==*/
2784 start_port_reenabled(0, speed);
2785 ret=dev_reset(speed,NULL);
2786 if(ret){
2787 mtk_test_dbg( "device reset failed!!!!!!!!!!\n");
2788 return ret;
2789 }
2790 ret = f_disable_slot();
2791 if(ret){
2792 mtk_test_dbg( "disable slot failed!!!!!!!!!!\n");
2793 return ret;
2794 }
2795 ret = f_reenable_port(0);
2796 if(ret != RET_SUCCESS){
2797 mtk_test_dbg( "device reenable failed!!!!!!!!!!\n");
2798 return ret;
2799 }
2800
2801 ret = f_enable_slot(NULL);
2802 if(ret){
2803 mtk_test_dbg( "enable slot failed!!!!!!!!!!\n");
2804 return ret;
2805 }
2806
2807 ret=f_address_slot(false, NULL);
2808 if(ret){
2809 mtk_test_dbg( "address slot failed!!!!!!!!!!\n");
2810 return ret;
2811 }
2812
2813 /* ==phase 1 : config EP==*/
2814 ret=dev_config_ep(ep_out_num,USB_RX,transfer_type,maxp,bInterval,dev_mult,burst,mult,NULL);
2815 if(ret)
2816 {
2817 mtk_test_dbg( "config dev EP fail!!\n");
2818 return ret;
2819 }
2820
2821 ret=dev_config_ep(ep_in_num,USB_TX,transfer_type,maxp,bInterval,dev_mult,burst,mult,NULL);
2822 if(ret)
2823 {
2824 mtk_test_dbg( "config dev EP fail!!\n");
2825 return ret;
2826 }
2827
2828 ret = f_config_ep(ep_out_num,EPADD_OUT,transfer_type,maxp,bInterval,burst,mult,NULL,0);
2829 if(ret)
2830 {
2831 mtk_test_dbg( "config EP fail!!\n");
2832 return ret;
2833 }
2834
2835 ret = f_config_ep(ep_in_num,EPADD_IN,transfer_type,maxp,bInterval,burst,mult, NULL,1);
2836 if(ret)
2837 {
2838 mtk_test_dbg( "config EP fail!!\n");
2839 return ret;
2840 }
2841
2842 /* ==phase 2 : loopback==*/
2843 bdp=1;
2844 gpd_buf_size=length;
2845 bd_buf_size=4096;
2846 //TODO: device should turn off extension length feature
2847 #if 0
2848 if(((length-10)%(bd_buf_size+6))<7){
2849 length+=12;
2850 }
2851 #endif
2852 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size,dram_offset,extension,NULL);
2853 if(ret)
2854 {
2855 mtk_test_dbg( "loopback request fail!!\n");
2856 return ret;
2857 }
2858
2859 ret = f_loopback_sg_loop(ep_out_num, ep_in_num, length, start_add, sg_len, NULL);
2860 if(ret)
2861 {
2862 mtk_test_dbg( "loopback fail!!\n");
2863 mtk_test_dbg( "length : %d\n",length);
2864 return ret;
2865 }
2866
2867 /* ==phase 3: get device status==*/
2868 ret=dev_polling_status(NULL);
2869 if(ret)
2870 {
2871 mtk_test_dbg( "query request fail!!\n");
2872 return ret;
2873 }
2874 return ret;
2875 }
2876
2877 //always use bulk transfer
2878 static int t_u3auto_random_suspend(int argc, char** argv){
2879 int ret,length,start_add;
2880 char bdp;
2881 int gpd_buf_size,bd_buf_size;
2882 int transfer_type;
2883 int maxp;
2884 int bInterval;
2885 int ep_out_num, ep_in_num;
2886 int speed;
2887 int mult, burst, dev_mult;
2888 int dram_offset, extension;
2889 int suspend_count, suspend_boundry;
2890 char isSuspend;
2891
2892 ret = 0;
2893 speed = DEV_SPEED_HIGH;;
2894 transfer_type = EPATT_BULK;
2895 maxp = 512;
2896 bInterval = 0;
2897 ep_out_num = 1;
2898 ep_in_num = 1;
2899 length = 65535;
2900 dev_mult = 1;
2901 burst = 8;
2902 mult = 0;
2903 suspend_count = 0;
2904 suspend_boundry = 10;
2905
2906 if(argc > 1){
2907 if(!strcmp(argv[1], "ss")){
2908 mtk_test_dbg( "Test super speed\n");
2909 speed = DEV_SPEED_SUPER; //TODO: superspeed
2910 }
2911 else if(!strcmp(argv[1], "hs")){
2912 mtk_test_dbg( "Test high speed\n");
2913 speed = DEV_SPEED_HIGH;
2914 }
2915 else if(!strcmp(argv[1], "fs")){
2916 mtk_test_dbg( "Test full speed\n");
2917 speed = DEV_SPEED_FULL;
2918 }
2919 }
2920 if(argc > 2){
2921 suspend_boundry = (int)simple_strtol(argv[2], &argv[2], 10);
2922 mtk_test_dbg( "suspend_boundry set to %d\n", suspend_boundry);
2923 }
2924 if(speed == DEV_SPEED_SUPER){
2925 maxp = 1024;
2926 }
2927 else if(speed == DEV_SPEED_HIGH){
2928 maxp = 512;
2929 }
2930 else if(speed == DEV_SPEED_FULL){
2931 maxp = 64;
2932 }
2933 bInterval = 0;
2934 //random length
2935 start_add = 0;
2936 ep_out_num = 1;
2937 ep_in_num = 1;
2938 burst = 8;
2939 mult = 0;
2940 #if 0
2941 if(u3auto_hcd_reset() != RET_SUCCESS)
2942 return RET_FAIL;
2943 #endif
2944
2945 /* ==phase 0 : device reset==*/
2946 start_port_reenabled(0, speed);
2947 ret=dev_reset(speed,NULL);
2948 if(ret){
2949 mtk_test_dbg( "device reset failed!!!!!!!!!!\n");
2950 return ret;
2951 }
2952
2953 ret = f_disable_slot();
2954 if(ret){
2955 mtk_test_dbg( "disable slot failed!!!!!!!!!!\n");
2956 return ret;
2957 }
2958
2959 ret = f_reenable_port(0);
2960 if(ret != RET_SUCCESS){
2961 mtk_test_dbg( "device reenable failed!!!!!!!!!!\n");
2962 return ret;
2963 }
2964
2965 ret = f_enable_slot(NULL);
2966 if(ret){
2967 mtk_test_dbg( "enable slot failed!!!!!!!!!!\n");
2968 return ret;
2969 }
2970
2971 ret=f_address_slot(false, NULL);
2972 if(ret){
2973 mtk_test_dbg( "address slot failed!!!!!!!!!!\n");
2974 return ret;
2975 }
2976 mtktest_mtk_xhci_scheduler_init();
2977 /* ==phase 1 : config EP==*/
2978 ret=dev_config_ep(ep_out_num,USB_RX,transfer_type,maxp,bInterval,dev_mult,burst,mult,NULL);
2979 if(ret)
2980 {
2981 mtk_test_dbg( "config dev EP fail!!\n");
2982 return ret;
2983 }
2984
2985 ret=dev_config_ep(ep_in_num,USB_TX,transfer_type,maxp,bInterval,dev_mult,burst,mult,NULL);
2986 if(ret)
2987 {
2988 mtk_test_dbg( "config dev EP fail!!\n");
2989 return ret;
2990 }
2991
2992 ret = f_config_ep(ep_out_num,EPADD_OUT,transfer_type,maxp,bInterval,burst,mult, NULL,0);
2993 if(ret)
2994 {
2995 mtk_test_dbg( "config EP fail!!\n");
2996 return ret;
2997 }
2998
2999 ret = f_config_ep(ep_in_num,EPADD_IN,transfer_type,maxp,bInterval,burst,mult, NULL,1);
3000 if(ret)
3001 {
3002 mtk_test_dbg( "config EP fail!!\n");
3003 return ret;
3004 }
3005 suspend_count = 0;
3006 while(suspend_count < suspend_boundry){
3007 isSuspend = (char)(get_random_int() % 2);
3008 if(isSuspend){
3009 mtk_test_dbg( "Suspend/Resume\n");
3010 ret = f_power_suspend();
3011 if(ret){
3012 return ret;
3013 }
3014 mtk_test_dbg( "Enter U3, Suspend success\n");
3015 mdelay(1000);
3016 ret = f_power_resume();
3017 if(ret){
3018 return ret;
3019 }
3020 mtk_test_dbg( "Enter U0, Resume success\n");
3021 suspend_count++;
3022 }
3023 length = (get_random_int() % 65535)+1;
3024 mtk_test_dbg( "count(%d), isSuspend(%d), loopback %d length\n",
3025 suspend_count, isSuspend, length);
3026 /* ==phase 2 : loopback==*/
3027 bdp=1;
3028 gpd_buf_size=length;
3029 bd_buf_size=8192;
3030 //TODO: device should turn off extension length feature
3031 #if 0
3032 if(((length-10)%(bd_buf_size+6))<7){
3033 length+=12;
3034 }
3035 #endif
3036 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size,dram_offset,extension,NULL);
3037 if(ret)
3038 {
3039 mtk_test_dbg( "loopback request fail!!\n");
3040 return ret;
3041 }
3042
3043 ret = f_loopback_loop(ep_out_num, ep_in_num, length, start_add,NULL);
3044 if(ret)
3045 {
3046 mtk_test_dbg( "loopback fail!!\n");
3047 mtk_test_dbg( "length : %d\n",length);
3048 return ret;
3049 }
3050
3051 /* ==phase 3: get device status==*/
3052 ret=dev_polling_status(NULL);
3053 if(ret)
3054 {
3055 mtk_test_dbg( "query request fail!!\n");
3056 return ret;
3057 }
3058
3059 }
3060 #if 0
3061 ret=dev_reset(speed,NULL);
3062 #endif
3063 return ret;
3064 }
3065
3066 static int t_u3auto_random_wakeup(int argc, char**argv){
3067 int ret,length,start_add, random_delay;
3068 char bdp;
3069 int gpd_buf_size,bd_buf_size;
3070 int transfer_type;
3071 int maxp;
3072 int bInterval;
3073 int ep_out_num, ep_in_num;
3074 int speed;
3075 int mult, burst, dev_mult;
3076 int dram_offset, extension;
3077 int suspend_count, suspend_boundry;
3078 char isSuspend;
3079
3080 ret = 0;
3081 speed = DEV_SPEED_HIGH;;
3082 transfer_type = EPATT_BULK;
3083 maxp = 512;
3084 bInterval = 0;
3085 ep_out_num = 1;
3086 ep_in_num = 1;
3087 length = 65535;
3088 dev_mult = 1;
3089 burst = 8;
3090 mult = 0;
3091 suspend_count = 0;
3092 suspend_boundry = 10;
3093
3094 if(argc > 1){
3095 if(!strcmp(argv[1], "ss")){
3096 mtk_test_dbg( "Test super speed\n");
3097 speed = DEV_SPEED_SUPER;
3098 }
3099 else if(!strcmp(argv[1], "hs")){
3100 mtk_test_dbg( "Test high speed\n");
3101 speed = DEV_SPEED_HIGH;
3102 }
3103 else if(!strcmp(argv[1], "fs")){
3104 mtk_test_dbg( "Test full speed\n");
3105 speed = DEV_SPEED_FULL;
3106 }
3107 }
3108 if(argc > 2){
3109 suspend_boundry = (int)simple_strtol(argv[2], &argv[2], 10);
3110 mtk_test_dbg( "wakeup_boundary set to %d\n", suspend_boundry);
3111 }
3112 if(speed == DEV_SPEED_SUPER){
3113 maxp = 1024;
3114 }
3115 else if(speed == DEV_SPEED_HIGH){
3116 maxp = 512;
3117 }
3118 else if(speed == DEV_SPEED_FULL){
3119 maxp = 64;
3120 }
3121 bInterval = 0;
3122 //random length
3123 start_add = 0;
3124 ep_out_num = 1;
3125 ep_in_num = 1;
3126 burst = 8;
3127 mult = 0;
3128 #if 0
3129 if(u3auto_hcd_reset() != RET_SUCCESS)
3130 return RET_FAIL;
3131 #endif
3132
3133 /* ==phase 0 : device reset==*/
3134 start_port_reenabled(0, speed);
3135 ret=dev_reset(speed,NULL);
3136 if(ret){
3137 mtk_test_dbg( "device reset failed!!!!!!!!!!\n");
3138 return ret;
3139 }
3140
3141 ret = f_disable_slot();
3142 if(ret){
3143 mtk_test_dbg( "disable slot failed!!!!!!!!!!\n");
3144 return ret;
3145 }
3146
3147 ret = f_reenable_port(0);
3148 if(ret != RET_SUCCESS){
3149 mtk_test_dbg( "device reenable failed!!!!!!!!!!\n");
3150 return ret;
3151 }
3152
3153 ret = f_enable_slot(NULL);
3154 if(ret){
3155 mtk_test_dbg( "enable slot failed!!!!!!!!!!\n");
3156 return ret;
3157 }
3158
3159 ret=f_address_slot(false, NULL);
3160 if(ret){
3161 mtk_test_dbg( "address slot failed!!!!!!!!!!\n");
3162 return ret;
3163 }
3164
3165 /* ==phase 1 : config EP==*/
3166 ret=dev_config_ep(ep_out_num,USB_RX,transfer_type,maxp,bInterval,dev_mult,burst,mult,NULL);
3167 if(ret)
3168 {
3169 mtk_test_dbg( "config dev EP fail!!\n");
3170 return ret;
3171 }
3172
3173 ret=dev_config_ep(ep_in_num,USB_TX,transfer_type,maxp,bInterval,dev_mult,burst,mult,NULL);
3174 if(ret)
3175 {
3176 mtk_test_dbg( "config dev EP fail!!\n");
3177 return ret;
3178 }
3179 mtktest_mtk_xhci_scheduler_init();
3180 ret = f_config_ep(ep_out_num,EPADD_OUT,transfer_type,maxp,bInterval,burst,mult, NULL,0);
3181 if(ret)
3182 {
3183 mtk_test_dbg( "config EP fail!!\n");
3184 return ret;
3185 }
3186
3187 ret = f_config_ep(ep_in_num,EPADD_IN,transfer_type,maxp,bInterval,burst,mult, NULL,1);
3188 if(ret)
3189 {
3190 mtk_test_dbg( "config EP fail!!\n");
3191 return ret;
3192 }
3193 suspend_count = 0;
3194 while(suspend_count < suspend_boundry){
3195 length = (get_random_int() % 65535)+1;
3196 mtk_test_dbg( "loopback %d length\n", length);
3197 random_delay = (get_random_int() % 300000)+1;
3198 bdp=1;
3199 gpd_buf_size=length;
3200 bd_buf_size=8192;
3201 isSuspend = (char)(get_random_int() % 2);
3202 if(isSuspend){
3203 mtk_test_dbg( "random_delay(%d)\n", random_delay);
3204 ret = dev_remotewakeup(random_delay);
3205 ret = f_power_remotewakeup();
3206 if(ret){
3207 return ret;
3208 }
3209 suspend_count++;
3210 }
3211
3212 /* ==phase 2 : loopback==*/
3213
3214 //TODO: device should turn off extension length feature
3215 #if 0
3216 if(((length-10)%(bd_buf_size+6))<7){
3217 length+=12;
3218 }
3219 #endif
3220 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size,dram_offset,extension,NULL);
3221 if(ret)
3222 {
3223 mtk_test_dbg( "loopback request fail!!\n");
3224 return ret;
3225 }
3226
3227 ret = f_loopback_loop(ep_out_num, ep_in_num, length, start_add,NULL);
3228 if(ret)
3229 {
3230 mtk_test_dbg( "loopback fail!!\n");
3231 mtk_test_dbg( "length : %d\n",length);
3232 return ret;
3233 }
3234
3235 /* ==phase 3: get device status==*/
3236 ret=dev_polling_status(NULL);
3237 if(ret)
3238 {
3239 mtk_test_dbg( "query request fail!!\n");
3240 return ret;
3241 }
3242
3243 }
3244 #if 0
3245 ret=dev_reset(speed,NULL);
3246 #endif
3247 return ret;
3248 }
3249
3250 static int t_u3auto_reconfig(int argc, char** argv){
3251 int dev_speed;
3252 unsigned int rnd_transfer_type, rdn_maxp, rdn_interval;
3253 unsigned int length;
3254 int rdn_ep_num;
3255 int num_ep, round;
3256 int i;
3257
3258 round = 2;
3259 num_ep = 1;
3260 rdn_ep_num = 1;
3261
3262 if(argc > 1){
3263 if(!strcmp(argv[1], "ss")){
3264 mtk_test_dbg( "Test super speed\n");
3265 dev_speed = DEV_SPEED_SUPER;
3266 }
3267 else if(!strcmp(argv[1], "hs")){
3268 mtk_test_dbg( "Test high speed\n");
3269 dev_speed = DEV_SPEED_HIGH;
3270 }
3271 else if(!strcmp(argv[1], "fs")){
3272 mtk_test_dbg( "Test full speed\n");
3273 dev_speed = DEV_SPEED_FULL;
3274 }
3275 else if(!strcmp(argv[1], "stop")){
3276 mtk_test_dbg( "STOP!!\n");
3277 g_correct = false;
3278 return RET_SUCCESS;
3279 }
3280 }
3281 if(argc > 2){
3282 round = (int)simple_strtol(argv[2], &argv[2], 10);
3283 }
3284 if(argc > 3){
3285 num_ep = (int)simple_strtol(argv[3], &argv[3], 10);
3286 }
3287
3288 for(i=0; i<round; i++){
3289 //random new endpoint
3290 rdn_ep_num = (get_random_int()%3)+1;
3291 rnd_transfer_type = (get_random_int()%3)+1;
3292 if(rnd_transfer_type == EPATT_ISO){
3293 rdn_interval = get_random_int()%3+1;
3294 rdn_maxp = (get_random_int()%8+1)*128;
3295 }
3296 else if(rnd_transfer_type == EPATT_BULK){
3297 rdn_interval = 0;
3298 if(dev_speed == DEV_SPEED_SUPER){
3299 rdn_maxp = 1024;
3300 }
3301 else if(dev_speed == DEV_SPEED_HIGH){
3302 rdn_maxp = 512;
3303 }
3304 else if(dev_speed == DEV_SPEED_FULL){
3305 rdn_maxp = 64;
3306 }
3307 }
3308 else if(rnd_transfer_type == EPATT_INT){
3309 rdn_interval = get_random_int()%4+1;
3310 rdn_maxp = (get_random_int()%8+1)*128;
3311 }
3312 //de-configure device endpoint
3313
3314 //de-configure endpoint
3315 if(i>0){
3316 f_deconfig_ep(1, 0, 0, NULL, 0);
3317 }
3318 //configure endpoints
3319
3320 //do loopback for 100 rounds
3321
3322 }
3323 }
3324
3325 static int t_u3auto_stress(int argc, char** argv){
3326 int ret, num_ep, i, speed;
3327 int transfer_type[5];
3328 int maxp[5],interval[5], burst[5],mult[5];
3329 char isCompare;
3330 char isEP0;
3331 int length;
3332 isCompare = true;
3333 isEP0 = false;
3334 int dev_num;
3335 int port_num;
3336 int dev_slot;
3337 struct usb_device *udev;
3338 int cur_index;
3339
3340 num_ep = 2;
3341 dev_slot = 3;
3342 ret = 0;
3343 if(argc > 1){
3344 if(!strcmp(argv[1], "ss")){
3345 mtk_test_dbg( "Test super speed\n");
3346 speed = DEV_SPEED_SUPER;
3347 }
3348 else if(!strcmp(argv[1], "hs")){
3349 mtk_test_dbg( "Test high speed\n");
3350 speed = DEV_SPEED_HIGH;
3351 }
3352 else if(!strcmp(argv[1], "fs")){
3353 mtk_test_dbg( "Test full speed\n");
3354 speed = DEV_SPEED_FULL;
3355 }
3356 else if(!strcmp(argv[1], "stop")){
3357 mtk_test_dbg( "STOP!!\n");
3358 g_correct = false;
3359 return RET_SUCCESS;
3360 }
3361 }
3362 if(argc > 2){
3363 dev_num = (int)simple_strtol(argv[2], &argv[2], 10);
3364 }
3365 if(argc > 3){
3366 //num of eps
3367 num_ep = (int)simple_strtol(argv[3], &argv[3], 10);
3368 }
3369 if(argc > 4){
3370 if(!strcmp(argv[4], "false")){
3371 isCompare = false;
3372 }
3373 }
3374 if(argc > 5){
3375 if(!strcmp(argv[5], "true")){
3376 isEP0 = true;
3377 }
3378 }
3379 //arg 6~9
3380 for(i=6; i<=9; i++){
3381 if(argc > i){
3382 cur_index = i-5;
3383 if(!strcmp(argv[i], "bulk")){
3384 mtk_test_dbg( "Test bulk transfer for ep %d\n", cur_index);
3385 transfer_type[cur_index] = EPATT_BULK;
3386 if(speed == DEV_SPEED_SUPER){
3387 maxp[cur_index] = 1024;
3388 burst[cur_index] = 8;
3389 mult[cur_index] = 0;
3390 interval[cur_index] = 1;
3391
3392 }
3393 else if(speed == DEV_SPEED_HIGH){
3394 maxp[cur_index] = 512;
3395 burst[cur_index] = 0;
3396 mult[cur_index] = 0;
3397 interval[cur_index] = 1;
3398
3399 }
3400 else if(speed == DEV_SPEED_FULL){
3401 maxp[cur_index] = 64;
3402 burst[cur_index] = 0;
3403 mult[cur_index] = 0;
3404 interval[cur_index] = 1;
3405
3406 }
3407 }
3408 else if(!strcmp(argv[i], "intr")){
3409 mtk_test_dbg( "Test intr transfer for ep %d\n", (cur_index));
3410 transfer_type[cur_index] = EPATT_INT;
3411 if(speed == DEV_SPEED_SUPER){
3412 maxp[cur_index] = 1024;
3413 burst[cur_index] = 0;
3414 mult[cur_index] = 0;
3415 interval[cur_index] = 1;
3416 }
3417 else if(speed == DEV_SPEED_HIGH){
3418 maxp[cur_index] = 1024;
3419 burst[cur_index] = 0;
3420 mult[cur_index] = 0;
3421 if(dev_num >= 5){
3422 //for LPM test
3423 interval[cur_index] = 4;
3424 }
3425 else{
3426 interval[cur_index] = 1;
3427 }
3428 }
3429 else if(speed == DEV_SPEED_FULL){
3430 maxp[cur_index] = 64;
3431 burst[cur_index] = 0;
3432 mult[cur_index] = 0;
3433 if(dev_num >= 5){
3434 //for LPM test
3435 interval[cur_index] = 3;
3436 }
3437 else{
3438 interval[cur_index] = 1;
3439 }
3440 }
3441 }
3442 else if(!strcmp(argv[i], "intr_pm")){
3443 mtk_test_dbg( "Test intr transfer for ep %d\n", (cur_index));
3444 transfer_type[cur_index] = EPATT_INT;
3445 if(speed == DEV_SPEED_SUPER){
3446 maxp[cur_index] = 1024;
3447 burst[cur_index] = 0;
3448 mult[cur_index] = 0;
3449 interval[cur_index] = 4;
3450 }
3451 }
3452 else if(!strcmp(argv[i], "intr_pm_u2")){
3453 mtk_test_dbg( "Test intr transfer for ep %d\n", (cur_index));
3454 transfer_type[cur_index] = EPATT_INT;
3455 if(speed == DEV_SPEED_SUPER){
3456 maxp[cur_index] = 1024;
3457 burst[cur_index] = 0;
3458 mult[cur_index] = 0;
3459 interval[cur_index] = 5;
3460 }
3461 }
3462 else if(!strcmp(argv[i], "isoc")){
3463 mtk_test_dbg( "Test isoc transfer for ep %d\n", (cur_index));
3464 transfer_type[cur_index] = EPATT_ISO;
3465 if(speed == DEV_SPEED_SUPER){
3466 maxp[cur_index] = 1024;
3467 burst[cur_index] = 0;
3468 mult[cur_index] = 0;
3469 interval[cur_index] = 4;
3470 }
3471 else if(speed == DEV_SPEED_HIGH){
3472 maxp[cur_index] = 1024;
3473 burst[cur_index] = 0;
3474 mult[cur_index] = 0;
3475 if(dev_num >= 5){
3476 //for LPM test
3477 interval[cur_index] = 4;
3478 }
3479 else{
3480 interval[cur_index] = 1;
3481 }
3482 }
3483 else if(speed == DEV_SPEED_FULL){
3484 maxp[cur_index] = 1023;
3485 burst[cur_index] = 0;
3486 mult[cur_index] = 0;
3487 if(dev_num >= 5){
3488 //for LPM test
3489 interval[cur_index] = 3;
3490 }
3491 else{
3492 interval[cur_index] = 1;
3493 }
3494
3495 }
3496 }
3497 else if(!strcmp(argv[i], "isoc_pm")){
3498 mtk_test_dbg( "Test isoc transfer for ep %d\n", (cur_index));
3499 transfer_type[cur_index] = EPATT_ISO;
3500 if(speed == DEV_SPEED_SUPER){
3501 maxp[cur_index] = 1024;
3502 burst[cur_index] = 0;
3503 mult[cur_index] = 0;
3504 interval[cur_index] = 5;
3505 }
3506 }
3507 }
3508 }
3509 udev = NULL;
3510 /* ==phase 0 : device reset==*/
3511 if(dev_num == 0){
3512 #if 0 //doesn't reset now, should reset to tested speed before execute this test item
3513 start_port_reenabled(0, speed);
3514 ret=dev_reset(speed, NULL);
3515 if(ret){
3516 mtk_test_dbg( "device reset failed!!!!!!!!!!\n");
3517 return ret;
3518 }
3519
3520 ret = f_disable_slot();
3521 if(ret){
3522 mtk_test_dbg( "disable slot failed!!!!!!!!!!\n");
3523 return ret;
3524 }
3525
3526 ret = f_reenable_port(0);
3527 if(ret != RET_SUCCESS){
3528 mtk_test_dbg( "device reenable failed!!!!!!!!!!\n");
3529 return ret;
3530 }
3531
3532 ret = f_enable_slot(NULL);
3533 if(ret){
3534 mtk_test_dbg( "enable slot failed!!!!!!!!!!\n");
3535 return ret;
3536 }
3537
3538 ret=f_address_slot(false, NULL);
3539 if(ret){
3540 mtk_test_dbg( "address slot failed!!!!!!!!!!\n");
3541 return ret;
3542 }
3543 udev = NULL;
3544 #endif
3545 }
3546 else if(dev_num < 5){
3547 udev = dev_list[dev_num-1];
3548 port_num = udev->portnum;
3549 f_hub_reset_dev(udev, dev_num, port_num, speed);
3550 udev = dev_list[dev_num-1];
3551 }
3552 /* ==phase 1 : config EP==*/
3553 for(i=1; i<=num_ep; i++){
3554 if(transfer_type[i] == EPATT_ISO){
3555 dev_slot = 3;
3556 }
3557 else{
3558 dev_slot = 1;
3559 }
3560 dev_config_ep(i,USB_RX, transfer_type[i], maxp[i], interval[i], dev_slot, burst[i],mult[i], udev);
3561 dev_config_ep(i,USB_TX, transfer_type[i], maxp[i], interval[i], dev_slot, burst[i],mult[i], udev);
3562
3563 f_config_ep(i,EPADD_OUT,transfer_type[i],maxp[i],interval[i],burst[i],mult[i],udev,0);
3564 if(i == num_ep){
3565 f_config_ep(i, EPADD_IN, transfer_type[i], maxp[i], interval[i],burst[i],mult[i],udev,1);
3566 }
3567 else{
3568 f_config_ep(i, EPADD_IN, transfer_type[i], maxp[i], interval[i],burst[i],mult[i],udev,0);
3569 }
3570 if(transfer_type[i] == EPATT_ISO){
3571 f_ring_enlarge(EPADD_OUT, i, -1);
3572 f_ring_enlarge(EPADD_OUT, i, -1);
3573 f_ring_enlarge(EPADD_IN, i, -1);
3574 f_ring_enlarge(EPADD_IN, i, -1);
3575 }
3576 }
3577
3578
3579 g_correct = true;
3580 ret=dev_stress(0,GPD_LENGTH_RDN ,GPD_LENGTH_RDN,0,num_ep, udev);
3581 msleep(2000);
3582 for(i=1; i<=num_ep; i++){
3583 f_add_rdn_len_str_threads(dev_num, i, maxp[i], isCompare, udev, isEP0);
3584 }
3585 if(ret){
3586 mtk_test_dbg( "stress request failed!!!!!!!!!!\n");
3587 return ret;
3588 }
3589 return ret;
3590 }
3591
3592 static int t_u3auto_isoc_frame_id(int argc, char** argv){
3593 int ret,length,start_add;
3594 char bdp;
3595 int gpd_buf_size,bd_buf_size;
3596 int transfer_type;
3597 int maxp;
3598 int bInterval;
3599 int ep_out_num, ep_in_num;
3600 int speed;
3601 int mult_dev, mult, burst;
3602 int dram_offset, extension;
3603 int i;
3604
3605 ret = 0;
3606 speed = DEV_SPEED_HIGH;;
3607 transfer_type = EPATT_ISO;
3608 bInterval = 1;
3609 ep_out_num = 1;
3610 ep_in_num = 1;
3611 length = 10241;
3612 start_add = 0;
3613 mult_dev = 3;
3614 mult = 0;
3615 burst = 0;
3616 dram_offset = 0;
3617 extension = 0;
3618
3619 if(argc > 1){
3620 if(!strcmp(argv[1], "ss")){
3621 mtk_test_dbg( "Test super speed\n");
3622 speed = DEV_SPEED_SUPER;
3623 }
3624 else if(!strcmp(argv[1], "hs")){
3625 mtk_test_dbg( "Test high speed\n");
3626 speed = DEV_SPEED_HIGH;
3627 }
3628 else if(!strcmp(argv[1], "fs")){
3629 mtk_test_dbg( "Test full speed\n");
3630 speed = DEV_SPEED_FULL;
3631 }
3632 }
3633 if(speed == DEV_SPEED_SUPER){
3634 maxp = 1024;
3635 }
3636 else if(speed == DEV_SPEED_HIGH){
3637 maxp = 1024;
3638 }
3639 else if(speed == DEV_SPEED_FULL){
3640 maxp = 1023;
3641 }
3642
3643
3644 //start test
3645 start_port_reenabled(0, speed);
3646 ret=dev_reset(speed, NULL);
3647 if(ret){
3648 mtk_test_dbg( "device reset failed!!!!!!!!!!\n");
3649 return ret;
3650 }
3651
3652 ret = f_disable_slot();
3653 if(ret){
3654 mtk_test_dbg( "disable slot failed!!!!!!!!!!\n");
3655 return ret;
3656 }
3657
3658 ret = f_reenable_port(0);
3659 if(ret != RET_SUCCESS){
3660 mtk_test_dbg( "device reenable failed!!!!!!!!!!\n");
3661 return ret;
3662 }
3663
3664 ret = f_enable_slot(NULL);
3665 if(ret){
3666 mtk_test_dbg( "enable slot failed!!!!!!!!!!\n");
3667 return ret;
3668 }
3669
3670 ret=f_address_slot(false, NULL);
3671 if(ret){
3672 mtk_test_dbg( "address slot failed!!!!!!!!!!\n");
3673 return ret;
3674 }
3675
3676 ret=dev_config_ep(ep_out_num,USB_RX,transfer_type,maxp,bInterval,mult_dev,burst,mult,NULL);
3677 if(ret)
3678 {
3679 mtk_test_dbg( "config dev EP fail!!\n");
3680 return ret;
3681 }
3682 ret=dev_config_ep(ep_in_num,USB_TX,transfer_type,maxp,bInterval,mult_dev,burst,mult,NULL);
3683 if(ret)
3684 {
3685 mtk_test_dbg( "config dev EP fail!!\n");
3686 return ret;
3687 }
3688
3689 ret = f_config_ep(ep_out_num,EPADD_OUT,transfer_type,maxp,bInterval,burst,mult, NULL,0);
3690 if(ret)
3691 {
3692 mtk_test_dbg( "config EP fail!!\n");
3693 return ret;
3694 }
3695
3696 ret = f_config_ep(ep_in_num,EPADD_IN,transfer_type,maxp,bInterval,burst,mult, NULL,1);
3697 if(ret)
3698 {
3699 mtk_test_dbg( "config EP fail!!\n");
3700 return ret;
3701 }
3702
3703 //10 round
3704 g_iso_frame = true;
3705 bdp=1;
3706 gpd_buf_size = length;
3707 bd_buf_size = 4096;
3708 for(i=0; i<10; i++){
3709 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size,dram_offset,extension,NULL);
3710 if(ret)
3711 {
3712 mtk_test_dbg( "loopback request fail!!\n");
3713 f_power_suspend();
3714 return ret;
3715 }
3716 ret = f_loopback_loop_gpd(
3717 ep_out_num, ep_in_num, length, start_add, gpd_buf_size, NULL);
3718 if(ret)
3719 {
3720 mtk_test_dbg( "loopback fail!!\n");
3721 mtk_test_dbg( "length : %d\n",length);
3722 f_power_suspend();
3723 return ret;
3724 }
3725 ret=dev_polling_status(NULL);
3726 if(ret)
3727 {
3728 f_power_suspend();
3729 mtk_test_dbg( "query request fail!!\n");
3730 return ret;
3731 }
3732 }
3733
3734 g_iso_frame = false;
3735 return RET_SUCCESS;
3736 }
3737
3738 static int t_ellysis_TD7_36(int argc, char** argv){
3739 int ret;
3740 struct device *dev;
3741 struct usb_device *udev, *rhdev;
3742 struct xhci_virt_device *virt_dev;
3743 struct xhci_hcd *xhci;
3744 struct urb *urb;
3745 struct usb_ctrlrequest *dr;
3746 struct usb_config_descriptor *desc;
3747 int i,j;
3748 char *tmp;
3749 struct urb *urb_rx;
3750 struct usb_host_endpoint *ep_rx;
3751 int ep_index_rx;
3752 void *buffer_rx;
3753 char *buffer;
3754 ret = 0;
3755
3756 if(u3auto_hcd_reset() != RET_SUCCESS)
3757 return RET_FAIL;
3758 xhci = hcd_to_xhci(my_hcd);
3759 rhdev = my_hcd->self.root_hub;
3760 udev = rhdev->children[g_port_id-1];
3761 dev = xhci_to_hcd(xhci)->self.controller;//dma stream buffer
3762 xhci_dbg(xhci, "device speed %d\n", udev->speed);
3763 //get descriptor (device)
3764 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
3765 dr->bRequestType = USB_DIR_IN;
3766 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
3767 dr->wValue = cpu_to_le16((USB_DT_DEVICE << 8) + 0);
3768 dr->wIndex = cpu_to_le16(0);
3769 dr->wLength = cpu_to_le16(8);
3770 desc = kmalloc(8, GFP_KERNEL);
3771 memset(desc, 0, 8);
3772 urb = alloc_ctrl_urb(dr, desc, udev);
3773 ret = f_ctrlrequest(urb, udev);
3774 kfree(dr);
3775 kfree(desc);
3776 usb_free_urb(urb);
3777 //get descriptor (device)
3778 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
3779 dr->bRequestType = USB_DIR_IN;
3780 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
3781 dr->wValue = cpu_to_le16((USB_DT_DEVICE << 8) + 0);
3782 dr->wIndex = cpu_to_le16(0);
3783 dr->wLength = cpu_to_le16(USB_DT_DEVICE_SIZE);
3784 desc = kmalloc(USB_DT_DEVICE_SIZE, GFP_KERNEL);
3785 memset(desc, 0, USB_DT_DEVICE_SIZE);
3786 urb = alloc_ctrl_urb(dr, desc, udev);
3787 ret = f_ctrlrequest(urb, udev);
3788 kfree(dr);
3789 kfree(desc);
3790 usb_free_urb(urb);
3791 //get descriptor (configure)
3792 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
3793 dr->bRequestType = USB_DIR_IN;
3794 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
3795 dr->wValue = cpu_to_le16((USB_DT_CONFIG << 8) + 0);
3796 dr->wIndex = cpu_to_le16(0);
3797 dr->wLength = cpu_to_le16(USB_DT_CONFIG_SIZE);
3798 desc = kmalloc(USB_DT_CONFIG_SIZE, GFP_KERNEL);
3799 memset(desc, 0, USB_DT_CONFIG_SIZE);
3800 urb = alloc_ctrl_urb(dr, desc, udev);
3801 ret = f_ctrlrequest(urb, udev);
3802 kfree(dr);
3803 kfree(desc);
3804 usb_free_urb(urb);
3805 //get descriptor (configure)
3806 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
3807 dr->bRequestType = USB_DIR_IN;
3808 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
3809 dr->wValue = cpu_to_le16((USB_DT_CONFIG << 8) + 0);
3810 dr->wIndex = cpu_to_le16(0);
3811 dr->wLength = cpu_to_le16(40);
3812 desc = kmalloc(40, GFP_KERNEL);
3813 memset(desc, 0, 40);
3814 urb = alloc_ctrl_urb(dr, desc, udev);
3815 ret = f_ctrlrequest(urb, udev);
3816 kfree(dr);
3817 kfree(desc);
3818 usb_free_urb(urb);
3819 //set configuration
3820 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
3821 dr->bRequestType = USB_DIR_OUT;
3822 dr->bRequest = USB_REQ_SET_CONFIGURATION;
3823 dr->wValue = cpu_to_le16(1);
3824 dr->wIndex = cpu_to_le16(0);
3825 dr->wLength = cpu_to_le16(0);
3826 urb = alloc_ctrl_urb(dr, NULL, udev);
3827 ret = f_ctrlrequest(urb,udev);
3828 kfree(dr);
3829 usb_free_urb(urb);
3830 //set idle
3831 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
3832 dr->bRequestType = USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE;
3833 dr->bRequest = 0x0A;
3834 dr->wValue = cpu_to_le16(0);
3835 dr->wIndex = cpu_to_le16(0);
3836 dr->wLength = cpu_to_le16(0);
3837 urb = alloc_ctrl_urb(dr, NULL, udev);
3838 ret = f_ctrlrequest(urb,udev);
3839 kfree(dr);
3840 usb_free_urb(urb);
3841 //get descriptor (HID report)
3842 ret = f_config_ep(1, EPADD_IN, EPATT_INT, 4, 7,0,0, udev, 1);
3843 //interrupt input
3844 ep_rx = udev->ep_in[1];
3845 ep_index_rx = mtktest_xhci_get_endpoint_index(&ep_rx->desc);
3846 xhci_err(xhci, "[INPUT]\n");
3847 for(i=0; i<10; i++){
3848 urb_rx = usb_alloc_urb(0, GFP_KERNEL);
3849 ret = f_fill_urb(urb_rx,1,4,0,EPADD_IN, 0, 4, udev);
3850 if(ret){
3851 xhci_err(xhci, "[ERROR]fill rx urb Error!!\n");
3852 return RET_FAIL;
3853 }
3854 urb_rx->transfer_flags &= ~URB_ZERO_PACKET;
3855 ret = f_queue_urb(urb_rx,1,udev);
3856 if(ret){
3857 xhci_err(xhci, "[ERROR]rx urb transfer failed!!\n");
3858 return RET_FAIL;
3859 }
3860 dma_sync_single_for_cpu(dev,urb_rx->transfer_dma, 4,DMA_BIDIRECTIONAL);
3861 for(j=0; j<urb_rx->transfer_buffer_length; j++){
3862 tmp = urb_rx->transfer_buffer+i;
3863 //xhci_err(xhci, "%x ", *tmp);
3864 }
3865 //xhci_err(xhci, "\n");
3866 usb_free_urb(urb_rx);
3867 }
3868
3869 return ret;
3870 }
3871
3872 static int t_class_keyboard(int argc, char** argv){
3873 int ret;
3874 struct device *dev;
3875 struct usb_device *udev, *rhdev;
3876 struct xhci_virt_device *virt_dev;
3877 struct xhci_hcd *xhci;
3878 struct urb *urb;
3879 struct usb_ctrlrequest *dr;
3880 int i;
3881 char *tmp;
3882 struct urb *urb_rx;
3883 struct usb_host_endpoint *ep_rx;
3884 int ep_index_rx;
3885 void *buffer_rx;
3886 char *buffer;
3887 ret = 0;
3888
3889 if(u3auto_hcd_reset() != RET_SUCCESS)
3890 return RET_FAIL;
3891
3892 //set configuration
3893 xhci = hcd_to_xhci(my_hcd);
3894 rhdev = my_hcd->self.root_hub;
3895 udev = rhdev->children[g_port_id-1];
3896 dev = xhci_to_hcd(xhci)->self.controller;//dma stream buffer
3897 xhci_dbg(xhci, "device speed %d\n", udev->speed);
3898 //set configuration
3899 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
3900 dr->bRequestType = USB_DIR_OUT;
3901 dr->bRequest = USB_REQ_SET_CONFIGURATION;
3902 dr->wValue = cpu_to_le16(1);
3903 dr->wIndex = cpu_to_le16(0);
3904 dr->wLength = cpu_to_le16(0);
3905 urb = alloc_ctrl_urb(dr, NULL, udev);
3906 ret = f_ctrlrequest(urb,udev);
3907 kfree(dr);
3908 usb_free_urb(urb);
3909 //set idle
3910 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
3911 dr->bRequestType = 0x21;
3912 dr->bRequest = 0x0a;
3913 dr->wValue = cpu_to_le16(0);
3914 dr->wIndex = cpu_to_le16(0);
3915 dr->wLength = cpu_to_le16(0);
3916 urb = alloc_ctrl_urb(dr, NULL, udev);
3917 ret = f_ctrlrequest(urb,udev);
3918 kfree(dr);
3919 usb_free_urb(urb);
3920 //set report
3921 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
3922 dr->bRequestType = 0x21;
3923 dr->bRequest = 0x09;
3924 dr->wValue = cpu_to_le16(0x200);
3925 dr->wIndex = cpu_to_le16(0);
3926 dr->wLength = cpu_to_le16(1);
3927 buffer = kmalloc(1, GFP_KERNEL);
3928 *buffer = 0x01;
3929 urb = alloc_ctrl_urb(dr, buffer, udev);
3930 ret = f_ctrlrequest(urb,udev);
3931 kfree(dr);
3932 usb_free_urb(urb);
3933 kfree(buffer);
3934
3935 //config a interrupt IN endpiont, ep_num=1
3936 ret = f_config_ep(1, EPADD_IN, EPATT_INT, 8, 10,0,0, udev, 1);
3937
3938 //continuous queue interrupt transfer for 10 times
3939 ep_rx = udev->ep_in[1];
3940 ep_index_rx = mtktest_xhci_get_endpoint_index(&ep_rx->desc);
3941 xhci_err(xhci, "[INPUT]\n");
3942 for(i=0; i<100; i++){
3943 urb_rx = usb_alloc_urb(0, GFP_KERNEL);
3944 ret = f_fill_urb(urb_rx,1,8,0,EPADD_IN, 0, 8, udev);
3945 if(ret){
3946 xhci_err(xhci, "[ERROR]fill rx urb Error!!\n");
3947 return RET_FAIL;
3948 }
3949 urb_rx->transfer_flags &= ~URB_ZERO_PACKET;
3950 ret = f_queue_urb(urb_rx,1,udev);
3951 if(ret){
3952 xhci_err(xhci, "[ERROR]rx urb transfer failed!!\n");
3953 return RET_FAIL;
3954 }
3955 dma_sync_single_for_cpu(dev,urb_rx->transfer_dma, 8,DMA_BIDIRECTIONAL);
3956 for(i=0; i<urb_rx->transfer_buffer_length; i++){
3957 tmp = urb_rx->transfer_buffer+i;
3958 xhci_err(xhci, "%x ", *tmp);
3959 }
3960 xhci_err(xhci, "\n");
3961 usb_free_urb(urb_rx);
3962 }
3963
3964 return ret;
3965 }
3966
3967 static int t_u3auto_randomstop_dev(int argc, char** argv){
3968 int ret;
3969 int speed, transfer_type_1, transfer_type_2, maxp_1, maxp_2, gpd_buf_size, bdp
3970 , bd_buf_size, ep_1_num, ep_2_num, dir_1, dir_2, dev_dir_1, dev_dir_2
3971 , urb_dir_1, urb_dir_2, length;
3972 int stop_count_1, stop_count_2;
3973
3974 //static parameters
3975 int bInterval = 1;
3976 int mult_dev = 1;
3977 int burst = 0;
3978
3979 speed = DEV_SPEED_HIGH;
3980 transfer_type_1 = transfer_type_2 = EPATT_BULK;
3981 maxp_1 = maxp_2 = 512;
3982 gpd_buf_size = 16*1024;
3983 bd_buf_size = 0;
3984 ep_1_num = 1;
3985 dir_1 = EPADD_OUT;
3986 dev_dir_1 = USB_RX;
3987 urb_dir_1 = URB_DIR_OUT;
3988
3989 ep_2_num = 2;
3990 dir_2 = EPADD_IN;
3991 dev_dir_2 = USB_TX;
3992 urb_dir_2 = URB_DIR_IN;
3993
3994 bInterval =0;
3995 mult_dev =1;
3996 burst =4;
3997
3998 stop_count_1 = stop_count_2 = 3;
3999
4000 if(argc > 1){
4001 if(!strcmp(argv[1], "ss")){
4002 mtk_test_dbg( "Test super speed\n");
4003 speed = DEV_SPEED_SUPER; //TODO: superspeed
4004 }
4005 else if(!strcmp(argv[1], "hs")){
4006 mtk_test_dbg( "Test high speed\n");
4007 speed = DEV_SPEED_HIGH;
4008 }
4009 else if(!strcmp(argv[1], "fs")){
4010 mtk_test_dbg( "Test full speed\n");
4011 speed = DEV_SPEED_FULL;
4012 }
4013 }
4014 if(argc > 2){
4015 if(!strcmp(argv[2], "bulk")){
4016 mtk_test_dbg( "Tx BULK transfer\n");
4017 transfer_type_1 = EPATT_BULK;
4018 }
4019 else if(!strcmp(argv[2], "intr")){
4020 mtk_test_dbg( "Tx INTERRUPT transfer\n");
4021 transfer_type_1 = EPATT_INT;
4022 }
4023 else if(!strcmp(argv[2], "isoc")){
4024 mtk_test_dbg( "Tx ISOC transfer\n");
4025 transfer_type_1 = EPATT_ISO;
4026 }
4027 }
4028 if(argc > 3){
4029 if(!strcmp(argv[3], "bulk")){
4030 mtk_test_dbg( "Rx BULK transfer\n");
4031 transfer_type_2 = EPATT_BULK;
4032 }
4033 else if(!strcmp(argv[3], "intr")){
4034 mtk_test_dbg( "Rx INTERRUPT transfer\n");
4035 transfer_type_2 = EPATT_INT;
4036 }
4037 else if(!strcmp(argv[3], "isoc")){
4038 mtk_test_dbg( "Rx ISOC transfer\n");
4039 transfer_type_2 = EPATT_ISO;
4040 }
4041 }
4042 if(argc > 4){
4043 ep_1_num= (int)simple_strtol(argv[4], &argv[4], 10);
4044 }
4045 if(argc > 5){
4046 ep_2_num= (int)simple_strtol(argv[5], &argv[5], 10);
4047 }
4048 if(argc > 6){
4049 if(!strcmp(argv[6], "OUT")){
4050 dir_1 = EPADD_OUT;
4051 dev_dir_1 = USB_RX;
4052 urb_dir_1 = URB_DIR_OUT;
4053 }
4054 else{
4055 dir_1 = EPADD_IN;
4056 dev_dir_1 = USB_TX;
4057 urb_dir_1 = URB_DIR_IN;
4058 }
4059 }
4060 if(argc > 7){
4061 if(!strcmp(argv[7], "OUT")){
4062 dir_2 = EPADD_OUT;
4063 dev_dir_2 = USB_RX;
4064 urb_dir_2 = URB_DIR_OUT;
4065 }
4066 else{
4067 dir_2 = EPADD_IN;
4068 dev_dir_2 = USB_TX;
4069 urb_dir_2 = URB_DIR_IN;
4070 }
4071 }
4072 if(argc > 8){
4073 maxp_1 = (int)simple_strtol(argv[8], &argv[8], 10);
4074 }
4075 if(argc > 9){
4076 maxp_2 = (int)simple_strtol(argv[9], &argv[9], 10);
4077 }
4078 if(argc > 10){
4079 gpd_buf_size = (int)simple_strtol(argv[10], &argv[10], 10);
4080 }
4081 if(argc > 11){
4082 bd_buf_size = (int)simple_strtol(argv[11], &argv[11], 10);
4083 }
4084 if(argc > 12){
4085 stop_count_1 = (int)simple_strtol(argv[12], &argv[12], 10);
4086 }
4087 if(argc > 13){
4088 stop_count_2 = (int)simple_strtol(argv[13], &argv[13], 10);
4089 }
4090 //config EP
4091 ret=dev_config_ep(ep_1_num,dev_dir_1,transfer_type_1,maxp_1, bInterval,mult_dev,burst,0, NULL);
4092 if(ret)
4093 {
4094 mtk_test_dbg( "config dev EP fail!!\n");
4095 return ret;
4096 }
4097
4098 ret=dev_config_ep(ep_2_num,dev_dir_2,transfer_type_2,maxp_2, bInterval,mult_dev,burst,0, NULL);
4099 if(ret)
4100 {
4101 mtk_test_dbg( "config dev EP fail!!\n");
4102 return ret;
4103 }
4104
4105 ret = f_config_ep(ep_1_num,dir_1,transfer_type_1,maxp_1,bInterval,8,0, NULL,0);
4106 if(ret)
4107 {
4108 mtk_test_dbg( "config EP fail!!\n");
4109 return ret;
4110 }
4111
4112 ret = f_config_ep(ep_2_num,dir_2,transfer_type_2,maxp_2,bInterval,8,0, NULL,1);
4113 if(ret)
4114 {
4115 mtk_test_dbg( "config EP fail!!\n");
4116 return ret;
4117 }
4118
4119
4120 length = gpd_buf_size;
4121
4122 ret=dev_random_stop(length, gpd_buf_size, bd_buf_size, dev_dir_1, dev_dir_2, stop_count_1, stop_count_2);
4123 if(ret){
4124 mtk_test_dbg( "random stop request failed!!!!!!!!!!\n");
4125 return ret;
4126 }
4127 ret = f_random_stop(ep_1_num, ep_2_num, stop_count_1, stop_count_2, urb_dir_1, urb_dir_2, length);
4128
4129
4130 return ret;
4131 }
4132
4133
4134 static int t_ring_random_ring_doorbell(int argc, char** argv){
4135 int ep_num, ep_dir, ep_index;
4136 struct xhci_hcd *xhci;
4137
4138 ep_dir = EPADD_OUT;
4139 ep_num = 1;
4140
4141 if(argc > 1){
4142 if(!strcmp(argv[1], "out")){
4143 mtk_test_dbg( "OUT EP\n");
4144 ep_dir = EPADD_OUT;
4145 }
4146 else if(!strcmp(argv[1], "in")){
4147 mtk_test_dbg( "IN EP\n");
4148 ep_dir = EPADD_IN;
4149 }
4150 }
4151 if(argc > 2){
4152 ep_num = (int)simple_strtol(argv[2], &argv[2], 10);
4153 mtk_test_dbg( "ep num set to %d\n", ep_num);
4154 }
4155 if(ep_num == 0){
4156 ep_index = 0;
4157 }
4158 else{
4159 if(ep_dir == EPADD_OUT){
4160 ep_index = ep_num * 2 - 1;
4161 }
4162 else{
4163 ep_index = ep_num * 2;
4164 }
4165 }
4166 xhci = hcd_to_xhci(my_hcd);
4167 f_add_random_ring_doorbell_thread(xhci, g_slot_id, ep_index);
4168 return RET_SUCCESS;
4169 }
4170
4171 static int t_power_random_access_regs(int argc, char** argv){
4172 int port_id, port_rev, power_required;
4173 struct xhci_hcd *xhci;
4174
4175 if(argc < 4){
4176 mtk_test_dbg( "arg: port_id port_rev is_power_required\n");
4177 }
4178 port_id = (int)simple_strtol(argv[1], &argv[1], 10);
4179 port_rev = (int)simple_strtol(argv[2], &argv[2], 10);
4180 if(!strcmp(argv[3], "true")){
4181 power_required = 1;
4182 }
4183 else{
4184 power_required = 0;
4185 }
4186 xhci = hcd_to_xhci(my_hcd);
4187 f_add_random_access_reg_thread(xhci, port_id, port_rev, power_required);
4188 return RET_SUCCESS;
4189 }
4190
4191 static int t_ring_random_stop_ep(int argc, char** argv){
4192 int ep_num, ep_dir, ep_index;
4193 struct xhci_hcd *xhci;
4194
4195 ep_dir = EPADD_OUT;
4196 ep_num = 1;
4197
4198 if(argc > 1){
4199 if(!strcmp(argv[1], "out")){
4200 mtk_test_dbg( "OUT EP\n");
4201 ep_dir = EPADD_OUT;
4202 }
4203 else if(!strcmp(argv[1], "in")){
4204 mtk_test_dbg( "IN EP\n");
4205 ep_dir = EPADD_IN;
4206 }
4207 }
4208 if(argc > 2){
4209 ep_num = (int)simple_strtol(argv[2], &argv[2], 10);
4210 mtk_test_dbg( "ep num set to %d\n", ep_num);
4211 }
4212 if(ep_num == 0){
4213 ep_index = 0;
4214 }
4215 else{
4216 if(ep_dir == EPADD_OUT){
4217 ep_index = ep_num * 2 - 1;
4218 }
4219 else{
4220 ep_index = ep_num * 2;
4221 }
4222 }
4223 xhci = hcd_to_xhci(my_hcd);
4224 g_test_random_stop_ep = true;
4225 f_add_random_stop_ep_thread(xhci, g_slot_id, ep_index);
4226 return RET_SUCCESS;
4227 }
4228
4229 static int t_loopback_configep(int argc, char** argv){
4230 int transfer_type;
4231 int maxp;
4232 int bInterval;
4233 int ep_num, ep_dir;
4234 char is_config;
4235 int mult, burst;
4236
4237
4238 transfer_type = EPATT_BULK;
4239 ep_dir = EPADD_OUT;
4240 maxp = 512;
4241 ep_num = 1;
4242 bInterval = 0;
4243 is_config=0;
4244
4245
4246 if(argc > 1){
4247 if(!strcmp(argv[1], "bulk")){
4248 mtk_test_dbg( "Test bulk transfer\n");
4249 transfer_type = EPATT_BULK;
4250 }
4251 else if(!strcmp(argv[1], "intr")){
4252 mtk_test_dbg( "Test intr transfer\n");
4253 transfer_type = EPATT_INT;
4254 }
4255 else if(!strcmp(argv[1], "isoc")){
4256 mtk_test_dbg( "Test isoc transfer\n");
4257 transfer_type = EPATT_ISO;
4258 }
4259 }
4260 if(argc > 2){
4261 if(!strcmp(argv[2], "out")){
4262 mtk_test_dbg( "OUT EP\n");
4263 ep_dir = EPADD_OUT;
4264 }
4265 else if(!strcmp(argv[2], "in")){
4266 mtk_test_dbg( "IN EP\n");
4267 ep_dir = EPADD_IN;
4268 }
4269 }
4270 if(argc > 3){
4271 maxp = (int)simple_strtol(argv[3], &argv[3], 10);
4272 mtk_test_dbg( "maxp set to %d\n", maxp);
4273 }
4274 if(argc > 4){
4275 bInterval = (int)simple_strtol(argv[4], &argv[4], 10);
4276 mtk_test_dbg( "interval set to %d\n", bInterval);
4277 }
4278 if(argc > 5){
4279 ep_num = (int)simple_strtol(argv[5], &argv[5], 10);
4280 mtk_test_dbg( "ep num set to %d\n", ep_num);
4281 }
4282 if(argc > 6){
4283 is_config = (int)simple_strtol(argv[6], &argv[6], 10);
4284 mtk_test_dbg( "is_config set to %d\n", is_config);
4285 }
4286 if(argc > 7){
4287 burst = (int)simple_strtol(argv[7], &argv[7], 10);
4288 mtk_test_dbg( "burst set to %d\n", burst);
4289 }
4290 if(argc > 8){
4291 mult = (int)simple_strtol(argv[8], &argv[8], 10);
4292 mtk_test_dbg( "mult set to %d\n", mult);
4293 }
4294 return f_config_ep(ep_num, ep_dir, transfer_type, maxp, bInterval,burst,mult, NULL, is_config);
4295 }
4296
4297 static int t_loopback_deconfigep(int argc, char** argv){
4298 //all or one-by-one
4299 int ep_num, ep_dir;
4300 char is_config;
4301 char is_all;
4302
4303
4304 ep_dir = EPADD_OUT;
4305 ep_num = 1;
4306 is_all = false;
4307 is_config=0;
4308
4309
4310 if(argc > 1){
4311 if(!strcmp(argv[1], "out")){
4312 mtk_test_dbg( "OUT EP\n");
4313 ep_dir = EPADD_OUT;
4314 }
4315 else if(!strcmp(argv[1], "in")){
4316 mtk_test_dbg( "IN EP\n");
4317 ep_dir = EPADD_IN;
4318 }
4319 else if(!strcmp(argv[1], "all")){
4320 mtk_test_dbg( "all EP\n");
4321 is_all = true;
4322 }
4323
4324 }
4325 if(argc > 2){
4326 ep_num = (int)simple_strtol(argv[2], &argv[2], 10);
4327 mtk_test_dbg( "ep num set to %d\n", ep_num);
4328 }
4329 if(argc > 3){
4330 is_config = (int)simple_strtol(argv[3], &argv[3], 10);
4331 mtk_test_dbg( "is_config set to %d\n", is_config);
4332 }
4333 f_deconfig_ep(is_all, ep_num, ep_dir, NULL, is_config);
4334 }
4335
4336 static int t_loopback_loop(int argc, char** argv){
4337 int ret,length,start_add;
4338 char bdp;
4339 int gpd_buf_size,bd_buf_size;
4340 int ep_out_num, ep_in_num;
4341 int speed;
4342 int sg_len;
4343 int round, i;
4344 int dram_offset, extension;
4345
4346 ret =0;
4347 speed = DEV_SPEED_HIGH;
4348 ep_out_num = 1;
4349 ep_in_num = 1;
4350 length = 65535;
4351 round=1;
4352 dram_offset = 0;
4353 extension = 0;
4354 sg_len = 0;
4355
4356 if(argc > 1){
4357 length = (int)simple_strtol(argv[1], &argv[1], 10);
4358 mtk_test_dbg( "length set to %d\n", length);
4359 }
4360 if(argc > 2){
4361 start_add = (int)simple_strtol(argv[2], &argv[2], 10);
4362 mtk_test_dbg( "start add offset set to %d\n", start_add);
4363 }
4364 if(argc > 3){
4365 ep_out_num = (int)simple_strtol(argv[3], &argv[3], 10);
4366 mtk_test_dbg( "ep out num set to %d\n", ep_out_num);
4367 }
4368 if(argc > 4){
4369 ep_in_num = (int)simple_strtol(argv[4], &argv[4], 10);
4370 mtk_test_dbg( "ep in num set to %d\n", ep_in_num);
4371 }
4372
4373 if(argc > 5){
4374 round = (int)simple_strtol(argv[5], &argv[5], 10);
4375 mtk_test_dbg( "Execute %d round\n", round);
4376 }
4377
4378 if(argc > 6){
4379 sg_len = (int)simple_strtol(argv[6], &argv[6], 10);
4380 mtk_test_dbg( "sg_len set to %d\n", sg_len);
4381 }
4382
4383 bdp=1;
4384 gpd_buf_size=length;
4385 bd_buf_size=4096;
4386 //TODO: device should turn off extension length feature
4387 #if 0
4388 if(((length-10)%(bd_buf_size+6))<7){
4389 length+=12;
4390 }
4391 #endif
4392 for(i=0; i<round; i++){
4393 if(round==1){}
4394 else{
4395 length = (get_random_int() % 65535) + 1;
4396 start_add = get_random_int() % 64;
4397 gpd_buf_size = length;
4398 mtk_test_dbg( "ROUND[%d] length[%d] start_add[%d]\n", i, length, start_add);
4399 }
4400 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size,dram_offset,extension,NULL);
4401 if(ret)
4402 {
4403 mtk_test_dbg( "loopback request fail!!\n");
4404 return ret;
4405 }
4406 if(sg_len == 0){
4407 ret = f_loopback_loop(ep_out_num, ep_in_num, length, start_add,NULL);
4408 }
4409 else{
4410 ret = f_loopback_sg_loop(ep_out_num,ep_in_num,length,start_add,sg_len,NULL);
4411 }
4412 if(ret)
4413 {
4414 mtk_test_dbg( "loopback fail!!\n");
4415 mtk_test_dbg( "length : %d\n",length);
4416 return ret;
4417 }
4418
4419 /* ==phase 3: get device status==*/
4420 ret=dev_polling_status(NULL);
4421 if(ret)
4422 {
4423 mtk_test_dbg( "query request fail!!\n");
4424 return ret;
4425 }
4426 }
4427 return ret;
4428 }
4429
4430 static int t_power_suspend(int argc, char** argv){
4431 return f_power_suspend();
4432 }
4433
4434 static int t_power_resume(int argc, char** argv){
4435 return f_power_resume();
4436 }
4437
4438 static int t_power_suspendport(int argc, char** argv){
4439 u32 __iomem *addr;
4440 int temp;
4441 int port_id;
4442 struct xhci_hcd *xhci;
4443
4444 port_id = g_port_id;
4445
4446 if(argc > 1){
4447 port_id = (int)simple_strtol(argv[1], &argv[1], 10);
4448 }
4449
4450 xhci = hcd_to_xhci(my_hcd);
4451
4452 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
4453 temp = xhci_readl(xhci, addr);
4454 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
4455 temp = mtktest_xhci_port_state_to_neutral(temp);
4456 temp = (temp & ~(0xf << 5));
4457 temp = (temp | (3 << 5) | PORT_LINK_STROBE);
4458 xhci_writel(xhci, temp, addr);
4459 mtk_xhci_handshake(xhci, addr, (15<<5), (3<<5), 30*1000);
4460 temp = xhci_readl(xhci, addr);
4461 if(PORT_PLS_VALUE(temp) != 3){
4462 xhci_err(xhci, "port not enter U3 state\n");
4463 return RET_FAIL;
4464 }
4465 return RET_SUCCESS;
4466 }
4467
4468 static int t_power_resumeport(int argc, char** argv){
4469 u32 __iomem *addr;
4470 int temp;
4471 int port_id;
4472 int i;
4473 struct xhci_hcd *xhci;
4474
4475 port_id = g_port_id;
4476
4477 if(argc > 1){
4478 port_id = (int)simple_strtol(argv[1], &argv[1], 10);
4479 }
4480
4481 xhci = hcd_to_xhci(my_hcd);
4482
4483 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
4484 temp = xhci_readl(xhci, addr);
4485 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
4486 if(PORT_PLS(temp) != (3 << 5)){
4487 xhci_err(xhci, "port not in U3 state\n");
4488 return RET_FAIL;
4489 }
4490
4491 temp = mtktest_xhci_port_state_to_neutral(temp);
4492 temp = (temp & ~(0xf << 5));
4493
4494 if(DEV_SUPERSPEED(temp)){
4495 //superspeed direct set U0
4496 temp = (temp | PORT_LINK_STROBE);
4497 xhci_writel(xhci, temp, addr);
4498 }
4499 else{
4500 //HS/FS, set resume for 20ms, then set U0
4501 temp = (temp | (15 << 5) | PORT_LINK_STROBE);
4502 xhci_writel(xhci, temp, addr);
4503 mdelay(20);
4504 temp = xhci_readl(xhci, addr);
4505 temp = mtktest_xhci_port_state_to_neutral(temp);
4506 temp = (temp & ~(0xf << 5));
4507 temp = (temp | PORT_LINK_STROBE);
4508 xhci_writel(xhci, temp, addr);
4509 }
4510 for(i=0; i<200; i++){
4511 temp = xhci_readl(xhci, addr);
4512 if(PORT_PLS_VALUE(temp) == 0){
4513 break;
4514 }
4515 msleep(1);
4516
4517 }
4518 if(PORT_PLS_VALUE(temp) != 0){
4519 xhci_err(xhci, "port not return U0 state\n");
4520 return RET_FAIL;
4521 }
4522 return RET_SUCCESS;
4523 }
4524
4525
4526 static int t_power_remotewakeup(int argc, char** argv){
4527 return f_power_remotewakeup();
4528 }
4529
4530 static int t_power_u1u2(int argc, char** argv){
4531 int ret;
4532 int u_num;
4533 int value1, value2;
4534
4535 u_num = 1;
4536 value1 = 1;
4537 value2 = 1;
4538 if(argc > 1){
4539 u_num = (int)simple_strtol(argv[1], &argv[1], 10);
4540 // xhci_dbg(xhci, "u_num set to %d\n", u_num);
4541 }
4542 if(argc > 2){
4543 value1 = (int)simple_strtol(argv[2], &argv[2], 10);
4544 // xhci_dbg(xhci, "value1 set to %d\n", value1);
4545 }
4546 if(argc > 3){
4547 value2 = (int)simple_strtol(argv[3], &argv[3], 10);
4548 // xhci_dbg(xhci, "value2 set to %d\n", value2);
4549 }
4550 if(u_num < 4){
4551 return f_power_set_u1u2(u_num, value1, value2);
4552 }
4553 else{
4554 if(u_num == 4){
4555 //reset counter
4556 f_power_reset_u1u2_counter(1);
4557 f_power_reset_u1u2_counter(2);
4558 return RET_SUCCESS;
4559
4560 }
4561 else if (u_num == 5){
4562 //print counter
4563 mtk_test_dbg( "u1 counter = %d\n", f_power_get_u1u2_counter(1));
4564 mtk_test_dbg( "u2 counter = %d\n", f_power_get_u1u2_counter(2));
4565 return RET_SUCCESS;
4566 }
4567 }
4568 }
4569
4570 static int t_power_u2_lpm(int argc, char** argv){
4571 int ret;
4572 int hle, rwe, hirdm, besl, besld, pdn, int_nak_active, bulk_nyet_active;
4573 int L1_timeout;
4574 if(argc > 1){
4575 hle = (int)simple_strtol(argv[1], &argv[1], 10);
4576 }
4577 if(argc > 2){
4578 rwe = (int)simple_strtol(argv[2], &argv[2], 10);
4579 }
4580 if(argc > 3){
4581 hirdm = (int)simple_strtol(argv[3], &argv[3], 10);
4582 }
4583 if(argc > 4){
4584 L1_timeout = (int)simple_strtol(argv[4], &argv[4], 10);
4585 }
4586 if(argc > 5){
4587 besl = (int)simple_strtol(argv[5], &argv[5], 10);
4588 }
4589 if(argc > 6){
4590 besld = (int)simple_strtol(argv[6], &argv[6], 10);
4591 }
4592 if(argc > 7){
4593 pdn = (int)simple_strtol(argv[7], &argv[7], 10);
4594 }
4595 if(argc > 8){
4596 int_nak_active = (int)simple_strtol(argv[8], &argv[8], 10);
4597 }
4598 if(argc > 9){
4599 bulk_nyet_active = (int)simple_strtol(argv[9], &argv[9], 10);
4600 }
4601
4602 //program hle, rwe
4603 f_power_config_lpm(g_slot_id, hirdm, L1_timeout, rwe, besl, besld, hle, int_nak_active, bulk_nyet_active);
4604
4605 return RET_SUCCESS;
4606 }
4607
4608 static int t_power_u2_swlpm(int argc, char** argv){
4609 int ret;
4610 int expected_L1S;
4611 struct xhci_hcd *xhci;
4612 u32 __iomem *addr;
4613 int temp;
4614 char is_wakeup;
4615 int num_u3_port;
4616
4617 ret = RET_SUCCESS;
4618 is_wakeup = false;
4619 if(argc > 1){
4620 //0:resume 1:accept, 2:NYET, 3:STALL, 4:timeout, 5:remote_wakeup, 6:reset counter, 7:print counter
4621 expected_L1S = (int)simple_strtol(argv[1], &argv[1], 10);
4622 }
4623 if(expected_L1S == 5){
4624 expected_L1S = 1;
4625 is_wakeup = true;
4626
4627 }
4628 if(expected_L1S == 6){
4629 f_power_reset_L1_counter(1);
4630 f_power_reset_L1_counter(2);
4631 return RET_SUCCESS;
4632 }
4633 if(expected_L1S == 7){
4634 //print counter
4635 mtk_test_dbg( "L1 entr counter = %d\n", f_power_get_L1_counter(1));
4636 mtk_test_dbg( "L1 exit counter = %d\n", f_power_get_L1_counter(2));
4637 return RET_SUCCESS;
4638 }
4639 g_port_plc = 0;
4640 xhci = hcd_to_xhci(my_hcd);
4641
4642 num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
4643 mtktest_enablePortClockPower((g_port_id-1-num_u3_port), 0x2);
4644
4645 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*((g_port_id-1) & 0xff);
4646 temp = xhci_readl(xhci, addr);
4647 temp = mtktest_xhci_port_state_to_neutral(temp);
4648 temp = (temp & ~(0xf << 5));
4649 if(expected_L1S == 0){
4650 temp = (temp | PORT_LINK_STROBE);
4651 xhci_writel(xhci, temp, addr);
4652 ret = mtk_xhci_handshake(xhci, addr, (0xf << 5), expected_L1S, ATTACH_TIMEOUT);
4653 if(ret != 0){
4654 xhci_err(xhci, "resume failed\n");
4655 return RET_FAIL;
4656 }
4657 else{
4658 return RET_SUCCESS;
4659 }
4660 #if 0
4661 temp = (temp | (0xf << 5) | PORT_LINK_STROBE);
4662 xhci_writel(xhci, temp, addr);
4663 msleep(20);
4664 temp = xhci_readl(xhci, addr);
4665 temp = mtktest_xhci_port_state_to_neutral(temp);
4666 temp = (temp & ~(0xf << 5));
4667 temp = (temp | PORT_LINK_STROBE);
4668 xhci_writel(xhci, temp, addr);
4669 ret = mtk_xhci_handshake(xhci, addr, (0xf << 5), expected_L1S, ATTACH_TIMEOUT);
4670 if(ret != 0){
4671 xhci_err(xhci, "resume failed\n");
4672 return RET_FAIL;
4673 }
4674 else{
4675 return RET_SUCCESS;
4676 }
4677 #endif
4678 }
4679 else{
4680 /* if expected_L1S != 1, go into L1 state */
4681 temp = (temp | (2 << 5) | PORT_LINK_STROBE);
4682 }
4683 if(is_wakeup){
4684 g_port_plc = 0;
4685 }
4686 xhci_writel(xhci, temp, addr);
4687 addr = &xhci->op_regs->port_power_base + NUM_PORT_REGS*((g_port_id-1) & 0xff);
4688 /* check L1 status of PORTPMSC */
4689 ret = mtk_xhci_handshake(xhci, addr, 0x7, expected_L1S, ATTACH_TIMEOUT);
4690 if(ret != 0){
4691 xhci_err(xhci, "L1S doesn't as expected, expected[%d], actual[%d]\n"
4692 , expected_L1S, xhci_readl(xhci, addr));
4693 return RET_FAIL;
4694 }
4695 if(expected_L1S == 2 || expected_L1S == 3 || expected_L1S == 4){
4696 if(g_port_plc == 0){
4697 xhci_err(xhci, "Doesn't get port PLC event\n");
4698 return RET_FAIL;
4699 }
4700 }
4701 if(expected_L1S == 1){
4702 mtktest_disablePortClockPower((g_port_id-1-num_u3_port), 0x2);
4703
4704 }
4705
4706 if(is_wakeup){
4707 wait_event_on_timeout(&g_port_plc, 1, 5000);
4708 if(g_port_plc == 0){
4709 xhci_err(xhci, "No port state change event\n");
4710 return RET_FAIL;
4711 }
4712 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*((g_port_id-1) & 0xff);
4713 ret = mtk_xhci_handshake(xhci, addr, (0xf << 5), 0, ATTACH_TIMEOUT);
4714 if(ret != 0){
4715 xhci_err(xhci, "Remote wakeup failed\n");
4716 }
4717 #if 0
4718 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*((g_port_id-1) & 0xff);
4719 ret = mtk_xhci_handshake(xhci, addr, (0xf << 5), 0, ATTACH_TIMEOUT);
4720 if(ret != 0){
4721 xhci_err(xhci, "Remote wakeup failed\n");
4722 }
4723 #endif
4724 }
4725 return ret;
4726 }
4727
4728 static int t_power_fla(int argc, char** argv){
4729 int ret;
4730 int fla_value;
4731
4732 if(argc > 1){
4733 fla_value = (int)simple_strtol(argv[1], &argv[1], 10);
4734 xhci_dbg(xhci, "fla_value set to %d\n", fla_value);
4735 }
4736 return f_power_send_fla(fla_value);
4737 }
4738
4739 static int t_power_occ(int argc, char** argv){
4740 int ret;
4741 u32 __iomem *addr;
4742 int temp;
4743 struct xhci_hcd *xhci;
4744 struct xhci_port *port;
4745 int i, port_id;
4746
4747 xhci = hcd_to_xhci(my_hcd);
4748 #if 1
4749 g_port_occ = false;
4750 g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
4751 g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
4752 //disable U2 port first
4753 for(i=1; i<=g_num_u2_port; i++){
4754 port_id=i+g_num_u3_port;
4755 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
4756 temp = xhci_readl(xhci, addr);
4757 temp = mtktest_xhci_port_state_to_neutral(temp);
4758 temp &= ~PORT_POWER;
4759 xhci_writel(xhci, temp, addr);
4760 }
4761 #endif
4762 addr = 0xf0008098;
4763 temp = readl(addr);
4764 temp |= (1<<16);
4765 writel(temp, addr);
4766 msleep(3);
4767 if(g_port_occ == true){
4768 ret = RET_SUCCESS;
4769 }
4770 else{
4771 mtk_test_dbg( "[ERROR] doesn't get over-current event\n");
4772 return RET_FAIL;
4773 }
4774 //check if PP=0
4775 //turn on PP, re-enable device
4776 //disable slot, port connection, enable...
4777 xhci = hcd_to_xhci(my_hcd);
4778 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(g_port_id-1 & 0xff);
4779 temp = xhci_readl(xhci, addr);
4780 if((temp & PORT_POWER)){
4781 mtk_test_dbg( "[ERROR] port_power bit is still 1\n");
4782 return RET_FAIL;
4783 }
4784 addr = 0xf0008098;
4785 temp = readl(addr);
4786 temp &= ~(1<<16);
4787 writel(temp, addr);
4788 f_disable_slot();
4789 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(g_port_id-1 & 0xff);
4790 temp = xhci_readl(xhci, addr);
4791 //start_port_reenabled(0, DEV_SPEED_SUPER);
4792 port = rh_port[0];
4793 port->port_status = DISCONNECTED;
4794
4795 msleep(1000);
4796
4797 temp = temp | PORT_POWER;
4798 xhci_writel(xhci, temp, addr);
4799 if(f_enable_port(0) != RET_SUCCESS){
4800 mtk_test_dbg( "[ERROR] port not reconnectted after set PP\n");
4801 }
4802 ret = f_enable_slot(NULL);
4803 ret = f_address_slot(false, NULL);
4804
4805 return ret;
4806 }
4807
4808 static int t_ring_enlarge(int argc, char** argv){
4809 int ep_dir, ep_num, ep_index, dev_num, slot_id;
4810 struct xhci_hcd *xhci;
4811 struct usb_host_endpoint *ep;
4812 struct xhci_virt_device *virt_dev;
4813 struct usb_device *udev, *rhdev;
4814 struct xhci_ring *ep_ring;
4815 struct xhci_segment *next, *prev;
4816 u32 val, cycle_bit;
4817 int i, ret;
4818
4819 ep_dir = EPADD_OUT;
4820 ep_num = 1;
4821 dev_num = -1;
4822 ret = 0;
4823
4824 if(argc > 1){
4825 if(!strcmp(argv[1], "out")){
4826 mtk_test_dbg( "OUT EP\n");
4827 ep_dir = EPADD_OUT;
4828 }
4829 else if(!strcmp(argv[1], "in")){
4830 mtk_test_dbg( "IN EP\n");
4831 ep_dir = EPADD_IN;
4832 }
4833 }
4834 if(argc > 2){
4835 ep_num = (int)simple_strtol(argv[2], &argv[2], 10);
4836 xhci_dbg(xhci, "ep_num set to %d\n", ep_num);
4837 }
4838 if(argc > 3){
4839 dev_num = (int)simple_strtol(argv[3], &argv[3], 10);
4840 xhci_dbg(xhci, "dev_num set to %d\n", dev_num);
4841 }
4842
4843 xhci = hcd_to_xhci(my_hcd);
4844 if(dev_num == -1){
4845 rhdev = my_hcd->self.root_hub;
4846 udev = rhdev->children[g_port_id-1];
4847 slot_id = udev->slot_id;
4848 }
4849 else{
4850 udev = dev_list[dev_num-1];
4851 slot_id = udev->slot_id;
4852 }
4853 virt_dev = xhci->devs[udev->slot_id];
4854 if(ep_dir == EPADD_OUT){
4855 ep = udev->ep_out[ep_num];
4856 }
4857 else{
4858 ep = udev->ep_in[ep_num];
4859 }
4860 ep_index = mtktest_xhci_get_endpoint_index(&ep->desc);
4861 ep_ring = (&(virt_dev->eps[ep_index]))->ring;
4862
4863 prev = ep_ring->enq_seg;
4864 next = mtktest_xhci_segment_alloc(xhci, GFP_NOIO);
4865 next->next = prev->next;
4866 next->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = prev->next->dma;
4867 val = next->trbs[TRBS_PER_SEGMENT-1].link.control;
4868 val &= ~TRB_TYPE_BITMASK;
4869 val |= TRB_TYPE(TRB_LINK);
4870 val |= TRB_CHAIN;
4871 next->trbs[TRBS_PER_SEGMENT-1].link.control = val;
4872 xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
4873 (unsigned long long)prev->dma,
4874 (unsigned long long)next->dma);
4875 //adjust cycle bit
4876 if(ep_ring->cycle_state == 1){
4877 cycle_bit = 0;
4878 }
4879 else{
4880 cycle_bit = 1;
4881 }
4882 for(i=0; i<TRBS_PER_SEGMENT; i++){
4883 val = next->trbs[i].generic.field[3];
4884 if(cycle_bit == 1){
4885 val |= cycle_bit;
4886 }
4887 else{
4888 val &= ~cycle_bit;
4889 }
4890 next->trbs[i].generic.field[3] = val;
4891 xhci_dbg(xhci, "Set new segment trb %d cycle bit 0x%x\n", i, val);
4892 }
4893 mtktest_xhci_link_segments(xhci, prev, next, true);
4894 if(prev->trbs[TRBS_PER_SEGMENT-1].link.control & LINK_TOGGLE){
4895 val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
4896 val &= ~LINK_TOGGLE;
4897 prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
4898 val = next->trbs[TRBS_PER_SEGMENT-1].link.control;
4899 val |= LINK_TOGGLE;
4900 next->trbs[TRBS_PER_SEGMENT-1].link.control = val;
4901 }
4902 return ret;
4903 }
4904
4905 static int t_ring_shrink(int argc, char**argv){
4906 int ep_dir, ep_num, ep_index, dev_num, slot_id;
4907 struct xhci_hcd *xhci;
4908 struct usb_host_endpoint *ep;
4909 struct xhci_virt_device *virt_dev;
4910 struct usb_device *udev, *rhdev;
4911 struct xhci_ring *ep_ring;
4912 struct xhci_segment *next, *prev;
4913 u32 val, cycle_bit;
4914 int i, ret;
4915
4916 ep_dir = EPADD_OUT;
4917 ep_num = 1;
4918 dev_num = -1;
4919 ret = 0;
4920
4921 if(argc > 1){
4922 if(!strcmp(argv[1], "out")){
4923 mtk_test_dbg( "OUT EP\n");
4924 ep_dir = EPADD_OUT;
4925 }
4926 else if(!strcmp(argv[1], "in")){
4927 mtk_test_dbg( "IN EP\n");
4928 ep_dir = EPADD_IN;
4929 }
4930 }
4931 if(argc > 2){
4932 ep_num = (int)simple_strtol(argv[2], &argv[2], 10);
4933 xhci_dbg(xhci, "ep_num set to %d\n", ep_num);
4934 }
4935 if(argc > 3){
4936 dev_num = (int)simple_strtol(argv[3], &argv[3], 10);
4937 xhci_dbg(xhci, "dev_num set to %d\n", dev_num);
4938 }
4939
4940 xhci = hcd_to_xhci(my_hcd);
4941 if(dev_num == -1){
4942 rhdev = my_hcd->self.root_hub;
4943 udev = rhdev->children[g_port_id-1];
4944 slot_id = udev->slot_id;
4945 }
4946 else{
4947 udev = dev_list[dev_num-1];
4948 slot_id = udev->slot_id;
4949 }
4950 virt_dev = xhci->devs[udev->slot_id];
4951 if(ep_dir == EPADD_OUT){
4952 ep = udev->ep_out[ep_num];
4953 }
4954 else{
4955 ep = udev->ep_in[ep_num];
4956 }
4957
4958 ep_index = mtktest_xhci_get_endpoint_index(&ep->desc);
4959 ep_ring = (&(virt_dev->eps[ep_index]))->ring;
4960
4961 prev = ep_ring->enq_seg;
4962 next = prev->next;
4963 if(prev == next){
4964 mtk_test_dbg( "This is the last segment, can not be remove\n");
4965 return RET_FAIL;
4966 }
4967 if(prev->trbs[TRBS_PER_SEGMENT-1].link.control & LINK_TOGGLE){
4968 ep_ring->first_seg = next->next;
4969 }
4970 else if(next->trbs[TRBS_PER_SEGMENT-1].link.control & LINK_TOGGLE){
4971 val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
4972 val |= LINK_TOGGLE;
4973 prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
4974 }
4975 mtktest_xhci_link_segments(xhci, prev, next->next, true);
4976 mtktest_xhci_segment_free(xhci, next);
4977 return RET_SUCCESS;
4978 }
4979
4980 static int t_ring_stop_ep(int argc, char** argv){
4981 int ep_dir, ep_num, ep_index, dev_num, slot_id;
4982 struct xhci_hcd *xhci;
4983 struct usb_host_endpoint *ep;
4984 struct xhci_virt_device *virt_dev;
4985 struct usb_device *udev, *rhdev;
4986
4987 ep_dir = EPADD_OUT;
4988 ep_num = 1;
4989 dev_num = -1;
4990
4991 if(argc > 1){
4992 if(!strcmp(argv[1], "out")){
4993 mtk_test_dbg( "OUT EP\n");
4994 ep_dir = EPADD_OUT;
4995 }
4996 else if(!strcmp(argv[1], "in")){
4997 mtk_test_dbg( "IN EP\n");
4998 ep_dir = EPADD_IN;
4999 }
5000 }
5001 if(argc > 2){
5002 ep_num = (int)simple_strtol(argv[2], &argv[2], 10);
5003 xhci_dbg(xhci, "ep_num set to %d\n", ep_num);
5004 }
5005 if(argc > 3){
5006 dev_num = (int)simple_strtol(argv[3], &argv[3], 10);
5007 xhci_dbg(xhci, "dev_num set to %d\n", dev_num);
5008 }
5009
5010 xhci = hcd_to_xhci(my_hcd);
5011 if(dev_num == -1){
5012 rhdev = my_hcd->self.root_hub;
5013 udev = rhdev->children[g_port_id-1];
5014 slot_id = udev->slot_id;
5015 }
5016 else{
5017 udev = dev_list[dev_num-1];
5018 slot_id = udev->slot_id;
5019 }
5020 virt_dev = xhci->devs[udev->slot_id];
5021 if(ep_dir == EPADD_OUT){
5022 ep = udev->ep_out[ep_num];
5023 }
5024 else{
5025 ep = udev->ep_in[ep_num];
5026 }
5027 ep_index = mtktest_xhci_get_endpoint_index(&ep->desc);
5028 return f_ring_stop_ep(slot_id, ep_index);
5029
5030 }
5031
5032 static int t_ring_stop_cmd(int argc, char** argv){
5033 return f_ring_stop_cmd();
5034 }
5035
5036 static int t_ring_abort_cmd_add(int argc, char** argv){
5037 int ret;
5038 struct xhci_hcd *xhci;
5039 struct usb_device *udev, *rhdev;
5040 struct xhci_virt_device *virt_dev;
5041
5042 ret = f_enable_port(0);
5043 if(ret != RET_SUCCESS){
5044 return RET_FAIL;
5045 }
5046 ret = f_enable_slot(NULL);
5047 if(ret != RET_SUCCESS){
5048 return RET_FAIL;
5049 }
5050
5051 //queue address slot command but not waiting for cmd complete
5052 xhci = hcd_to_xhci(my_hcd);
5053 rhdev = my_hcd->self.root_hub;
5054 udev = rhdev->children[g_port_id-1];
5055 mtktest_xhci_setup_addressable_virt_dev(xhci, udev);
5056 virt_dev = xhci->devs[udev->slot_id];
5057 ret = mtktest_xhci_queue_address_device(xhci, virt_dev->in_ctx->dma, udev->slot_id, false);
5058
5059 //abort command ring right now
5060 return f_ring_abort_cmd();
5061 }
5062
5063 static int t_ring_intr_moderation(int argc, char** argv){
5064 int i;
5065 int intr_mod_value;
5066 u32 temp;
5067 struct xhci_hcd *xhci;
5068
5069 xhci = hcd_to_xhci(my_hcd);
5070 intr_mod_value = 0;
5071
5072 if(argc > 1){
5073 intr_mod_value = (int)simple_strtol(argv[1], &argv[1], 10);
5074 xhci_dbg(xhci, "intr_mod_value set to %d\n", intr_mod_value);
5075 }
5076
5077 temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
5078 temp &= ~0xFFFF;
5079 temp |=intr_mod_value;
5080 xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
5081 g_intr_handled = 0;
5082 for(i=0; i<1000; i++){
5083 mtktest_mtk_xhci_setup_one_noop(xhci);
5084 }
5085 msleep(10);
5086 xhci_err(xhci, "interrupt handler executed %ld times\n", g_intr_handled);
5087 g_intr_handled = -1;
5088 return RET_SUCCESS;
5089 }
5090
5091 static int t_ring_er_full(int argc, char** argv){
5092 int ret;
5093 struct xhci_hcd *xhci;
5094 int i;
5095 u32 temp;
5096 union xhci_trb *event;
5097
5098 g_event_full = true;
5099 if(my_hcd == NULL){
5100 mtk_test_dbg( "[ERROR]host controller driver not initiated\n");
5101 return RET_FAIL;
5102 }
5103 xhci = hcd_to_xhci(my_hcd);
5104 i = 1000;
5105 //turn off interrupt first
5106 temp = xhci_readl(xhci, &xhci->op_regs->command);
5107 temp &= (~CMD_EIE);
5108 xhci_dbg(xhci, "// Disable interrupts, cmd = 0x%x.\n", temp);
5109 xhci_writel(xhci, temp, &xhci->op_regs->command);
5110 //continuous queue no-op command
5111 while(i>0){
5112 event = xhci->event_ring->dequeue;
5113 struct xhci_generic_trb *event_trb = &event->generic;
5114 if((event->event_cmd.flags & TRB_CYCLE) == xhci->event_ring->cycle_state){
5115 xhci_dbg(xhci, "SW own current event\n");
5116 if(GET_COMP_CODE(event_trb->field[2]) == COMP_ER_FULL){
5117 xhci_dbg(xhci, "Got event ring full\n");
5118 return RET_SUCCESS;
5119 }
5120 else{
5121 xhci_dbg(xhci, "Increase command ring dequeue pointer\n");
5122 mtktest_inc_deq(xhci, xhci->cmd_ring, false);
5123 }
5124 mtktest_inc_deq(xhci, xhci->event_ring, true);
5125 }
5126 xhci_dbg(xhci, "Queue No-Op command\n");
5127 mdelay(50);
5128 mtktest_mtk_xhci_setup_one_noop(xhci);
5129 i--;
5130 }
5131 return RET_FAIL;
5132 }
5133
5134 static int t_ring_idt(int argc, char** argv){
5135 //do loopback set IDT
5136 int ret,length,start_add;
5137 char bdp;
5138 int gpd_buf_size,bd_buf_size;
5139 int transfer_type;
5140 int maxp;
5141 int bInterval;
5142 int ep_out_num, ep_in_num;
5143 int speed;
5144 int mult_dev, mult, burst;
5145
5146 struct xhci_hcd *xhci;
5147 struct device *dev;
5148 struct usb_device *udev, *rhdev;
5149 u8 *tmp1, *tmp2;
5150 struct urb *urb_tx, *urb_rx;
5151 int iso_num_packets;
5152 struct usb_host_endpoint *ep_tx, *ep_rx;
5153 int max_esit_payload;
5154 void *buffer_tx, *buffer_rx;
5155 dma_addr_t mapping_tx, mapping_rx;
5156
5157 ret = 0;
5158 speed = DEV_SPEED_SUPER;
5159 transfer_type = EPATT_BULK;
5160 maxp = 1024;
5161 bInterval = 0;
5162 ep_out_num = 1;
5163 ep_in_num = 1;
5164 length = 7;
5165 mult_dev = 3;
5166 mult = 0;
5167 burst = 8;
5168 start_add = 0;
5169 bdp=1;
5170 gpd_buf_size = 65535;
5171 bd_buf_size = 4096;
5172
5173 start_port_reenabled(0, speed);
5174 ret=dev_reset(speed, NULL);
5175 if(ret){
5176 mtk_test_dbg( "device reset failed!!!!!!!!!!\n");
5177 return ret;
5178 }
5179
5180 ret = f_disable_slot();
5181 if(ret){
5182 mtk_test_dbg( "disable slot failed!!!!!!!!!!\n");
5183 return ret;
5184 }
5185
5186 ret = f_reenable_port(0);
5187 if(ret != RET_SUCCESS){
5188 mtk_test_dbg( "device reenable failed!!!!!!!!!!\n");
5189 return ret;
5190 }
5191
5192 ret = f_enable_slot(NULL);
5193 if(ret){
5194 mtk_test_dbg( "enable slot failed!!!!!!!!!!\n");
5195 return ret;
5196 }
5197
5198 ret=f_address_slot(false, NULL);
5199 if(ret){
5200 mtk_test_dbg( "address slot failed!!!!!!!!!!\n");
5201 return ret;
5202 }
5203
5204 /* ==phase 1 : config EP==*/
5205 ret=dev_config_ep(ep_out_num,USB_RX,transfer_type,maxp,bInterval,mult_dev,burst,mult,NULL);
5206 if(ret)
5207 {
5208 mtk_test_dbg( "config dev EP fail!!\n");
5209 return ret;
5210 }
5211 ret=dev_config_ep(ep_in_num,USB_TX,transfer_type,maxp,bInterval,mult_dev,burst,mult,NULL);
5212 if(ret)
5213 {
5214 mtk_test_dbg( "config dev EP fail!!\n");
5215 return ret;
5216 }
5217
5218 ret = f_config_ep(ep_out_num,EPADD_OUT,transfer_type,maxp,bInterval,burst,mult, NULL,0);
5219 if(ret)
5220 {
5221 mtk_test_dbg( "config EP fail!!\n");
5222 return ret;
5223 }
5224
5225 ret = f_config_ep(ep_in_num,EPADD_IN,transfer_type,maxp,bInterval,burst,mult, NULL,1);
5226 if(ret)
5227 {
5228 mtk_test_dbg( "config EP fail!!\n");
5229 return ret;
5230 }
5231 g_idt_transfer = true;
5232
5233 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size,0,0,NULL);
5234 if(ret)
5235 {
5236 mtk_test_dbg( "loopback request fail!!\n");
5237 return ret;
5238 }
5239
5240 ret = f_loopback_loop_gpd(ep_out_num, ep_in_num, length, start_add, gpd_buf_size, NULL);
5241 if(ret){
5242 mtk_test_dbg( "loopback fail!!\n");
5243 return ret;
5244 }
5245
5246 g_idt_transfer = false;
5247
5248 return RET_SUCCESS;
5249 }
5250
5251 static int t_ring_bei(int argc, char** argv){
5252 //do loopback set BEI
5253 //after tx round should not get URB complete status
5254 //queue no-op without set BEI
5255 //get URB complete status
5256 //do the same to Rx round
5257 int ret,length,start_add;
5258 char bdp;
5259 int gpd_buf_size,bd_buf_size;
5260 int transfer_type;
5261 int maxp;
5262 int bInterval;
5263 int ep_out_num, ep_in_num;
5264 int speed;
5265 int mult_dev, mult, burst;
5266
5267 struct xhci_hcd *xhci;
5268 struct device *dev;
5269 struct usb_device *udev, *rhdev;
5270 u8 *tmp1, *tmp2;
5271 struct urb *urb_tx, *urb_rx;
5272 int iso_num_packets;
5273 struct usb_host_endpoint *ep_tx, *ep_rx;
5274 int max_esit_payload;
5275 void *buffer_tx, *buffer_rx;
5276 dma_addr_t mapping_tx, mapping_rx;
5277
5278 ret = 0;
5279 speed = DEV_SPEED_SUPER;
5280 transfer_type = EPATT_BULK;
5281 maxp = 1024;
5282 bInterval = 0;
5283 ep_out_num = 1;
5284 ep_in_num = 1;
5285 length = 65535;
5286 mult_dev = 3;
5287 mult = 0;
5288 burst = 8;
5289 start_add = 0;
5290 bdp=1;
5291 gpd_buf_size = 65535;
5292 bd_buf_size = 4096;
5293
5294
5295 start_port_reenabled(0, speed);
5296 ret=dev_reset(speed, NULL);
5297 if(ret){
5298 mtk_test_dbg( "device reset failed!!!!!!!!!!\n");
5299 return ret;
5300 }
5301
5302 ret = f_disable_slot();
5303 if(ret){
5304 mtk_test_dbg( "disable slot failed!!!!!!!!!!\n");
5305 return ret;
5306 }
5307
5308 ret = f_reenable_port(0);
5309 if(ret != RET_SUCCESS){
5310 mtk_test_dbg( "device reenable failed!!!!!!!!!!\n");
5311 return ret;
5312 }
5313
5314 ret = f_enable_slot(NULL);
5315 if(ret){
5316 mtk_test_dbg( "enable slot failed!!!!!!!!!!\n");
5317 return ret;
5318 }
5319
5320 ret=f_address_slot(false, NULL);
5321 if(ret){
5322 mtk_test_dbg( "address slot failed!!!!!!!!!!\n");
5323 return ret;
5324 }
5325
5326 /* ==phase 1 : config EP==*/
5327 ret=dev_config_ep(ep_out_num,USB_RX,transfer_type,maxp,bInterval,mult_dev,burst,mult,NULL);
5328 if(ret)
5329 {
5330 mtk_test_dbg( "config dev EP fail!!\n");
5331 return ret;
5332 }
5333 ret=dev_config_ep(ep_in_num,USB_TX,transfer_type,maxp,bInterval,mult_dev,burst,mult,NULL);
5334 if(ret)
5335 {
5336 mtk_test_dbg( "config dev EP fail!!\n");
5337 return ret;
5338 }
5339
5340 ret = f_config_ep(ep_out_num,EPADD_OUT,transfer_type,maxp,bInterval,burst,mult, NULL,0);
5341 if(ret)
5342 {
5343 mtk_test_dbg( "config EP fail!!\n");
5344 return ret;
5345 }
5346
5347 ret = f_config_ep(ep_in_num,EPADD_IN,transfer_type,maxp,bInterval,burst,mult, NULL,1);
5348 if(ret)
5349 {
5350 mtk_test_dbg( "config EP fail!!\n");
5351 return ret;
5352 }
5353 g_is_bei = true;
5354
5355 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size,0,0,NULL);
5356 if(ret)
5357 {
5358 mtk_test_dbg( "loopback request fail!!\n");
5359 f_power_suspend();
5360 return ret;
5361 }
5362 //do Tx with BEI
5363 iso_num_packets = 0;
5364 xhci = hcd_to_xhci(my_hcd);
5365 dev = xhci_to_hcd(xhci)->self.controller;//dma stream buffer
5366 rhdev = my_hcd->self.root_hub;
5367 udev = rhdev->children[g_port_id-1];
5368 ep_tx = udev->ep_out[ep_out_num];
5369 ep_rx = udev->ep_in[ep_in_num];
5370
5371 ret = 0;
5372 buffer_tx = kmalloc(length, GFP_KERNEL);
5373 mapping_tx = dma_map_single(dev, buffer_tx,length, DMA_BIDIRECTIONAL);
5374 urb_tx = usb_alloc_urb(iso_num_packets, GFP_KERNEL);
5375 f_fill_urb_with_buffer(urb_tx, ep_out_num, length, buffer_tx
5376 , start_add, URB_DIR_OUT, iso_num_packets, max_esit_payload, mapping_tx, udev);
5377 if(ret){
5378 xhci_err(xhci, "[ERROR]fill tx urb Error!!\n");
5379 return RET_FAIL;
5380 }
5381 ret = f_queue_urb(urb_tx,0,NULL);
5382 if(ret){
5383 xhci_err(xhci, "[ERROR]queue tx urb Error!!\n");
5384 return RET_FAIL;
5385 }
5386 msleep(100);
5387 if(urb_tx->status == 0){
5388 xhci_err(xhci, "URB_TX status become 0, BEI seems doesn't work\n");
5389 return RET_FAIL;
5390 }
5391 //queue a no-op
5392 mtktest_mtk_xhci_setup_one_noop(xhci);
5393 msleep(10);
5394 if(urb_tx->status != 0){
5395 xhci_err(xhci, "URB_TX status doesn't become 0 after interrupt\n");
5396 return RET_FAIL;
5397 }
5398 usb_free_urb(urb_tx);
5399
5400 buffer_rx = kmalloc(length, GFP_KERNEL);
5401 memset(buffer_rx, 0, length);
5402 mapping_rx = dma_map_single(dev, buffer_rx,length, DMA_BIDIRECTIONAL);
5403 urb_rx = usb_alloc_urb(iso_num_packets, GFP_KERNEL);
5404 f_fill_urb_with_buffer(urb_rx, ep_in_num, length, buffer_rx
5405 , start_add, URB_DIR_IN, iso_num_packets, max_esit_payload, mapping_rx,udev);
5406 if(ret){
5407 xhci_err(xhci, "[ERROR]fill tx urb Error!!\n");
5408 return RET_FAIL;
5409 }
5410 ret = f_queue_urb(urb_rx,0,NULL);
5411 if(ret){
5412 xhci_err(xhci, "[ERROR]queue rx urb Error!!\n");
5413 return RET_FAIL;
5414 }
5415 msleep(100);
5416 if(urb_rx->status == 0){
5417 xhci_err(xhci, "URB_RX status become 0, BEI seems doesn't work\n");
5418 return RET_FAIL;
5419 }
5420 //queue a no-op
5421 mtktest_mtk_xhci_setup_one_noop(xhci);
5422 msleep(10);
5423 if(urb_tx->status != 0){
5424 xhci_err(xhci, "URB_RX status doesn't become 0 after interrupt\n");
5425 return RET_FAIL;
5426 }
5427 urb_rx->transfer_buffer = NULL;
5428 urb_rx->transfer_dma = NULL;
5429 usb_free_urb(urb_rx);
5430 kfree(buffer_tx);
5431 kfree(buffer_rx);
5432
5433 g_is_bei = false;
5434
5435 return RET_SUCCESS;
5436 }
5437
5438 static int t_ring_noop_transfer(int argc, char** argv){
5439 int ret,length,start_add;
5440 char bdp;
5441 int gpd_buf_size,bd_buf_size;
5442 int transfer_type;
5443 int maxp;
5444 int bInterval;
5445 int ep_out_num, ep_in_num;
5446 int speed;
5447 int mult_dev, mult, burst;
5448
5449 struct xhci_hcd *xhci;
5450 struct device *dev;
5451 struct usb_device *udev, *rhdev;
5452 u8 *tmp1, *tmp2;
5453 struct urb *urb_tx1, *urb_tx2, *urb_rx1, *urb_rx2;
5454 int iso_num_packets;
5455 struct usb_host_endpoint *ep_tx, *ep_rx;
5456 int max_esit_payload;
5457 void *buffer_tx1, *buffer_tx2, *buffer_rx1, *buffer_rx2;
5458 dma_addr_t mapping_tx1, mapping_tx2, mapping_rx1, mapping_rx2;
5459
5460 ret = 0;
5461 speed = DEV_SPEED_SUPER;
5462 transfer_type = EPATT_BULK;
5463 maxp = 1024;
5464 bInterval = 0;
5465 ep_out_num = 1;
5466 ep_in_num = 1;
5467 length = 65535;
5468 mult_dev = 3;
5469 mult = 0;
5470 burst = 8;
5471 start_add = 0;
5472 bdp=1;
5473 gpd_buf_size = 65535;
5474 bd_buf_size = 4096;
5475
5476
5477 start_port_reenabled(0, speed);
5478 ret=dev_reset(speed, NULL);
5479 if(ret){
5480 mtk_test_dbg( "device reset failed!!!!!!!!!!\n");
5481 return ret;
5482 }
5483
5484 ret = f_disable_slot();
5485 if(ret){
5486 mtk_test_dbg( "disable slot failed!!!!!!!!!!\n");
5487 return ret;
5488 }
5489
5490 ret = f_reenable_port(0);
5491 if(ret != RET_SUCCESS){
5492 mtk_test_dbg( "device reenable failed!!!!!!!!!!\n");
5493 return ret;
5494 }
5495
5496 ret = f_enable_slot(NULL);
5497 if(ret){
5498 mtk_test_dbg( "enable slot failed!!!!!!!!!!\n");
5499 return ret;
5500 }
5501
5502 ret=f_address_slot(false, NULL);
5503 if(ret){
5504 mtk_test_dbg( "address slot failed!!!!!!!!!!\n");
5505 return ret;
5506 }
5507
5508 /* ==phase 1 : config EP==*/
5509 ret=dev_config_ep(ep_out_num,USB_RX,transfer_type,maxp,bInterval,mult_dev,burst,mult,NULL);
5510 if(ret)
5511 {
5512 mtk_test_dbg( "config dev EP fail!!\n");
5513 return ret;
5514 }
5515 ret=dev_config_ep(ep_in_num,USB_TX,transfer_type,maxp,bInterval,mult_dev,burst,mult,NULL);
5516 if(ret)
5517 {
5518 mtk_test_dbg( "config dev EP fail!!\n");
5519 return ret;
5520 }
5521
5522 ret = f_config_ep(ep_out_num,EPADD_OUT,transfer_type,maxp,bInterval,burst,mult, NULL,0);
5523 if(ret)
5524 {
5525 mtk_test_dbg( "config EP fail!!\n");
5526 return ret;
5527 }
5528
5529 ret = f_config_ep(ep_in_num,EPADD_IN,transfer_type,maxp,bInterval,burst,mult, NULL,1);
5530 if(ret)
5531 {
5532 mtk_test_dbg( "config EP fail!!\n");
5533 return ret;
5534 }
5535
5536 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size,0,0,NULL);
5537 if(ret)
5538 {
5539 mtk_test_dbg( "loopback request fail!!\n");
5540 f_power_suspend();
5541 return ret;
5542 }
5543
5544 //queue 2 URB, the first is false, and doesn't ring doorbell
5545
5546 iso_num_packets = 0;
5547 xhci = hcd_to_xhci(my_hcd);
5548 dev = xhci_to_hcd(xhci)->self.controller;//dma stream buffer
5549 rhdev = my_hcd->self.root_hub;
5550 udev = rhdev->children[g_port_id-1];
5551 ep_tx = udev->ep_out[ep_out_num];
5552 ep_rx = udev->ep_in[ep_in_num];
5553
5554 ret = 0;
5555 //first OUT urb
5556 buffer_tx1 = kmalloc(1000, GFP_KERNEL);
5557 mapping_tx1 = dma_map_single(dev, buffer_tx1,1000, DMA_BIDIRECTIONAL);
5558 urb_tx1 = usb_alloc_urb(iso_num_packets, GFP_KERNEL);
5559 f_fill_urb_with_buffer(urb_tx1, ep_out_num, 1000, buffer_tx1
5560 , start_add, URB_DIR_OUT, iso_num_packets, max_esit_payload, mapping_tx1, udev);
5561 if(ret){
5562 xhci_err(xhci, "[ERROR]fill tx urb Error!!\n");
5563 return RET_FAIL;
5564 }
5565
5566 g_td_to_noop = true;
5567 ret = f_queue_urb(urb_tx1,0,NULL);
5568 if(ret){
5569 xhci_err(xhci, "[ERROR]queue tx urb Error!!\n");
5570 return RET_FAIL;
5571 }
5572 g_td_to_noop = false;
5573
5574 //second OUT urb
5575 buffer_tx2 = kmalloc(length, GFP_KERNEL);
5576 mapping_tx2 = dma_map_single(dev, buffer_tx2,length, DMA_BIDIRECTIONAL);
5577 urb_tx2 = usb_alloc_urb(iso_num_packets, GFP_KERNEL);
5578 f_fill_urb_with_buffer(urb_tx2, ep_out_num, length, buffer_tx2
5579 , start_add, URB_DIR_OUT, iso_num_packets, max_esit_payload, mapping_tx2, udev);
5580 if(ret){
5581 xhci_err(xhci, "[ERROR]fill tx urb Error!!\n");
5582 return RET_FAIL;
5583 }
5584 ret = f_queue_urb(urb_tx2,1,NULL);
5585 if(ret){
5586 xhci_err(xhci, "[ERROR]queue tx urb Error!!\n");
5587 return RET_FAIL;
5588 }
5589 urb_tx1->transfer_buffer = NULL;
5590 urb_tx2->transfer_buffer = NULL;
5591 urb_tx1->transfer_dma = NULL;
5592 urb_tx2->transfer_dma = NULL;
5593 usb_free_urb(urb_tx1);
5594 usb_free_urb(urb_tx2);
5595
5596 //first IN urb
5597 buffer_rx1 = kmalloc(1000, GFP_KERNEL);
5598 memset(buffer_rx1, 0, 1000);
5599 mapping_rx1 = dma_map_single(dev, buffer_rx1,1000, DMA_BIDIRECTIONAL);
5600 urb_rx1 = usb_alloc_urb(iso_num_packets, GFP_KERNEL);
5601 f_fill_urb_with_buffer(urb_rx1, ep_in_num, 1000, buffer_rx1
5602 , start_add, URB_DIR_IN, iso_num_packets, max_esit_payload, mapping_rx1,udev);
5603 if(ret){
5604 xhci_err(xhci, "[ERROR]fill tx urb Error!!\n");
5605 return RET_FAIL;
5606 }
5607 g_td_to_noop = true;
5608 ret = f_queue_urb(urb_rx1,0,NULL);
5609 if(ret){
5610 xhci_err(xhci, "[ERROR]queue rx urb Error!!\n");
5611 return RET_FAIL;
5612 }
5613 g_td_to_noop = false;
5614
5615 //second IN urb
5616 buffer_rx2 = kmalloc(length, GFP_KERNEL);
5617 memset(buffer_rx2, 0, length);
5618 mapping_rx2 = dma_map_single(dev, buffer_rx2,length, DMA_BIDIRECTIONAL);
5619 urb_rx2 = usb_alloc_urb(iso_num_packets, GFP_KERNEL);
5620 f_fill_urb_with_buffer(urb_rx2, ep_in_num, length, buffer_rx2
5621 , start_add, URB_DIR_IN, iso_num_packets, max_esit_payload, mapping_rx2,udev);
5622 if(ret){
5623 xhci_err(xhci, "[ERROR]fill tx urb Error!!\n");
5624 return RET_FAIL;
5625 }
5626
5627 ret = f_queue_urb(urb_rx2,1,NULL);
5628 if(ret){
5629 xhci_err(xhci, "[ERROR]queue rx urb Error!!\n");
5630 return RET_FAIL;
5631 }
5632
5633 urb_rx1->transfer_buffer = NULL;
5634 urb_rx1->transfer_dma = NULL;
5635 urb_rx2->transfer_buffer = NULL;
5636 urb_rx2->transfer_dma = NULL;
5637 usb_free_urb(urb_rx1);
5638 usb_free_urb(urb_rx2);
5639 kfree(buffer_tx1);
5640 kfree(buffer_tx2);
5641 kfree(buffer_rx1);
5642 kfree(buffer_rx2);
5643
5644 return RET_SUCCESS;
5645
5646 }
5647
5648 static int t_hub_selsuspendss(int argc, char** argv){
5649 int hub_num, port_num;
5650 int ret;
5651
5652 hub_num = 1;
5653 port_num = 1;
5654
5655 if(argc > 1){ //hub number
5656 hub_num = (int)simple_strtol(argv[1], &argv[1], 10);
5657 xhci_dbg(xhci, "hub_num set to %d\n", hub_num);
5658 }
5659 if(argc > 2){ //port number
5660 port_num = (int)simple_strtol(argv[2], &argv[2], 10);
5661 xhci_dbg(xhci, "port_num set to %d\n", port_num);
5662 }
5663 return f_hub_setportfeature(hub_num, HUB_FEATURE_PORT_LINK_STATE, port_num | (3<<8));
5664 }
5665
5666 static int t_hub_selsuspend(int argc, char** argv){
5667 int hub_num, port_num;
5668 int ret;
5669 int speed;
5670
5671 hub_num = 1;
5672 port_num = 1;
5673 speed = USB_SPEED_HIGH;
5674
5675 if(argc > 1){ //hub number
5676 hub_num = (int)simple_strtol(argv[1], &argv[1], 10);
5677 xhci_dbg(xhci, "hub_num set to %d\n", hub_num);
5678 }
5679 if(argc > 2){ //port number
5680 port_num = (int)simple_strtol(argv[2], &argv[2], 10);
5681 xhci_dbg(xhci, "port_num set to %d\n", port_num);
5682 }
5683 if(argc > 3){
5684 if(!strcmp(argv[3], "ss")){
5685 mtk_test_dbg( "SUPERSPEED\n");
5686 speed = USB_SPEED_SUPER;
5687 }
5688 }
5689 if(speed == USB_SPEED_HIGH){
5690 return f_hub_setportfeature(hub_num, HUB_FEATURE_PORT_SUSPEND, port_num);
5691 }
5692 else if(speed == USB_SPEED_SUPER){
5693 return f_hub_setportfeature(hub_num, HUB_FEATURE_PORT_LINK_STATE, port_num | (3<<8));
5694 }
5695 else{
5696 mtk_test_dbg( "Error speed value\n");
5697 }
5698 }
5699
5700
5701 static int t_hub_selresume(int argc, char** argv){
5702
5703 int hub_num, port_num;
5704 int ret;
5705 int speed;
5706
5707 hub_num = 1;
5708 port_num = 1;
5709 speed = USB_SPEED_HIGH;
5710
5711 if(argc > 1){ //hub number
5712 hub_num = (int)simple_strtol(argv[1], &argv[1], 10);
5713 xhci_dbg(xhci, "hub_num set to %d\n", hub_num);
5714 }
5715 if(argc > 2){ //port number
5716 port_num = (int)simple_strtol(argv[2], &argv[2], 10);
5717 xhci_dbg(xhci, "port_num set to %d\n", port_num);
5718 }
5719 if(argc > 3){
5720 if(!strcmp(argv[3], "ss")){
5721 mtk_test_dbg( "SUPERSPEED\n");
5722 speed = USB_SPEED_SUPER;
5723 }
5724 }
5725 if(speed == USB_SPEED_HIGH){
5726 return f_hub_clearportfeature(hub_num, HUB_FEATURE_PORT_SUSPEND, port_num);
5727 }
5728 else if(speed == USB_SPEED_SUPER){
5729 return f_hub_setportfeature(hub_num, HUB_FEATURE_PORT_LINK_STATE, port_num);
5730 }
5731 else{
5732 mtk_test_dbg( "Error speed value\n");
5733 }
5734 }
5735
5736 static int t_hub_configurehub(int argc, char** argv){
5737 int ret;
5738 struct xhci_hcd *xhci;
5739 struct usb_device *udev, *rhdev;
5740 struct xhci_virt_device *virt_dev;
5741 struct xhci_command *config_cmd;
5742 struct xhci_input_control_ctx *ctrl_ctx;
5743 struct xhci_slot_ctx *slot_ctx;
5744 int i;
5745 int port_index;
5746 struct xhci_port *port;
5747 port_index = 0;
5748
5749 if(my_hcd == NULL){
5750 mtk_test_dbg( "my_hcd is NULL\n");
5751 return RET_FAIL;
5752 }
5753 if(argc > 1){
5754 port_index = (int)simple_strtol(argv[1], &argv[1], 10);
5755 xhci_dbg(xhci, "port_index set to %d\n", port_index);
5756 }
5757 xhci = hcd_to_xhci(my_hcd);
5758 ret = f_enable_port(port_index);
5759 if(ret != RET_SUCCESS){
5760 xhci_err(xhci, "[ERROR] enable port failed\n");
5761 return RET_FAIL;
5762 }
5763 port = rh_port[port_index];
5764 xhci_err(xhci, "Port[%d] speed: %d\n", port_index, port->port_speed);
5765 ret = f_enable_slot(NULL);
5766 if(ret != RET_SUCCESS){
5767 xhci_err(xhci, "[ERROR] enable slot failed\n");
5768 return RET_FAIL;
5769 }
5770 ret = f_address_slot(false, NULL);
5771 if(ret != RET_SUCCESS){
5772 xhci_err(xhci, "[ERROR] address device failed\n");
5773 return RET_FAIL;
5774 }
5775 rhdev = my_hcd->self.root_hub;
5776 udev = rhdev->children[port->port_id-1];
5777 virt_dev = xhci->devs[udev->slot_id];
5778 g_slot_id = 0;
5779 hdev_list[port_index] = udev;
5780 f_update_hub_device(udev, 4);
5781 if(f_hub_configep(port_index+1, port_index) != RET_SUCCESS){
5782 xhci_err(xhci, "config hub endpoint failed\n");
5783 return RET_FAIL;
5784 }
5785 mtktest_xhci_dbg_slot_ctx(xhci, virt_dev->out_ctx);
5786 //set port_power
5787 for(i=1; i<=4; i++){
5788 if(f_hub_setportfeature((port_index+1), HUB_FEATURE_PORT_POWER, i) != RET_SUCCESS){
5789 xhci_err(xhci, "[ERROR] set port_power 1 failed\n");
5790 return RET_FAIL;
5791 }
5792 }
5793 //clear C_PORT_CONNECTION
5794 for(i=1; i<=4; i++){
5795 if(f_hub_clearportfeature((port_index+1), HUB_FEATURE_C_PORT_CONNECTION, i) != RET_SUCCESS){
5796 xhci_err(xhci, "[ERROR] clear c_port_connection failed\n");
5797 }
5798 }
5799
5800 return RET_SUCCESS;
5801 }
5802
5803 static int t_hub_ixia_stress(int argc, char** argv){
5804 struct xhci_hcd *xhci;
5805 struct mutex *lock;
5806 int dev_count;
5807 int i;
5808
5809 if(argc > 1){
5810 dev_count = (int)simple_strtol(argv[1], &argv[1], 10);
5811 xhci_dbg(xhci, "dev_count set to %d\n", dev_count);
5812 }
5813
5814 xhci = hcd_to_xhci(my_hcd);
5815 for(i=0; i<dev_count; i++){
5816 f_add_ixia_thread(xhci,i+1, ix_dev_list[i]);
5817 }
5818 return RET_SUCCESS;
5819 }
5820
5821 static int t_hub_loop_stress(int argc, char** argv){
5822 struct xhci_hcd *xhci;
5823 struct mutex *lock;
5824 int dev_count, ep_count;
5825 int i,j;
5826 struct usb_device *udev;
5827 struct usb_host_endpoint *ep;
5828 char isEP0;
5829 int maxp;
5830 int ret;
5831
5832 isEP0 = false;
5833
5834 if(argc > 1){
5835 dev_count = (int)simple_strtol(argv[1], &argv[1], 10);
5836 xhci_dbg(xhci, "dev_count set to %d\n", dev_count);
5837 }
5838 if(argc > 2){
5839 ep_count = (int)simple_strtol(argv[2], &argv[2], 10);
5840 xhci_dbg(xhci, "ep_count set to %d\n", ep_count);
5841 }
5842 if(argc > 3){
5843 if(!strcmp(argv[3], "true")){
5844 isEP0 = true;
5845 }
5846 }
5847 g_correct = true;
5848 for(i=0; i<dev_count; i++){
5849 udev = dev_list[i];
5850 ret=dev_stress(0,GPD_LENGTH ,GPD_LENGTH,0,ep_count, udev);
5851 if(ret){
5852 mtk_test_dbg( "stress request failed!!!!!!!!!!\n");
5853 return ret;
5854 }
5855 }
5856 for(i=0; i<dev_count; i++){
5857 udev = dev_list[i];
5858 for(j=1; j<=ep_count; j++){
5859 ep = udev->ep_out[j];
5860 maxp = ep->desc.wMaxPacketSize & 0x7ff;
5861 f_add_str_threads(i,j,maxp,true, udev, isEP0);
5862 }
5863 }
5864 return RET_SUCCESS;
5865 }
5866
5867 static int t_hub_loop(int argc, char** argv){
5868 struct usb_device *udev;
5869 int ret,length,start_add;
5870 char bdp;
5871 int gpd_buf_size,bd_buf_size;
5872 int ep_out_num, ep_in_num;
5873 int speed;
5874 int sg_len;
5875 int hub_num, port_num, dev_num, round, i;
5876 int dram_offset, extension;
5877
5878 ret =0;
5879 ep_out_num = 1;
5880 ep_in_num = 1;
5881 length = 65535;
5882 round=1;
5883 dram_offset = 0;
5884 extension = 0;
5885
5886 if(argc > 1){ //hub number
5887 hub_num = (int)simple_strtol(argv[1], &argv[1], 10);
5888 xhci_dbg(xhci, "hub_num set to %d\n", hub_num);
5889 }
5890 if(argc > 2){ //port number
5891 port_num = (int)simple_strtol(argv[2], &argv[2], 10);
5892 xhci_dbg(xhci, "port_num set to %d\n", port_num);
5893 }
5894 if(argc > 3){ //device number
5895 dev_num = (int)simple_strtol(argv[3], &argv[3], 10);
5896 xhci_dbg(xhci, "dev_num set to %d\n", dev_num);
5897 }
5898 if(argc > 4){
5899 length = (int)simple_strtol(argv[4], &argv[4], 10);
5900 mtk_test_dbg( "length set to %d\n", length);
5901 }
5902 if(argc > 5){
5903 ep_out_num = (int)simple_strtol(argv[5], &argv[5], 10);
5904 mtk_test_dbg( "ep out num set to %d\n", ep_out_num);
5905 }
5906 if(argc > 6){
5907 ep_in_num = (int)simple_strtol(argv[6], &argv[6], 10);
5908 mtk_test_dbg( "ep in num set to %d\n", ep_in_num);
5909 }
5910 if(argc > 7){
5911 round = (int)simple_strtol(argv[7], &argv[7], 10);
5912 mtk_test_dbg( "Execute %d round\n", round);
5913 }
5914 if(argc > 8){
5915 sg_len = (int)simple_strtol(argv[8], &argv[8], 10);
5916 mtk_test_dbg( "sg_len %d\n", sg_len);
5917 }
5918
5919 bdp=0;
5920 gpd_buf_size=0xFC00;
5921 bd_buf_size=0x1FFF;
5922 udev = dev_list[dev_num-1];
5923 //TODO: device should turn off extension length feature
5924 #if 0
5925 if(((length-10)%(bd_buf_size+6))<7){
5926 length+=12;
5927 }
5928 #endif
5929
5930 if(ep_out_num == 0 || ep_in_num == 0){
5931 if(round==1){
5932 ret = dev_ctrl_loopback(length, udev);
5933 if(ret){
5934 mtk_test_dbg( "Control loopback failed!!\n");
5935 return ret;
5936 }
5937 return RET_SUCCESS;
5938 }
5939 else{
5940 for(i=0; i<round; i++){
5941 length = get_random_int() % 2048;
5942 length = length - (length %4);
5943 if(length == 0)
5944 length = 2048;
5945 mtk_test_dbg( "Loopback control length[%d]\n", length);
5946 ret = dev_ctrl_loopback(length, udev);
5947 if(ret){
5948 mtk_test_dbg( "Control loopback failed!!\n");
5949 return ret;
5950 }
5951 }
5952 return RET_SUCCESS;
5953 }
5954 }
5955 if(round == 1){
5956 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size,dram_offset,extension,udev);
5957 if(ret)
5958 {
5959 mtk_test_dbg( "loopback request fail!!\n");
5960 return ret;
5961 }
5962 if(sg_len == 0){
5963 ret = f_loopback_loop(ep_out_num, ep_in_num, length, start_add,udev);
5964 }
5965 else{
5966 ret = f_loopback_sg_loop(ep_out_num,ep_in_num, length, start_add
5967 , sg_len, udev);
5968 }
5969 ret=dev_polling_status(udev);
5970 if(ret)
5971 {
5972 mtk_test_dbg( "query request fail!!\n");
5973 return ret;
5974 }
5975 return RET_SUCCESS;
5976 }
5977 for(i=0; i<round; i++){
5978 length = (get_random_int() % 3072/*65535 for bulk, 3072 for intr*/) + 1;
5979 start_add = (get_random_int() % 63) + 1;
5980 sg_len = (get_random_int() % 9) * 8/*512 for bulk, 8 for intr*/;
5981 mtk_test_dbg( "Loopback length[%d] start_add[%d] sg_len[%d]\n", length, start_add, sg_len);
5982 if((sg_len != 0) && (length/sg_len) > 61){
5983 i--;
5984 mtk_test_dbg( "SKIP\n");
5985 continue;
5986 }
5987 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size,dram_offset,extension,udev);
5988 if(ret)
5989 {
5990 mtk_test_dbg( "loopback request fail!!\n");
5991 return ret;
5992 }
5993 if(sg_len == 0){
5994 ret = f_loopback_loop(ep_out_num, ep_in_num, length, start_add,udev);
5995 }
5996 else{
5997 ret = f_loopback_sg_loop(ep_out_num,ep_in_num, length, start_add
5998 , sg_len, udev);
5999 }
6000 if(ret)
6001 {
6002 mtk_test_dbg( "loopback fail!!\n");
6003 mtk_test_dbg( "length : %d\n",length);
6004 return ret;
6005 }
6006
6007 /* ==phase 3: get device status==*/
6008 ret=dev_polling_status(udev);
6009 if(ret)
6010 {
6011 mtk_test_dbg( "query request fail!!\n");
6012 return ret;
6013 }
6014 }
6015 return RET_SUCCESS;
6016 }
6017
6018 static int t_hub_configuresubhub(int argc, char** argv){
6019 int parent_hub_num, hub_num, port_num;
6020 struct xhci_hcd *xhci;
6021 xhci = hcd_to_xhci(my_hcd);
6022 parent_hub_num = 1;
6023 hub_num = parent_hub_num+1;
6024 // hdev = hdev_list[parent_hub_num-1];
6025 if(argc > 1){
6026 parent_hub_num = (int)simple_strtol(argv[1], &argv[1], 10);
6027 xhci_dbg(xhci, "parent_hub_num set to %d\n", parent_hub_num);
6028 }
6029 if(argc > 2){
6030 hub_num = (int)simple_strtol(argv[2], &argv[2], 10);
6031 xhci_dbg(xhci, "hub_num set to %d\n", hub_num);
6032 }
6033 if(argc > 3){
6034 port_num = (int)simple_strtol(argv[3], &argv[3], 10);
6035 xhci_dbg(xhci, "port_num set to %d\n", port_num);
6036 }
6037 return f_hub_config_subhub(parent_hub_num, hub_num, port_num);
6038 }
6039
6040 static int t_hub_configure_eth_device(int argc, char** argv){
6041 int hub_num, port_num, dev_num;
6042 int ret;
6043
6044 ret = 0;
6045
6046 if(argc > 1){ //hub number
6047 hub_num = (int)simple_strtol(argv[1], &argv[1], 10);
6048 xhci_dbg(xhci, "hub_num set to %d\n", hub_num);
6049 }
6050 if(argc > 2){ //port number
6051 port_num = (int)simple_strtol(argv[2], &argv[2], 10);
6052 xhci_dbg(xhci, "port_num set to %d\n", port_num);
6053 }
6054 if(argc > 3){ //device number
6055 dev_num = (int)simple_strtol(argv[3], &argv[3], 10);
6056 xhci_dbg(xhci, "dev_num set to %d\n", dev_num);
6057 }
6058
6059 ret = f_hub_configuredevice(hub_num, port_num, dev_num
6060 , 0, 0, 0, false, false, 0);
6061 if(ret)
6062 {
6063 mtk_test_dbg( "Config device failed\n");
6064 return ret;
6065 }
6066 ret = f_hub_configure_eth_device(hub_num, port_num, dev_num);
6067 if(ret)
6068 {
6069 mtk_test_dbg( "Config eth device failed\n");
6070 return ret;
6071 }
6072 return ret;
6073 }
6074
6075 static int t_hub_configuredevice(int argc, char** argv){
6076 int hub_num, port_num, dev_num;
6077 int transfer_type, bInterval, maxp;
6078 char is_config_ep, is_stress;
6079 int stress_config;
6080 int ret;
6081
6082 hub_num = 1;
6083 port_num = 1;
6084 dev_num = 1;
6085 transfer_type = EPATT_BULK;
6086 bInterval = 0;
6087 maxp = 512;
6088 is_config_ep = true;
6089 is_stress = false;
6090
6091 if(argc > 1){ //hub number
6092 hub_num = (int)simple_strtol(argv[1], &argv[1], 10);
6093 xhci_dbg(xhci, "hub_num set to %d\n", hub_num);
6094 }
6095 if(argc > 2){ //port number
6096 port_num = (int)simple_strtol(argv[2], &argv[2], 10);
6097 xhci_dbg(xhci, "port_num set to %d\n", port_num);
6098 }
6099 if(argc > 3){ //device number
6100 dev_num = (int)simple_strtol(argv[3], &argv[3], 10);
6101 xhci_dbg(xhci, "dev_num set to %d\n", dev_num);
6102 }
6103 if(argc > 4){ //transfer type
6104 if(!strcmp(argv[4], "bulk")){
6105 transfer_type = EPATT_BULK;
6106 xhci_dbg(xhci, "transfer type set to BULK\n");
6107 }
6108 else if(!strcmp(argv[4], "intr")){
6109 xhci_dbg(xhci, "transfer type set to INTR\n");
6110 transfer_type = EPATT_INT;
6111 }
6112 else if(!strcmp(argv[4], "iso")){
6113 xhci_dbg(xhci, "transfer type set to ISO\n");
6114 transfer_type = EPATT_ISO;
6115 }
6116 else if(!strcmp(argv[4], "stress1")){
6117 xhci_dbg(xhci, "transfer type set to STRESS1 BULK+INT\n");
6118 is_stress = true;
6119 stress_config = 1;
6120 is_config_ep = false;
6121 }
6122 else if(!strcmp(argv[4], "stress2")){
6123 xhci_dbg(xhci, "transfer type set to STRESS2 BULK_ISO\n");
6124 is_stress = true;
6125 stress_config = 2;
6126 is_config_ep = false;
6127 }
6128 }
6129 else{
6130 is_config_ep = false;
6131 }
6132 if(argc > 5){ //maxp
6133 maxp = (int)simple_strtol(argv[5], &argv[5], 10);
6134 xhci_dbg(xhci, "maxp set to %d\n", maxp);
6135 }
6136 if(argc > 6){ //interval
6137 bInterval= (int)simple_strtol(argv[6], &argv[6], 10);
6138 xhci_dbg(xhci, "bInterval set to %d\n", bInterval);
6139 }
6140
6141 return f_hub_configuredevice(hub_num, port_num, dev_num
6142 , transfer_type, maxp, bInterval, is_config_ep, is_stress, stress_config);
6143 }
6144
6145 static int t_hub_reset_dev(int argc, char** argv){
6146 struct xhci_hcd *xhci;
6147 int hub_num, port_num, dev_num;
6148 int transfer_type, bInterval, maxp;
6149 struct usb_device *udev;
6150 USB_DEV_SPEED speed;
6151 int ret;
6152
6153 hub_num = 1;
6154 port_num = 1;
6155 dev_num = 1;
6156 ret = 0;
6157 xhci = hcd_to_xhci(my_hcd);
6158 if(argc > 1){ //hub number
6159 hub_num = (int)simple_strtol(argv[1], &argv[1], 10);
6160 xhci_dbg(xhci, "hub_num set to %d\n", hub_num);
6161 }
6162 if(argc > 2){ //port number
6163 port_num = (int)simple_strtol(argv[2], &argv[2], 10);
6164 xhci_dbg(xhci, "port_num set to %d\n", port_num);
6165 }
6166 if(argc > 3){ //device number
6167 dev_num = (int)simple_strtol(argv[3], &argv[3], 10);
6168 xhci_dbg(xhci, "dev_num set to %d\n", dev_num);
6169 }
6170 if(argc > 4){
6171 if(!strcmp(argv[4], "hs")){
6172 mtk_test_dbg( "[DEV]Reset device to high speed\n");
6173 speed = DEV_SPEED_HIGH;
6174 }
6175 else if(!strcmp(argv[4], "fs")){
6176 mtk_test_dbg( "[DEV]Reset device to full speed\n");
6177 speed = DEV_SPEED_FULL;
6178 }
6179 }
6180
6181 udev = dev_list[dev_num-1];
6182 g_slot_id = udev->slot_id;
6183 ret = dev_reset(speed,udev);
6184 if(f_hub_clearportfeature(hub_num, HUB_FEATURE_PORT_POWER, dev_num) != RET_SUCCESS){
6185 xhci_err(xhci, "[ERROR] clear port_power %d failed\n", dev_num);
6186 return RET_FAIL;
6187 }
6188 mdelay(500);
6189 if(f_hub_setportfeature(hub_num, HUB_FEATURE_PORT_POWER, dev_num) != RET_SUCCESS){
6190 xhci_err(xhci, "[ERROR] set port_power %d failed\n", dev_num);
6191 return RET_FAIL;
6192 }
6193 if(f_hub_clearportfeature(hub_num, HUB_FEATURE_C_PORT_CONNECTION, dev_num) != RET_SUCCESS){
6194 xhci_err(xhci, "[ERROR] clear c_port_connection failed\n");
6195 }
6196 f_disable_slot();
6197 kfree(udev);
6198 dev_list[dev_num-1] = NULL;
6199 return RET_SUCCESS;
6200 }
6201
6202 static int t_hub_queue_intr(int argc, char** argv){
6203 u32 status;
6204 int ret;
6205 struct usb_device *hdev;
6206 struct xhci_hcd *xhci;
6207 struct urb *urb;
6208 struct usb_host_endpoint *ep;
6209 int ep_index, data_length;
6210
6211 xhci = hcd_to_xhci(my_hcd);
6212 hdev = hdev_list[0];
6213 ep = hdev->ep_in[1];
6214 ep_index = mtktest_xhci_get_endpoint_index(&ep->desc);
6215 urb = usb_alloc_urb(0, GFP_KERNEL);
6216 data_length = 2;
6217
6218 ret = f_fill_urb(urb,1,data_length,0,URB_DIR_IN, 0, 2, hdev);
6219 if(ret){
6220 xhci_err(xhci, "[ERROR]fill urb Error!!\n");
6221 return RET_FAIL;
6222 }
6223 ret = f_queue_urb(urb,0,hdev);
6224 if(ret){
6225 xhci_err(xhci, "[ERROR]urb transfer failed!!\n");
6226 return RET_FAIL;
6227 }
6228 return RET_SUCCESS;
6229 }
6230
6231 static int t_hub_remotewakeup_dev(int argc, char** argv){
6232 int hub_num, port_num, dev_num;
6233 int transfer_type, bInterval, maxp;
6234 struct usb_device *udev;
6235 USB_DEV_SPEED speed;
6236 int ret;
6237 int length;
6238 int bdp, gpd_buf_size, bd_buf_size;
6239
6240 bdp=0;
6241 gpd_buf_size=0xFC00;
6242 bd_buf_size=0x1FFF;
6243 length=513;
6244 hub_num = 1;
6245 port_num = 1;
6246 dev_num = 1;
6247 ret = 0;
6248
6249 if(argc > 1){ //hub number
6250 hub_num = (int)simple_strtol(argv[1], &argv[1], 10);
6251 xhci_dbg(xhci, "hub_num set to %d\n", hub_num);
6252 }
6253 if(argc > 2){ //port number
6254 port_num = (int)simple_strtol(argv[2], &argv[2], 10);
6255 xhci_dbg(xhci, "port_num set to %d\n", port_num);
6256 }
6257 if(argc > 3){ //device number
6258 dev_num = (int)simple_strtol(argv[3], &argv[3], 10);
6259 xhci_dbg(xhci, "dev_num set to %d\n", dev_num);
6260 }
6261 if(argc > 4){
6262 length = (int)simple_strtol(argv[4], &argv[4], 10);
6263 mtk_test_dbg( "length set to %d\n", length);
6264 }
6265
6266 udev = dev_list[dev_num-1];
6267 g_slot_id = udev->slot_id;
6268 return dev_remotewakeup(0);
6269 }
6270
6271 #define HUB_FEATURE_PORT_U1_TIMEOUT 23
6272 #define HUB_FEATURE_PORT_U2_TIMEOUT 24
6273
6274 static int t_hub_set_u1u2(int argc, char** argv){
6275 int u_num, value1, value2, value;
6276 int feature_selector;
6277 int port_num;
6278
6279 u_num = 1;
6280 value1 = 1;
6281 value2 = 1;
6282 value = 1;
6283 port_num = 1;
6284
6285
6286 if(argc > 1){
6287 u_num = (int)simple_strtol(argv[1], &argv[1], 10);
6288 xhci_dbg(xhci, "u_num set to %d\n", u_num);
6289 }
6290 if(argc > 2){
6291 value1 = (int)simple_strtol(argv[2], &argv[2], 10);
6292 xhci_dbg(xhci, "value1 set to %d\n", value1);
6293 }
6294 if(argc > 3){
6295 value2 = (int)simple_strtol(argv[3], &argv[3], 10);
6296 xhci_dbg(xhci, "value2 set to %d\n", value2);
6297 }
6298 if(argc > 4){
6299 port_num = (int)simple_strtol(argv[4], &argv[4], 10);
6300 xhci_dbg(xhci, "port_num set to %d\n", port_num);
6301 }
6302
6303 if(u_num == 1){
6304 feature_selector = HUB_FEATURE_PORT_U1_TIMEOUT;
6305 value = value1;
6306 }
6307 else if(u_num == 2){
6308 feature_selector = HUB_FEATURE_PORT_U2_TIMEOUT;
6309 value = value2;
6310 }
6311
6312 f_hub_setportfeature(1, feature_selector, (port_num | (value<<8)));
6313 return RET_SUCCESS;
6314 }
6315
6316 #define HUB_FEATURE_FORCE_LINKPM_ACCEPT 30
6317 static int t_hub_force_pm(int argc, char** argv){
6318 f_hub_sethubfeature(1, HUB_FEATURE_FORCE_LINKPM_ACCEPT);
6319 return RET_SUCCESS;
6320 }
6321
6322 static int t_dev_notification(int argc, char** argv){
6323 int ret;
6324 int type;
6325 int type_value;
6326 int value;
6327
6328 ret = 0;
6329 type = 1;
6330 value = 1;
6331
6332 if(!g_port_reset){
6333 mtk_test_dbg( "[ERROR] device not reset\n");
6334 return RET_FAIL;
6335 }
6336 if(g_slot_id == 0){
6337 mtk_test_dbg( "[ERROR] slot not enabled\n");
6338 return RET_FAIL;
6339 }
6340 if(argc > 1){
6341 //[DEV_NOTIF_FUNC_WAKE: 1]; [DEV_NOTIF_LTM: 2];
6342 //[DEV_NOTIF_BUS_INT_ADJ: 3];[VENDOR_DEV_TEST: 4]
6343 type = (int)simple_strtol(argv[1], &argv[1], 10);
6344 }
6345 if(argv > 2){
6346 value = (int)simple_strtol(argv[2], &argv[2], 10);
6347 }
6348 f_enable_dev_note();
6349 g_dev_notification = 256;
6350 g_dev_not_value = 0;
6351 // type_value = type+1;
6352 //TODO: device notification interface has been modified
6353 ret = dev_notifiaction(type,value & 0xffffffff,(value >> 32) & 0xffffffff);
6354 if(ret)
6355 {
6356 mtk_test_dbg( "set device notification failed!!\n");
6357 return ret;
6358 }
6359 ret=dev_polling_status(NULL);
6360 if(ret)
6361 {
6362 mtk_test_dbg( "query request fail!!\n");
6363 return ret;
6364 }
6365 ret = wait_event_on_timeout(&g_dev_notification, type,CMD_TIMEOUT);
6366 if(ret){
6367 mtk_test_dbg( "device notification event not received!!\n");
6368 return ret;
6369 }
6370 if(g_dev_not_value != value){
6371 mtk_test_dbg( "device notification value error, expected %d, recived %ld!!\n", value, g_dev_not_value);
6372 return RET_FAIL;
6373 }
6374 return ret;
6375 }
6376
6377 static int t_dev_init(int argc, char** argv){
6378 if(u3auto_hcd_reset() != RET_SUCCESS)
6379 return RET_FAIL;
6380 }
6381
6382 static int t_dev_u1u2(int argc, char** argv){
6383 int ret;
6384 int value1, value2;
6385 char en_u1, en_u2;
6386 int dev_num;
6387 int mode;
6388 struct usb_device *udev;
6389
6390 value1 = 0;
6391 value2 = 0;
6392 en_u1 = 1;
6393 en_u2 = 1;
6394 udev = NULL;
6395 mode = 0;
6396
6397 if(argc > 1){
6398 value1 = (int)simple_strtol(argv[1], &argv[1], 10);
6399 xhci_dbg(xhci, "u1 value set to %d\n", value1);
6400 }
6401 if(argc > 2){
6402 value2 = (int)simple_strtol(argv[2], &argv[2], 10);
6403 xhci_dbg(xhci, "u2 value set to %d\n", value2);
6404 }
6405 if(argc > 3){
6406 en_u1 = (int)simple_strtol(argv[3], &argv[3], 10);
6407 xhci_dbg(xhci, "en_u1 set to %d\n", en_u1);
6408 }
6409 if(argc > 4){
6410 en_u2 = (int)simple_strtol(argv[4], &argv[4], 10);
6411 xhci_dbg(xhci, "en_u2 set to %d\n", en_u2);
6412 }
6413 if(argc > 5){
6414 dev_num = (int)simple_strtol(argv[5], &argv[5], 10);
6415 udev = dev_list[dev_num-1];
6416 }
6417 if(argc > 6){
6418 mode = (int)simple_strtol(argv[6], &argv[6], 10);
6419 }
6420 return dev_power(mode, value1, value2, en_u1, en_u2, udev);
6421 }
6422
6423 static int t_dev_lpm(int argc, char** argv){
6424 int ret;
6425 int lpm_mode, wakeup, beslck, beslck_u3, beslckd, cond, cond_en;
6426
6427 lpm_mode = 0;
6428 wakeup = 0;
6429 beslck = 0;
6430 beslck_u3 = 0;
6431 beslckd = 0;
6432 cond = 0;
6433 cond_en = 0;
6434
6435 if(argc > 1){
6436 lpm_mode = (int)simple_strtol(argv[1], &argv[1], 10);
6437 }
6438 if(argc > 2){
6439 wakeup = (int)simple_strtol(argv[2], &argv[2], 10);
6440 }
6441 if(argc > 3){
6442 beslck = (int)simple_strtol(argv[3], &argv[3], 10);
6443 }
6444 if(argc > 4){
6445 beslck_u3 = (int)simple_strtol(argv[4], &argv[4], 10);
6446 }
6447 if(argc > 5){
6448 beslckd = (int)simple_strtol(argv[5], &argv[5], 10);
6449 }
6450 if(argc > 6){
6451 cond = (int)simple_strtol(argv[6], &argv[6], 10);
6452 }
6453 if(argc > 7){
6454 cond_en = (int)simple_strtol(argv[7], &argv[7], 10);
6455 }
6456
6457 dev_lpm_config_host(lpm_mode, wakeup, beslck, beslck_u3, beslckd, cond, cond_en);
6458 }
6459
6460 static int t_dev_reset(int argc, char** argv){
6461 USB_DEV_SPEED speed;
6462 int ret;
6463
6464 ret = 0;
6465 if(!g_port_reset){
6466 mtk_test_dbg( "[ERROR] device not reset\n");
6467 return RET_FAIL;
6468 }
6469 if(g_slot_id == 0){
6470 mtk_test_dbg( "[ERROR] slot not enabled\n");
6471 return RET_FAIL;
6472 }
6473 speed = DEV_SPEED_HIGH;
6474 if(argc > 1){
6475 if(!strcmp(argv[1], "ss")){
6476 mtk_test_dbg( "[DEV]Reset device to super speed\n");
6477 speed = DEV_SPEED_SUPER;
6478 }
6479 if(!strcmp(argv[1], "hs")){
6480 mtk_test_dbg( "[DEV]Reset device to high speed\n");
6481 speed = DEV_SPEED_HIGH;
6482 }
6483 else if(!strcmp(argv[1], "fs")){
6484 mtk_test_dbg( "[DEV]Reset device to full speed\n");
6485 speed = DEV_SPEED_FULL;
6486 }
6487 }
6488 start_port_reenabled(0, speed);
6489 ret = dev_reset(speed,NULL);
6490 if(ret){
6491 mtk_test_dbg( "[ERROR] reset device failed\n");
6492 return RET_FAIL;
6493 }
6494 ret = f_disable_slot();
6495 if(ret){
6496 mtk_test_dbg( "disable slot failed!!!!!!!!!!\n");
6497 return ret;
6498 }
6499 ret = f_reenable_port(0);
6500 if(ret){
6501 mtk_test_dbg( "[ERROR] port reenable failed\n");
6502 return RET_FAIL;
6503 }
6504 ret = f_enable_slot(NULL);
6505 if(ret){
6506 mtk_test_dbg( "enable slot failed!!!!!!!!!!\n");
6507 return ret;
6508 }
6509
6510 ret=f_address_slot(false, NULL);
6511 if(ret){
6512 mtk_test_dbg( "address slot failed!!!!!!!!!!\n");
6513 return ret;
6514 }
6515 //reset SW scheduler algorithm
6516 mtktest_mtk_xhci_scheduler_init();
6517 return ret;
6518 }
6519
6520 static int t_dev_query_status(int argc, char** argv){
6521 if(!g_port_reset){
6522 mtk_test_dbg( "[ERROR] device not reset\n");
6523 return RET_FAIL;
6524 }
6525 if(g_slot_id == 0){
6526 mtk_test_dbg( "[ERROR] slot not enabled\n");
6527 return RET_FAIL;
6528 }
6529 return dev_query_status(NULL);
6530 }
6531
6532 static int t_dev_polling_status(int argc, char** argv){
6533 if(!g_port_reset){
6534 mtk_test_dbg( "[ERROR] device not reset\n");
6535 return RET_FAIL;
6536 }
6537 if(g_slot_id == 0){
6538 mtk_test_dbg( "[ERROR] slot not enabled\n");
6539 return RET_FAIL;
6540 }
6541 return dev_polling_status(NULL);
6542 }
6543
6544 static int t_dev_config_ep(int argc, char** argv){
6545 char ep_num;
6546 char dir;
6547 char type;
6548 short int maxp;
6549 char bInterval;
6550 int mult_dev, burst, mult;
6551
6552 if(!g_port_reset){
6553 mtk_test_dbg( "[ERROR] device not reset\n");
6554 return RET_FAIL;
6555 }
6556 if(g_slot_id == 0){
6557 mtk_test_dbg( "[ERROR] slot not enabled\n");
6558 return RET_FAIL;
6559 }
6560 //ep_out_num,USB_RX,transfer_type,maxp,bInterval
6561 ep_num = 1;
6562 dir= USB_TX;
6563 type=EPATT_BULK;
6564 maxp=512;
6565 bInterval=0;
6566 mult_dev = 3;
6567 burst = 8;
6568 mult = 0;
6569
6570 if(argc > 1){
6571 ep_num = (int)simple_strtol(argv[1], &argv[1], 10);
6572 mtk_test_dbg( "ep_num set to %d\n", ep_num);
6573 }
6574 if(argc > 2){
6575 if(!strcmp(argv[2], "tx")){
6576 mtk_test_dbg( "TX endpoint\n");
6577 dir = USB_TX;
6578 }
6579 else if(!strcmp(argv[2], "rx")){
6580 mtk_test_dbg( "RX endpoint\n");
6581 dir = USB_RX;
6582 }
6583 }
6584 if(argc > 3){
6585 if(!strcmp(argv[3], "bulk")){
6586 mtk_test_dbg( "Test bulk transfer\n");
6587 type = EPATT_BULK;
6588 }
6589 else if(!strcmp(argv[3], "intr")){
6590 mtk_test_dbg( "Test intr transfer\n");
6591 type = EPATT_INT;
6592 }
6593 else if(!strcmp(argv[3], "isoc")){
6594 mtk_test_dbg( "Test isoc transfer\n");
6595 type = EPATT_ISO;
6596 }
6597 }
6598 if(argc > 4){
6599 maxp = (int)simple_strtol(argv[4], &argv[4], 10);
6600 mtk_test_dbg( "maxp set to %d\n", maxp);
6601 }
6602 if(argc > 5){
6603 bInterval = (int)simple_strtol(argv[5], &argv[5], 10);
6604 mtk_test_dbg( "bInterval set to %d\n", bInterval);
6605 }
6606 if(argc > 6){
6607 burst = (int)simple_strtol(argv[6], &argv[6], 10);
6608 mtk_test_dbg( "burst set to %d\n", burst);
6609 }
6610 if(argc > 7){
6611 mult = (int)simple_strtol(argv[7], &argv[7], 10);
6612 mtk_test_dbg( "mult set to %d\n", mult);
6613 }
6614 return dev_config_ep(ep_num, dir, type, maxp, bInterval,mult_dev,burst,mult,NULL);
6615 }
6616
6617 static int t_dev_remotewakeup(int argc, char** argv){
6618 int delay_us;
6619 int bdp, gpd_buf_size, bd_buf_size;
6620
6621 bdp=0;
6622 gpd_buf_size=0xFC00;
6623 bd_buf_size=0x1FFF;
6624
6625 if(!g_port_reset){
6626 mtk_test_dbg( "[ERROR] device not reset\n");
6627 return RET_FAIL;
6628 }
6629 if(g_slot_id == 0){
6630 mtk_test_dbg( "[ERROR] slot not enabled\n");
6631 return RET_FAIL;
6632 }
6633 if(argc > 1){
6634 delay_us = (int)simple_strtol(argv[1], &argv[1], 10);
6635 mtk_test_dbg( "Device delay %d us\n", delay_us);
6636 }
6637 return dev_remotewakeup(delay_us);
6638 }
6639
6640 //Test concurrently resume case
6641 static int t_u3auto_concurrent_remotewakeup(int argc, char** argv){
6642 int ret,loop,length,j,i;
6643 char bdp;
6644 short gpd_buf_size,bd_buf_size;
6645 int speed,host_speed;
6646 int maxp, count,mult;
6647 uint rand_num;
6648 uint dev_delay_us, host_delay_ms;
6649
6650 struct xhci_hcd *xhci;
6651 u32 __iomem *addr;
6652 int temp;
6653 int delay_time;
6654
6655 xhci = hcd_to_xhci(my_hcd);
6656 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(g_port_id-1 & 0xff);
6657
6658 ret = 0;
6659
6660 speed = DEV_SPEED_HIGH;
6661 count = 100;
6662 delay_time = 40;
6663 if(argc > 1){
6664 if(!strcmp(argv[1], "ss")){
6665 mtk_test_dbg( "Test super speed\n");
6666 speed = DEV_SPEED_SUPER;
6667 }
6668 else if(!strcmp(argv[1], "hs")){
6669 mtk_test_dbg( "Test high speed\n");
6670 speed = DEV_SPEED_HIGH;
6671 }
6672 else if(!strcmp(argv[1], "fs")){
6673 mtk_test_dbg( "Test full speed\n");
6674 speed = DEV_SPEED_FULL;
6675 }
6676 }
6677
6678 if(argc > 2){
6679 count = (int)simple_strtol(argv[2], &argv[2], 10);
6680 }
6681 if(argc > 3){
6682 delay_time = (int)simple_strtol(argv[3], &argv[3], 10);
6683 }
6684
6685 maxp = 1024;
6686 g_concurrent_resume = true;
6687 /* ==phase 1 : config EP==*/
6688
6689 #if 0
6690 ret=dev_config_ep(2,USB_RX,EPATT_BULK,maxp,0,3,0,0,NULL);
6691 if(ret)
6692 {
6693 mtk_test_dbg( "config dev EP fail!!\n");
6694 return ret;
6695 }
6696
6697 ret=dev_config_ep(2,USB_TX,EPATT_BULK,maxp,0,3,0,0,NULL);
6698 if(ret)
6699 {
6700 mtk_test_dbg( "config dev EP fail!!\n");
6701 return ret;
6702 }
6703
6704 ret = f_config_ep(2,EPADD_OUT,EPATT_BULK,maxp,0,0 ,0,NULL,0);
6705 if(ret)
6706 {
6707 mtk_test_dbg( "config EP fail!!\n");
6708 return ret;
6709 }
6710
6711 ret = f_config_ep(2,EPADD_IN,EPATT_BULK,maxp,0,0 ,0,NULL,1);
6712 if(ret)
6713 {
6714 mtk_test_dbg( "config EP fail!!\n");
6715 return ret;
6716 }
6717 #endif
6718
6719 for(i=0;i<count;i++)
6720 {
6721 #if 0
6722 get_random_bytes(&rand_num , sizeof(rand_num));
6723 host_delay_ms = //suspend 30~60 ms to make sure the host side check timing saving
6724 get_random_bytes(&rand_num , sizeof(rand_num));
6725 dev_delay_ms = 30 + rand_num % 30; //suspend 30~60 ms to make sure the host side check timing saving
6726 #else
6727 dev_delay_us = 0;
6728 #endif
6729
6730 mtk_test_dbg( "count: %d, host_delay: %d, dev_delay: %d\n", i, host_delay_ms, dev_delay_us);
6731
6732 ret = dev_remotewakeup(dev_delay_us);
6733 if(ret)
6734 {
6735 mtk_test_dbg( "remote wakeup request fail!!\n");
6736 g_concurrent_resume = false;
6737 return ret;
6738 }
6739
6740 ret = f_power_suspend();
6741 if(ret)
6742 {
6743 mtk_test_dbg( "suspend fail!!!\n");
6744 }
6745
6746 #if 0 //original remote wakeup test logic
6747 ret = f_power_remotewakeup();
6748 if(ret)
6749 {
6750 mtk_test_dbg( "remote wakeup fail!!\n");
6751 return ret;
6752 }
6753 #else //enhanced remote wakeup test logic
6754 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(g_port_id-1 & 0xff);
6755 mdelay(10);
6756 udelay(delay_time);
6757 //delay(i);
6758
6759 ret=f_power_resume(0);
6760 if(ret)
6761 {
6762 mtk_test_dbg( "wakeup fail!!\n");
6763 g_concurrent_resume = false;
6764 return ret;
6765 }
6766 #endif
6767
6768 mdelay(500);
6769 #if 0
6770 /* ==phase 2 : loopback== */
6771 bdp=0;
6772 gpd_buf_size=0xFC00;
6773 bd_buf_size=0x1000;
6774 length=8*1024;
6775
6776
6777 ret=dev_loopback(bdp,length,gpd_buf_size,bd_buf_size, 0, 0,NULL);
6778 if(ret)
6779 {
6780 mtk_test_dbg( "loopback request fail!!\n");
6781 mtk_test_dbg( "length : %d\n",length);
6782 return ret;
6783 }
6784
6785 ret = f_loopback_loop(2,2,length, 0,NULL);
6786 if(ret)
6787 {
6788 mtk_test_dbg( "loopback fail!!\n");
6789 mtk_test_dbg( "length : %d\n",length);
6790 return ret;
6791 }
6792
6793 ret=dev_polling_status(NULL);
6794 if(ret)
6795 {
6796 mtk_test_dbg( "query request fail!!\n");
6797 return ret;
6798 }
6799
6800 mdelay(10);
6801
6802 mtk_test_dbg( "length : %d\n",length);
6803 #endif
6804 }
6805 g_concurrent_resume = false;
6806 return ret;
6807 }
6808
6809 static int t_u3auto_concurrent_u1u2_exit(int argc, char** argv){
6810 int ret,loop,length,j,i;
6811 char bdp;
6812 short gpd_buf_size,bd_buf_size;
6813 int speed,host_speed;
6814 int maxp, count,mult;
6815 uint rand_num;
6816 struct xhci_hcd *xhci;
6817 u32 __iomem *addr;
6818 int temp;
6819 int dev_delay_time, host_delay_time, do_ux;
6820 int port_id;
6821
6822 struct usb_ctrlrequest *dr;
6823 struct usb_device *udev, *rhdev;
6824 struct urb *urb;
6825 struct protocol_query *query;
6826
6827 xhci = hcd_to_xhci(my_hcd);
6828 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(g_port_id-1 & 0xff);
6829
6830 ret = 0;
6831
6832 speed = DEV_SPEED_SUPER;
6833 count = 100;
6834 port_id = 1;
6835
6836 if(argc > 1){
6837 count = (int)simple_strtol(argv[1], &argv[1], 10);
6838 }
6839 if(argc > 2){
6840 dev_delay_time = (int)simple_strtol(argv[2], &argv[2], 10);
6841 }
6842 if(argc > 3){
6843 host_delay_time = (int)simple_strtol(argv[3], &argv[3], 10);
6844 }
6845 if(argc > 4){
6846 do_ux = (int)simple_strtol(argv[4], &argv[4], 10);
6847 }
6848 if(argc > 5){
6849 port_id = (int)simple_strtol(argv[5], &argv[5], 10);
6850 }
6851 for(i=0; i<count; i++){
6852 ret = dev_remotewakeup(dev_delay_time);
6853 if(ret)
6854 {
6855 mtk_test_dbg( "remote wakeup request fail!!\n");
6856 return ret;
6857 }
6858 mdelay(100);
6859 ret = f_port_set_pls(port_id, do_ux);
6860 if(ret){
6861 continue;
6862 }
6863 udelay(host_delay_time);
6864 ret = f_port_set_pls(1, 0);
6865 }
6866 //dev_power(0, 0, 0, 1, 1, NULL);
6867 //f_port_set_pls(1, 0);
6868
6869 return RET_SUCCESS;
6870 }
6871
6872 static int t_u3auto_concurrent_u1u2_enter(int argc, char** argv){
6873 int ret,loop,length,j,i;
6874 char bdp;
6875 short gpd_buf_size,bd_buf_size;
6876 int speed,host_speed;
6877 int maxp, count,mult;
6878 uint rand_num;
6879 uint dev_delay_ms, host_delay_ms;
6880 uint do_ux;
6881 struct xhci_hcd *xhci;
6882 u32 __iomem *addr;
6883 int temp;
6884 int delay_time, dev_u1_delay, dev_u2_delay;
6885
6886 struct usb_ctrlrequest *dr;
6887 struct usb_device *udev, *rhdev;
6888 struct urb *urb;
6889 struct protocol_query *query;
6890
6891 xhci = hcd_to_xhci(my_hcd);
6892 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(g_port_id-1 & 0xff);
6893
6894 ret = 0;
6895
6896 speed = DEV_SPEED_SUPER;
6897 count = 100;
6898 delay_time = 40;
6899
6900 dev_u1_delay = 0;
6901 dev_u2_delay = 0;
6902
6903 if(argc > 1){
6904 count = (int)simple_strtol(argv[1], &argv[1], 10);
6905 }
6906 if(argc > 2){
6907 delay_time = (int)simple_strtol(argv[2], &argv[2], 10);
6908 }
6909 if(argc > 3){
6910 dev_u1_delay= (int)simple_strtol(argv[3], &argv[3], 10);
6911 }
6912 if(argc > 4){
6913 dev_u2_delay= (int)simple_strtol(argv[4], &argv[4], 10);
6914 }
6915 if(argc > 5){
6916 do_ux = (int)simple_strtol(argv[5], &argv[5], 10);
6917 }
6918
6919 maxp = 1024;
6920 #if 0
6921 /* ==phase 1 : config EP==*/
6922 ret=dev_config_ep(2,USB_RX,EPATT_BULK,maxp,0,3,0,0,NULL);
6923 if(ret)
6924 {
6925 mtk_test_dbg( "config dev EP fail!!\n");
6926 return ret;
6927 }
6928
6929 ret=dev_config_ep(2,USB_TX,EPATT_BULK,maxp,0,3,0,0,NULL);
6930 if(ret)
6931 {
6932 mtk_test_dbg( "config dev EP fail!!\n");
6933 return ret;
6934 }
6935
6936 ret = f_config_ep(2,EPADD_OUT,EPATT_BULK,maxp,0,0 ,0,NULL,0);
6937 if(ret)
6938 {
6939 mtk_test_dbg( "config EP fail!!\n");
6940 return ret;
6941 }
6942
6943 ret = f_config_ep(2,EPADD_IN,EPATT_BULK,maxp,0,0 ,0,NULL,1);
6944 if(ret)
6945 {
6946 mtk_test_dbg( "config EP fail!!\n");
6947 return ret;
6948 }
6949 #endif
6950 #if 1
6951 //set device u1u2 timeout
6952 if(dev_u1_delay > 0){
6953 dev_power(1, dev_u1_delay, 0, 1, 1, NULL);
6954 //do_ux = 2;
6955 }
6956 else if(dev_u2_delay > 0){
6957 dev_power(2, 0, dev_u2_delay, 1, 1, NULL);
6958 //do_ux = 1;
6959 }
6960 else{
6961 mtk_test_dbg( "[ERROR] Doesn't set device u1 or u2 timeout value\n");
6962 return RET_FAIL;
6963 }
6964 #endif
6965 //host side only set accept u1u2
6966 f_power_set_u1u2(3, 255, 255);
6967 msleep(5);
6968 #if 0
6969 g_con_is_enter = true;
6970 g_con_delay_us = delay_time;
6971 g_con_enter_ux = do_ux;
6972 #endif
6973 for(i=0; i<count; i++){
6974 //get_random_bytes(&rand_num , sizeof(rand_num));
6975
6976 /* ==phase 1 : do some transfer to back to U0== */
6977 //dev_query_status(NULL);
6978 #if 1
6979 rhdev = my_hcd->self.root_hub;
6980 udev = rhdev->children[g_port_id-1];
6981
6982
6983 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
6984 query= kmalloc(AT_CMD_ACK_DATA_LENGTH, GFP_NOIO);
6985
6986 memset(query, 0, AT_CMD_ACK_DATA_LENGTH);
6987
6988 dr->bRequestType = USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE;;
6989 dr->bRequest = AT_CMD_ACK;
6990 dr->wValue = cpu_to_le16(0);
6991 dr->wIndex = cpu_to_le16(0);
6992 dr->wLength = cpu_to_le16(AT_CMD_ACK_DATA_LENGTH);
6993 urb = alloc_ctrl_urb(dr, query, udev);
6994 ret = f_ctrlrequest_nowait(urb, udev);
6995
6996 //**************************************************/
6997 //wait_not_event_on_timeout(&(urb->status), -EINPROGRESS, TRANS_TIMEOUT);
6998 #if 1
6999 mdelay(3);
7000 udelay(delay_time);
7001 /* ==phase 2 : transfer U1 or U2 packet== */
7002 //mtk_test_dbg( "[DBG] set port pls = %d\n", do_ux);
7003 f_port_set_pls(1, do_ux);
7004 udelay(100);
7005 if(do_ux == 3){
7006 f_port_set_pls(1, 0);
7007 }
7008 //mtk_test_dbg( "[DBG] set port pls = 0\n");
7009 //f_port_set_pls(1, 0);
7010
7011 wait_not_event_on_timeout(&(urb->status), -EINPROGRESS, TRANS_TIMEOUT);
7012 mtktest_xhci_urb_free_priv(xhci, urb->hcpriv);
7013 #endif
7014 #endif
7015 //* clear some trash left */
7016 kfree(dr);
7017 kfree(query);
7018 // kfree(urb);
7019 usb_free_urb(urb);
7020 //************************************************/
7021 dev_query_status(NULL);
7022 }
7023 dev_power(0, 0, 0, 1, 1, NULL);
7024 //f_port_set_pls(1, 0);
7025
7026 return RET_SUCCESS;
7027 }
7028
7029 static int t_start_host_test_mode(int argc, char** argv){
7030 int td_no;
7031
7032 printk(KERN_ERR "[OTG_H] call t_start_host_test_mode\n");
7033
7034 td_no = 0; // td_no = 6 ~ 12 (0x6 ~ 0xc)
7035 if(argc > 1){
7036 td_no = (int)simple_strtol(argv[1], &argv[1], 10);
7037 }
7038 f_host_test_mode(td_no) ;
7039
7040 return RET_SUCCESS;
7041 }
7042
7043 static int t_stop_host_test_mode(int argc, char** argv){
7044 int td_no;
7045
7046 td_no = 0;
7047 if(argc > 1){
7048 td_no = (int)simple_strtol(argv[1], &argv[1], 10);
7049 }
7050
7051 f_host_test_mode_stop() ;
7052
7053 return RET_SUCCESS;
7054 }
7055
7056
7057 static int t_drv_vbus(int argc, char** argv){
7058 f_drv_vbus() ;
7059 return RET_SUCCESS;
7060 }
7061
7062 static int t_stop_vbus(int argc, char** argv){
7063 f_stop_vbus() ;
7064 return RET_SUCCESS;
7065 }
7066
7067 //initial code attached to A-connector
7068 static int t_u3h_otg_dev_A_host(int argc, char** argv){
7069 u32 temp;
7070 g_otg_test = true;
7071 g_otg_dev_B = false;
7072 //enable OTG interrupt
7073 temp = readl(SSUSB_OTG_INT_EN);
7074 temp = temp | SSUSB_ATTACH_A_ROLE_INT_EN | SSUSB_CHG_A_ROLE_A_INT_EN
7075 | SSUSB_CHG_B_ROLE_A_INT_EN | SSUSB_SRP_REQ_INTR_EN;
7076 writel(temp, SSUSB_OTG_INT_EN);
7077 #if 0
7078 //disable SIFSLV CLK gating
7079 temp = readl(SSUSB_CSR_CK_CTRL);
7080 temp = temp & ~SSUSB_SIFSLV_MCU_BUS_CK_GATE_EN;
7081 writel(temp, SSUSB_CSR_CK_CTRL);
7082 #endif
7083 kthread_run(otg_dev_A_host_thread, NULL, "otg_A_host");
7084 return RET_SUCCESS;
7085 }
7086
7087 //initial code attached to B-connector
7088 static int t_u3h_otg_dev_B_host(int argc, char** argv){
7089 u32 temp;
7090 g_otg_test = true;
7091 g_otg_dev_B = true;
7092 //enable OTG interrupt
7093 temp = readl(SSUSB_OTG_INT_EN);
7094 temp = temp | SSUSB_ATTACH_A_ROLE_INT_EN | SSUSB_CHG_A_ROLE_A_INT_EN
7095 | SSUSB_CHG_B_ROLE_A_INT_EN | SSUSB_SRP_REQ_INTR_EN;
7096 writel(temp, SSUSB_OTG_INT_EN);
7097 #if 0
7098 //disable SIFSLV CLK gating
7099 temp = readl(SSUSB_CSR_CK_CTRL);
7100 temp = temp & ~SSUSB_SIFSLV_MCU_BUS_CK_GATE_EN;
7101 writel(temp, SSUSB_CSR_CK_CTRL);
7102 #endif
7103 if(f_test_lib_init() != RET_SUCCESS){
7104 printk(KERN_ERR "[OTG_H] controller driver init failed\n");
7105 return RET_FAIL;
7106 }
7107 return RET_SUCCESS;
7108 }
7109
7110 //B device wait for hnp and become host
7111 static int t_u3h_otg_dev_B_hnp(int argc, char** argv){
7112 g_otg_hnp_become_host = false;
7113 kthread_run(otg_dev_B_hnp, NULL, "otg_dev_B_hnp");
7114 return RET_SUCCESS;
7115 }
7116
7117 //A device wait hnp and become device
7118 static int t_u3h_otg_dev_A_hnp(int argc, char** argv){
7119 g_otg_hnp_become_dev = false;
7120 kthread_run(otg_dev_A_hnp, NULL, "otg_dev_A_hnp");
7121 return RET_SUCCESS;
7122 }
7123
7124 //A device back to host after hnp
7125 static int t_u3h_otg_dev_A_hnp_back(int argc, char** argv){
7126 g_otg_hnp_become_host = false;
7127 kthread_run(otg_dev_A_hnp_back, NULL, "otg_dev_A_hnp_back");
7128 return RET_SUCCESS;
7129 }
7130
7131 //B device back to host after hnp
7132 static int t_u3h_otg_dev_B_hnp_back(int argc, char** argv){
7133 g_otg_hnp_become_dev = false;
7134 kthread_run(otg_dev_B_hnp_back, NULL, "otg_dev_B_hnp_back");
7135 return RET_SUCCESS;
7136 }
7137
7138 //A device srp
7139 static int t_u3h_otg_dev_A_srp(int argc, char** argv){
7140 kthread_run(otg_dev_A_srp, NULL, "dev_A_srp");
7141 return RET_SUCCESS;
7142 }
7143
7144 //OTG OPT
7145 static int t_u3h_otg_uut_A(int argc, char** argv){
7146 kthread_run(otg_opt_uut_a, NULL, "[OTG_H]opt_uut_A");
7147 return RET_SUCCESS;
7148 }
7149
7150 static int t_u3h_otg_uut_B(int argc, char** argv){
7151 kthread_run(otg_opt_uut_b, NULL, "[OTG_H]opt_uut_B");
7152 return RET_SUCCESS;
7153 }
7154
7155 static int t_u3h_otg_pet_uutA(int argc, char** argv){
7156 kthread_run(otg_pet_uut_a, NULL, "[OTG_H]pet_uut_A");
7157 return RET_SUCCESS;
7158 }
7159
7160 static int t_u3h_otg_pet_uutB(int argc, char** argv){
7161 kthread_run(otg_pet_uut_b, NULL, "[OTG_H]pet_uut_B");
7162 return RET_SUCCESS;
7163 }
7164
7165 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
7166 static struct xhci_container_ctx *mtk_xhci_alloc_container_ctx(struct xhci_hcd *xhci,
7167 int type, gfp_t flags)
7168 {
7169 struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
7170 if (!ctx)
7171 return NULL;
7172
7173 BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
7174 ctx->type = type;
7175 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
7176 if (type == XHCI_CTX_TYPE_INPUT)
7177 ctx->size += CTX_SIZE(xhci->hcc_params);
7178
7179 ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
7180 memset(ctx->bytes, 0, ctx->size);
7181 return ctx;
7182 }
7183
7184 static int dbg_reg_ewe(int argc, char** argv){
7185 struct xhci_hcd *xhci;
7186 u32 __iomem *addr;
7187 int temp;
7188 int ret;
7189
7190 xhci = hcd_to_xhci(my_hcd);
7191 g_mfindex_event = 0;
7192 temp = xhci_readl(xhci, &xhci->op_regs->command);
7193 temp |= CMD_EWE;
7194 xhci_writel(xhci, temp, &xhci->op_regs->command);
7195 msleep(3000);
7196 if(g_mfindex_event > 0){
7197 ret = RET_SUCCESS;
7198 }
7199 else{
7200 ret = RET_FAIL;
7201 }
7202 temp = xhci_readl(xhci, &xhci->op_regs->command);
7203 temp &= ~CMD_EWE;
7204 xhci_writel(xhci, temp, &xhci->op_regs->command);
7205 return ret;
7206 }
7207
7208 static int ct_check_hcd(){
7209 if(!my_hcd){
7210 if(f_test_lib_init()){
7211 mtk_test_dbg( "init host controller FAILED\n");
7212 return RET_FAIL;
7213 }
7214 }
7215 return RET_SUCCESS;
7216 }
7217
7218 static int u3ct_lecroy7061(){
7219 if(ct_check_hcd()){
7220 return RET_FAIL;
7221 }
7222 mtk_test_dbg( "STEP 1: enable port and slot, address device(BSR=1)...\n");
7223 if(f_enable_port(0)){
7224 mtk_test_dbg( "enable port FAILED!!\n");
7225 return RET_FAIL;
7226 }
7227 if(f_enable_slot(NULL)){
7228 mtk_test_dbg( "enable slot FAILED!!\n");
7229 return RET_FAIL;
7230 }
7231 if(f_address_slot(true, NULL)){
7232 mtk_test_dbg( "address device (BSR=1) FAILED!!\n");
7233 return RET_FAIL;
7234 }
7235 return RET_SUCCESS;
7236 }
7237
7238 static int u3ct_lecroy7062(){
7239 int ret;
7240 struct usb_device *udev, *rhdev;
7241 struct xhci_virt_device *virt_dev;
7242 struct xhci_hcd *xhci;
7243 struct urb *urb;
7244 struct usb_ctrlrequest *dr;
7245 struct usb_config_descriptor *desc;
7246 int i;
7247 char *tmp;
7248
7249 mtk_test_dbg( "STEP 2: get_descriptor, whether success or failed...\n");
7250 ret = 0;
7251 if(g_slot_id == 0){
7252 mtk_test_dbg( "[ERROR] slot ID not valid\n");
7253 return RET_FAIL;
7254 }
7255
7256 xhci = hcd_to_xhci(my_hcd);
7257 rhdev = my_hcd->self.root_hub;
7258 udev = rhdev->children[g_port_id-1];
7259
7260 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
7261 dr->bRequestType = USB_DIR_IN;
7262 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
7263 dr->wValue = cpu_to_le16((USB_DT_DEVICE << 8) + 0);
7264 dr->wIndex = cpu_to_le16(0);
7265 dr->wLength = cpu_to_le16(USB_DT_DEVICE_SIZE);
7266 desc = kmalloc(USB_DT_DEVICE_SIZE, GFP_KERNEL);
7267 memset(desc, 0, USB_DT_DEVICE_SIZE);
7268
7269 urb = alloc_ctrl_urb(dr, desc, udev);
7270 ret = f_ctrlrequest(urb, udev);
7271 if(urb->status == -EINPROGRESS){
7272 //timeout, stop endpoint, set TR dequeue pointer
7273 f_ring_stop_ep(g_slot_id, 0);
7274 f_ring_set_tr_dequeue_pointer(g_slot_id, 0, urb);
7275 }
7276 kfree(dr);
7277 kfree(desc);
7278 usb_free_urb(urb);
7279
7280 return ret;
7281 }
7282
7283 static int u3ct_lecroy718(){
7284 mtk_test_dbg( "Reset host controller\n");
7285 if(my_hcd){
7286 if(f_test_lib_cleanup()){
7287 mtk_test_dbg( "cleanup host controller FAILED\n");
7288 return RET_FAIL;
7289 }
7290 }
7291 if(f_test_lib_init()){
7292 mtk_test_dbg( "init host controller FAILED\n");
7293 return RET_FAIL;
7294 }
7295 mtk_test_dbg( "wait 1 sec\n");
7296 msleep(1000);
7297
7298 mtk_test_dbg( "enable port, slot, address (BSR=1)\n");
7299 if(f_enable_port(0)){
7300 mtk_test_dbg( "enable port FAILED!!\n");
7301 return RET_FAIL;
7302 }
7303 if(f_enable_slot(NULL)){
7304 mtk_test_dbg( "enable slot FAILED!!\n");
7305 return RET_FAIL;
7306 }
7307 if(f_address_slot(true, NULL)){
7308 mtk_test_dbg( "address device (BSR=1) FAILED!!\n");
7309 return RET_FAIL;
7310 }
7311
7312 mtk_test_dbg( "set u1 timeout value=127\n");
7313 if(f_power_set_u1u2(3, 127, 0)){
7314 mtk_test_dbg( "set u1 timeout FAILED!!\n");
7315 return RET_FAIL;
7316 }
7317
7318 return RET_SUCCESS;
7319 }
7320
7321 static int u3ct_lecroy719(){
7322 if(ct_check_hcd()){
7323 return RET_FAIL;
7324 }
7325 mtk_test_dbg( "direct set u1 timeout value=0, u2 timeout value=127\n");
7326 if(f_power_set_u1u2(3, 0, 127)){
7327 mtk_test_dbg( "set u1/u2 timeout FAILED!!\n");
7328 return RET_FAIL;
7329 }
7330
7331 return RET_SUCCESS;
7332 }
7333
7334 static int u3ct_lecroy720(){
7335 if(ct_check_hcd()){
7336 return RET_FAIL;
7337 }
7338 mtk_test_dbg( "STEP 1: enable port and slot, address device(BSR=1)...\n");
7339 if(f_enable_port(0)){
7340 mtk_test_dbg( "enable port FAILED!!\n");
7341 return RET_FAIL;
7342 }
7343 if(f_enable_slot(NULL)){
7344 mtk_test_dbg( "enable slot FAILED!!\n");
7345 return RET_FAIL;
7346 }
7347 if(f_address_slot(true, NULL)){
7348 mtk_test_dbg( "address device (BSR=1) FAILED!!\n");
7349 return RET_FAIL;
7350 }
7351 mtk_test_dbg( "set u1 timeout value=127\n");
7352 if(f_power_set_u1u2(3, 127, 0)){
7353 mtk_test_dbg( "set u1 timeout FAILED!!\n");
7354 return RET_FAIL;
7355 }
7356
7357 return RET_SUCCESS;
7358 }
7359
7360 static int u3ct_lecroy721(){
7361 if(ct_check_hcd()){
7362 return RET_FAIL;
7363 }
7364 mtk_test_dbg( "STEP 1: enable port and slot, address device(BSR=1)...\n");
7365 if(f_enable_port(0)){
7366 mtk_test_dbg( "enable port FAILED!!\n");
7367 return RET_FAIL;
7368 }
7369 if(f_enable_slot(NULL)){
7370 mtk_test_dbg( "enable slot FAILED!!\n");
7371 return RET_FAIL;
7372 }
7373 if(f_address_slot(true, NULL)){
7374 mtk_test_dbg( "address device (BSR=1) FAILED!!\n");
7375 return RET_FAIL;
7376 }
7377 mtk_test_dbg( "set u1 timeout value=127\n");
7378 if(f_power_set_u1u2(3, 127, 0)){
7379 mtk_test_dbg( "set u1 timeout FAILED!!\n");
7380 return RET_FAIL;
7381 }
7382
7383 return RET_SUCCESS;
7384 }
7385
7386 static int u3ct_lecroy729(){
7387 u32 __iomem *addr;
7388 int temp;
7389 int port_id;
7390 char isWarmReset;
7391 struct xhci_hcd *xhci;
7392
7393 mtk_test_dbg( "hot reset port...\n");
7394 port_id = g_port_id;
7395
7396 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
7397 temp = xhci_readl(xhci, addr);
7398 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
7399 temp = mtktest_xhci_port_state_to_neutral(temp);
7400 temp = (temp | PORT_RESET);
7401 xhci_writel(xhci, temp, addr);
7402 return RET_SUCCESS;
7403 }
7404
7405 static int u3ct_lecroy731(){
7406 u32 __iomem *addr;
7407 int temp;
7408 int port_id;
7409 char isWarmReset;
7410 struct xhci_hcd *xhci;
7411
7412 mtk_test_dbg( "hot reset port...\n");
7413 port_id = g_port_id;
7414 xhci = hcd_to_xhci(my_hcd);
7415
7416 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
7417 temp = xhci_readl(xhci, addr);
7418 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
7419 temp = mtktest_xhci_port_state_to_neutral(temp);
7420 temp = (temp | PORT_RESET);
7421 xhci_writel(xhci, temp, addr);
7422 return RET_SUCCESS;
7423 }
7424
7425 static int u3ct_lecroy7341(){
7426 mtk_test_dbg( "Reset host controller\n");
7427 if(my_hcd){
7428 if(f_test_lib_cleanup()){
7429 mtk_test_dbg( "cleanup host controller FAILED\n");
7430 return RET_FAIL;
7431 }
7432 }
7433 if(f_test_lib_init()){
7434 mtk_test_dbg( "init host controller FAILED\n");
7435 return RET_FAIL;
7436 }
7437 return RET_SUCCESS;
7438 }
7439
7440 static int u3ct_lecroy7342(){
7441 u32 __iomem *addr;
7442 int temp;
7443 int port_id;
7444 char isWarmReset;
7445 struct xhci_hcd *xhci;
7446
7447 mtk_test_dbg( "warm reset port\n");
7448 port_id = g_port_id;
7449 xhci = hcd_to_xhci(my_hcd);
7450
7451 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
7452 temp = xhci_readl(xhci, addr);
7453 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
7454 temp = mtktest_xhci_port_state_to_neutral(temp);
7455 temp = (temp | PORT_WR);
7456 xhci_writel(xhci, temp, addr);
7457 return RET_SUCCESS;
7458 }
7459
7460 static int u3ct_lecroy735(){
7461 u32 __iomem *addr;
7462 int temp;
7463 int port_id;
7464 struct xhci_hcd *xhci;
7465
7466 port_id = g_port_id;
7467 xhci = hcd_to_xhci(my_hcd);
7468
7469 mtk_test_dbg( "suspend port\n");
7470 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
7471 temp = xhci_readl(xhci, addr);
7472 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
7473 temp = mtktest_xhci_port_state_to_neutral(temp);
7474 temp = (temp & ~(0xf << 5));
7475 temp = (temp | (3 << 5) | PORT_LINK_STROBE);
7476 xhci_writel(xhci, temp, addr);
7477 mtk_xhci_handshake(xhci, addr, (15<<5), (3<<5), 30*1000);
7478 temp = xhci_readl(xhci, addr);
7479 if(PORT_PLS_VALUE(temp) != 3){
7480 xhci_err(xhci, "port not enter U3 state\n");
7481 return RET_FAIL;
7482 }
7483
7484 mtk_test_dbg( "delay 1 sec\n");
7485 msleep(1000);
7486 mtk_test_dbg( "warm reset port\n");
7487 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
7488 temp = xhci_readl(xhci, addr);
7489 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
7490 temp = mtktest_xhci_port_state_to_neutral(temp);
7491 temp = (temp | PORT_WR);
7492 xhci_writel(xhci, temp, addr);
7493 return RET_FAIL;
7494 }
7495
7496 static int u3ct_lecroy7361(){
7497 u32 __iomem *addr;
7498 int temp;
7499 int port_id;
7500 struct xhci_hcd *xhci;
7501
7502 port_id = g_port_id;
7503 xhci = hcd_to_xhci(my_hcd);
7504
7505 mtk_test_dbg( "suspend port\n");
7506 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
7507 temp = xhci_readl(xhci, addr);
7508 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
7509 temp = mtktest_xhci_port_state_to_neutral(temp);
7510 temp = (temp & ~(0xf << 5));
7511 temp = (temp | (3 << 5) | PORT_LINK_STROBE);
7512 xhci_writel(xhci, temp, addr);
7513 mtk_xhci_handshake(xhci, addr, (15<<5), (3<<5), 30*1000);
7514 temp = xhci_readl(xhci, addr);
7515 if(PORT_PLS_VALUE(temp) != 3){
7516 xhci_err(xhci, "port not enter U3 state\n");
7517 return RET_FAIL;
7518 }
7519 return RET_SUCCESS;
7520 }
7521
7522 static int u3ct_lecroy7362(){
7523 u32 __iomem *addr;
7524 int temp;
7525 int port_id;
7526 struct xhci_hcd *xhci;
7527 int i;
7528
7529 port_id = g_port_id;
7530 xhci = hcd_to_xhci(my_hcd);
7531
7532 mtk_test_dbg( "resume port\n");
7533 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
7534 temp = xhci_readl(xhci, addr);
7535 temp = mtktest_xhci_port_state_to_neutral(temp);
7536 temp = (temp & ~(0xf << 5));
7537 temp = (temp | PORT_LINK_STROBE);
7538 xhci_writel(xhci, temp, addr);
7539 for(i=0; i<200; i++){
7540 temp = xhci_readl(xhci, addr);
7541 if(PORT_PLS_VALUE(temp) == 0){
7542 break;
7543 }
7544 msleep(1);
7545
7546 }
7547 if(PORT_PLS_VALUE(temp) != 0){
7548 xhci_err(xhci, "port not return U0 state\n");
7549 return RET_FAIL;
7550 }
7551 return RET_SUCCESS;
7552 }
7553
7554
7555 static int dbg_u3ct_lecroy(int argc, char** argv){
7556 int td_no;
7557
7558 td_no = 0;
7559 if(argc > 1){
7560 td_no = (int)simple_strtol(argv[1], &argv[1], 10);
7561 }
7562 switch(td_no){
7563 case 706:
7564 mtk_test_dbg( "(7061) STEP 1, (7062) STEP 2\n");
7565 break;
7566 case 7061:
7567 return u3ct_lecroy7061();
7568 break;
7569 case 7062:
7570 return u3ct_lecroy7062();
7571 break;
7572 case 718:
7573 return u3ct_lecroy718();
7574 break;
7575 case 719:
7576 return u3ct_lecroy719();
7577 break;
7578 case 720:
7579 return u3ct_lecroy720();
7580 break;
7581 case 721:
7582 return u3ct_lecroy721();
7583 break;
7584 case 729:
7585 return u3ct_lecroy729();
7586 break;
7587 case 731:
7588 return u3ct_lecroy731();
7589 break;
7590 case 734:
7591 mtk_test_dbg( "(7341) STEP 1, (7342) STEP 2\n");
7592 break;
7593 case 7341:
7594 return u3ct_lecroy7341();
7595 break;
7596 case 7342:
7597 return u3ct_lecroy7342();
7598 break;
7599 case 735:
7600 return u3ct_lecroy735();
7601 break;
7602 case 736:
7603 mtk_test_dbg( "(7361) STEP 1, (7362) STEP 2\n");
7604 break;
7605 case 7361:
7606 return u3ct_lecroy7361();
7607 break;
7608 case 7362:
7609 return u3ct_lecroy7362();
7610 break;
7611 default:
7612 mtk_test_dbg( "enter td number\n");
7613 break;
7614 }
7615 }
7616
7617 static int u3ct_ellisys7061(){
7618 if(ct_check_hcd()){
7619 return RET_FAIL;
7620 }
7621 mtk_test_dbg( "STEP 1: enable port and slot, address device(BSR=1)...\n");
7622 if(f_enable_port(0)){
7623 mtk_test_dbg( "enable port FAILED!!\n");
7624 return RET_FAIL;
7625 }
7626 if(f_enable_slot(NULL)){
7627 mtk_test_dbg( "enable slot FAILED!!\n");
7628 return RET_FAIL;
7629 }
7630 if(f_address_slot(true, NULL)){
7631 mtk_test_dbg( "address device (BSR=1) FAILED!!\n");
7632 return RET_FAIL;
7633 }
7634 return RET_SUCCESS;
7635 }
7636
7637 static int u3ct_ellisys7062(){
7638 int ret;
7639 struct usb_device *udev, *rhdev;
7640 struct xhci_virt_device *virt_dev;
7641 struct xhci_hcd *xhci;
7642 struct urb *urb;
7643 struct usb_ctrlrequest *dr;
7644 struct usb_config_descriptor *desc;
7645 int i;
7646 char *tmp;
7647
7648 mtk_test_dbg( "STEP 2: get_descriptor, whether success or failed...\n");
7649 ret = 0;
7650 if(g_slot_id == 0){
7651 mtk_test_dbg( "[ERROR] slot ID not valid\n");
7652 return RET_FAIL;
7653 }
7654
7655 xhci = hcd_to_xhci(my_hcd);
7656 rhdev = my_hcd->self.root_hub;
7657 udev = rhdev->children[g_port_id-1];
7658
7659 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
7660 dr->bRequestType = USB_DIR_IN;
7661 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
7662 dr->wValue = cpu_to_le16((USB_DT_DEVICE << 8) + 0);
7663 dr->wIndex = cpu_to_le16(0);
7664 dr->wLength = cpu_to_le16(USB_DT_DEVICE_SIZE);
7665 desc = kmalloc(USB_DT_DEVICE_SIZE, GFP_KERNEL);
7666 memset(desc, 0, USB_DT_DEVICE_SIZE);
7667
7668 urb = alloc_ctrl_urb(dr, desc, udev);
7669 ret = f_ctrlrequest(urb, udev);
7670 if(urb->status == -EINPROGRESS){
7671 //timeout, stop endpoint, set TR dequeue pointer
7672 f_ring_stop_ep(g_slot_id, 0);
7673 f_ring_set_tr_dequeue_pointer(g_slot_id, 0, urb);
7674 }
7675 kfree(dr);
7676 kfree(desc);
7677 usb_free_urb(urb);
7678
7679 return ret;
7680 }
7681
7682 static int u3ct_ellisys718(){
7683 mtk_test_dbg( "Reset host controller\n");
7684 if(my_hcd){
7685 if(f_test_lib_cleanup()){
7686 mtk_test_dbg( "cleanup host controller FAILED\n");
7687 return RET_FAIL;
7688 }
7689 }
7690 if(f_test_lib_init()){
7691 mtk_test_dbg( "init host controller FAILED\n");
7692 return RET_FAIL;
7693 }
7694 mtk_test_dbg( "wait 1 sec\n");
7695 msleep(1000);
7696
7697 mtk_test_dbg( "enable port, slot, address (BSR=1)\n");
7698 if(f_enable_port(0)){
7699 mtk_test_dbg( "enable port FAILED!!\n");
7700 return RET_FAIL;
7701 }
7702 if(f_enable_slot(NULL)){
7703 mtk_test_dbg( "enable slot FAILED!!\n");
7704 return RET_FAIL;
7705 }
7706 if(f_address_slot(true, NULL)){
7707 mtk_test_dbg( "address device (BSR=1) FAILED!!\n");
7708 return RET_FAIL;
7709 }
7710
7711 mtk_test_dbg( "set u1 timeout value=127\n");
7712 if(f_power_set_u1u2(3, 127, 0)){
7713 mtk_test_dbg( "set u1 timeout FAILED!!\n");
7714 return RET_FAIL;
7715 }
7716
7717 return RET_SUCCESS;
7718 }
7719
7720 static int u3ct_ellisys719(){
7721 mtk_test_dbg( "direct set u1 timeout value=0, u2 timeout value=127\n");
7722 if(f_power_set_u1u2(3, 0, 127)){
7723 mtk_test_dbg( "set u1/u2 timeout FAILED!!\n");
7724 return RET_FAIL;
7725 }
7726
7727 return RET_SUCCESS;
7728 }
7729
7730 static int u3ct_ellisys720(){
7731 if(ct_check_hcd()){
7732 return RET_FAIL;
7733 }
7734 mtk_test_dbg( "STEP 1: enable port and slot, address device(BSR=1)...\n");
7735 if(f_enable_port(0)){
7736 mtk_test_dbg( "enable port FAILED!!\n");
7737 return RET_FAIL;
7738 }
7739 if(f_enable_slot(NULL)){
7740 mtk_test_dbg( "enable slot FAILED!!\n");
7741 return RET_FAIL;
7742 }
7743 if(f_address_slot(true, NULL)){
7744 mtk_test_dbg( "address device (BSR=1) FAILED!!\n");
7745 return RET_FAIL;
7746 }
7747 mtk_test_dbg( "set u1 timeout value=127\n");
7748 if(f_power_set_u1u2(3, 127, 0)){
7749 mtk_test_dbg( "set u1 timeout FAILED!!\n");
7750 return RET_FAIL;
7751 }
7752
7753 return RET_SUCCESS;
7754 }
7755
7756 static int u3ct_ellisys721(){
7757 if(ct_check_hcd()){
7758 return RET_FAIL;
7759 }
7760 mtk_test_dbg( "STEP 1: enable port and slot, address device(BSR=1)...\n");
7761 if(f_enable_port(0)){
7762 mtk_test_dbg( "enable port FAILED!!\n");
7763 return RET_FAIL;
7764 }
7765 if(f_enable_slot(NULL)){
7766 mtk_test_dbg( "enable slot FAILED!!\n");
7767 return RET_FAIL;
7768 }
7769 if(f_address_slot(true, NULL)){
7770 mtk_test_dbg( "address device (BSR=1) FAILED!!\n");
7771 return RET_FAIL;
7772 }
7773 mtk_test_dbg( "set u1 timeout value=127\n");
7774 if(f_power_set_u1u2(3, 127, 0)){
7775 mtk_test_dbg( "set u1 timeout FAILED!!\n");
7776 return RET_FAIL;
7777 }
7778
7779 return RET_SUCCESS;
7780 }
7781
7782 static int u3ct_ellisys729(){
7783 u32 __iomem *addr;
7784 int temp;
7785 int port_id;
7786 char isWarmReset;
7787 struct xhci_hcd *xhci;
7788
7789 mtk_test_dbg( "hot reset port...\n");
7790 port_id = g_port_id;
7791
7792 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
7793 temp = xhci_readl(xhci, addr);
7794 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
7795 temp = mtktest_xhci_port_state_to_neutral(temp);
7796 temp = (temp | PORT_RESET);
7797 xhci_writel(xhci, temp, addr);
7798 return RET_SUCCESS;
7799 }
7800
7801 static int u3ct_ellisys731(){
7802 u32 __iomem *addr;
7803 int temp;
7804 int port_id;
7805 char isWarmReset;
7806 struct xhci_hcd *xhci;
7807
7808 mtk_test_dbg( "hot reset port...\n");
7809 port_id = g_port_id;
7810 xhci = hcd_to_xhci(my_hcd);
7811
7812 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
7813 temp = xhci_readl(xhci, addr);
7814 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
7815 temp = mtktest_xhci_port_state_to_neutral(temp);
7816 temp = (temp | PORT_RESET);
7817 xhci_writel(xhci, temp, addr);
7818 return RET_SUCCESS;
7819 }
7820
7821 static int u3ct_ellisys7341(){
7822 mtk_test_dbg( "Reset host controller\n");
7823 if(my_hcd){
7824 if(f_test_lib_cleanup()){
7825 mtk_test_dbg( "cleanup host controller FAILED\n");
7826 return RET_FAIL;
7827 }
7828 }
7829 if(f_test_lib_init()){
7830 mtk_test_dbg( "init host controller FAILED\n");
7831 return RET_FAIL;
7832 }
7833 return RET_SUCCESS;
7834 }
7835
7836 static int u3ct_ellisys7342(){
7837 u32 __iomem *addr;
7838 int temp;
7839 int port_id;
7840 char isWarmReset;
7841 struct xhci_hcd *xhci;
7842
7843 mtk_test_dbg( "warm reset port\n");
7844 port_id = g_port_id;
7845 xhci = hcd_to_xhci(my_hcd);
7846
7847 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
7848 temp = xhci_readl(xhci, addr);
7849 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
7850 temp = mtktest_xhci_port_state_to_neutral(temp);
7851 temp = (temp | PORT_WR);
7852 xhci_writel(xhci, temp, addr);
7853 return RET_SUCCESS;
7854 }
7855
7856 static int u3ct_ellisys735(){
7857 u32 __iomem *addr;
7858 int temp;
7859 int port_id;
7860 struct xhci_hcd *xhci;
7861
7862 port_id = g_port_id;
7863 xhci = hcd_to_xhci(my_hcd);
7864
7865 mtk_test_dbg( "suspend port\n");
7866 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
7867 temp = xhci_readl(xhci, addr);
7868 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
7869 temp = mtktest_xhci_port_state_to_neutral(temp);
7870 temp = (temp & ~(0xf << 5));
7871 temp = (temp | (3 << 5) | PORT_LINK_STROBE);
7872 xhci_writel(xhci, temp, addr);
7873 mtk_xhci_handshake(xhci, addr, (15<<5), (3<<5), 30*1000);
7874 temp = xhci_readl(xhci, addr);
7875 if(PORT_PLS_VALUE(temp) != 3){
7876 xhci_err(xhci, "port not enter U3 state\n");
7877 return RET_FAIL;
7878 }
7879
7880 mtk_test_dbg( "delay 1 sec\n");
7881 msleep(1000);
7882 mtk_test_dbg( "warm reset port\n");
7883 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
7884 temp = xhci_readl(xhci, addr);
7885 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
7886 temp = mtktest_xhci_port_state_to_neutral(temp);
7887 temp = (temp | PORT_WR);
7888 xhci_writel(xhci, temp, addr);
7889 return RET_FAIL;
7890 }
7891
7892 static int u3ct_ellisys7361(){
7893 int ret;
7894 struct device *dev;
7895 struct usb_device *udev, *rhdev;
7896 struct xhci_virt_device *virt_dev;
7897 struct xhci_hcd *xhci;
7898 struct urb *urb;
7899 struct usb_ctrlrequest *dr;
7900 struct usb_config_descriptor *desc;
7901 int i,j;
7902 char *tmp;
7903 struct urb *urb_rx;
7904 struct usb_host_endpoint *ep_rx;
7905 int ep_index_rx;
7906 void *buffer_rx;
7907 char *buffer;
7908 ret = 0;
7909
7910 mtk_test_dbg( "Reset host controller\n");
7911 if(my_hcd){
7912 if(f_test_lib_cleanup()){
7913 mtk_test_dbg( "cleanup host controller FAILED\n");
7914 return RET_FAIL;
7915 }
7916 }
7917 if(u3auto_hcd_reset() != RET_SUCCESS){
7918 mtk_test_dbg( "init host controller, enable slot, address dev FAILED\n");
7919 return RET_FAIL;
7920 }
7921 xhci = hcd_to_xhci(my_hcd);
7922 rhdev = my_hcd->self.root_hub;
7923 udev = rhdev->children[g_port_id-1];
7924 dev = xhci_to_hcd(xhci)->self.controller;//dma stream buffer
7925 xhci_dbg(xhci, "device speed %d\n", udev->speed);
7926 //get descriptor (device)
7927 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
7928 dr->bRequestType = USB_DIR_IN;
7929 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
7930 dr->wValue = cpu_to_le16((USB_DT_DEVICE << 8) + 0);
7931 dr->wIndex = cpu_to_le16(0);
7932 dr->wLength = cpu_to_le16(8);
7933 desc = kmalloc(8, GFP_KERNEL);
7934 memset(desc, 0, 8);
7935 urb = alloc_ctrl_urb(dr, desc, udev);
7936 ret = f_ctrlrequest(urb, udev);
7937 kfree(dr);
7938 kfree(desc);
7939 usb_free_urb(urb);
7940 //get descriptor (device)
7941 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
7942 dr->bRequestType = USB_DIR_IN;
7943 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
7944 dr->wValue = cpu_to_le16((USB_DT_DEVICE << 8) + 0);
7945 dr->wIndex = cpu_to_le16(0);
7946 dr->wLength = cpu_to_le16(USB_DT_DEVICE_SIZE);
7947 desc = kmalloc(USB_DT_DEVICE_SIZE, GFP_KERNEL);
7948 memset(desc, 0, USB_DT_DEVICE_SIZE);
7949 urb = alloc_ctrl_urb(dr, desc, udev);
7950 ret = f_ctrlrequest(urb, udev);
7951 kfree(dr);
7952 kfree(desc);
7953 usb_free_urb(urb);
7954 //get descriptor (configure)
7955 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
7956 dr->bRequestType = USB_DIR_IN;
7957 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
7958 dr->wValue = cpu_to_le16((USB_DT_CONFIG << 8) + 0);
7959 dr->wIndex = cpu_to_le16(0);
7960 dr->wLength = cpu_to_le16(USB_DT_CONFIG_SIZE);
7961 desc = kmalloc(USB_DT_CONFIG_SIZE, GFP_KERNEL);
7962 memset(desc, 0, USB_DT_CONFIG_SIZE);
7963 urb = alloc_ctrl_urb(dr, desc, udev);
7964 ret = f_ctrlrequest(urb, udev);
7965 kfree(dr);
7966 kfree(desc);
7967 usb_free_urb(urb);
7968 //get descriptor (configure)
7969 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
7970 dr->bRequestType = USB_DIR_IN;
7971 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
7972 dr->wValue = cpu_to_le16((USB_DT_CONFIG << 8) + 0);
7973 dr->wIndex = cpu_to_le16(0);
7974 dr->wLength = cpu_to_le16(40);
7975 desc = kmalloc(40, GFP_KERNEL);
7976 memset(desc, 0, 40);
7977 urb = alloc_ctrl_urb(dr, desc, udev);
7978 ret = f_ctrlrequest(urb, udev);
7979 kfree(dr);
7980 kfree(desc);
7981 usb_free_urb(urb);
7982 //set configuration
7983 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
7984 dr->bRequestType = USB_DIR_OUT;
7985 dr->bRequest = USB_REQ_SET_CONFIGURATION;
7986 dr->wValue = cpu_to_le16(1);
7987 dr->wIndex = cpu_to_le16(0);
7988 dr->wLength = cpu_to_le16(0);
7989 urb = alloc_ctrl_urb(dr, NULL, udev);
7990 ret = f_ctrlrequest(urb,udev);
7991 kfree(dr);
7992 usb_free_urb(urb);
7993 //set idle
7994 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
7995 dr->bRequestType = USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE;
7996 dr->bRequest = 0x0A;
7997 dr->wValue = cpu_to_le16(0);
7998 dr->wIndex = cpu_to_le16(0);
7999 dr->wLength = cpu_to_le16(0);
8000 urb = alloc_ctrl_urb(dr, NULL, udev);
8001 ret = f_ctrlrequest(urb,udev);
8002 kfree(dr);
8003 usb_free_urb(urb);
8004 //get descriptor (HID report)
8005 ret = f_config_ep(1, EPADD_IN, EPATT_INT, 4, 7,0,0, udev, 1);
8006 //interrupt input
8007 ep_rx = udev->ep_in[1];
8008 ep_index_rx = mtktest_xhci_get_endpoint_index(&ep_rx->desc);
8009 xhci_err(xhci, "[INPUT]\n");
8010 for(i=0; i<10; i++){
8011 urb_rx = usb_alloc_urb(0, GFP_KERNEL);
8012 ret = f_fill_urb(urb_rx,1,4,0,EPADD_IN, 0, 4, udev);
8013 if(ret){
8014 xhci_err(xhci, "[ERROR]fill rx urb Error!!\n");
8015 return RET_FAIL;
8016 }
8017 urb_rx->transfer_flags &= ~URB_ZERO_PACKET;
8018 ret = f_queue_urb(urb_rx,1,udev);
8019 if(ret){
8020 xhci_err(xhci, "[ERROR]rx urb transfer failed!!\n");
8021 return RET_FAIL;
8022 }
8023 dma_sync_single_for_cpu(dev,urb_rx->transfer_dma, 4,DMA_BIDIRECTIONAL);
8024 for(j=0; j<urb_rx->transfer_buffer_length; j++){
8025 tmp = urb_rx->transfer_buffer+i;
8026 //xhci_err(xhci, "%x ", *tmp);
8027 }
8028 //xhci_err(xhci, "\n");
8029 usb_free_urb(urb_rx);
8030 }
8031
8032 return ret;
8033 }
8034
8035 static int u3ct_ellisys7362(){
8036 u32 __iomem *addr;
8037 int temp;
8038 int port_id;
8039 struct xhci_hcd *xhci;
8040
8041 port_id = g_port_id;
8042 xhci = hcd_to_xhci(my_hcd);
8043
8044 mtk_test_dbg( "suspend port\n");
8045 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8046 temp = xhci_readl(xhci, addr);
8047 xhci_dbg(xhci, "before reset port %d = 0x%x\n", port_id-1, temp);
8048 temp = mtktest_xhci_port_state_to_neutral(temp);
8049 temp = (temp & ~(0xf << 5));
8050 temp = (temp | (3 << 5) | PORT_LINK_STROBE);
8051 xhci_writel(xhci, temp, addr);
8052 mtk_xhci_handshake(xhci, addr, (15<<5), (3<<5), 30*1000);
8053 temp = xhci_readl(xhci, addr);
8054 if(PORT_PLS_VALUE(temp) != 3){
8055 xhci_err(xhci, "port not enter U3 state\n");
8056 return RET_FAIL;
8057 }
8058 return RET_SUCCESS;
8059 }
8060
8061 static int u3ct_ellisys7363(){
8062 u32 __iomem *addr;
8063 int temp;
8064 int port_id;
8065 struct xhci_hcd *xhci;
8066 int i;
8067
8068 port_id = g_port_id;
8069 xhci = hcd_to_xhci(my_hcd);
8070
8071 mtk_test_dbg( "resume port\n");
8072 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8073 temp = xhci_readl(xhci, addr);
8074 temp = mtktest_xhci_port_state_to_neutral(temp);
8075 temp = (temp & ~(0xf << 5));
8076 temp = (temp | PORT_LINK_STROBE);
8077 xhci_writel(xhci, temp, addr);
8078 for(i=0; i<200; i++){
8079 temp = xhci_readl(xhci, addr);
8080 if(PORT_PLS_VALUE(temp) == 0){
8081 break;
8082 }
8083 msleep(1);
8084
8085 }
8086 if(PORT_PLS_VALUE(temp) != 0){
8087 xhci_err(xhci, "port not return U0 state\n");
8088 return RET_FAIL;
8089 }
8090 return RET_SUCCESS;
8091 }
8092
8093
8094 static int dbg_u3ct_ellisys(int argc, char** argv){
8095 int td_no;
8096
8097 td_no = 0;
8098 if(argc > 1){
8099 td_no = (int)simple_strtol(argv[1], &argv[1], 10);
8100 }
8101 switch(td_no){
8102 case 706:
8103 mtk_test_dbg( "(7061) STEP 1, (7062) STEP 2\n");
8104 break;
8105 case 7061:
8106 return u3ct_ellisys7061();
8107 break;
8108 case 7062:
8109 return u3ct_ellisys7062();
8110 break;
8111 case 718:
8112 return u3ct_ellisys718();
8113 break;
8114 case 719:
8115 return u3ct_ellisys719();
8116 break;
8117 case 720:
8118 return u3ct_ellisys720();
8119 break;
8120 case 721:
8121 return u3ct_ellisys721();
8122 break;
8123 case 729:
8124 return u3ct_ellisys729();
8125 break;
8126 case 731:
8127 return u3ct_ellisys731();
8128 break;
8129 case 734:
8130 mtk_test_dbg( "(7341) STEP 1, (7342) STEP 2\n");
8131 break;
8132 case 7341:
8133 return u3ct_ellisys7341();
8134 break;
8135 case 7342:
8136 return u3ct_ellisys7342();
8137 break;
8138 case 735:
8139 return u3ct_ellisys735();
8140 break;
8141 case 736:
8142 mtk_test_dbg( "(7361) STEP 1, (7362) STEP 2, (7363) STEP 3\n");
8143 break;
8144 case 7361:
8145 return u3ct_ellisys7361();
8146 break;
8147 case 7362:
8148 return u3ct_ellisys7362();
8149 break;
8150 case 7363:
8151 return u3ct_ellisys7363();
8152 break;
8153 default:
8154 mtk_test_dbg( "enter td number\n");
8155 break;
8156 }
8157 }
8158
8159 static int u2ct_signal_quality(){
8160 u32 __iomem *addr;
8161 struct xhci_hcd *xhci;
8162 u32 temp, port_id;
8163 int test_value;
8164
8165
8166 //initial host controller
8167 if(ct_check_hcd()){
8168 return RET_FAIL;
8169 }
8170 xhci = hcd_to_xhci(my_hcd);
8171 //turn off port power
8172 g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
8173 port_id = g_num_u3_port+1;
8174 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8175 temp = xhci_readl(xhci, addr);
8176 temp = mtktest_xhci_port_state_to_neutral(temp);
8177 temp &= ~PORT_POWER;
8178 xhci_writel(xhci, temp, addr);
8179
8180 mtk_test_dbg( "issue test packet\n");
8181 //test mode - test packet
8182 test_value = 4;
8183 addr = &xhci->op_regs->port_power_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8184 temp = xhci_readl(xhci, addr);
8185 temp &= ~(0xf<<28);
8186 temp |= (test_value<<28);
8187 xhci_writel(xhci, temp, addr);
8188 return RET_SUCCESS;
8189 }
8190
8191 static int u2ct_packet_parameter_init(){
8192
8193 mtk_test_dbg( "Reset host controller\n");
8194 if(my_hcd){
8195 if(f_test_lib_cleanup()){
8196 mtk_test_dbg( "cleanup host controller FAILED\n");
8197 return RET_FAIL;
8198 }
8199 }
8200 if(f_test_lib_init()){
8201 mtk_test_dbg( "init host controller FAILED\n");
8202 return RET_FAIL;
8203 }
8204 mtk_test_dbg( "STEP 1: enable port and slot, address device(BSR=1)...\n");
8205 if(f_enable_port(0)){
8206 mtk_test_dbg( "enable port FAILED!!\n");
8207 return RET_FAIL;
8208 }
8209 if(f_enable_slot(NULL)){
8210 mtk_test_dbg( "enable slot FAILED!!\n");
8211 return RET_FAIL;
8212 }
8213 if(f_address_slot(false, NULL)){
8214 mtk_test_dbg( "address device (BSR=1) FAILED!!\n");
8215 return RET_FAIL;
8216 }
8217 }
8218
8219 static int u2ct_packet_parameter_getdesc(){
8220 int ret;
8221 struct usb_device *udev, *rhdev;
8222 struct xhci_virt_device *virt_dev;
8223 struct xhci_hcd *xhci;
8224 struct urb *urb;
8225 struct usb_ctrlrequest *dr;
8226 struct usb_config_descriptor *desc;
8227 int i;
8228 char *tmp;
8229 ret = 0;
8230
8231 if(g_slot_id == 0){
8232 mtk_test_dbg( "[ERROR] slot ID not valid\n");
8233 return RET_FAIL;
8234 }
8235
8236 xhci = hcd_to_xhci(my_hcd);
8237 rhdev = my_hcd->self.root_hub;
8238 udev = rhdev->children[g_port_id-1];
8239
8240 dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
8241 dr->bRequestType = USB_DIR_IN;
8242 dr->bRequest = USB_REQ_GET_DESCRIPTOR;
8243 dr->wValue = cpu_to_le16((USB_DT_DEVICE << 8) + 0);
8244 dr->wIndex = cpu_to_le16(0);
8245 dr->wLength = cpu_to_le16(USB_DT_DEVICE_SIZE);
8246 desc = kmalloc(USB_DT_DEVICE_SIZE, GFP_KERNEL);
8247 memset(desc, 0, USB_DT_DEVICE_SIZE);
8248
8249 urb = alloc_ctrl_urb(dr, desc, udev);
8250 ret = f_ctrlrequest(urb, udev);
8251 if(urb->status == -EINPROGRESS){
8252 //timeout, stop endpoint, set TR dequeue pointer
8253 f_ring_stop_ep(g_slot_id, 0);
8254 f_ring_set_tr_dequeue_pointer(g_slot_id, 0, urb);
8255 }
8256 kfree(dr);
8257 kfree(desc);
8258 usb_free_urb(urb);
8259
8260 return ret;
8261 }
8262
8263 static int u2ct_disconnect_detect(){
8264 u32 __iomem *addr;
8265 struct xhci_hcd *xhci;
8266 u32 temp, port_id;
8267 int test_value;
8268
8269 mtk_test_dbg( "Reset host controller\n");
8270 if(my_hcd){
8271 if(f_test_lib_cleanup()){
8272 mtk_test_dbg( "cleanup host controller FAILED\n");
8273 return RET_FAIL;
8274 }
8275 }
8276 if(f_test_lib_init()){
8277 mtk_test_dbg( "init host controller FAILED\n");
8278 return RET_FAIL;
8279 }
8280 //turn off power
8281 xhci = hcd_to_xhci(my_hcd);
8282 //turn off port power
8283 g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
8284 port_id = g_num_u3_port+1;
8285 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8286 temp = xhci_readl(xhci, addr);
8287 temp = mtktest_xhci_port_state_to_neutral(temp);
8288 temp &= ~PORT_POWER;
8289 xhci_writel(xhci, temp, addr);
8290 //let SW doesn't do reset after get discon/conn events
8291 g_hs_block_reset = true;
8292 g_port_connect = false;
8293 mb() ;
8294 printk(KERN_ERR "[OTG_H] u2ct_disconnect_detect, g_port_connect is %d\n", g_port_connect);
8295
8296 //test mode - force enable
8297 test_value = 5;
8298 addr = &xhci->op_regs->port_power_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8299 temp = xhci_readl(xhci, addr);
8300 temp &= ~(0xf<<28);
8301 temp |= (test_value<<28);
8302 xhci_writel(xhci, temp, addr);
8303 mtk_test_dbg( "Please connect device in 30 secs\n");
8304 //waiting for conn event
8305 wait_event_on_timeout(&g_port_connect, true, TRANS_TIMEOUT);
8306 if(!g_port_connect){
8307 mtk_test_dbg( "Port not connected\n");
8308 g_hs_block_reset = false;
8309 return RET_FAIL;
8310 }
8311 mtk_test_dbg( "Device connected\n");
8312 mtk_test_dbg( "Please disconnect device in 30 secs\n");
8313 //waiting for discon event
8314 wait_event_on_timeout(&g_port_connect, false, TRANS_TIMEOUT);
8315 if(g_port_connect){
8316 mtk_test_dbg( "Port not disconnected\n");
8317 g_hs_block_reset = false;
8318 return RET_FAIL;
8319 }
8320 mtk_test_dbg( "Device disconnected\n");
8321 g_hs_block_reset = false;
8322 return RET_SUCCESS;
8323 }
8324
8325 static int u2ct_chirp_timing(){
8326 mtk_test_dbg( "Reset host controller\n");
8327 if(my_hcd){
8328 if(f_test_lib_cleanup()){
8329 mtk_test_dbg( "cleanup host controller FAILED\n");
8330 return RET_FAIL;
8331 }
8332 }
8333 if(f_test_lib_init()){
8334 mtk_test_dbg( "init host controller FAILED\n");
8335 return RET_FAIL;
8336 }
8337 return RET_SUCCESS;
8338 }
8339
8340 static int u2ct_suspend_resume_timing_init(){
8341 mtk_test_dbg( "Reset host controller\n");
8342 if(my_hcd){
8343 if(f_test_lib_cleanup()){
8344 mtk_test_dbg( "cleanup host controller FAILED\n");
8345 return RET_FAIL;
8346 }
8347 }
8348 if(f_test_lib_init()){
8349 mtk_test_dbg( "init host controller FAILED\n");
8350 return RET_FAIL;
8351 }
8352 return RET_SUCCESS;
8353 }
8354
8355 static int u2ct_suspend_resume_timing_suspend(){
8356 return f_power_suspend();
8357 }
8358
8359 static int u2ct_suspend_resume_timing_resume(){
8360 return f_power_resume();
8361 }
8362
8363 static int u2ct_j(){
8364 u32 __iomem *addr;
8365 struct xhci_hcd *xhci;
8366 u32 temp, port_id;
8367 int test_value;
8368
8369 if(ct_check_hcd()){
8370 return RET_FAIL;
8371 }
8372 xhci = hcd_to_xhci(my_hcd);
8373 //turn off port power
8374 g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
8375 port_id = g_num_u3_port+1;
8376 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8377 temp = xhci_readl(xhci, addr);
8378 temp = mtktest_xhci_port_state_to_neutral(temp);
8379 temp &= ~PORT_POWER;
8380 xhci_writel(xhci, temp, addr);
8381 //test mode - test j
8382 test_value = 1;
8383 addr = &xhci->op_regs->port_power_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8384 temp = xhci_readl(xhci, addr);
8385 temp &= ~(0xf<<28);
8386 temp |= (test_value<<28);
8387 xhci_writel(xhci, temp, addr);
8388
8389 return RET_SUCCESS;
8390 }
8391
8392 static int u2ct_k(){
8393 u32 __iomem *addr;
8394 struct xhci_hcd *xhci;
8395 u32 temp, port_id;
8396 int test_value;
8397
8398 if(ct_check_hcd()){
8399 return RET_FAIL;
8400 }
8401
8402 xhci = hcd_to_xhci(my_hcd);
8403 //turn off port power
8404 g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
8405 port_id = g_num_u3_port+1;
8406 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8407 temp = xhci_readl(xhci, addr);
8408 temp = mtktest_xhci_port_state_to_neutral(temp);
8409 temp &= ~PORT_POWER;
8410 xhci_writel(xhci, temp, addr);
8411 //test mode - test k
8412 test_value = 2;
8413 addr = &xhci->op_regs->port_power_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8414 temp = xhci_readl(xhci, addr);
8415 temp &= ~(0xf<<28);
8416 temp |= (test_value<<28);
8417 xhci_writel(xhci, temp, addr);
8418
8419 return RET_SUCCESS;
8420 }
8421
8422 static int u2ct_se0_nak(){
8423 u32 __iomem *addr;
8424 struct xhci_hcd *xhci;
8425 u32 temp, port_id;
8426 int test_value;
8427
8428 if(ct_check_hcd()){
8429 return RET_FAIL;
8430 }
8431
8432 xhci = hcd_to_xhci(my_hcd);
8433 //turn off port power
8434 g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
8435 port_id = g_num_u3_port+1;
8436 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8437 temp = xhci_readl(xhci, addr);
8438 temp = mtktest_xhci_port_state_to_neutral(temp);
8439 temp &= ~PORT_POWER;
8440 xhci_writel(xhci, temp, addr);
8441 //test mode - test k
8442 test_value = 3;
8443 addr = &xhci->op_regs->port_power_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8444 temp = xhci_readl(xhci, addr);
8445 temp &= ~(0xf<<28);
8446 temp |= (test_value<<28);
8447 xhci_writel(xhci, temp, addr);
8448
8449 return RET_SUCCESS;
8450 }
8451
8452 static int dbg_u2ct(int argc, char** argv){
8453 int td_no;
8454
8455 td_no = 0;
8456 if(argc > 1){
8457 td_no = (int)simple_strtol(argv[1], &argv[1], 10);
8458 }
8459 switch(td_no){
8460 case 6: case 3: case 7:
8461 return u2ct_signal_quality();
8462 break;
8463 case 21: case 25: case 23: case 22: case 55:
8464 mtk_test_dbg( "(211, 251, 231, 221, 551) STEP 1, (212, 252, 232, 222, 552) STEP 2, (213, 253, 233, 223, 553) STEP 3\n");
8465 break;
8466 case 211: case 251: case 231: case 221: case 551:
8467 return u2ct_packet_parameter_init();
8468 break;
8469 case 212: case 213: case 252: case 253: case 232: case 233: case 222: case 223: case 552: case 553:
8470 return u2ct_packet_parameter_getdesc();
8471 break;
8472 case 37: case 36:
8473 return u2ct_disconnect_detect();
8474 break;
8475 case 33: case 34: case 35:
8476 return u2ct_chirp_timing();
8477 break;
8478 case 39: case 41:
8479 mtk_test_dbg( "(391,411) STEP 1, (392, 412) STEP 2, (393, 413) STEP 3\n");
8480 break;
8481 case 391: case 411:
8482 return u2ct_suspend_resume_timing_init();
8483 break;
8484 case 392: case 412:
8485 return u2ct_suspend_resume_timing_suspend();
8486 break;
8487 case 393: case 413:
8488 return u2ct_suspend_resume_timing_resume();
8489 break;
8490 case 8:
8491 mtk_test_dbg( "(81) J test (82) K test\n");
8492 break;
8493 case 81:
8494 return u2ct_j();
8495 break;
8496 case 82:
8497 return u2ct_k();
8498 break;
8499 case 9:
8500 return u2ct_se0_nak();
8501 break;
8502 default:
8503 mtk_test_dbg( "please enter EL number\n");
8504 break;
8505 }
8506 }
8507
8508 #define EP_SPEED_SS 1
8509 #define EP_SPEED_HS 2
8510 #define EP_SPEED_FS 3
8511 #define EP_SPEED_LS 4
8512 #define EP_SPEED_RANDOM 0
8513 #define EP_OUT 1
8514 #define EP_IN 0
8515
8516 #define MAX_EPNUM 100
8517
8518 static int dbg_sch_algorithm(int argc, char** argv){
8519 struct xhci_hcd *xhci;
8520 struct usb_device *udev_ss, *udev_hs, *udev_fs, *udev_ls, *rhdev, *udev;
8521 int test_speed, cur_speed;
8522 struct usb_host_endpoint *ep;
8523 struct xhci_ep_ctx *ep_ctx;
8524 char is_continue, ep_boundary, ep_num;
8525 int ep_dir, transfer_type, maxp, bInterval, mult, burst;
8526 int ret;
8527 int ep_index, i;
8528 struct usb_host_endpoint *ep_list[MAX_EPNUM];
8529 struct xhci_virt_device *virt_dev;
8530 struct xhci_slot_ctx *slot_ctx;
8531 int interval;
8532 int isTT;
8533 struct sch_ep *sch_ep;
8534 test_speed = EP_SPEED_HS;
8535 ep_boundary = 30;
8536
8537 if(argc > 1){
8538 //0: all(except for ss), 1: ss, 2: hs, 3: fs, 4: ls
8539 test_speed = (int)simple_strtol(argv[1], &argv[1], 10);
8540 mtk_test_dbg( "Test speed %d\n", test_speed);
8541 }
8542 if(argc > 2){
8543 ep_boundary = (int)simple_strtol(argv[2], &argv[2], 10);
8544 mtk_test_dbg( "Try %d EPs\n", ep_boundary);
8545 if(ep_boundary > MAX_EPNUM){
8546 mtk_test_dbg( "EP num too much!!\n");
8547 return RET_FAIL;
8548 }
8549 }
8550
8551 xhci = hcd_to_xhci(my_hcd);
8552 //create 4 device, ss, hs, fs(tt), ls(tt)
8553 rhdev = my_hcd->self.root_hub;
8554 //ss
8555 udev_ss = mtk_usb_alloc_dev(rhdev, rhdev->bus, 1);
8556 udev_ss->speed = USB_SPEED_SUPER;
8557 udev_ss->level = rhdev->level + 1;
8558 udev_ss->slot_id = 1;
8559 mtktest_xhci_alloc_virt_device(xhci, 1, udev_ss, GFP_KERNEL);
8560 //hs
8561 udev_hs = mtk_usb_alloc_dev(rhdev, rhdev->bus, 2);
8562 udev_hs->speed = USB_SPEED_HIGH;
8563 udev_hs->level = rhdev->level + 1;
8564 udev_hs->slot_id = 2;
8565 mtktest_xhci_alloc_virt_device(xhci, 2, udev_hs, GFP_KERNEL);
8566 //fs
8567 udev_fs = mtk_usb_alloc_dev(rhdev, udev_hs->bus, 1);
8568 udev_fs->speed = USB_SPEED_FULL;
8569 udev_fs->level = udev_hs->level + 1;
8570 udev_fs->tt = kzalloc(sizeof(struct usb_tt), GFP_KERNEL);
8571 udev_fs->tt->hub = udev_hs;
8572 udev_fs->tt->multi = false;
8573 udev_fs->tt->think_time = 0;
8574 udev_fs->ttport = 1;
8575 udev_fs->slot_id = 3;
8576 mtktest_xhci_alloc_virt_device(xhci, 3, udev_fs, GFP_KERNEL);
8577 virt_dev = xhci->devs[3];
8578 slot_ctx = mtktest_xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
8579 slot_ctx->tt_info = 0x1;
8580 //ls
8581 udev_ls = mtk_usb_alloc_dev(rhdev, udev_hs->bus, 2);
8582 udev_ls->speed = USB_SPEED_LOW;
8583 udev_ls->level = udev_hs->level + 1;
8584 udev_ls->tt = kzalloc(sizeof(struct usb_tt), GFP_KERNEL);
8585 udev_ls->tt->hub = udev_hs;
8586 udev_ls->tt->multi = false;
8587 udev_ls->tt->think_time = 0;
8588 udev_ls->ttport = 2;
8589 udev_ls->slot_id = 4;
8590 mtktest_xhci_alloc_virt_device(xhci, 4, udev_ls, GFP_KERNEL);
8591 virt_dev = xhci->devs[4];
8592 slot_ctx = mtktest_xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
8593 slot_ctx->tt_info = 0x1;
8594 //1.random add ep (speed(fix or random), iso or intr, maxp, interrupt, mult, burst)
8595 //2.record this EP
8596 //3.directly call add/remove ep scheduler API
8597 //4.check if success, if failed over 10 times next, else goto 1
8598 ep_num = 0;
8599 ep_index = 0;
8600 while(ep_num < ep_boundary){
8601 ep_dir = get_random_int() % 2;
8602 burst = 0;
8603 mult = 0;
8604 isTT=0;
8605 if(test_speed == 0){
8606 cur_speed = (get_random_int()%3)+2;
8607 }
8608 else{
8609 cur_speed = test_speed;
8610 }
8611 switch(cur_speed){
8612 case EP_SPEED_SS:
8613 udev = udev_ss;
8614 transfer_type = get_random_int() % 2;
8615 if(transfer_type == 0){
8616 transfer_type = EPATT_INT;
8617 burst = get_random_int() % 3;
8618 if(burst > 0){
8619 maxp = 1024;
8620 }
8621 else{
8622 maxp = ((get_random_int() % 16)+1)*64;
8623 }
8624 bInterval = (get_random_int()%8)+1;
8625 }
8626 else{
8627 burst = get_random_int() % 16;
8628 if(burst > 0){
8629 maxp = 1024;
8630 }
8631 else{
8632 maxp = ((get_random_int() % 4)+1)*256;
8633 }
8634 mult = get_random_int() % 3;
8635 bInterval = (get_random_int()%8)+1;
8636 }
8637 break;
8638 case EP_SPEED_HS:
8639 udev = udev_hs;
8640 transfer_type = get_random_int() % 2;
8641 if(transfer_type == 0){
8642 transfer_type = EPATT_INT;
8643 maxp = ((get_random_int() % 16)+1)*64;
8644 mult = get_random_int() % 3;
8645 burst = 0;
8646 bInterval = (get_random_int()%8)+1;
8647 }
8648 else{
8649 maxp = ((get_random_int() % 16) + 1)*64;
8650 mult = get_random_int() % 3;
8651 burst = 0;
8652 bInterval = (get_random_int()%8)+1;
8653 }
8654 break;
8655 case EP_SPEED_FS:
8656 udev = udev_fs;
8657 transfer_type = get_random_int() % 2;
8658 if(transfer_type == 0){
8659 transfer_type = EPATT_INT;
8660 maxp = ((get_random_int() % 8)+1)*8;
8661 burst = 0;
8662 mult = 0;
8663 bInterval = (get_random_int()%256)+1;
8664 isTT=1;
8665 }
8666 else{
8667 maxp = ((get_random_int() % 16) + 1)*64;
8668 if(maxp==1024){
8669 maxp = 1023;
8670 }
8671 burst = 0;
8672 mult = 0;
8673 bInterval = (get_random_int()%6)+1;
8674 isTT=1;
8675 }
8676 break;
8677 case EP_SPEED_LS:
8678 udev = udev_ls;
8679 transfer_type = EPATT_INT;
8680 maxp = 8;
8681 bInterval = (get_random_int()%256)+1;
8682 isTT=1;
8683 break;
8684 }
8685 ep = kmalloc(sizeof(struct usb_host_endpoint), GFP_NOIO);
8686 ep->desc.bDescriptorType = USB_DT_ENDPOINT;
8687 if(ep_dir == EP_OUT){
8688 ep->desc.bEndpointAddress = EPADD_NUM(1) | EPADD_OUT;
8689 }
8690 else{
8691 ep->desc.bEndpointAddress = EPADD_NUM(1) | EPADD_IN;
8692 }
8693 ep->desc.bmAttributes = transfer_type;
8694 if(cur_speed == EP_SPEED_SS){
8695 ep->desc.wMaxPacketSize = maxp;
8696 ep->ss_ep_comp.bmAttributes = mult;
8697 ep->ss_ep_comp.bMaxBurst = burst;
8698 }
8699 else{
8700 ep->desc.wMaxPacketSize = maxp | (mult << 11);
8701 ep->ss_ep_comp.bmAttributes = 0;
8702 ep->ss_ep_comp.bMaxBurst = 0;
8703 }
8704 ep->desc.bInterval = bInterval;
8705 interval = 1<<(bInterval-1);
8706 ep_ctx = mtk_xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, GFP_NOIO);
8707 if(transfer_type == EPATT_INT && (cur_speed == EP_SPEED_FS || cur_speed == EP_SPEED_LS)){
8708 //rounding interval
8709 interval = fls(8 * ep->desc.bInterval) - 1;
8710 interval = clamp_val(interval, 3, 10);
8711 mtk_test_dbg( "ROUNDING interval to %d\n", interval);
8712 ep_ctx->ep_info = EP_INTERVAL(interval);
8713 }
8714 mtk_test_dbg( "[EP]Speed[%d]dir[%d]transfer_type[%d]bInterval[%d]maxp[%d]burst[%d]mult[%d]"
8715 , cur_speed, ep_dir, transfer_type, bInterval, maxp, burst, mult);
8716 #if MTK_SCH_NEW
8717 sch_ep = kmalloc(sizeof(struct sch_ep), GFP_KERNEL);
8718 ret = mtktest_mtk_xhci_scheduler_add_ep(udev->speed, usb_endpoint_dir_in(&ep->desc), isTT
8719 , transfer_type, maxp, interval, burst, mult, (u32 *)ep, (u32 *)ep_ctx, sch_ep);
8720 #else
8721 ret = mtktest_mtk_xhci_scheduler_add_ep(xhci, udev, ep, ep_ctx);
8722 #endif
8723 if(ret == SCH_SUCCESS){
8724 mtk_test_dbg( "......Success\n");
8725 ep_list[ep_index] = ep;
8726 ep = NULL;
8727 ep_index++;
8728 }
8729 else{
8730 mtk_test_dbg( "......Failed\n");
8731 }
8732 ep_num++;
8733 }
8734 //dump EP list and scheduler result
8735 //mtk_xhci_scheduler_dump_all(xhci);
8736 return RET_SUCCESS;
8737 }
8738
8739 static int dbg_u3_calibration(int argc, char** argv){
8740 char u1TimeDelay;
8741 char u1TimingValue;
8742 char u1PhyDrvValue;
8743 char u1TxSel;
8744 char u1RxSel;
8745 char u1PhyDrv;
8746 int u4LatchValue;
8747 char *pu1Buf;
8748 char *pu2Buf;
8749 char u1ReadTimingValue;
8750 char u1ReadPhyClkDrvValue;
8751 int u4USBStsVal;
8752 int u4P1ScVal;
8753 char u1P1PlsVal;
8754 char u1TmpP1PlsVal;
8755 char u1Macltssm;
8756 char u1TmpMacltssm;
8757 int u4ErrorCnt;
8758 int u4RecoveryCnt;
8759 int u4CorrectCnt;
8760 int u4ResetValue;
8761 char u1IsPass;
8762 char i;
8763 int temp;
8764 int num_u3_port, num_u2_port;
8765 __u32 __iomem *ip_reset_addr;
8766 __u32 __iomem *latch_sel_addr;
8767 __u32 __iomem *u3_cmd_addr;
8768 __u32 __iomem *u3_sts_addr;
8769 __u32 __iomem *u3_p1_sc_addr;
8770 __u32 __iomem *u3_p1_ltssm_addr;
8771 __u32 __iomem *u3_link_err_count_addr;
8772 __u32 __iomem *u3_recovery_count_addr;
8773
8774 num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
8775 num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
8776
8777 latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
8778 u3_cmd_addr = U3_XHCI_CMD_ADDR;
8779 u3_sts_addr = U3_XHCI_STS_ADDR;
8780 u3_p1_sc_addr = U3_P1_SC;
8781 u3_p1_ltssm_addr = U3_P1_LTSSM;
8782 u3_link_err_count_addr = U3_LINK_ERR_COUNT;
8783 u3_recovery_count_addr = U3_RECOVERY_COUNT;
8784 u3phy_init();
8785 u1TxSel = 0;
8786 for(u1RxSel = 0; u1RxSel<2; u1RxSel++){
8787 u1PhyDrv = 2;
8788 for(u1TimeDelay=0; u1TimeDelay<32; u1TimeDelay++){
8789 mtk_test_dbg( "Test TxSel[0x%02x] RxSel[0x%02x] TimingDelay[0x%02x] Reg[0x%02x]...\n"
8790 , u1TxSel, u1RxSel, u1TimeDelay, u1TimeDelay<<3);
8791 //write phase, drv
8792 u3phy_ops->change_pipe_phase(u3phy, u1PhyDrv, u1TimeDelay);
8793 //reset U3H IP
8794 writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
8795 writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
8796 writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
8797
8798 //turn on power, clock of each port
8799 for(i=0; i<num_u3_port; i++){
8800 temp = readl(SSUSB_U3_CTRL(i));
8801 temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
8802 writel(temp, SSUSB_U3_CTRL(i));
8803 }
8804 for(i=0; i<num_u2_port; i++){
8805 temp = readl(SSUSB_U2_CTRL(i));
8806 temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
8807 writel(temp, SSUSB_U2_CTRL(i));
8808 }
8809 msleep(10);
8810 //set pipe latch
8811 u4LatchValue = (u1TxSel<<2) | u1RxSel;
8812 writel(u4LatchValue, latch_sel_addr);
8813 //set hcrst
8814 writel(2, u3_cmd_addr);
8815 //polling CNR
8816 for(i=0; i<500; i++){
8817 u4USBStsVal = readl(u3_sts_addr);
8818 if(!((u4USBStsVal&U3_CNR) == U3_CNR)){
8819 break;
8820 }
8821 }
8822 if((u4USBStsVal&U3_CNR) == U3_CNR){
8823 mtk_test_dbg( "CNR not 0 after HCRST \n");
8824 continue;
8825 }
8826
8827 //for loopback mode, write mac3 t2r loopback
8828 // writel(0x1, 0xf00426dc);
8829
8830 //enable port power of port 1 in xHC port reg
8831 temp = readl(u3_p1_sc_addr);
8832 temp = mtktest_xhci_port_state_to_neutral(temp);
8833 temp |= PORT_POWER;
8834 writel(temp, u3_p1_sc_addr);
8835 //Wait 100 ms
8836 msleep(100);
8837 //polling PLS
8838 u4CorrectCnt=0;
8839 u1IsPass=1;
8840 u1TmpMacltssm = 0;
8841 u1TmpP1PlsVal = 0;
8842 //polling 200 times
8843 //if PLS in compliance, set warm reset
8844 //if polling status in U0 more than 3 times, check recovery & link error count, report PASS
8845 // print phase information
8846 //else report FAIL
8847 for(i=0; i<200; i++){
8848 u4P1ScVal = readl(u3_p1_sc_addr);
8849 u1P1PlsVal = (u4P1ScVal>>U3_PLS_OFFSET) & 0xf;
8850 u1Macltssm = readl(u3_p1_ltssm_addr);
8851 u1Macltssm = u1Macltssm & 0x1f;
8852 if(u1TmpMacltssm != u1Macltssm || u1TmpP1PlsVal != u1P1PlsVal){
8853 mtk_test_dbg( "Polling %d PLS=%d LTSSM=%d\n", i, u1P1PlsVal, u1Macltssm);
8854 u1TmpMacltssm = u1Macltssm;
8855 u1TmpP1PlsVal = u1P1PlsVal;
8856 }
8857 if(u1P1PlsVal == 10){
8858 u4P1ScVal = u4P1ScVal | (int)(1<<31);
8859 writel(u4P1ScVal, u3_p1_sc_addr);
8860 }
8861 if(u1P1PlsVal == 0){
8862 u4CorrectCnt++;
8863 }
8864 if(u4CorrectCnt==3){
8865 //clear recovery count
8866 writel((1<<16), u3_recovery_count_addr);
8867 u1IsPass = 0;
8868 //read error count
8869 u4ErrorCnt = readl(u3_link_err_count_addr);
8870 msleep(500);
8871 //read error count and recovery count in these period
8872 u4ErrorCnt = readl(u3_link_err_count_addr);
8873 u4RecoveryCnt = readl(u3_recovery_count_addr);
8874 u4CorrectCnt=4;
8875 }
8876 msleep(10);
8877 }
8878 if(u1IsPass == 0){
8879 mtk_test_dbg( "[PASS] PLS=0, Error=%d, Recovery=%d, TxSel[0x%02x] RxSel[0x%02x] PhyDrv[0x%02x] Reg[0x%02x] TimingDelay[0x%02x] Reg[0x%02x]\n"
8880 , u4ErrorCnt, u4RecoveryCnt, u1TxSel, u1RxSel, u1PhyDrv, u1PhyDrvValue, u1TimeDelay, u1TimingValue);
8881 }
8882 else{
8883 mtk_test_dbg( "[FAIL] PLS=%d\n", u1P1PlsVal);
8884 }
8885 msleep(3);
8886 }
8887 }
8888 }
8889
8890 static int dbg_printhccparams(int argc, char** argv){
8891 struct xhci_hcd *xhci;
8892 xhci = hcd_to_xhci(my_hcd);
8893 u32 __iomem *addr;
8894 int temp, tmp_add, i;
8895
8896 // mtktest_xhci_print_registers(xhci);
8897 xhci_dbg(xhci, "hcs_params1 add: 0x%p\n", &xhci->cap_regs->hcs_params1);
8898 xhci_dbg(xhci, "hcs_params2 add: 0x%p\n", &xhci->cap_regs->hcs_params2);
8899 xhci_dbg(xhci, "hcs_params3 add: 0x%p\n", &xhci->cap_regs->hcs_params3);
8900 xhci_dbg(xhci, "hc_capbase add: 0x%p\n", &xhci->cap_regs->hc_capbase);
8901 xhci_dbg(xhci, "hcc_params add: 0x%p\n", &xhci->cap_regs->hcc_params);
8902 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
8903 xhci_dbg(xhci, "hcc_params: 0x%x\n", temp);
8904 tmp_add = temp >> 16;
8905 addr = ((&xhci->cap_regs->hc_capbase) + (temp >>16));
8906 i = 1;
8907 while(tmp_add != 0){
8908 xhci_dbg(xhci, "cap pointer %d[0x%p: \n",i, addr);
8909 temp = xhci_readl(xhci, addr);
8910 xhci_dbg(xhci, "0x%x\n", temp);
8911 tmp_add = (temp >> 8) & 0xff;
8912 temp = xhci_readl(xhci, addr+1);
8913 xhci_dbg(xhci, "0x%x\n", temp);
8914 temp = xhci_readl(xhci, addr+2);
8915 xhci_dbg(xhci, "0x%x\n", temp);
8916 temp = xhci_readl(xhci, addr+3);
8917 xhci_dbg(xhci, "0x%x\n", temp);
8918 i++;
8919 addr = addr + tmp_add;
8920 }
8921
8922 return RET_SUCCESS;
8923 }
8924
8925 static dbg_port_set_pls(int argc, char** argv){
8926 struct xhci_hcd *xhci;
8927 u32 __iomem *addr;
8928 int temp;
8929 int pls, port_id;
8930
8931 if(argc > 1){
8932 port_id = (int)simple_strtol(argv[1], &argv[1], 10);
8933 xhci_dbg(xhci, "port_id = %d\n", port_id);
8934 }
8935
8936 if(argc > 2){
8937 pls = (int)simple_strtol(argv[2], &argv[2], 10);
8938 xhci_dbg(xhci, "pls set to %d\n", pls);
8939 }
8940 xhci = hcd_to_xhci(my_hcd);
8941 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8942 temp = xhci_readl(xhci, addr);
8943 temp = mtktest_xhci_port_state_to_neutral(temp);
8944 temp = temp & ~(PORT_PLS_MASK);
8945 temp = temp | (pls << 5) | PORT_LINK_STROBE;
8946 xhci_writel(xhci, temp, addr);
8947 return RET_SUCCESS;
8948 }
8949
8950 static int dbg_port_set_ped(int argc, char** argv){
8951 struct xhci_hcd *xhci;
8952 u32 __iomem *addr;
8953 int temp;
8954 int port_id;
8955
8956 if(argc > 1){
8957 port_id = (int)simple_strtol(argv[1], &argv[1], 10);
8958 xhci_dbg(xhci, "port_id = %d\n", port_id);
8959 }
8960 xhci = hcd_to_xhci(my_hcd);
8961 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8962 temp = xhci_readl(xhci, addr);
8963 temp = mtktest_xhci_port_state_to_neutral(temp);
8964 temp = temp | PORT_PE;
8965 xhci_writel(xhci, temp, addr);
8966 return RET_SUCCESS;
8967 }
8968
8969 static int dbg_port_reset(int argc, char** argv){
8970 struct xhci_hcd *xhci;
8971 u32 __iomem *addr;
8972 int temp, port_id;
8973 char isWarmReset;
8974
8975 port_id = g_port_id;
8976 isWarmReset = true;
8977
8978 if(argc > 1){
8979 port_id = (int)simple_strtol(argv[1], &argv[1], 10);
8980 xhci_dbg(xhci, "port_id = %d\n", port_id);
8981 }
8982
8983 if(argc > 2){
8984 if(!strcmp(argv[2], "true")){
8985 mtk_test_dbg( "test WarmReset=true\n");
8986 isWarmReset = true;
8987 }
8988 }
8989 xhci = hcd_to_xhci(my_hcd);
8990 if(isWarmReset){
8991 //do warm reset
8992 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
8993 temp = xhci_readl(xhci, addr);
8994 temp = mtktest_xhci_port_state_to_neutral(temp);
8995 temp = (temp | PORT_WR);
8996 xhci_writel(xhci, temp, addr);
8997 }
8998 else{
8999 //hot reset port
9000 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
9001 temp = xhci_readl(xhci, addr);
9002 temp = mtktest_xhci_port_state_to_neutral(temp);
9003 temp = (temp | PORT_RESET);
9004 xhci_writel(xhci, temp, addr);
9005 }
9006 return RET_SUCCESS;
9007 }
9008
9009 static int dbg_printportstatus(int argc, char** argv){
9010 struct xhci_hcd *xhci;
9011 u32 __iomem *addr;
9012 int temp, port_id;
9013
9014 port_id = g_port_id;
9015 if(argc > 1){
9016 port_id = (int)simple_strtol(argv[1], &argv[1], 10);
9017 xhci_dbg(xhci, "port_id = %d\n", port_id);
9018 }
9019 xhci = hcd_to_xhci(my_hcd);
9020 addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
9021 temp = xhci_readl(xhci, addr);
9022 xhci_dbg(xhci, "port %d = 0x%x\n", port_id, temp);
9023 return RET_SUCCESS;
9024 }
9025
9026 static int dbg_delayms(int argc, char** argv){
9027 int msecs;
9028 g_stopped = true;
9029 #if 0
9030 msecs = 10;
9031 if(argc > 1){
9032 msecs = (int)simple_strtol(argv[1], &argv[1], 10);
9033 xhci_dbg(xhci, "delay %d msecs\n", msecs);
9034 }
9035
9036 msleep(msecs);
9037 #endif
9038 return RET_SUCCESS;
9039 }
9040
9041 extern PHY_INT32 _U3Read_Reg(PHY_INT32 address);
9042 extern PHY_INT32 _U3Write_Reg(PHY_INT32 address, PHY_INT32 value);
9043
9044 static int dbg_u3w(int argc, char**argv){
9045 int u4TimingValue;
9046 char u1TimingValue;
9047 int u4TimingAddress;
9048
9049 if (argc<3)
9050 {
9051 mtk_test_dbg( "Arg: address value\n");
9052 return RET_FAIL;
9053 }
9054 u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
9055 u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
9056 u1TimingValue = u4TimingValue & 0xff;
9057 //_U3Write_Reg(u4TimingAddress, u1TimingValue);
9058 U3PhyWriteReg8(u4TimingAddress, u1TimingValue);
9059 mtk_test_dbg( "Write done\n");
9060 return RET_SUCCESS;
9061 }
9062
9063 static int dbg_u3r(int argc, char**argv){
9064 char u1ReadTimingValue;
9065 int u4TimingAddress;
9066 if (argc<2)
9067 {
9068 mtk_test_dbg( "Arg: address\n");
9069 return 0;
9070 }
9071 mdelay(500);
9072 u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
9073 //u1ReadTimingValue = _U3Read_Reg(u4TimingAddress);
9074 u1ReadTimingValue = U3PhyReadReg8(u4TimingAddress);
9075 mtk_test_dbg( "Value = 0x%x\n", u1ReadTimingValue);
9076 return 0;
9077 }
9078
9079 #if 0
9080 extern PHY_INT32 u2_slew_rate_calibration_d60802(struct u3phy_info *info);
9081 static int dbg_u3PHY_init(int argc, char**argv){
9082 int ret;
9083 ret = u3phy_init();
9084 mtk_test_dbg( "phy registers and operations initial done\n");
9085 if(u3phy_ops->u2_slew_rate_calibration){
9086 u3phy_ops->u2_slew_rate_calibration(u3phy);
9087 }
9088 else{
9089 mtk_test_dbg( "WARN: PHY doesn't implement u2 slew rate calibration function\n");
9090 }
9091 if(u3phy_ops->init(u3phy) == PHY_TRUE)
9092 return RET_SUCCESS;
9093 return RET_FAIL;
9094 }
9095 #else
9096
9097 // USBIF , skip slew rate calibration ?
9098 extern void phy_probe_out_x();
9099 extern void phy_dump_regs();
9100 extern void phy_probe_reg();
9101 extern void phy_reset();
9102
9103 static int dbg_u3PHY_init(int argc, char**argv){
9104 u3phy_init();
9105 mtk_test_dbg( "phy registers and operations initial done\n");
9106 u3phy_ops->init(u3phy);
9107 return RET_SUCCESS;
9108 }
9109
9110 #endif
9111
9112 static int dbg_phy_eyescan(int argc, char** argv){
9113 _rEye1.bX_tl = (int)simple_strtol(argv[1], &argv[1], 10);
9114 _rEye1.bY_tl = (int)simple_strtol(argv[2], &argv[2], 10);
9115 _rEye1.bX_br = (int)simple_strtol(argv[3], &argv[3], 10);
9116 _rEye1.bY_br = (int)simple_strtol(argv[4], &argv[4], 10);
9117 _rEye1.bDeltaX = (int)simple_strtol(argv[5], &argv[5], 10);
9118 _rEye1.bDeltaY = (int)simple_strtol(argv[6], &argv[6], 10);
9119
9120 _rEye2.bX_tl = (int)simple_strtol(argv[1], &argv[1], 10);
9121 _rEye2.bY_tl = (int)simple_strtol(argv[2], &argv[2], 10);
9122 _rEye2.bX_br = (int)simple_strtol(argv[3], &argv[3], 10);
9123 _rEye2.bY_br = (int)simple_strtol(argv[4], &argv[4], 10);
9124 _rEye2.bDeltaX = (int)simple_strtol(argv[5], &argv[5], 10);
9125 _rEye2.bDeltaY = (int)simple_strtol(argv[6], &argv[6], 10);
9126
9127 _rTestCycle.wEyeCnt = (int)simple_strtol(argv[7], &argv[7], 10);
9128 _rTestCycle.bNumOfEyeCnt = (int)simple_strtol(argv[8], &argv[8], 10);
9129 _rTestCycle.bNumOfIgnoreCnt = (int)simple_strtol(argv[9], &argv[9], 10);
9130 _rTestCycle.bPICalEn = 1;
9131
9132 u3phy_init();
9133 u3phy_ops->eyescan(u3phy, _rEye1.bX_tl, _rEye1.bY_tl, _rEye1.bX_br, _rEye1.bY_br, _rEye1.bDeltaX, _rEye1.bDeltaY
9134 , _rTestCycle.wEyeCnt, _rTestCycle.bNumOfEyeCnt, _rTestCycle.bPICalEn, _rTestCycle.bNumOfIgnoreCnt);
9135 return RET_SUCCESS;
9136 }
9137
9138 static int dbg_u2_testmode(int argc, char** argv){
9139 struct xhci_hcd *xhci;
9140 u32 __iomem *addr;
9141 int temp, port_id;
9142 int test_value;
9143
9144 if(argc<2){
9145 mtk_test_dbg( "Args: test mode value\n");
9146 mtk_test_dbg( " (0)not enabled (1)J_STATE (2)K_STATE (3)SE0_NAK (4)Packet (5)FORCE_ENABLE (15)Port test control error\n");
9147 return RET_FAIL;
9148 }
9149 port_id = 2;
9150
9151 test_value = (int)simple_strtol(argv[1], &argv[1], 10);
9152 xhci_dbg(xhci, "test_value = %d\n", test_value);
9153
9154 xhci = hcd_to_xhci(my_hcd);
9155 addr = &xhci->op_regs->port_power_base + NUM_PORT_REGS*(port_id-1 & 0xff);
9156 temp = xhci_readl(xhci, addr);
9157 temp &= ~(0xf<<28);
9158 temp |= (test_value<<28);
9159 xhci_writel(xhci, temp, addr);
9160 return RET_SUCCESS;
9161
9162
9163
9164 }
9165
9166 static int dbg_memorywrite(int argc, char** argv){
9167 unsigned int addr, value;
9168 if (argc<3)
9169 {
9170 mtk_test_dbg( "Arg: address value\n");
9171 return RET_FAIL;
9172 }
9173
9174 addr = (int)simple_strtol(argv[1], &argv[1], 16);
9175 value = (int)simple_strtol(argv[2], &argv[2], 16);
9176
9177 writel(value, addr);
9178 }
9179
9180 static int dbg_memoryread(int argc, char** argv){
9181 unsigned int addr, value;
9182 if (argc<2)
9183 {
9184 mtk_test_dbg( "Arg: address\n");
9185 return RET_FAIL;
9186 }
9187 addr = (int)simple_strtol(argv[1], &argv[1], 16);
9188 value = readl(addr);
9189 mtk_test_dbg( "Addr: 0x%x, Value: 0x%x\n", addr, value);
9190 }
9191
9192 static int dbg_printslotcontext(int argc, char** argv){
9193 struct xhci_hcd *xhci;
9194 struct xhci_container_ctx *out_ctx, *in_ctx;
9195 int slot_id;
9196
9197 slot_id = g_slot_id;
9198
9199 if(argc > 1){
9200 slot_id = (int)simple_strtol(argv[1], &argv[1], 10);
9201 xhci_dbg(xhci, "slot id set to %d\n", slot_id);
9202 }
9203
9204 xhci = hcd_to_xhci(my_hcd);
9205 in_ctx = xhci->devs[slot_id]->in_ctx;
9206 mtktest_xhci_dbg_ctx(xhci, in_ctx, 5);
9207 out_ctx = xhci->devs[slot_id]->out_ctx;
9208 mtktest_mtk_xhci_dbg_ctx(xhci, out_ctx, 5);
9209 return RET_SUCCESS;
9210 }
9211
9212 static int dbg_read_xhci(int argc, char** argv)
9213 {
9214 u32 u4SrcAddr;
9215 u32 u4Addr;
9216 u32 u4Len;
9217 u32 u4Idx;
9218 u32 temp1, temp2, temp3, temp4;
9219
9220 struct xhci_hcd *xhci = hcd_to_xhci(my_hcd);
9221
9222 //4-bytes alignment
9223 u4SrcAddr = simple_strtoul(argv[1], NULL, 16) & 0xfffffffc;
9224 u4Len = simple_strtoul(argv[2], NULL, 16);
9225
9226 //no operation is needed
9227 if (u4Len == 0)
9228 {
9229 return 0;
9230 }
9231
9232 //the maximum number of bytes
9233 if (u4Len > 0x1000)
9234 {
9235 u4Len = 0x1000;
9236 }
9237
9238 //sum together xhci register base address and offset
9239 u4SrcAddr += ((u32)(unsigned long)xhci->cap_regs);
9240
9241 for (u4Idx = 0; u4Idx < u4Len; u4Idx += 16)
9242 {
9243 temp1 = xhci_readl(xhci, (u4SrcAddr + u4Idx + 0));
9244 temp2 = xhci_readl(xhci, (u4SrcAddr + u4Idx + 4));
9245 temp3 = xhci_readl(xhci, (u4SrcAddr + u4Idx + 8));
9246 temp4 = xhci_readl(xhci, (u4SrcAddr + u4Idx + 12));
9247
9248 mtk_test_dbg("0x%08x | %08x %08x %08x %08x\r\n", (u4SrcAddr + u4Idx), temp1, temp2, temp3, temp4);
9249 }
9250
9251 return 0;
9252 }
9253
9254 static int dbg_dump_regs(int argc, char** argv)
9255 {
9256 struct xhci_hcd *xhci = hcd_to_xhci(my_hcd);
9257
9258 mtktest_xhci_print_registers(xhci);
9259
9260 return 0;
9261 }
9262
9263 struct file_operations xhci_mtk_test_fops_host = {
9264 owner: THIS_MODULE,
9265 read: xhci_mtk_test_read,
9266 write: xhci_mtk_test_write,
9267 #if KERNEL_30
9268 unlocked_ioctl: xhci_mtk_test_unlock_ioctl,
9269 #else
9270 ioctl: xhci_mtk_test_ioctl,
9271 #endif
9272 open: xhci_mtk_test_open,
9273 release: xhci_mtk_test_release,
9274 };
9275
9276 // USBIF , to send IF uevent
9277 int usbif_u3h_test_send_event(char* event)
9278 {
9279 char udev_event[128];
9280 char *envp[] = {udev_event, NULL };
9281 int ret ;
9282
9283 snprintf(udev_event, 128, "USBIF_EVENT=%s",event);
9284 printk("usbif_u3h_test_send_event - sending event - %s in %s\n", udev_event, kobject_get_path(&mu3h_test_uevent_device.this_device->kobj, GFP_KERNEL));
9285 ret = kobject_uevent_env(&mu3h_test_uevent_device.this_device->kobj, KOBJ_CHANGE, envp);
9286 if (ret < 0)
9287 printk("usbif_u3h_test_send_event sending failed with ret = %d, \n", ret);
9288
9289 return ret;
9290 }
9291
9292 static int __init mtk_test_init(void)
9293 {
9294 int retval = 0;
9295 struct class *cli_class ;
9296 dev_t cli_dev_t = MKDEV(XHCI_MTK_TEST_MAJOR, 0) ;
9297 struct device *cli_dev ;
9298
9299 mtk_test_dbg( "xchi_mtk_test Init\n");
9300
9301 cli_class = class_create(THIS_MODULE, DEVICE_NAME);
9302 if (IS_ERR(cli_class))
9303 mtk_test_dbg("%s: failed to create cli class ", __func__);
9304
9305 cli_dev = device_create(cli_class, NULL, cli_dev_t, NULL, DEVICE_NAME);
9306 if (IS_ERR(cli_dev))
9307 mtk_test_dbg("%s: failed to create cli dev ", __func__);
9308
9309 retval = register_chrdev(XHCI_MTK_TEST_MAJOR, DEVICE_NAME, &xhci_mtk_test_fops_host);
9310 if(retval < 0)
9311 {
9312 mtk_test_dbg( "xchi_mtk_test Init failed, %d\n", retval);
9313 goto fail;
9314 }
9315 g_port_connect = false;
9316 g_port_reset = false;
9317 g_event_full = false;
9318 g_port_id = 0;
9319 g_slot_id = 0;
9320 g_speed = 0; // UNKNOWN_SPEED
9321 g_cmd_status = CMD_DONE;
9322 // g_trans_status = TRANS_DONE;
9323 g_exec_done = true ;
9324 g_stopped = true ;
9325 mb() ;
9326
9327 printk(KERN_ERR "[OTG_H] mtk_test_init, g_port_connect is %d\n", g_port_connect);
9328
9329 if (!misc_register(&mu3h_test_uevent_device)){
9330 printk("create the mu3h_test_uevent_device uevent device OK!\n") ;
9331
9332 }else{
9333 printk("[ERROR] create the mu3h_test_uevent_device uevent device fail\n") ;
9334 }
9335
9336 return 0;
9337 fail:
9338 return retval;
9339 }
9340 module_init(mtk_test_init);
9341
9342 static void __exit mtk_test_cleanup(void)
9343 {
9344 mtk_test_dbg( "xchi_mtk_test End\n");
9345 misc_deregister(&mu3h_test_uevent_device);
9346
9347 unregister_chrdev(XHCI_MTK_TEST_MAJOR, DEVICE_NAME);
9348 if(my_hcd != NULL){
9349 mtk_xhci_hcd_cleanup();
9350 }
9351 }
9352 module_exit(mtk_test_cleanup);
9353
9354 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)