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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / mu3d / test_drv / mu3d_test_usb_drv.c
1 #include <linux/mu3d/hal/mu3d_hal_osal.h>
2 #define _DEV_USB_DRV_EXT_
3 #include <linux/mu3d/test_drv/mu3d_test_usb_drv.h>
4 #undef _DEV_USB_DRV_EXT_
5 #include <linux/mu3d/hal/mu3d_hal_hw.h>
6 #include <linux/mu3d/hal/mu3d_hal_qmu_drv.h>
7 #include <linux/mu3d/hal/mu3d_hal_usb_drv.h>
8 #include <linux/mu3d/test_drv/mu3d_test_qmu_drv.h>
9
10 static u64 mu3d_if_dmamask = DMA_BIT_MASK(32);
11 static struct device mu3d_if_dev = {
12 .dma_mask = &mu3d_if_dmamask,
13 .coherent_dma_mask = DMA_BIT_MASK(32),
14 };
15
16
17 // USBIF
18 #include <mach/battery_common.h>
19
20
21 extern void BATTERY_SetUSBState(int usb_state);
22 extern void wake_up_bat(void);
23
24 EP0_STATE g_ep0_state = EP0_IDLE;
25 DEV_UINT8* g_dma_buffer[2 * MAX_EP_NUM + 1];
26 dma_addr_t g_mu3d_dma_debug;
27 static DEV_UINT8 bAddress_Offset = 0;
28 DEV_UINT8* loopback_buffer;
29 extern DEV_UINT16 g_nirq;
30
31 void u3d_sync_with_bat(int usb_state)
32 {
33 printk("[U3D_T] u3d_sync_with_bat, usb_state is %d\n", usb_state);
34 #ifndef CONFIG_MTK_FPGA
35 BATTERY_SetUSBState(usb_state);
36 wake_up_bat();
37 #endif
38 }
39
40
41 // 12 bytes
42 // USBIF, should change to ROME phone MTK vendor ID, product ID
43 DEV_UINT8 device_descriptor[] =
44 {
45 0x12,
46 0x01,
47 0x00, //0x0200
48 0x02,
49 0x00,
50 0x00,
51 0x00,
52 0x40,
53 0x8D, //0x0E8D , Mediatek
54 0x0E,
55 0x03, //0x0C03, STORAGE + ADB
56 0x0C,
57 0x00, //0x0200
58 0x02,
59 0x01,
60 0x02,
61 0x03,
62 0x01
63 };
64
65 // 9 bytes
66 DEV_UINT8 configuration_descriptor[] =
67 {
68 0x09,
69 0x02,
70 0x25, //0x0025
71 0x00,
72 0x01,
73 0x01,
74 0x00,
75 0x80, //set to bus power and not remote wakeup , orig : 0xc0,
76 0xFA, // 0x32 : 100 mA , 0x60 : 192 mA , 0xfa : 500 mA
77 };
78
79 // 9 bytes
80 DEV_UINT8 interface_descriptor[] =
81 {
82 0x09,
83 0x04,
84 0x00,
85 0x00,
86 0x02,
87 0x08,
88 0x06,
89 0x50,
90 0x00
91 };
92
93 // 7 bytes
94 DEV_UINT8 endpoint_descriptor_in[] =
95 {
96 0x07,
97 0x05,
98 0x81,
99 0x02,
100 0x00, //0x0200
101 0x02,
102 0x00
103 };
104
105 // 7 bytes
106 DEV_UINT8 endpoint_descriptor_out[] =
107 {
108 0x07,
109 0x05,
110 0x02,
111 0x02,
112 0x00, //0x0200
113 0x02,
114 0x00
115 };
116
117 // 5 bytes
118 DEV_UINT8 otg_descriptor[] =
119 {
120 0x05,
121 0x09,
122 0x03,
123 0x00,
124 0x02 // bcdOTG version
125 };
126
127 // 4 bytes
128 DEV_UINT8 string_descriptor_0[] =
129 {
130 0x04,
131 0x03,
132 0x09,
133 0x04
134 };
135
136 // 18 bytes
137 DEV_UINT8 string_descriptor_1[] =
138 {
139 0x12,
140 0x03,
141 0x4d,
142 0x00,
143 0x65,
144 0x00,
145 0x64,
146 0x00,
147 0x69,
148 0x00,
149 0x61,
150 0x00,
151 0x54,
152 0x00,
153 0x65,
154 0x00,
155 0x6b,
156 0x00
157 };
158
159 // 44 bytes
160 DEV_UINT8 string_descriptor_2[] =
161 {
162 0x2a,
163 0x03,
164 0x4d,
165 0x00,
166 0x54,
167 0x00,
168 0x36,
169 0x00,
170 0x35,
171 0x00,
172 0x78,
173 0x00,
174 0x78,
175 0x00,
176 0x20,
177 0x00,
178 0x41,
179 0x00,
180 0x6e,
181 0x00,
182 0x64,
183 0x00,
184 0x72,
185 0x00,
186 0x6f,
187 0x00,
188 0x69,
189 0x00,
190 0x64,
191 0x00,
192 0x20,
193 0x00,
194 0x50,
195 0x00,
196 0x68,
197 0x00,
198 0x6f,
199 0x00,
200 0x6e,
201 0x00,
202 0x65,
203 0x00
204 };
205
206 // 34 bytes
207 DEV_UINT8 string_descriptor_3[] =
208 {
209 0x22,
210 0x03,
211 0x30,
212 0x00,
213 0x31,
214 0x00,
215 0x32,
216 0x00,
217 0x33,
218 0x00,
219 0x34,
220 0x00,
221 0x35,
222 0x00,
223 0x36,
224 0x00,
225 0x37,
226 0x00,
227 0x38,
228 0x00,
229 0x39,
230 0x00,
231 0x41,
232 0x00,
233 0x42,
234 0x00,
235 0x43,
236 0x00,
237 0x44,
238 0x00,
239 0x45,
240 0x00,
241 0x46,
242 0x00
243 };
244
245 DEV_UINT8 string_one[] =
246 {
247 0x01
248 };
249
250 DEV_UINT8 string_zero[] =
251 {
252 0x00
253 };
254
255
256 /**
257 * u3d_init_ctrl - initialize ep0 ctrl req
258 *
259 */
260 void u3d_init_ctrl(void)
261 {
262 struct USB_REQ *req;
263
264 os_printk(K_ERR, "%s\n", __func__);
265
266 req = mu3d_hal_get_req(0, USB_TX);
267 req->count = USB_BUF_SIZE;
268 req->complete = 0;
269 req->actual = 0;
270 req->needZLP = 0;
271 }
272
273
274 /**
275 * u3d_init - initialize mac & qmu/bmu
276 *
277 */
278 DEV_UINT8 *isrbuffer;
279 DEV_UINT8 *isrbuffer1;
280 DEV_UINT8 *isrbuffer2;
281
282 void u3d_init_mem(void){
283 isrbuffer = (DEV_UINT8 *)os_mem_alloc(10);
284 u3d_allocate_ep0_buffer();
285 u3d_alloc_req();
286 //u3d_rst_request();
287
288 #if (BUS_MODE==QMU_MODE)
289 printk("mu3d_hal_alloc_qmu_mem\n");
290 /* Initialize QMU GPD/BD memory. */
291 mu3d_hal_alloc_qmu_mem();
292
293 #endif
294
295 isrbuffer1 = (DEV_UINT8 *)os_mem_alloc(10);
296 os_printk(K_ERR, "isrbuffer1: %p\n", isrbuffer1);
297
298 isrbuffer2 = (DEV_UINT8 *)os_mem_alloc(10);
299 os_printk(K_ERR, "isrbuffer2: %p\n", isrbuffer2);
300
301 }
302 void u3d_init(void){
303
304 /* disable ip power down, disable U2/U3 ip power down */
305 // USBIF , in ROME real chip , we should disable VBUS_FRC_EN
306 //os_writel(U3D_MISC_CTRL, 0x0);
307
308 mu3d_hal_ssusb_en();
309 /* reset U3D all dev module. */
310 mu3d_hal_rst_dev();
311 /* apply default register values */
312 mu3d_hal_dft_reg();
313
314 /* register U3D ISR. */
315 mu3d_hal_initr_dis();
316 mu3d_hal_clear_intr() ;
317
318 /* register SSUSB_DEV_INT */
319 //USBIF isrbuffer = (DEV_UINT8 *)os_mem_alloc(10);
320 if(OS_R_OK != os_reg_isr((DEV_UINT16)g_nirq, u3d_inter_handler, isrbuffer)){
321 os_printk(K_ERR,"Roll: Can't register IRQ %d\n", g_nirq);
322 return;
323 }
324 else{
325 os_printk(K_DEBUG,"Register IRQ %d\n", g_nirq);
326 }
327 os_printk(K_DEBUG,"USB Disable IRQ: %d\n", g_nirq);
328 os_disableIrq(g_nirq);
329 g_usb_irq = 0;
330
331 //USBIF u3d_allocate_ep0_buffer();
332 //USBIF u3d_alloc_req();
333 u3d_rst_request();
334
335 //USBIF# if (BUS_MODE==QMU_MODE)
336 //USBIF printk("mu3d_hal_alloc_qmu_mem\n");
337 /* Initialize QMU GPD/BD memory. */
338 //USBIF mu3d_hal_alloc_qmu_mem();
339 //USBIF #endif
340
341 /* Initialize usb speed. */
342 mu3d_hal_set_speed(U3D_DFT_SPEED);
343 /* Detect usb speed. */
344 //speed depends on host/cable/device; so speed chk is bypassed
345 //mu3d_hal_det_speed(U3D_DFT_SPEED, 0);
346 os_ms_delay(1000);
347
348 /* initialize usb ep0 & system */
349 u3d_irq_en();
350 u3d_initialize_drv();
351 #if (BUS_MODE==QMU_MODE)
352 /* Initialize QMU module. */
353 mu3d_hal_init_qmu();
354 #endif
355 #ifdef POWER_SAVING_MODE
356 mu3d_hal_pdn_cg_en();
357 #endif
358
359 // USBIF , in ROME real chip , we should disable VBUS_FRC_EN
360 os_writel(U3D_MISC_CTRL, 0);
361
362 #ifdef EXT_VBUS_DET
363 // USBIF, in ROME real chip , this should be change to use polling vbus method or .... call back from PMIC
364 os_writel(FPGA_REG, (os_readl(FPGA_REG) &~ VBUS_MSK ) | VBUS_FALL_BIT);
365
366 /* register SSUSB_VBUS_RISE_INT */
367 //USBIF isrbuffer1 = (DEV_UINT8 *)os_mem_alloc(10);
368 //USBIF os_printk(K_ERR, "isrbuffer1: %x\n", isrbuffer1);
369
370 if(ret = os_reg_isr((DEV_UINT16)VBUS_RISE_IRQ, u3d_vbus_rise_handler, isrbuffer1)){
371 os_printk(K_ERR,"Roll: Can't register IRQ %d, error code: %d\n", VBUS_RISE_IRQ, ret);
372 return;
373 }
374 else{
375 os_printk(K_DEBUG,"Register IRQ %d\n", VBUS_RISE_IRQ);
376 }
377 os_printk(K_DEBUG,"USB Disable IRQ: %d\n", VBUS_RISE_IRQ);
378 os_disableIrq(VBUS_RISE_IRQ);
379 os_enableIrq(VBUS_RISE_IRQ);
380
381 /* register SSUSB_VBUS_FALL_INT */
382 //USBIF isrbuffer2 = (DEV_UINT8 *)os_mem_alloc(10);
383 //USBIF os_printk(K_ERR, "isrbuffer2: %x\n", isrbuffer2);
384
385 if(ret = os_reg_isr((DEV_UINT16)VBUS_FALL_IRQ, u3d_vbus_fall_handler, isrbuffer2)){
386 os_printk(K_ERR,"Roll: Can't register IRQ %d, error code: %d\n", VBUS_FALL_IRQ, ret);
387 return;
388 }
389 else{
390 os_printk(K_DEBUG,"Register IRQ %d\n", VBUS_FALL_IRQ);
391 }
392 os_printk(K_DEBUG,"USB Disable IRQ: %d\n", VBUS_FALL_IRQ);
393 os_disableIrq(VBUS_FALL_IRQ);
394 os_enableIrq(VBUS_FALL_IRQ);
395 #endif
396 }
397
398 void u3d_deinit(void){
399 /* register U3D ISR. */
400 mu3d_hal_initr_dis();
401 mu3d_hal_clear_intr();
402
403 /* release SSUSB_DEV_INT */
404 os_disableIrq(g_nirq);
405 os_free_isr((DEV_UINT16)g_nirq, isrbuffer) ;
406
407 #ifdef EXT_VBUS_DET
408 // KKKKK, in ROME real chip , this should be change to use polling vbus method or .... call back from PMIC
409 /* release EXT VBUS RISE INT */
410 os_disableIrq(VBUS_RISE_IRQ);
411 os_free_isr((DEV_UINT16)VBUS_RISE_IRQ, isrbuffer1) ;
412 /* release EXT VBUS FALL INT */
413 os_disableIrq(VBUS_FALL_IRQ);
414 os_free_isr((DEV_UINT16)VBUS_FALL_IRQ, isrbuffer2) ;
415
416 #endif
417
418 /* reset U3D all dev module. */
419 //mu3d_hal_rst_dev();
420
421 }
422
423
424 void u3d_irq_en(void){
425 os_printk(K_ERR, "%s\n", __func__);
426 os_writel(U3D_LV1IESR, 0xFFFFFFFF);
427 os_enableIrq(g_nirq);
428 g_usb_irq = 1;
429 }
430
431 static void u3d_free_dma0(void){
432
433 DEV_INT32 ep_index, ep_num;
434 struct USB_EP_SETTING *ep_setting;
435
436 os_writel(U3D_EP0DMACTRL, 0);
437 os_writel(U3D_EP0DMASTRADDR, 0);
438 os_writel(U3D_EP0DMATFRCOUNT, 0);
439 ep_index = ep_num =0;
440 ep_setting = &g_u3d_setting.ep_setting[ep_index];
441
442 return;
443 }
444
445
446
447 void u3d_power_mode(DEV_INT32 mode, DEV_INT8 u1_value, DEV_INT8 u2_value, DEV_INT8 en_u1, DEV_INT8 en_u2){
448
449 DEV_INT32 temp;
450
451 printk("mode : 0x%08X\n",mode);
452 printk("u1_value : 0x%08X\n",u1_value);
453 printk("u2_value : 0x%08X\n",u2_value);
454 printk("en_u1 : 0x%08X\n",en_u1);
455 printk("en_u2 : 0x%08X\n",en_u2);
456
457 if((mode == 0)||(mode == 4)){
458 os_writel(U3D_LINK_POWER_CONTROL, 0);
459 }
460 if(mode == 1){
461 //os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) | LGO_U1);
462 os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) & ~(SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE));
463 os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) | SW_U1_REQUEST_ENABLE);
464 temp = os_readl(U3D_LINK_UX_INACT_TIMER);
465 temp &= ~U1_INACT_TIMEOUT_VALUE;
466 temp |= u1_value;
467 os_writel(U3D_LINK_UX_INACT_TIMER, temp);
468 }
469 if(mode == 2){
470 //os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) | LGO_U2);
471 os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) & ~(SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE));
472 os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) | SW_U2_REQUEST_ENABLE);
473 temp = os_readl(U3D_LINK_UX_INACT_TIMER);
474 temp &= ~DEV_U2_INACT_TIMEOUT_VALUE;
475 temp |= (u2_value<<16);
476 os_writel(U3D_LINK_UX_INACT_TIMER, temp);
477 }
478 if(mode == 3){
479
480 if(en_u1){
481
482 os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) & ~(SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE));
483 os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) | SW_U1_REQUEST_ENABLE);
484 temp = os_readl(U3D_LINK_UX_INACT_TIMER);
485 temp &= ~U1_INACT_TIMEOUT_VALUE;
486 temp |= u1_value;
487 os_writel(U3D_LINK_UX_INACT_TIMER, temp);
488 while(!((os_readl(U3D_LINK_STATE_MACHINE)&LTSSM)==STATE_U1_STATE));
489 os_ms_delay(500);
490 os_writel(U3D_LINK_UX_INACT_TIMER, 0);
491 os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) | UX_EXIT);
492 while((os_readl(U3D_LINK_POWER_CONTROL) & UX_EXIT));
493
494 }
495 if(en_u2){
496
497 os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) & ~(SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE));
498 os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) | SW_U2_REQUEST_ENABLE);
499 temp = os_readl(U3D_LINK_UX_INACT_TIMER);
500 temp &= ~DEV_U2_INACT_TIMEOUT_VALUE;
501 temp |= (u2_value<<16);
502 os_writel(U3D_LINK_UX_INACT_TIMER, temp);
503 while(!((os_readl(U3D_LINK_STATE_MACHINE)&LTSSM)==STATE_U2_STATE));
504 os_ms_delay(500);
505 os_writel(U3D_LINK_UX_INACT_TIMER, 0);
506 os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) | UX_EXIT);
507 while((os_readl(U3D_LINK_POWER_CONTROL) & UX_EXIT));
508 }
509 }
510 if(en_u1){
511 os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) | SW_U1_ACCEPT_ENABLE | SW_U1_REQUEST_ENABLE);
512 }
513 if(en_u2){
514 os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) | SW_U2_ACCEPT_ENABLE | SW_U2_REQUEST_ENABLE);
515 }
516 if(mode == 4){
517 os_ms_delay(200);
518 os_writel(U3D_LINK_POWER_CONTROL, os_readl(U3D_LINK_POWER_CONTROL) | UX_EXIT);
519 }
520 }
521
522 DEV_UINT8 u3d_transfer_complete(DEV_INT32 ep_num, USB_DIR dir){
523 DEV_INT32 ep_index=0;
524
525 if(dir == USB_TX){
526 ep_index = ep_num;
527 }
528 else if(dir == USB_RX){
529 ep_index = ep_num + MAX_EP_NUM;
530 }
531 else{
532 BUG_ON(1);
533 }
534
535 return g_u3d_req[ep_index].complete;
536 }
537
538 DEV_UINT8 req_complete(DEV_INT32 ep_num, USB_DIR dir){
539 struct USB_REQ *req = mu3d_hal_get_req(ep_num, dir);
540 os_ms_delay(1);
541 if(req->complete){
542 return true;
543 }
544 else{
545 return false;
546 }
547 }
548
549
550 /**
551 * u3d_config_dma0 - config ep0 dma
552 *
553 */
554 static void u3d_config_dma0(DEV_INT32 burst_mode, DEV_INT32 dir, DEV_INT32 addr, DEV_INT32 count){
555
556 DEV_UINT32 usb_dma_cntl = 0;
557 #if defined(USB_RISC_CACHE_ENABLED)
558 os_flushinvalidateDcache();
559 #endif
560 os_printk(K_DEBUG, "u3d_config_dma0\n");
561 os_printk(K_DEBUG, "DMA CTRL0 :%d\n", usb_dma_cntl);
562 os_printk(K_DEBUG, "addr: %x\n",addr);
563 os_printk(K_DEBUG, "count: %x\n",count);
564
565 usb_dma_cntl = ((dir&0x1)<<1) | INTEN;
566 os_writel(U3D_EP0DMACTRL, usb_dma_cntl);
567 os_writel(U3D_EP0DMASTRADDR, addr);
568 os_writel(U3D_EP0DMATFRCOUNT, count);
569 // USBIF
570 /*<Caution> DMA_OUTSTAND_NUM at U3D_EP0DMARLCOUNT should NOT clear to 0. If so, DMA does NOT work anymore.*/
571 os_writel(U3D_EP0DMARLCOUNT, os_readl(U3D_EP0DMARLCOUNT) | ((burst_mode&0x3) << DMA_BURST_OFST));
572 os_writel(U3D_EP0DMACTRL, os_readl(U3D_EP0DMACTRL)|DMA_EN);
573 }
574
575
576 /**
577 * u3d_ep0en - enable ep0 function
578 *
579 */
580 void u3d_ep0en(void)
581 {
582 DEV_UINT32 temp;
583 struct USB_EP_SETTING *ep_setting;
584
585 os_printk(K_ERR, "%s\n", __func__);
586
587 ep_setting = &g_u3d_setting.ep_setting[0];
588 ep_setting->transfer_type = USB_CTRL;
589 ep_setting->dir = USB_TX;
590 ep_setting->fifoaddr = 0;
591 ep_setting->enabled = 1;
592 if((os_readl(U3D_DEVICE_CONF) & SSUSB_DEV_SPEED) == SSUSB_SPEED_SUPER)
593 {
594 ep_setting->fifosz = 512;
595 ep_setting->maxp = 512;
596 }
597 else
598 {
599 ep_setting->fifosz = 64;
600 ep_setting->maxp = 64;
601 }
602
603 //EP0CSR
604 temp = ep_setting->maxp;
605 #ifdef AUTOSET
606 temp |= EP0_AUTOSET;
607 #endif
608 #ifdef AUTOCLEAR
609 temp |= EP0_AUTOCLEAR;
610 #endif
611 //leave this bit on so that EP0 flow can switch between PIO & DMA easily
612 //there is no EP0 DMA interrupt event under PIO mode
613 //temp |= ((g_ep0_mode == PIO_MODE) ? EP0_DMAREQEN : 0);
614 #if (EP0_BUS_MODE==DMA_MODE)
615 temp |= EP0_DMAREQEN;
616 #endif
617 os_writel(U3D_EP0CSR, temp);
618
619 //enable EP0 interrupts
620 os_setmsk(U3D_EPIESR, (EP0ISR | SETUPENDISR));
621
622 return;
623 }
624
625
626 void u3d_allocate_ep0_buffer(void)
627 {
628 g_dma_buffer[0] = (DEV_UINT8 *)os_mem_alloc(USB_BUF_SIZE);
629 }
630
631 void u3d_initialize_drv(void){
632 DEV_INT32 i;
633 USB_SPEED speed = g_u3d_setting.speed;
634
635 os_printk(K_ERR, "%s\n", __func__);
636
637 /* initialize ep fifo address*/
638 g_TxFIFOadd = USB_TX_FIFO_START_ADDRESS;
639 g_RxFIFOadd = USB_RX_FIFO_START_ADDRESS;
640 /* initialize ep0 state*/
641 g_ep0_state = EP0_IDLE;
642 /* initialize test setting and test status structures */
643 os_memset((DEV_UINT32 *)(&g_u3d_setting), 0 , sizeof(struct USB_TEST_SETTING));
644 g_u3d_setting.speed = speed; /* reserve speed setting */
645 os_memset((DEV_UINT32 *)(&g_usb_status), 0 , sizeof(struct USB_TEST_STATUS));
646
647 for(i = 0; i < 2 * MAX_EP_NUM + 1; i++){
648 os_memset((DEV_UINT32 *)(&g_u3d_req[i]), 0 , sizeof(struct USB_REQ));
649 }
650 g_u3d_req[0].buf = g_dma_buffer[0];
651 g_u3d_status = READY;
652
653 //enable system global interrupt
654 mu3d_hal_system_intr_en();
655
656 //initialize EP0
657 u3d_init_ctrl();
658 u3d_ep0en();
659
660 g_run_stress = false;
661 g_insert_hwo = false;
662
663 #if !defined(USB_RISC_CACHE_ENABLED)
664 os_disableDcache();
665 #endif
666 }
667
668 void u3d_set_address(DEV_INT32 addr){
669
670 os_writel(U3D_DEVICE_CONF, (addr<<DEV_ADDR_OFST));
671 return;
672 }
673
674 void u3d_rxep_dis(DEV_INT32 ep_num){
675 os_writel(U3D_EPIECR, os_readl(U3D_EPIECR)|(BIT16 << ep_num));
676 }
677
678 /**
679 * u3d_ep_start_transfer - epn start to transfer data, do not be used in qmu mode
680 *@args -arg1:ep number, arg2: dir
681 */
682 void u3d_ep_start_transfer(DEV_INT32 ep_num, USB_DIR dir){
683
684 DEV_INT32 ep_index=0, length, maxp;
685 struct USB_EP_SETTING *ep_setting;
686 struct USB_REQ *req;
687 DEV_UINT8 *bp;
688 DEV_UINT8 need_zlp;
689
690 if(dir == USB_TX){
691 ep_index = ep_num;
692 }
693 else if(dir == USB_RX){
694 ep_index = ep_num + MAX_EP_NUM;
695 }
696 else{
697 BUG_ON(1);
698 }
699
700 ep_setting = &g_u3d_setting.ep_setting[ep_index];
701 req = &g_u3d_req[ep_index];
702
703 if(ep_setting->enabled){
704
705 if((dir == USB_TX) && (ep_num != 0)){
706
707 os_writel(U3D_EPIESR, os_readl(U3D_EPIESR)|(BIT0 << ep_num));
708 req->actual = 0;
709 req->complete = 0;
710
711 #if (BUS_MODE==PIO_MODE)
712 bp = req->buf + req->actual;
713
714 maxp = ep_setting->maxp;
715 need_zlp = 0;
716 if(req->count - req->actual > maxp){
717 length = ep_setting->maxp;
718 }
719 else{
720 length = req->count - req->actual;
721 }
722 req->actual += length;
723
724 need_zlp = ((req->actual == req->count) && (!(req->count % maxp)) && ep_num!=0);
725 mu3d_hal_write_fifo(ep_num, length, bp, maxp);
726
727 /* Here is really tricky, need to print this log to pass EPn PIO loopback
728 * No time to figure out why. Sorry~
729 */
730 printk("zlp=%d\n",need_zlp);
731 if(need_zlp) {
732 while(!(USB_ReadCsr32(U3D_TX1CSR0, ep_num) & TX_FIFOFULL)) {
733 os_printk(K_ALET, "send zlp\n");
734 mu3d_hal_write_fifo(ep_num, 0, bp, maxp);
735 break;
736 }
737 }
738 #endif
739 }
740 else if(dir == USB_RX){
741 req->actual = 0;
742 req->complete = 0;
743 req->count = USB_BUF_SIZE;
744 os_writel(U3D_EPIESR, os_readl(U3D_EPIESR)|(BIT16 << ep_num));
745 }
746 else{
747 BUG_ON(1);
748 }
749 } else {
750 os_printk(K_ALET,"EP%d is not enabled\n", ep_num);
751 BUG_ON(1);
752 }
753
754 return;
755 }
756
757
758 DEV_UINT8 u3d_command(void){
759 return Request->bCommand;
760 }
761
762 void *u3d_req_buffer(void){
763 return AT_CMD->buffer;
764 }
765
766 void u3d_alloc_req(void){
767 Request=(DEV_REQ *)os_mem_alloc(sizeof(DEV_REQ));
768 Request->buffer=(DEV_UINT8 *)os_mem_alloc(2048);
769 AT_CMD=(DEV_AT_CMD *)os_mem_alloc(sizeof(DEV_AT_CMD));
770 AT_CMD->buffer=(DEV_UINT8 *)os_mem_alloc(2048);
771 }
772
773
774 DEV_UINT8 u3d_req_valid(void){
775 return Request->bValid;
776 }
777
778 void u3d_rst_request(void)
779 {
780 os_printk(K_ERR, "%s\n", __func__);
781
782 Request->bmRequestType=0;
783 Request->bRequest=0;
784 Request->wValue=0;
785 Request->wIndex=0;
786 Request->wLength=0;
787 Request->bValid=0;
788 }
789
790 void dev_power_mode(DEV_INT32 mode, DEV_INT8 u1_value, DEV_INT8 u2_value, DEV_INT8 en_u1, DEV_INT8 en_u2){
791 u3d_power_mode(mode,u1_value,u2_value,en_u1, en_u2);
792 }
793
794 void dev_send_one_packet(DEV_INT32 ep_tx){
795
796 struct USB_REQ *req;
797 dma_addr_t mapping;
798 DEV_UINT8* dma_buf;
799
800 req = mu3d_hal_get_req(ep_tx, USB_TX);
801 dma_buf = g_loopback_buffer[0];
802 req->buf = g_loopback_buffer[0];
803 os_memset(req->buf, 0 , 1000000);
804 mapping = dma_map_single(NULL, dma_buf,g_dma_buffer_size, DMA_BIDIRECTIONAL);
805 dma_sync_single_for_device(NULL, mapping, g_dma_buffer_size, DMA_BIDIRECTIONAL);
806 req->dma_adr = mapping;
807 req->count = 1024;
808 mu3d_hal_insert_transfer_gpd(ep_tx,USB_TX, req->dma_adr, req->count , true, true, false, false, 1024);
809 mu3d_hal_resume_qmu(ep_tx, USB_TX);
810 mapping=req->dma_adr;
811 dma_sync_single_for_cpu(NULL, mapping, g_dma_buffer_size, DMA_BIDIRECTIONAL);
812 dma_unmap_single(NULL, mapping, g_dma_buffer_size,DMA_BIDIRECTIONAL);
813 }
814
815 void dev_send_erdy(DEV_INT8 opt,DEV_INT32 ep_rx , DEV_INT32 ep_tx){
816 if(opt==6){
817 //send ERDY until LTSSM goes to U1/U2
818 while ((os_readl(U3D_LINK_STATE_MACHINE)&LTSSM) == STATE_U0_STATE);
819 os_writel(U3D_USB3_SW_ERDY, (ep_tx<<2)|SW_SEND_ERDY);
820 }
821 }
822
823 void dev_receive_ep0_test_packet(DEV_INT8 opt){
824 unsigned long flags;
825
826 if(opt==1){
827
828 spin_lock_irqsave(&_lock, flags);
829 os_writel(U3D_EP0CSR, os_readl(U3D_EP0CSR) & (~EP0_DMAREQEN));
830 while(!(os_readl(U3D_EP0CSR)&EP0_SETUPPKTRDY));
831 mu3d_hal_read_fifo(0,g_u3d_req[0].buf);
832 os_ms_delay(3000);
833 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DATAEND);
834 os_writel(U3D_EP0CSR, os_readl(U3D_EP0CSR) | EP0_DMAREQEN); // protect for PIO mode
835 spin_unlock_irqrestore(&_lock, flags);
836 }
837 }
838
839
840 void dev_u1u2_en_cond(DEV_INT8 opt,DEV_INT8 cond,DEV_INT32 ep_rx , DEV_INT32 ep_tx){
841
842 struct USB_REQ *treq, *rreq;
843 dma_addr_t mapping;
844 DEV_UINT32 temp, maxp;
845 DEV_UINT8* dma_buf,zlp;
846
847 rreq = mu3d_hal_get_req(ep_rx, USB_RX);
848 treq = mu3d_hal_get_req(ep_tx, USB_TX);
849 dma_buf = g_loopback_buffer[0];
850 treq->buf =rreq->buf =g_loopback_buffer[0];
851 os_memset(rreq->buf, 0 , 1000000);
852 mapping = dma_map_single(NULL, dma_buf,g_dma_buffer_size, DMA_BIDIRECTIONAL);
853 dma_sync_single_for_device(NULL, mapping, g_dma_buffer_size, DMA_BIDIRECTIONAL);
854 treq->dma_adr=rreq->dma_adr=mapping;
855 treq->count=rreq->count=0x1000;
856 zlp = (USB_ReadCsr32(U3D_TX1CSR1, ep_tx) & TYPE_ISO) ? false : true;
857 maxp = USB_ReadCsr32(U3D_RX1CSR0, ep_rx) & RX_RXMAXPKTSZ;
858
859 if(cond){
860 if(opt==2){
861 mu3d_hal_insert_transfer_gpd(ep_tx,USB_TX, treq->dma_adr,treq->count , true, true, false, zlp, maxp);
862 mu3d_hal_resume_qmu(ep_tx, USB_TX);
863 }
864 if(opt==3){
865 mu3d_hal_insert_transfer_gpd(ep_rx,USB_RX, rreq->dma_adr, rreq->count, true, true, false, zlp, maxp);
866 mu3d_hal_resume_qmu(ep_rx, USB_RX);
867 }
868 if(opt==4){
869 temp = USB_ReadCsr32(U3D_TX1CSR0, ep_tx) & 0xFFFEFFFF;
870 USB_WriteCsr32(U3D_TX1CSR0, ep_tx, (temp &~ TX_DMAREQEN) | TX_AUTOSET);
871 os_writel(U3D_QGCSR, 0);
872 os_memset(treq->buf, 0xff , 1000000);
873 treq->count=2048;
874 mu3d_hal_write_fifo_burst(ep_tx,treq->count,treq->buf, maxp);
875 }
876 } else {
877 mu3d_hal_stop_qmu(ep_tx, USB_TX);
878 while((os_readl(USB_QMU_TQCSR(ep_tx)) & (QMU_Q_ACTIVE)));
879 mu3d_hal_stop_qmu(ep_rx, USB_RX);
880 while((os_readl(USB_QMU_RQCSR(ep_rx)) & (QMU_Q_ACTIVE)));
881 }
882 mapping=rreq->dma_adr;
883 dma_sync_single_for_cpu(NULL, mapping, g_dma_buffer_size, DMA_BIDIRECTIONAL);
884 dma_unmap_single(NULL, mapping, g_dma_buffer_size,DMA_BIDIRECTIONAL);
885 }
886
887 void dev_u1u2_en_ctrl(DEV_INT8 type,DEV_INT8 u_num,DEV_INT8 opt,DEV_INT8 cond,DEV_INT8 u1_value, DEV_INT8 u2_value){
888
889 DEV_INT32 temp,ux_en_ctrl,ux_base;
890
891 os_printk(K_ALET,"type :%d\n",type);
892 os_printk(K_ALET,"u_num :%d\n",u_num);
893 os_printk(K_ALET,"opt :%d\n",opt);
894 os_printk(K_ALET,"cond :%d\n",cond);
895 os_printk(K_ALET,"value1 :%d\n",u1_value);
896 os_printk(K_ALET,"value2 :%d\n",u2_value);
897
898
899 ux_en_ctrl = (u_num == 1) ? U3D_MAC_U1_EN_CTRL : U3D_MAC_U2_EN_CTRL;
900 ux_base = (type == 2) ? 16 : 0;
901
902 if(opt==6){
903 temp = (!cond) ? cond : EXIT_BY_ERDY_DIS;
904 os_writel(ux_en_ctrl, temp);
905 }
906 else if(opt==1){
907 temp = (!cond) ? cond : 1<<(opt+ux_base-1);
908 os_writel(ux_en_ctrl, temp);
909 }
910 else{
911 if(opt){
912 os_writel(ux_en_ctrl, 1<<(opt+ux_base-1));
913 }
914 }
915
916 if(type == 1){// request
917
918 if(u_num == 1){
919 os_writel(U3D_LINK_POWER_CONTROL, SW_U1_REQUEST_ENABLE);
920 }
921 if(u_num == 2){
922 os_writel(U3D_LINK_POWER_CONTROL, SW_U2_REQUEST_ENABLE);
923 }
924 temp = os_readl(U3D_LINK_UX_INACT_TIMER);
925 temp &= ~(DEV_U2_INACT_TIMEOUT_VALUE | U1_INACT_TIMEOUT_VALUE);
926 temp |= ((u1_value)|(u2_value<<16));
927 os_writel(U3D_LINK_UX_INACT_TIMER, temp);
928 }
929 if(type == 2){// accept
930 if(u_num == 1){
931 os_writel(U3D_LINK_POWER_CONTROL, SW_U1_ACCEPT_ENABLE);
932 }
933 if(u_num == 2){
934 os_writel(U3D_LINK_POWER_CONTROL, SW_U2_ACCEPT_ENABLE);
935 }
936 }
937 if(type == 3){// end
938 os_writel(U3D_LINK_UX_INACT_TIMER, 0);
939 os_writel(U3D_LINK_POWER_CONTROL, 0);
940 os_writel(U3D_MAC_U1_EN_CTRL, 0);
941 os_writel(U3D_MAC_U2_EN_CTRL, 0);
942 }
943 }
944
945 #define STS_CHK_CLEAR 0
946 #define STS_CHK_U1 1
947 #define STS_CHK_U2 2
948 #define STS_CHK_U1_REJECT 3
949 #define STS_CHK_U2_REJECT 4
950 #define STS_CHK_HOT_RST 5
951 #define STS_CHK_WARM_RST 6
952 #define STS_CHK_FORCE_LINK_PM_ACPT 7
953 #define STS_CHK_RX_LEN_ERR 8
954 DEV_INT8 dev_stschk(DEV_INT8 type, DEV_INT8 change){
955 DEV_UINT32 cnt = 0;
956
957 switch (type)
958 {
959 case STS_CHK_CLEAR: //clear mode
960 //reset counter
961 #ifdef SUPPORT_U3
962 if (!(os_readl(U3D_SSUSB_U3_CTRL_0P) & SSUSB_U3_PORT_PDN))
963 {
964 os_writel(U3D_USB3_U1_STATE_INFO, CLR_USB3_U1_CNT);
965 os_writel(U3D_USB3_U2_STATE_INFO, CLR_USB3_U2_CNT);
966 os_writel(U3D_USB3_U1_REJECT, CLR_USB3_U1_REJECT_CNT);
967 os_writel(U3D_USB3_U2_REJECT, CLR_USB3_U2_REJECT_CNT);
968 }
969
970 g_hot_rst_cnt = 0;
971 g_warm_rst_cnt = 0;
972 #endif
973 g_rx_len_err_cnt = 0;
974 break;
975 #ifdef SUPPORT_U3
976 case STS_CHK_U1: //U1
977 cnt = os_readl(U3D_USB3_U1_STATE_INFO)&USB3_U1_CNT;
978 break;
979 case STS_CHK_U2: //U2
980 cnt = os_readl(U3D_USB3_U2_STATE_INFO)&USB3_U2_CNT;
981 break;
982 case STS_CHK_U1_REJECT: //U1_reject
983 cnt = os_readl(U3D_USB3_U1_REJECT)&USB3_U1_REJECT_CNT;
984 break;
985 case STS_CHK_U2_REJECT: //U2_reject
986 cnt = os_readl(U3D_USB3_U2_REJECT)&USB3_U2_REJECT_CNT;
987 break;
988 case STS_CHK_HOT_RST: //hot reset
989 cnt = g_hot_rst_cnt;
990 break;
991 case STS_CHK_WARM_RST: //warm reset
992 cnt = g_warm_rst_cnt;
993 break;
994 case STS_CHK_FORCE_LINK_PM_ACPT: //force link pm
995 cnt = (os_readl(U3D_HOST_SET_PORT_CTRL) & FORCE_LINK_PM_ACPT) ? 1 : 0;
996 break;
997 #endif
998 case STS_CHK_RX_LEN_ERR: //RX length error
999 cnt = g_rx_len_err_cnt;
1000 break;
1001 }
1002
1003
1004 //cnt should be greater than 0 if change is expected
1005 //cnt should be 0 if change is not expected
1006 os_printk(K_NOTICE, "type: %d, change: %d, cnt: %x\n", type, change, cnt);
1007 if ((change && cnt) || (!change && !cnt) || (type == 0))
1008 return RET_SUCCESS; //RET_SUCCESS
1009 else
1010 return RET_FAIL; //RET_FAIL
1011 }
1012
1013 void dev_lpm_config_dev(LPM_INFO *lpm_info){
1014 #define LPM_MODE_NORMAL 0
1015 #define LPM_MODE_FRC_REJECT 1
1016 #define LPM_MODE_FRC_ACCEPT 2
1017 #define LPM_MODE_FRC_TIMEOUT 3
1018 #define LPM_MODE_FRC_STALL 4
1019 #define LPM_MODE_HW_LPM 5
1020 #define LPM_RESUME_HOST 0
1021 #define LPM_RESUME_DEVICE_SW 1
1022 #define LPM_RESUME_DEVICE_HW 2
1023 #define LPM_RESUME_DEVICE_SW_2 3
1024 #define LPM_INACT_EP0 0
1025 #define LPM_INACT_TXQ 1
1026 #define LPM_INACT_RXQ 2
1027 #define LPM_INACT_BMU_TX 3
1028 #define LPM_INACT_BMU_RX 4
1029
1030 DEV_UINT32 dwTemp;
1031
1032 os_printk(K_ALET,"dev_lpm_config_dev\n");
1033 os_printk(K_ALET,"lpm_mode: %d\n",lpm_info->lpm_mode);
1034 os_printk(K_ALET,"wakeup: %d\n",lpm_info->wakeup);
1035 os_printk(K_ALET,"beslck: %d\n",lpm_info->beslck);
1036 os_printk(K_ALET,"beslck_u3: %d\n",lpm_info->beslck_u3);
1037 os_printk(K_ALET,"besldck: %d\n",lpm_info->besldck);
1038 os_printk(K_ALET,"cond: %d\n",lpm_info->cond);
1039 os_printk(K_ALET,"cond_en: %d\n",lpm_info->cond_en);
1040 os_printk(K_ALET,"\n");
1041
1042
1043 //LPM_MODE
1044 os_writel(U3D_POWER_MANAGEMENT,
1045 (os_readl(U3D_POWER_MANAGEMENT) &~ LPM_MODE)
1046 | (((lpm_info->lpm_mode == LPM_MODE_HW_LPM) ? LPM_MODE_NORMAL : lpm_info->lpm_mode)<<8));
1047
1048 //LPM_FORCE_STALL
1049 os_writel(U3D_USB2_TEST_MODE,
1050 (os_readl(U3D_USB2_TEST_MODE) & ~(FIFO_ACCESS | LPM_FORCE_STALL))
1051 | ((lpm_info->lpm_mode == LPM_MODE_FRC_STALL) ? LPM_FORCE_STALL : 0));
1052
1053
1054 //RESUME method
1055 //HRWE
1056 #if 1
1057 os_writel(U3D_POWER_MANAGEMENT,
1058 (os_readl(U3D_POWER_MANAGEMENT) &~ LPM_HRWE)
1059 | ((lpm_info->wakeup == LPM_RESUME_DEVICE_HW) ? LPM_HRWE : 0));
1060 #else
1061 //enable HRWE by default; let RWE bit in LPM token decides if remote wakeup is enabled
1062 os_writel(U3D_POWER_MANAGEMENT, os_readl(U3D_POWER_MANAGEMENT) | LPM_HRWE);
1063 #endif
1064 //EXIT CHK
1065 os_writel(U3D_USB2_EPCTL_LPM,
1066 ((lpm_info->wakeup == LPM_RESUME_DEVICE_HW) ?
1067 (L1_EXIT_EP0_CHK | L1_EXIT_EP_IN_CHK | L1_EXIT_EP_OUT_CHK) : 0));
1068
1069 //SW REMOTE WAKEUP
1070 g_sw_rw = (lpm_info->wakeup == LPM_RESUME_DEVICE_SW) ? 1 : 0;
1071 //SW REMOTE WAKEUP TEST MODE, drive resume before entering suspend
1072 if (lpm_info->wakeup == LPM_RESUME_DEVICE_SW_2)
1073 {
1074 os_writel(U3D_POWER_MANAGEMENT, os_readl(U3D_POWER_MANAGEMENT) | RESUME);
1075 }
1076 //HW REMOTE WAKEUP
1077 g_hw_rw = (lpm_info->wakeup == LPM_RESUME_DEVICE_HW) ? 1 : 0;
1078
1079
1080 //BESLCK <= BESLCK_U3 <= BESLDCK
1081 dwTemp = (((DEV_UINT32)lpm_info->beslck_u3<<BESLCK_U3_OFST) & BESLCK_U3)
1082 | (((DEV_UINT32)lpm_info->beslck<<BESLCK_OFST) & BESLCK)
1083 | (((DEV_UINT32)lpm_info->besldck<<BESLDCK_OFST) & BESLDCK);
1084 os_writel(U3D_USB20_LPM_PARAMETER, dwTemp);
1085
1086 //STALL or NYET
1087 os_writelmsk(U3D_POWER_MANAGEMENT,
1088 (lpm_info->beslck&0x10) ? LPM_BESL_STALL : 0, LPM_BESL_STALL);
1089 os_writelmsk(U3D_POWER_MANAGEMENT,
1090 (lpm_info->besldck&0x10) ? LPM_BESLD_STALL : 0, LPM_BESLD_STALL);
1091
1092
1093 //LPM INACTIVITY checker
1094 #if LPM_STRESS
1095 os_writel(U3D_MAC_U2_EN_CTRL, ACCEPT_EP0_INACTIVE_CHK);
1096 #else
1097 os_writel(U3D_MAC_U2_EN_CTRL,
1098 (os_readl(U3D_MAC_U2_EN_CTRL) & ~(0x1f<<16))
1099 | (lpm_info->cond_en ? 1<<(lpm_info->cond+16) : 0));
1100 #endif
1101 }
1102
1103 /**
1104 * reset_dev - device reset flow
1105 *
1106 */
1107 void reset_dev(USB_SPEED speed, DEV_UINT8 det_speed, DEV_UINT8 sw_rst){
1108 /* Reset usb ip. */
1109 if (g_usb_irq)
1110 {
1111 os_disableIrq(g_nirq);
1112 g_usb_irq = 0;
1113 }
1114
1115
1116 //reset or just disconnect IP
1117 if (sw_rst)
1118 {
1119 //reset
1120 mu3d_hal_rst_dev();
1121 }
1122 else
1123 {
1124 mu3d_hal_ssusb_en();
1125
1126 #ifdef SUPPORT_U3
1127 os_writel(U3D_USB3_CONFIG, 0);
1128 #endif
1129 mu3d_hal_u2dev_disconn();
1130
1131 //make sure speed_chg_intr is cleared before enabling U2 or U3 port again
1132 os_writel(U3D_DEV_LINK_INTR_ENABLE, 0);
1133 os_writel(U3D_DEV_LINK_INTR, SSUSB_DEV_SPEED_CHG_INTR);
1134 }
1135 os_ms_delay(50);
1136
1137
1138 //disable IP/U2 MAC/U3 MAC power down
1139 mu3d_hal_ssusb_en();
1140
1141 //apply default register values
1142 mu3d_hal_dft_reg();
1143
1144
1145 //set device speed
1146 mu3d_hal_set_speed(speed);
1147 //detect connect speed
1148 mu3d_hal_det_speed(speed, det_speed);
1149
1150
1151 //initialize device
1152 /*
1153 * Don't enable interrupt at this moment.
1154 * Before enable interrput, We should finish all the setting
1155 */
1156 /*u3d_irq_en();*/
1157 u3d_initialize_drv();
1158 #if (BUS_MODE==QMU_MODE)
1159 //initialize QMU
1160 mu3d_hal_init_qmu();
1161 #endif
1162
1163
1164 #ifdef POWER_SAVING_MODE
1165 //power down unused port
1166 mu3d_hal_pdn_cg_en();
1167 #endif
1168
1169 // USBIF
1170 u3d_irq_en();
1171 }
1172
1173 /**
1174 * u3d_stall_status - return stall status
1175 *
1176 */
1177
1178 DEV_UINT8 u3d_stall_status(void){
1179 DEV_UINT32 i, tx_ep_num, rx_ep_num;
1180 DEV_UINT8 ret;
1181
1182 #ifdef HARDCODE_EP
1183 tx_ep_num = MAX_QMU_EP;
1184 rx_ep_num = MAX_QMU_EP;
1185 #else
1186 tx_ep_num = os_readl(U3D_CAP_EPINFO) & CAP_TX_EP_NUM;
1187 rx_ep_num = (os_readl(U3D_CAP_EPINFO) & CAP_RX_EP_NUM) >> 8;
1188 #endif
1189
1190 ret = 0;
1191 for(i=1; i<=tx_ep_num; i++){
1192 if(USB_ReadCsr32(U3D_TX1CSR0, i) & TX_SENDSTALL){
1193 ret = 1;
1194 }
1195 if(USB_ReadCsr32(U3D_TX1CSR0, i) & TX_SENTSTALL){
1196 ret = 1;
1197 }
1198 }
1199 for(i=1; i<=rx_ep_num; i++){
1200 if(USB_ReadCsr32(U3D_RX1CSR0, i) & RX_SENDSTALL){
1201 ret = 1;
1202 }
1203 if(USB_ReadCsr32(U3D_TX1CSR0, i) & RX_SENTSTALL){
1204 ret = 1;
1205 }
1206 }
1207 return ret;
1208 }
1209
1210
1211 /**
1212 *
1213 * u3d_clear_stall_all - clear all stall
1214 */
1215
1216 void u3d_clear_stall_all(void){
1217 DEV_UINT32 i, tx_ep_num, rx_ep_num, tx_q_num, rx_q_num;
1218
1219 #ifdef HARDCODE_EP
1220 tx_q_num = tx_ep_num = MAX_QMU_EP;
1221 rx_q_num = rx_ep_num = MAX_QMU_EP;
1222 #else
1223 tx_q_num = tx_ep_num = os_readl(U3D_CAP_EPINFO) & CAP_TX_EP_NUM;
1224 rx_q_num = rx_ep_num = (os_readl(U3D_CAP_EPINFO) & CAP_RX_EP_NUM) >> 8;
1225 #endif
1226
1227 for(i=1; i<=tx_ep_num; i++){
1228 USB_WriteCsr32(U3D_TX1CSR0, i, USB_ReadCsr32(U3D_TX1CSR0, i) & ~TX_SENDSTALL);
1229 USB_WriteCsr32(U3D_TX1CSR0, i, USB_ReadCsr32(U3D_TX1CSR0, i) | TX_SENTSTALL);
1230 }
1231 for(i=1; i<=rx_ep_num; i++){
1232 USB_WriteCsr32(U3D_RX1CSR0, i, USB_ReadCsr32(U3D_RX1CSR0, i) & ~RX_SENDSTALL);
1233 USB_WriteCsr32(U3D_RX1CSR0, i, USB_ReadCsr32(U3D_RX1CSR0, i) | RX_SENTSTALL);
1234 }
1235
1236 for(i=1; i<=tx_q_num; i++){
1237
1238 mu3d_hal_flush_qmu(i,USB_TX);
1239 mu3d_hal_restart_qmu(i,USB_TX);
1240 }
1241 for(i=1; i<=rx_q_num; i++){
1242
1243 mu3d_hal_flush_qmu(i,USB_RX);
1244 mu3d_hal_restart_qmu(i,USB_RX);
1245 }
1246 }
1247
1248
1249 /**
1250 * u3d_stall_all - stall all epn
1251 *
1252 */
1253
1254 void u3d_stall_all(void){
1255 DEV_UINT32 i, tx_ep_num, rx_ep_num;
1256
1257 #ifdef HARDCODE_EP
1258 tx_ep_num = MAX_QMU_EP;
1259 rx_ep_num = MAX_QMU_EP;
1260 #else
1261 tx_ep_num = os_readl(U3D_CAP_EPINFO) & CAP_TX_EP_NUM;
1262 rx_ep_num = (os_readl(U3D_CAP_EPINFO) & CAP_RX_EP_NUM) >> 8;
1263 #endif
1264
1265 for(i=1; i<=tx_ep_num; i++){
1266 USB_WriteCsr32(U3D_TX1CSR0, i, USB_ReadCsr32(U3D_TX1CSR0, i) | TX_SENDSTALL);
1267 }
1268
1269 for(i=1; i<=rx_ep_num; i++){
1270 USB_WriteCsr32(U3D_RX1CSR0, i, USB_ReadCsr32(U3D_RX1CSR0, i) | RX_SENDSTALL);
1271 }
1272 }
1273
1274
1275 /**
1276 * u3d_send_ep0_stall - send an ep0 stall
1277 *
1278 */
1279
1280 void u3d_send_ep0_stall(void){
1281 //toggle EP0_RST
1282 // USBIF
1283 //os_setmsk(U3D_EP_RST, EP0_RST);
1284 //os_clrmsk(U3D_EP_RST, EP0_RST);
1285
1286 os_writel(U3D_EP0CSR, os_readl(U3D_EP0CSR) | EP0_SENDSTALL);
1287 while(!(os_readl(U3D_EP0CSR) & EP0_SENTSTALL));
1288 os_writel(U3D_EP0CSR, os_readl(U3D_EP0CSR) | EP0_SENTSTALL);
1289 }
1290
1291
1292 void u3d_dev_loopback(DEV_INT32 ep_rx,DEV_INT32 ep_tx){
1293 struct USB_REQ *treq, *rreq;
1294
1295 rreq = mu3d_hal_get_req(ep_rx, USB_RX);
1296 treq = mu3d_hal_get_req(ep_tx, USB_TX);
1297 treq->buf = g_loopback_buffer[0];
1298 rreq->buf = g_loopback_buffer[0];
1299 /* epn rx enable. */
1300 u3d_ep_start_transfer(ep_rx, USB_RX);
1301 os_printk(K_DEBUG,"RX start..\n");
1302 while(!req_complete(ep_rx, USB_RX));
1303 os_printk(K_DEBUG,"RX complete!!\n");
1304
1305 do{
1306 if(TransferLength > gpd_buf_size){
1307 treq->count = gpd_buf_size;
1308 TransferLength -= gpd_buf_size;
1309 }else{
1310 treq->count = TransferLength;
1311 TransferLength = 0;
1312 }
1313 /* epn start to transmit data. */
1314 u3d_ep_start_transfer(ep_tx, USB_TX);
1315 os_printk(K_DEBUG,"TX start..\n");
1316 while(!req_complete(ep_tx, USB_TX));
1317 treq->buf +=gpd_buf_size;
1318 }while(TransferLength>0);
1319
1320 os_printk(K_DEBUG,"TX complete!!\n");
1321 treq->count = rreq->actual =0;
1322 u3d_rxep_dis(ep_rx);
1323 }
1324
1325 DEV_UINT8 u3d_device_halt(void){
1326 return g_device_halt;
1327 }
1328
1329 void u3d_ep0_tx(void)
1330 {
1331 DEV_INT32 count, length, maxp;
1332 struct USB_EP_SETTING *ep_setting;
1333 struct USB_REQ *req;
1334 DEV_UINT8 *bp;
1335
1336 req = &g_u3d_req[0];
1337 ep_setting = &g_u3d_setting.ep_setting[0];
1338
1339 if (g_ep0_mode == PIO_MODE)
1340 {
1341 bp = req->buf + req->actual;
1342 maxp = ep_setting->maxp;
1343
1344 if(req->count - req->actual > maxp)
1345 length = ep_setting->maxp;
1346 else
1347 length = req->count - req->actual;
1348
1349 req->actual += length;
1350 count = mu3d_hal_write_fifo(0, length, bp, maxp);
1351
1352 if(!count)
1353 {
1354 g_ep0_state = EP0_IDLE;
1355 req->complete = 1;
1356 req->count = 0;
1357 req->actual = 0;
1358 }
1359
1360 os_printk(K_DEBUG,"count :%d\n",count);
1361 os_printk(K_DEBUG,"ep_setting->maxp :%d\n",ep_setting->maxp);
1362 os_printk(K_DEBUG,"needZLP :%d\n",g_u3d_req[0].needZLP);
1363 os_printk(K_DEBUG,"U3D_EP0CSR :%x\n", os_readl(U3D_EP0CSR));
1364 os_printk(K_DEBUG,"g_u3d_req[0].actual :%x\n",g_u3d_req[0].actual);
1365 os_printk(K_DEBUG,"g_u3d_req[0].count :%x\n",g_u3d_req[0].count);
1366 os_printk(K_DEBUG,"req->count :%d\n",req->count);
1367 os_printk(K_DEBUG,"req->actual :%d\n",req->count);
1368 }
1369 else
1370 {
1371 req = &g_u3d_req[0];
1372
1373 if(req->complete == 1)
1374 {
1375 os_printk(K_ERR,"1 completed!\r\n");
1376 u3d_free_dma0();
1377 }
1378 else
1379 {
1380 os_printk(K_DEBUG,"req->actual : %d\n",req->actual);
1381 os_printk(K_DEBUG,"req->count : %d\n",req->count);
1382 req->currentCount = ((req->count - req->actual) > ep_setting->maxp) ? ep_setting->maxp : req->count - req->actual;
1383
1384 if(req->actual >= req->count)
1385 {
1386 os_writel(U3D_EP0CSR, os_readl(U3D_EP0CSR) | EP0_DATAEND);
1387 os_printk(K_DEBUG,"USB_EP0_DATAEND\r\n");
1388 u3d_free_dma0();
1389 g_ep0_state = EP0_IDLE;
1390 req->complete = 1;
1391 os_printk(K_ERR, "2 completed\n");
1392 dma_sync_single_for_cpu(&mu3d_if_dev, (dma_addr_t)req->dma_adr, USB_BUF_SIZE, DMA_BIDIRECTIONAL);
1393 dma_unmap_single(&mu3d_if_dev, req->dma_adr, USB_BUF_SIZE, DMA_BIDIRECTIONAL);
1394 os_printk(K_DEBUG,"Dma han (02): EP[0] complete, send %d bytes\r\n", req->actual);
1395 }
1396 else
1397 {
1398 os_printk(K_DEBUG,"usb_config_dma 00\n");
1399 /* config ep0 tx dma channel */
1400 u3d_config_dma0(0, USB_TX, (DEV_UINT32)((u32)req->dma_adr + req->actual), req->currentCount);
1401 }
1402 }
1403 }
1404
1405 return;
1406 }
1407
1408 void u3d_ep0_rx(void)
1409 {
1410 DEV_UINT8 *ptr1;
1411 DEV_UINT8 *ptr2=0, *bp;
1412 DEV_INT32 count,i;
1413 struct USB_EP_SETTING *ep_setting;
1414 struct USB_REQ *req;
1415
1416 os_printk(K_DEBUG,"ep0 rx start !!\n");
1417
1418 ep_setting = &g_u3d_setting.ep_setting[0];
1419
1420 if (g_ep0_mode == PIO_MODE)
1421 {
1422 req = &g_u3d_req[0];
1423 bp = req->buf + req->actual;
1424 count = mu3d_hal_read_fifo(0,bp);
1425 req->actual += count;
1426
1427 if(Request->bRequest==AT_CMD_SET)
1428 {
1429 os_printk(K_DEBUG,"AT_CMD_SET\n");
1430 ptr1=(DEV_UINT8 *)AT_CMD;
1431 ptr2=req->buf;
1432
1433 for(i=0;i<AT_CMD_SET_BUFFER_OFFSET;i++)
1434 {
1435 *(ptr1+i)=*(ptr2+i);
1436 }
1437
1438 ptr1= AT_CMD->buffer;
1439 ptr2=req->buf;
1440
1441 for(i=0;i<(count-AT_CMD_SET_BUFFER_OFFSET);i++)
1442 {
1443 *(ptr1+i)=*(ptr2+i+AT_CMD_SET_BUFFER_OFFSET);
1444 }
1445
1446 g_u3d_status = BUSY;
1447 }
1448
1449 if((count < ep_setting->maxp)||(req->actual==req->count))
1450 {
1451 os_writel(U3D_EP0CSR, os_readl(U3D_EP0CSR) | EP0_DATAEND);
1452 g_ep0_state = EP0_IDLE;
1453 req->complete = 1;
1454 Request->bCommand=AT_CMD->tsfun;
1455
1456 if(Request->bRequest!=AT_CTRL_TEST) {
1457 os_printk(K_DEBUG,"bValid=1\n");
1458 Request->bValid=1;
1459 }
1460 }
1461 }
1462 else
1463 {
1464 req = &g_u3d_req[0];
1465 req->currentCount = os_readl(U3D_RXCOUNT0);
1466 os_printk(K_DEBUG,"RxCount : %d\n",os_readl(U3D_RXCOUNT0));
1467
1468 if(req->currentCount == 0)
1469 {
1470 req->complete = 1;
1471 u3d_free_dma0();
1472 }
1473 else
1474 {
1475 /* config ep0 rx dma channel */
1476 u3d_config_dma0(0, USB_RX, (DEV_UINT32)((u32)req->dma_adr + req->actual), req->currentCount);
1477 }
1478 }
1479
1480 return;
1481 }
1482
1483 DEV_UINT8* u3d_fill_in_buffer(DEV_UINT8 *ptr, DEV_UINT8 size, DEV_UINT8 *array)
1484 {
1485 DEV_UINT8 i;
1486
1487 for (i = 0; i < size; i++)
1488 *(ptr+i) = *(array+i);
1489
1490 return ptr+size;
1491 }
1492
1493 void u3d_ep0_idle(void){
1494 DEV_INT32 i;
1495 DEV_UINT32 word[8];
1496 struct USB_REQ *req;
1497 dma_addr_t mapping;
1498 DEV_UINT8 *ptr1;
1499
1500 req = mu3d_hal_get_req(0, USB_TX);
1501
1502 if(os_readl(U3D_RXCOUNT0) == 0){
1503 os_printk(K_ERR, "RXCOUNT == 0\n");
1504 return;
1505 }
1506
1507 if (g_ep0_mode == PIO_MODE)
1508 {
1509 /* decode command */
1510 for(i = 0; i < 2; i++)
1511 {
1512 word[i] = os_readl(USB_FIFO(0));
1513 }
1514 }
1515 else
1516 {
1517 req->currentCount=os_readl(U3D_RXCOUNT0);
1518 req->buf = g_dma_buffer[0];
1519
1520 mapping = dma_map_single(&mu3d_if_dev, req->buf, USB_BUF_SIZE, DMA_BIDIRECTIONAL);
1521 g_mu3d_dma_debug = mapping;
1522 dma_sync_single_for_device(&mu3d_if_dev, mapping, USB_BUF_SIZE, DMA_BIDIRECTIONAL);
1523 req->dma_adr = mapping;
1524 u3d_config_dma0(0, USB_RX, (u32)req->dma_adr, req->currentCount);
1525
1526 os_printk(K_DEBUG, "dma move\n");
1527
1528 return;
1529 }
1530
1531 Request->bmRequestType=(word[0]&0x000000FF);
1532 Request->bRequest=(word[0]&0x0000FF00)>>8;
1533 Request->wValue=((word[0]&0x00FF0000)>>16)|((word[0]&0xFF000000)>>16);
1534 Request->wIndex=(word[1]&0x000000FF)|(word[1]&0x0000FF00);
1535 Request->wLength=((word[1]&0x00FF0000)>>16)|((word[1]&0xFF000000)>>16);
1536
1537 os_printk(K_INFO,"Request->bmRequestType : %x \n",Request->bmRequestType);
1538 os_printk(K_INFO,"Request->bRequest : %x \n",Request->bRequest);
1539 os_printk(K_INFO,"Request->wValue : %x \n",Request->wValue);
1540 os_printk(K_INFO,"Request->wIndex : %x \n",Request->wIndex);
1541 os_printk(K_INFO,"Request->wLength : %x \n",Request->wLength);
1542
1543
1544 if (os_readl(U3D_EPISR) & SETUPENDISR) //SETUPEND
1545 {
1546 os_printk(K_ERR, "Abort this command because of SETUP\n");
1547 return;
1548 }
1549
1550
1551 if(((Request->bmRequestType&USB_TYPE_MASK)==USB_TYPE_STANDARD)&&
1552 (Request->bRequest==USB_REQ_SET_ADDRESS)){
1553
1554 u3d_set_address(Request->wValue);
1555 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DATAEND);
1556
1557 return;
1558 }
1559
1560 if(((Request->bmRequestType&USB_TYPE_MASK)==USB_TYPE_STANDARD)&&
1561 ((Request->bmRequestType&USB_RECIP_MASK)==USB_RECIP_ENDPOINT)){
1562
1563 if(Request->bmRequestType & USB_DIR_IN){
1564
1565 g_ep0_state = EP0_TX;
1566 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DPHTX);
1567
1568 if(Request->bRequest==USB_REQ_GET_STATUS){
1569 ptr1 = req->buf = g_dma_buffer[0];
1570 *ptr1 = u3d_stall_status();
1571 *(ptr1+1) = 0;
1572 req->count = USB_STATUS_SIZE;
1573 req->complete = 0;
1574 req->actual = 0;
1575 req->needZLP = 0;
1576 }
1577 if(Request->bRequest==USB_REQ_EP0_IN_STALL){
1578 g_ep0_state = EP0_IDLE;
1579 u3d_send_ep0_stall();
1580 return;
1581 }
1582 }
1583 else{
1584 if((Request->bRequest==USB_REQ_SET_FEATURE) &&
1585 (Request->wValue==ENDPOINT_HALT)){
1586 u3d_stall_all();
1587 g_device_halt = 1;
1588 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DATAEND);
1589 return;
1590 }
1591 if((Request->bRequest==USB_REQ_CLEAR_FEATURE) &&
1592 (Request->wValue==ENDPOINT_HALT)){
1593 u3d_clear_stall_all();
1594 g_device_halt = 0;
1595 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DATAEND);
1596 return;
1597 }
1598 if((Request->bRequest==USB_REQ_EP0_STALL) &&
1599 (Request->wValue==ENDPOINT_HALT)){
1600 u3d_send_ep0_stall();
1601 return;
1602 }
1603 if(Request->bRequest==USB_REQ_EP0_OUT_STALL){
1604 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY);
1605 u3d_send_ep0_stall();
1606 return;
1607 }
1608 }
1609
1610 }
1611
1612 if(Request->bmRequestType==0x00C0){
1613 g_ep0_state = EP0_TX;
1614 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DPHTX);
1615
1616 if(Request->bRequest==AT_CMD_ACK){
1617 os_printk(K_DEBUG, "AT_CMD_ACK valid=%x, %d\n", Request->bValid, g_u3d_status);
1618 ptr1 = req->buf = g_dma_buffer[0];
1619 *ptr1 = 0x55;
1620 *(ptr1+1) = 0xAA;
1621 *(ptr1+2) = AT_CMD_ACK_DATA_LENGTH&0xFF;
1622 *(ptr1+3) = AT_CMD_ACK_DATA_LENGTH>>8;
1623 *(ptr1+4) = (!Request->bValid) ? READY : BUSY;
1624 *(ptr1+5) = 0;
1625 *(ptr1+6) = g_u3d_status;
1626 *(ptr1+7) = 0;
1627
1628 req->count = AT_CMD_ACK_DATA_LENGTH;
1629 req->complete = 0;
1630 req->actual = 0;
1631 req->needZLP = 0;
1632 }
1633 else if(Request->bRequest==AT_CTRL_TEST){
1634 os_printk(K_DEBUG,"AT_CTRL_TEST\n");
1635
1636 #ifdef BOUNDARY_4K
1637 req->buf =loopback_buffer;
1638 #else
1639 req->buf =g_loopback_buffer[1];
1640 #endif
1641
1642 req->count = req->actual;
1643 req->complete = 0;
1644 req->actual = 0;
1645 req->needZLP = 0;
1646
1647 os_printk(K_DEBUG,"req->buf=%p\n",req->buf);
1648 }
1649 else if(Request->bRequest==AT_PW_STS_CHK)
1650 {
1651 os_printk(K_DEBUG, "AT_CMD_GET\n");
1652
1653 ptr1 = req->buf = g_dma_buffer[0];
1654 *ptr1 = 0x55;
1655 *(ptr1+1) = 0xAA;
1656 *(ptr1+2) = AT_PW_STS_CHK_DATA_LENGTH&0xFF;
1657 *(ptr1+3) = AT_PW_STS_CHK_DATA_LENGTH>>8;
1658 *(ptr1+4) = 0;
1659 *(ptr1+5) = 0;
1660 *(ptr1+6) = dev_stschk(Request->wIndex, Request->wValue);
1661 *(ptr1+7) = 0;
1662
1663 req->count = AT_PW_STS_CHK_DATA_LENGTH;
1664 req->complete = 0;
1665 req->actual = 0;
1666 req->needZLP = 0;
1667 }
1668
1669 os_printk(K_DEBUG,"g_u3d_req[0].count: %x \n",g_u3d_req[0].count);
1670 }
1671 else if(Request->bmRequestType==0x0040){
1672 g_ep0_state = EP0_RX;
1673 req->buf =g_loopback_buffer[1];
1674 #ifdef BOUNDARY_4K
1675 loopback_buffer = g_loopback_buffer[1]+(0x1000-(DEV_INT32)(unsigned long)g_loopback_buffer[1]%0x1000)-0x08+bAddress_Offset;
1676 bAddress_Offset++;
1677 bAddress_Offset%=4;
1678 req->buf =loopback_buffer;
1679 #else
1680 req->buf =g_loopback_buffer[1];
1681 #endif
1682 req->count = Request->wLength;
1683 req->complete = 0;
1684 req->actual = 0;
1685 req->needZLP = 0;
1686 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY);
1687 os_printk(K_DEBUG,"EP0 RX\n");
1688 }
1689
1690 if(g_ep0_state == EP0_IDLE){ //no data phase
1691
1692 g_u3d_req[0].complete = 1;
1693 }
1694 else if(g_ep0_state == EP0_TX){//data phase in
1695
1696 os_printk(K_DEBUG,"u3d_ep0_tx 0 \n");
1697 u3d_ep0_tx();
1698 }
1699 return;
1700
1701 }
1702
1703 void u3d_ep0_handler(void){
1704 //starts for EP0_IDLE for normal and abnormal case (SETUPEND)
1705 if (os_readl(U3D_EP0CSR) & EP0_SETUPPKTRDY){
1706 os_printk(K_DEBUG, "EP0_IDLE\n");
1707 u3d_ep0_idle();
1708 }
1709 else if(g_ep0_state == EP0_RX){
1710 os_printk(K_DEBUG, "EP0_IDLE RX\n");
1711 u3d_ep0_rx();
1712 }
1713 else if(g_ep0_state == EP0_TX){
1714 os_printk(K_DEBUG, "EP0_IDLE TX\n");
1715 u3d_ep0_tx();
1716 }
1717
1718 return;
1719 }
1720
1721
1722 void u3d_epx_handler(DEV_INT32 ep_num, USB_DIR dir){
1723
1724 DEV_INT32 ep_index, maxp, length;
1725 #if (BUS_MODE!=QMU_MODE)
1726 DEV_INT32 count;
1727 #endif
1728 DEV_UINT8 *bp;
1729 struct USB_EP_SETTING *ep_setting;
1730 struct USB_REQ *req;
1731
1732 os_printk(K_DEBUG,"ep_num :%x\n",ep_num);
1733 os_printk(K_DEBUG,"dir :%x\n",dir);
1734
1735 if(dir == USB_TX){
1736 ep_index = ep_num;
1737 ep_setting = &g_u3d_setting.ep_setting[ep_index];
1738 req = &g_u3d_req[ep_index];
1739 maxp = ep_setting->maxp;
1740 os_printk(K_DEBUG,"g_u3d_req[%d].buf@0x%p\n", ep_index, g_u3d_req[ep_index].buf);
1741 #if (BUS_MODE==PIO_MODE)
1742 bp = req->buf + req->actual;
1743 length = req->count - req->actual;
1744
1745 if(req->actual == req->count){
1746 req->count = 0;
1747 req->actual = 0;
1748 req->complete = 1;
1749 }
1750 else{
1751 count = mu3d_hal_write_fifo_burst(ep_num,length,bp, maxp);
1752 req->actual += count;
1753
1754 if((req->actual == req->count)&&(!(req->count % maxp))){
1755 mu3d_hal_write_fifo_burst(ep_num,0,bp, maxp);
1756 }
1757 }
1758
1759 #endif
1760 }
1761 else if(dir == USB_RX){
1762
1763 ep_index = ep_num + MAX_EP_NUM;
1764 ep_setting = &g_u3d_setting.ep_setting[ep_index];
1765 req = &g_u3d_req[ep_index];
1766 #if (BUS_MODE==PIO_MODE)
1767 bp = req->buf + req->actual;
1768 count = mu3d_hal_read_fifo_burst(ep_num,bp);
1769 req->actual += count;
1770 #endif
1771 if(req->actual==TransferLength){
1772 req->complete = 1;
1773 }
1774 } else {
1775 BUG_ON(1);
1776 }
1777
1778 return;
1779 }
1780
1781
1782 /**
1783 * u3d_dma_handler - receive setup in idle state, data phase in(TX) in tx state, data phase out(RX) in rx state
1784 *
1785 */
1786 void u3d_dma_handler(DEV_INT32 DMAIntSts){
1787
1788 struct USB_REQ *req;
1789 DEV_INT32 ep_index, ep_num, i, count;
1790 DEV_INT16 dir;
1791 DEV_UINT8 *ptr1;
1792 DEV_UINT8 *ptr2;
1793 struct USB_EP_SETTING *ep_setting;
1794 dma_addr_t mapping;
1795
1796 if (DMAIntSts & EP0DMAISR) {//ep0
1797
1798 ep_index = ep_num = 0;
1799 ep_setting = &g_u3d_setting.ep_setting[ep_index];
1800 req = &g_u3d_req[ep_index];
1801 count = req->currentCount;
1802 dir = (os_readl(U3D_EP0DMACTRL)&DMA_DIR)>>1;
1803 os_printk(K_DEBUG,"req->actual :%d\n",req->actual);
1804 os_printk(K_DEBUG,"req->currentCount :%d\n",req->currentCount);
1805 os_printk(K_DEBUG,"ep_setting->maxp :%d\n",ep_setting->maxp);
1806
1807 u3d_free_dma0();
1808
1809 if((os_readl(U3D_EP0CSR) & EP0_SETUPPKTRDY) //SETUPEND case; restarts from EP0_IDLE
1810 || (g_ep0_state == EP0_IDLE)){
1811 os_printk(K_ERR, "DMA EP0_IDLE\n");
1812 /* decode and handle ep0 setup packet*/
1813 mapping=req->dma_adr;
1814 dma_sync_single_for_cpu(&mu3d_if_dev, mapping, USB_BUF_SIZE, DMA_BIDIRECTIONAL);
1815 dma_unmap_single(&mu3d_if_dev, mapping, USB_BUF_SIZE,DMA_BIDIRECTIONAL);
1816 ptr1=req->buf;
1817 Request->bmRequestType=*ptr1;
1818 Request->bRequest=*(ptr1+1);
1819 Request->wValue=*(ptr1+2)|(*(ptr1+3)<<8);
1820 Request->wIndex=*(ptr1+4)|(*(ptr1+5)<<8);
1821 Request->wLength=*(ptr1+6)|(*(ptr1+7)<<8);
1822
1823 os_printk(K_DEBUG, "DMA move done\n");
1824 os_printk(K_DEBUG ,"Request->bmRequestType : %x \n",Request->bmRequestType);
1825 os_printk(K_DEBUG ,"Request->bRequest : %x \n",Request->bRequest);
1826 os_printk(K_DEBUG ,"Request->wValue : %x \n",Request->wValue);
1827 os_printk(K_DEBUG ,"Request->wIndex : %x \n",Request->wIndex);
1828 os_printk(K_DEBUG ,"Request->wLength : %x \n",Request->wLength);
1829
1830
1831 if (os_readl(U3D_EPISR) & SETUPENDISR) //SETUPEND
1832 {
1833 os_printk(K_ERR, "Abort this command because of SETUP\n");
1834 return;
1835 }
1836
1837
1838 if ((Request->bmRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
1839 {
1840 //DEVICE
1841 if ((Request->bmRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE)
1842 {
1843 //0x0
1844 if (Request->bRequest == USB_REQ_GET_STATUS)
1845 {
1846 printk("==DEV - USB_REQ_GET_STATUS==\n");
1847 ptr1 = req->buf = g_dma_buffer[0];
1848
1849 //OTG status
1850 // USBIF OTG , HNP polling
1851 if (Request->wIndex == 0xf000)
1852 {
1853 os_printk(K_ERR, "g_otg_hnp_reqd = %d %s)\n", g_otg_hnp_reqd, __func__);
1854 mb();
1855 if (g_otg_hnp_reqd)
1856 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(string_one), string_one);
1857 else
1858 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(string_zero), string_zero);
1859 }
1860
1861 req->count = ptr1 - req->buf;
1862 // os_printk(K_ERR, "length: %d\n", req->count);
1863 req->complete = 0;
1864 req->actual = 0;
1865 req->needZLP = 0;
1866
1867 mapping = dma_map_single(&mu3d_if_dev, req->buf,USB_BUF_SIZE, DMA_BIDIRECTIONAL);
1868 dma_sync_single_for_device(&mu3d_if_dev, mapping, USB_BUF_SIZE, DMA_BIDIRECTIONAL);
1869 req->dma_adr=mapping;
1870
1871 g_ep0_state = EP0_TX;
1872 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DPHTX);
1873 }
1874
1875 #ifdef SUPPORT_OTG
1876 //0x1
1877 if (Request->bRequest == USB_REQ_CLEAR_FEATURE)
1878 {
1879 printk("==DEV - USB_REQ_CLEAR_FEATURE==\n");
1880 //B_HNP_ENABLE
1881 if (Request->wValue == 0x0003)
1882 {
1883 g_ep0_state = EP0_IDLE;
1884 u3d_send_ep0_stall();
1885 }
1886 }
1887
1888 //0x3
1889 if (Request->bRequest == USB_REQ_SET_FEATURE)
1890 {
1891 printk("==DEV - USB_REQ_SET_FEATURE==\n");
1892 printk("Request wValue = 0x%x, Request wIndex = 0x%x\n", Request->wValue, Request->wIndex);
1893 //TEST_MODE
1894 if (Request->wValue == 0x0002)
1895 {
1896 //otg_srp_reqd
1897 if (Request->wIndex == 0x600)
1898 {
1899 printk("== set g_otg_srp_reqd = 1 ==\n");
1900 g_otg_srp_reqd = 1;
1901 mb() ;
1902 os_printk(K_ERR, "g_otg_srp_reqd = 1\n");
1903 }
1904 else if (Request->wIndex == 0x700)
1905 {
1906 printk("== set g_otg_hnp_reqd = 1 ==\n");
1907 g_otg_hnp_reqd = 1;
1908
1909 mb() ;
1910 os_printk(K_ERR, "g_otg_hnp_reqd = 1 (%s)\n", __func__);
1911 }
1912 }
1913 //B_HNP_ENABLE
1914 else if (Request->wValue == 0x0003)
1915 {
1916 g_otg_b_hnp_enable = 1;
1917 mb() ;
1918 os_printk(K_ERR, "set g_otg_b_hnp_enable = 1 (%s)\n", __func__);
1919 }
1920
1921 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DATAEND);
1922
1923 }
1924 #endif
1925
1926 //0x5
1927 if (Request->bRequest == USB_REQ_SET_ADDRESS)
1928 {
1929 u3d_sync_with_bat(USB_UNCONFIGURED) ;
1930 printk("==DEV - USB_REQ_SET_ADDRESS==\n");
1931 #ifdef SUPPORT_OTG
1932 //g_otg_config = 0;
1933 //mb();
1934 #endif
1935
1936 /* set device address*/
1937 u3d_set_address(Request->wValue);
1938
1939 os_printk(K_DEBUG,"Device Address :%x\n",(os_readl(U3D_DEVICE_CONF)>>DEV_ADDR_OFST));
1940 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DATAEND);
1941 }
1942
1943 //0x6
1944 if (Request->bRequest == USB_REQ_GET_DESCRIPTOR)
1945 {
1946 printk("==DEV - USB_REQ_GET_DESCRIPTOR==\n");
1947 ptr1 = req->buf = g_dma_buffer[0];
1948
1949 //device
1950 if (Request->wValue == 0x100)
1951 {
1952 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(device_descriptor), device_descriptor);
1953 os_printk(K_ERR, "device_descriptor\n");
1954 }
1955 //configuration
1956 else if (Request->wValue == 0x200)
1957 {
1958 if (Request->wLength == 9)
1959 {
1960 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(configuration_descriptor), configuration_descriptor);
1961 os_printk(K_ERR, "configuration_descriptor\n");
1962 }
1963 else
1964 {
1965 //9 bytes
1966 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(configuration_descriptor), configuration_descriptor);
1967 //5 bytes
1968 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(otg_descriptor), otg_descriptor);
1969 //9 bytes
1970 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(interface_descriptor), interface_descriptor);
1971 //7 bytes
1972 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(endpoint_descriptor_in), endpoint_descriptor_in);
1973 //7 bytes
1974 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(endpoint_descriptor_out), endpoint_descriptor_out);
1975 os_printk(K_ERR, "5 descriptors\n");
1976 }
1977 }
1978 //string
1979 else if ((Request->wValue & 0xff00) == 0x300)
1980 {
1981 switch (Request->wValue & 0xff)
1982 {
1983 case 0:
1984 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(string_descriptor_0), string_descriptor_0);
1985 break;
1986 case 1:
1987 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(string_descriptor_1), string_descriptor_1);
1988 break;
1989 case 2:
1990 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(string_descriptor_2), string_descriptor_2);
1991 break;
1992 case 3:
1993 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(string_descriptor_3), string_descriptor_3);
1994 break;
1995 }
1996 }
1997 //OTG
1998 else if (Request->wValue == 0x900)
1999 {
2000 ptr1 = u3d_fill_in_buffer(ptr1, sizeof(otg_descriptor), otg_descriptor);
2001 }
2002
2003 req->count = ptr1 - req->buf;
2004 // os_printk(K_ERR, "length: %d\n", req->count);
2005 req->complete = 0;
2006 req->actual = 0;
2007 req->needZLP = 0;
2008
2009 mapping = dma_map_single(&mu3d_if_dev, req->buf,USB_BUF_SIZE, DMA_BIDIRECTIONAL);
2010 dma_sync_single_for_device(&mu3d_if_dev, mapping, USB_BUF_SIZE, DMA_BIDIRECTIONAL);
2011 req->dma_adr=mapping;
2012
2013 g_ep0_state = EP0_TX;
2014 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DPHTX);
2015 }
2016
2017 //0x9
2018 if (Request->bRequest == USB_REQ_SET_CONFIGURATION)
2019 {
2020 printk("==DEV - USB_REQ_SET_CONFIGURATION==\n");
2021 #ifdef SUPPORT_OTG
2022 g_otg_config = 1;
2023 mb() ;
2024 #endif
2025 printk("==DEV - USB_REQ_SET_CONFIGURATION== done, g_otg_config %d\n", g_otg_config);
2026
2027 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DATAEND);
2028
2029 // USBIF
2030 u3d_sync_with_bat(USB_CONFIGURED) ;
2031 }
2032 }
2033
2034
2035 //ENDPOINT
2036 if ((Request->bmRequestType & USB_RECIP_MASK) == USB_RECIP_ENDPOINT)
2037 {
2038 if (Request->bmRequestType & USB_DIR_IN)
2039 {
2040 g_ep0_state = EP0_TX;
2041 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DPHTX);
2042
2043 if (Request->bRequest == USB_REQ_GET_STATUS)
2044 {
2045 printk("==EP - USB_REQ_GET_STATUS==\n");
2046 ptr1 = req->buf = g_dma_buffer[0];
2047 *ptr1 = u3d_stall_status();
2048 *(ptr1+1) = 0x00;
2049 req->count = USB_STATUS_SIZE;
2050 req->complete = 0;
2051 req->actual = 0;
2052 req->needZLP = 0;
2053 mapping = dma_map_single(&mu3d_if_dev, req->buf,USB_BUF_SIZE, DMA_BIDIRECTIONAL);
2054 dma_sync_single_for_device(&mu3d_if_dev, mapping, USB_BUF_SIZE, DMA_BIDIRECTIONAL);
2055 req->dma_adr=mapping;
2056 }
2057
2058 if (Request->bRequest == USB_REQ_EP0_IN_STALL)
2059 {
2060 printk("==EP - USB_REQ_EP0_IN_STALL==\n");
2061 g_ep0_state = EP0_IDLE;
2062 u3d_send_ep0_stall();
2063 }
2064 }
2065 else
2066 {
2067 if((Request->bRequest==USB_REQ_SET_FEATURE) &&
2068 (Request->wValue == ENDPOINT_HALT))
2069 {
2070 printk("==EP - USB_REQ_SET_FEATURE to EP HALT==\n");
2071 u3d_stall_all();
2072 g_device_halt = 1;
2073 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DATAEND);
2074 }
2075
2076 if((Request->bRequest==USB_REQ_CLEAR_FEATURE) &&
2077 (Request->wValue == ENDPOINT_HALT))
2078 {
2079 printk("==EP - USB_REQ_CLEAR_FEATURE to EP HALT==\n");
2080 u3d_clear_stall_all();
2081 g_device_halt = 0;
2082 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY | EP0_DATAEND);
2083 }
2084
2085 if((Request->bRequest==USB_REQ_EP0_STALL) &&
2086 (Request->wValue == ENDPOINT_HALT))
2087 {
2088 printk("==EP - USB_REQ_EP0_STALL to EP HALT==\n");
2089 u3d_send_ep0_stall();
2090 }
2091
2092 if (Request->bRequest == USB_REQ_EP0_OUT_STALL)
2093 {
2094 printk("==EP - USB_REQ_EP0_STALL==\n");
2095 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY);
2096 u3d_send_ep0_stall();
2097 }
2098 }
2099 }
2100 }
2101
2102
2103 if (Request->bmRequestType == USB_TYPE_VENDOR)
2104 {
2105 if (Request->bmRequestType & USB_DIR_IN)
2106 {
2107 os_printk(K_DEBUG,"EP0_TX \n");
2108 g_ep0_state = EP0_TX;
2109 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR)| EP0_SETUPPKTRDY | EP0_DPHTX);
2110
2111 if (Request->bRequest == AT_CMD_ACK)
2112 {
2113 os_printk(K_DEBUG,"AT_CMD_ACK valid: %x \n",Request->bValid);
2114
2115 /* handle AT_CMD_ACK status*/
2116 ptr1 = req->buf = g_dma_buffer[0];
2117 *ptr1 = 0x55;
2118 *(ptr1+1) = 0xAA;
2119 *(ptr1+2) = AT_CMD_ACK_DATA_LENGTH&0xFF;
2120 *(ptr1+3) = AT_CMD_ACK_DATA_LENGTH>>8;
2121 *(ptr1+4) = (!Request->bValid) ? READY : BUSY;
2122 *(ptr1+5) = 0;
2123 *(ptr1+6) = g_u3d_status;
2124 *(ptr1+7) = 0;
2125
2126 req->count = AT_CMD_ACK_DATA_LENGTH;
2127 req->complete = 0;
2128 req->actual = 0;
2129 req->needZLP = 0;
2130 }
2131 else if (Request->bRequest == AT_CTRL_TEST)
2132 {
2133 os_printk(K_DEBUG,"AT_CTRL_TEST\n");
2134
2135 /* handle AT_CTRL_TEST for unit test ctrl loopback*/
2136 #ifdef BOUNDARY_4K
2137 req->buf =loopback_buffer;
2138 #else
2139 req->buf =g_loopback_buffer[1];
2140 #endif
2141
2142 req->count = req->actual;
2143 req->complete = 0;
2144 req->actual = 0;
2145 req->needZLP = 0;
2146 }
2147 else if(Request->bRequest==AT_PW_STS_CHK)
2148 {
2149 os_printk(K_DEBUG, "AT_CMD_GET\n");
2150
2151 ptr1 = req->buf = g_dma_buffer[0];
2152 *ptr1 = 0x55;
2153 *(ptr1+1) = 0xAA;
2154 *(ptr1+2) = AT_PW_STS_CHK_DATA_LENGTH&0xFF;
2155 *(ptr1+3) = AT_PW_STS_CHK_DATA_LENGTH>>8;
2156 *(ptr1+4) = 0;
2157 *(ptr1+5) = 0;
2158 *(ptr1+6) = dev_stschk(Request->wIndex, Request->wValue);
2159 *(ptr1+7) = 0;
2160
2161 req->count = AT_PW_STS_CHK_DATA_LENGTH;
2162 req->complete = 0;
2163 req->actual = 0;
2164 req->needZLP = 0;
2165 }
2166
2167 mapping = dma_map_single(&mu3d_if_dev, req->buf,USB_BUF_SIZE, DMA_BIDIRECTIONAL);
2168 dma_sync_single_for_device(&mu3d_if_dev, mapping, USB_BUF_SIZE, DMA_BIDIRECTIONAL);
2169 os_printk(K_INFO,"mapping : 0x%p\n",(void *)(unsigned long)mapping);
2170 req->dma_adr=mapping;
2171
2172 os_printk(K_DEBUG,"g_u3d_req[0].count: %x \n",g_u3d_req[0].count);
2173 }
2174 else
2175 {
2176 os_printk(K_DEBUG,"EP0_RX \n");
2177 g_ep0_state = EP0_RX;
2178
2179 #ifdef BOUNDARY_4K
2180 loopback_buffer = g_loopback_buffer[1]+(0x1000-(DEV_INT32)(unsigned long)g_loopback_buffer[1]%0x1000)-0x08+bAddress_Offset;
2181 bAddress_Offset++;
2182 bAddress_Offset%=4;
2183 req->buf =loopback_buffer;
2184 #else
2185 req->buf =g_loopback_buffer[1];
2186 #endif
2187
2188 req->count = Request->wLength;
2189 req->complete = 0;
2190 req->actual = 0;
2191 req->needZLP = 0;
2192 os_writel(U3D_EP0CSR,os_readl(U3D_EP0CSR) | EP0_SETUPPKTRDY);
2193
2194 mapping = dma_map_single(&mu3d_if_dev, req->buf,USB_BUF_SIZE, DMA_BIDIRECTIONAL);
2195 dma_sync_single_for_device(&mu3d_if_dev, mapping, USB_BUF_SIZE, DMA_BIDIRECTIONAL);
2196 os_printk(K_INFO,"req->buf: %p, mapping : 0x%p\n", req->buf, (void *)(unsigned long)mapping);
2197 req->dma_adr=mapping;
2198 }
2199 }
2200
2201
2202 if(g_ep0_state == EP0_IDLE) //no data phase
2203 g_u3d_req[0].complete = 1;
2204 else if(g_ep0_state == EP0_TX) //data in
2205 u3d_ep0_tx();
2206
2207 return;
2208 }
2209 else if(g_ep0_state == EP0_RX){
2210 /* handle data phase out(rx)*/
2211 os_printk(K_INFO, "DMA EP0_RX\n");
2212 req->actual += count;
2213 os_printk(K_DEBUG,"receive : %d\n",req->actual);
2214
2215 if(Request->bRequest==AT_CMD_SET){
2216
2217 ptr1=(DEV_UINT8 *)AT_CMD;
2218 ptr2=g_u3d_req[0].buf;
2219 for(i=0;i<AT_CMD_SET_BUFFER_OFFSET;i++){
2220 *(ptr1+i)=*(ptr2+i);
2221 }
2222 ptr1=AT_CMD->buffer;
2223 ptr2=g_u3d_req[0].buf;
2224 for(i=0;i<(count-AT_CMD_SET_BUFFER_OFFSET);i++){
2225 *(ptr1+i)=*(ptr2+i+AT_CMD_SET_BUFFER_OFFSET);
2226 }
2227 g_u3d_status = BUSY;
2228 }
2229 #ifndef AUTOCLEAR
2230 os_writel(U3D_EP0CSR, os_readl(U3D_EP0CSR)|EP0_RXPKTRDY);
2231 #endif
2232 if((count < ep_setting->maxp)||(req->actual==req->count)){
2233
2234 os_writel(U3D_EP0CSR, os_readl(U3D_EP0CSR) | EP0_DATAEND);
2235
2236 g_ep0_state = EP0_IDLE;
2237 req->complete = 1;
2238
2239 if(Request->bRequest!=AT_CTRL_TEST){
2240 Request->bValid=1;
2241 }
2242 os_printk(K_DEBUG,"bValid !!\n");
2243 Request->bCommand=AT_CMD->tsfun;
2244 dma_sync_single_for_cpu(&mu3d_if_dev, req->dma_adr, USB_BUF_SIZE, DMA_BIDIRECTIONAL);
2245 dma_unmap_single(&mu3d_if_dev, req->dma_adr, USB_BUF_SIZE, DMA_BIDIRECTIONAL);
2246 }
2247 }
2248 else if(g_ep0_state == EP0_TX){
2249 /* handle data phase in(tx)*/
2250 os_printk(K_INFO, "DMA EP0_TX\n");
2251 req->actual += req->currentCount;
2252 os_printk(K_DEBUG,"req->actual :%d\n",req->actual);
2253 os_printk(K_DEBUG,"req->currentCount :%d\n",req->currentCount);
2254 #ifdef AUTOSET
2255 if(req->currentCount<ep_setting->maxp){
2256 os_writel(U3D_EP0CSR, os_readl(U3D_EP0CSR)| EP0_TXPKTRDY);
2257 }
2258 #else
2259 os_writel(U3D_EP0CSR, os_readl(U3D_EP0CSR)| EP0_TXPKTRDY);
2260 #endif
2261 }
2262 }
2263
2264 return;
2265 }
2266
2267 // USBIF
2268 #if 0
2269 void mt_usb_disconnect(void)
2270 {
2271 os_printk(K_DEBUG,"[MUSB] USB is ready for disconnect\n");
2272
2273 os_printk(K_DEBUG,"[MUSB] USB disconnect\n");
2274 }
2275 EXPORT_SYMBOL_GPL(mt_usb_disconnect);
2276
2277 void mt_usb_connect(void)
2278 {
2279 os_printk(K_DEBUG,"[MUSB] USB is ready for connect\n");
2280
2281 os_printk(K_DEBUG,"[MUSB] USB connect\n");
2282 }
2283 EXPORT_SYMBOL_GPL(mt_usb_connect);
2284 #endif
2285
2286
2287
kernel source for telekom puls (alcatel/mediatek)