drivers/misc/mediatek/m4u/mt8127/m4u.c

   1 #include <mach/m4u.h>
   2 #include <mach/m4u_reg.h>
   3
   4 #include <linux/m4u_profile.h>
   5 #include "m4u_priv.h"
   6
   7 int m4u_dump_reg(int m4u_index)
   8 {
   9     return 0;
  10 }
  11 int m4u_power_on(int m4u_index)
  12 {
  13     return 0;
  14 }
  15
  16 int m4u_power_off(int m4u_index)
  17 {
  18     return 0;
  19 }
  20
  21
  22 int m4u_query_mva(M4U_MODULE_ID_ENUM eModuleID,
  23                                                                   const unsigned int BufAddr,
  24                                                                   const unsigned int BufSize,
  25                                                                   unsigned int *pRetMVABuf,
  26                                                                   struct file * a_pstFile)
  27 {
  28     return m4u_do_query_mva(eModuleID, BufAddr, BufSize, pRetMVABuf, a_pstFile);
  29 }
  30
  31
  32 int m4u_alloc_mva(M4U_MODULE_ID_ENUM eModuleID,
  33                                                                   const unsigned int BufAddr,
  34                                                                   const unsigned int BufSize,
  35                                                                   int security,
  36                                                                   int cache_coherent,
  37                                                                   unsigned int *pRetMVABuf)
  38 {
  39     mva_info_t *pMvaInfo = NULL;
  40     int ret;
  41     pMvaInfo=m4u_alloc_garbage_list(0,BufSize,eModuleID,BufAddr,0,security,cache_coherent);
  42     ret = __m4u_alloc_mva(pMvaInfo, NULL);
  43
  44     if(ret == 0)
  45     {
  46         *pRetMVABuf = pMvaInfo->mvaStart;
  47     }
  48     else
  49     {
  50         *pRetMVABuf = 0;
  51     }
  52     return ret;
  53 }
  54
  55
  56 int m4u_alloc_mva_sg(M4U_MODULE_ID_ENUM eModuleID,
  57                                                                   struct sg_table *sg_table,
  58                                                                   const unsigned int BufSize,
  59                                                                   int security,
  60                                                                   int cache_coherent,
  61                                                                   unsigned int *pRetMVABuf)
  62 {
  63     mva_info_t *pMvaInfo = NULL;
  64     int ret;
  65     pMvaInfo=m4u_alloc_garbage_list(0,BufSize,eModuleID,0,0,security,cache_coherent);
  66     ret = __m4u_alloc_mva(pMvaInfo, sg_table);
  67
  68     if(ret == 0)
  69     {
  70         *pRetMVABuf = pMvaInfo->mvaStart;
  71     }
  72     else
  73     {
  74         *pRetMVABuf = 0;
  75     }
  76     return ret;
  77 }
  78
  79 int m4u_dealloc_mva(M4U_MODULE_ID_ENUM eModuleID,
  80                                                                         const unsigned int BufAddr,
  81                                                                         const unsigned int BufSize,
  82                                                                         const unsigned int MVA)
  83 {
  84     return __m4u_dealloc_mva(eModuleID, BufAddr, BufSize, MVA, NULL);
  85 }
  86
  87 int m4u_dealloc_mva_sg(M4U_MODULE_ID_ENUM eModuleID,
  88                                                                         struct sg_table* sg_table,
  89                                                                         const unsigned int BufSize,
  90                                                                         const unsigned int MVA)
  91 {
  92     return __m4u_dealloc_mva(eModuleID, 0, BufSize, MVA, sg_table);
  93 }
  94
  95
  96 int m4u_insert_seq_range(M4U_MODULE_ID_ENUM eModuleID,
  97                              unsigned int MVAStart,
  98                              unsigned int MVAEnd,
  99                              M4U_RANGE_PRIORITY_ENUM ePriority,
 100                              unsigned int entryCount) //0:disable multi-entry, 1,2,4,8,16: enable multi-entry
 101 {
 102
 103     int ret;
 104
 105     MMProfileLogEx(M4U_MMP_Events[PROFILE_INSERT_TLB], MMProfileFlagStart, eModuleID, MVAStart);
 106     ret = m4u_do_insert_seq_range(eModuleID, MVAStart, MVAEnd, entryCount);
 107     MMProfileLogEx(M4U_MMP_Events[PROFILE_INSERT_TLB], MMProfileFlagEnd, eModuleID, MVAEnd-MVAStart+1);
 108
 109     return ret;
 110
 111 }
 112
 113 int m4u_invalid_seq_range(M4U_MODULE_ID_ENUM eModuleID, unsigned int MVAStart, unsigned int MVAEnd)
 114 {
 115     m4u_invalid_seq_range_by_mva(m4u_module_2_m4u_id(eModuleID), MVAStart, MVAEnd);
 116     return 0;
 117
 118 }
 119
 120
 121
 122 int m4u_insert_wrapped_range(M4U_MODULE_ID_ENUM eModuleID,
 123                              M4U_PORT_ID_ENUM portID,
 124                              unsigned int MVAStart,
 125                              unsigned int MVAEnd)
 126 {
 127     return 0;
 128 }
 129
 130 int m4u_invalid_wrapped_range(M4U_MODULE_ID_ENUM eModuleID,
 131                               M4U_PORT_ID_ENUM portID,
 132                               unsigned int MVAStart,
 133                               unsigned int MVAEnd)
 134 {
 135     return 0;
 136 }
 137
 138
 139
 140 int m4u_config_port(M4U_PORT_STRUCT* pM4uPort) //native
 141 {
 142     return m4u_do_config_port(pM4uPort);
 143 }
 144
 145
 146 int m4u_config_port_rotator(M4U_PORT_STRUCT_ROTATOR *pM4uPort)
 147 {
 148     return 0;
 149 }
 150
 151 int m4u_monitor_start(int m4u_id)
 152 {
 153     return m4u_do_monitor_start(m4u_id);
 154 }
 155
 156 int m4u_monitor_stop(int m4u_id)
 157 {
 158     return m4u_do_monitor_stop(m4u_id);
 159 }
 160
 161 int m4u_dma_cache_maint(M4U_MODULE_ID_ENUM eModuleID, const void *start, size_t size, int direction)
 162 {
 163     return m4u_do_dma_cache_maint(eModuleID, start, size, direction);
 164 }
 165
 166 extern void  smp_inner_dcache_flush_all(void);
 167 int m4u_dma_cache_flush_all()
 168 {
 169
 170     //mutex_lock(&gM4uMutex);
 171
 172     // L1 cache clean before hw read
 173     smp_inner_dcache_flush_all();
 174
 175         // L2 cache maintenance by physical pages
 176     outer_flush_all();
 177
 178     //mutex_unlock(&gM4uMutex);
 179
 180     return 0;
 181 }
 182
 183 int m4u_dump_info(int m4u_index)
 184 {
 185     return m4u_do_dump_info(m4u_index);
 186 }
 187
 188
 189 int m4u_log_on(void)
 190 {
 191     return m4u_do_log_on();
 192 }
 193
 194 int m4u_log_off(void)
 195 {
 196     return m4u_do_log_off();
 197 }
 198
 199 int m4u_mau_check_pagetable(unsigned int start_addr, unsigned int end_addr)
 200 {
 201     return 0;
 202 }
 203
 204 int m4u_mva_map_kernel(unsigned int mva, unsigned int size, int sec,
 205                         unsigned int* map_va, unsigned int* map_size)
 206 {
 207     return m4u_do_mva_map_kernel(mva, size, sec, map_va, map_size);
 208 }
 209
 210
 211 int m4u_mva_unmap_kernel(unsigned int mva, unsigned int size, unsigned int va)
 212 {
 213     return m4u_do_mva_unmap_kernel(mva, size, va);
 214 }
 215
 216 int m4u_sync_nonsec_sec_pgtable(unsigned int mva,
 217                                 unsigned int size,
 218                                 int port)
 219 {
 220   return m4u_do_sync_nonsec_sec_pgtable(mva, size, port);
 221 }
 222
 223 int m4u_debug_command(unsigned int command)
 224 {
 225     return m4u_do_debug_command(command);
 226 }
 227
 228