drivers/misc/mediatek/lcm/otm1283a/otm1283a_6589_hd_dsi.c

   1 #ifndef BUILD_LK
   2 #include <linux/string.h>
   3 #endif
   4 #include "lcm_drv.h"
   5
   6 #ifdef BUILD_LK
   7         #include <platform/mt_gpio.h>
   8 #elif defined(BUILD_UBOOT)
   9         #include <asm/arch/mt_gpio.h>
  10 #else
  11         #include <mach/mt_gpio.h>
  12 #endif
  13
  14
  15 // ---------------------------------------------------------------------------
  16 //  Local Constants
  17 // ---------------------------------------------------------------------------
  18
  19 #define FRAME_WIDTH                                                                             (720)
  20 #define FRAME_HEIGHT                                                                            (1280)
  21
  22 #define REGFLAG_DELAY                                                                   0XFEFF
  23 #define REGFLAG_END_OF_TABLE                                                            0xFFFF   // END OF REGISTERS MARKER
  24
  25 //#define LCM_DSI_CMD_MODE                                                                      0
  26
  27 #define LCM_ID_OTM1283 0x40
  28
  29 // ---------------------------------------------------------------------------
  30 //  Local Variables
  31 // ---------------------------------------------------------------------------
  32
  33 static LCM_UTIL_FUNCS lcm_util = {0};
  34
  35 #define SET_RESET_PIN(v)                                                                (lcm_util.set_reset_pin((v)))
  36 #define SET_GPIO_OUT(gpio_num,val)                                              (lcm_util.set_gpio_out((gpio_num),(val)))
  37
  38
  39 #define UDELAY(n)                                                                                       (lcm_util.udelay(n))
  40 #define MDELAY(n)                                                                                       (lcm_util.mdelay(n))
  41
  42
  43
  44 //#define _SYNA_INFO_
  45 //#define _SYNA_DEBUG_
  46
  47 #ifdef _LCM_DEBUG_
  48 #define lcm_debug(fmt, args...) printk(fmt, ##args)
  49 #else
  50 #define lcm_debug(fmt, args...) do { } while (0)
  51 #endif
  52
  53 #ifdef _LCM_INFO_
  54 #define lcm_info(fmt, args...) printk(fmt, ##args)
  55 #else
  56 #define lcm_info(fmt, args...) do { } while (0)
  57 #endif
  58 #define lcm_err(fmt, args...) printk(fmt, ##args)
  59
  60 // ---------------------------------------------------------------------------
  61 //  Local Functions
  62 // ---------------------------------------------------------------------------
  63
  64 #define dsi_set_cmdq_V2(cmd, count, ppara, force_update)        lcm_util.dsi_set_cmdq_V2(cmd, count, ppara, force_update)
  65 #define dsi_set_cmdq(pdata, queue_size, force_update)           lcm_util.dsi_set_cmdq(pdata, queue_size, force_update)
  66 #define wrtie_cmd(cmd)                                                                          lcm_util.dsi_write_cmd(cmd)
  67 #define write_regs(addr, pdata, byte_nums)                                      lcm_util.dsi_write_regs(addr, pdata, byte_nums)
  68 #define read_reg                                                                                        lcm_util.dsi_read_reg()
  69 #define read_reg_v2(cmd, buffer, buffer_size)                           lcm_util.dsi_dcs_read_lcm_reg_v2(cmd, buffer, buffer_size)
  70
  71
  72 static struct LCM_setting_table {
  73     unsigned cmd;
  74     unsigned char count;
  75     unsigned char para_list[64];
  76 };
  77
  78 static struct LCM_setting_table lcm_initialization_setting[] = {
  79
  80         /*
  81         Note :
  82
  83         Data ID will depends on the following rule.
  84
  85                 count of parameters > 1 => Data ID = 0x39
  86                 count of parameters = 1 => Data ID = 0x15
  87                 count of parameters = 0 => Data ID = 0x05
  88
  89         Structure Format :
  90
  91         {DCS command, count of parameters, {parameter list}}
  92         {REGFLAG_DELAY, milliseconds of time, {}},
  93
  94         ...
  95
  96         Setting ending by predefined flag
  97
  98         {REGFLAG_END_OF_TABLE, 0x00, {}}
  99         */
 100
 101
 102         //must use 0x39 for init setting for all register.
 103
 104         {0x00, 1, {0x00}},
 105         //{REGFLAG_DELAY, 10, {}},
 106         {0xff, 3, {0x12,0x83,0x01}},
 107         //{REGFLAG_DELAY, 10, {}},
 108
 109         {0x00, 1, {0x80}},
 110         //{REGFLAG_DELAY, 10, {}},
 111         {0xff, 2, {0x12,0x83}},
 112         //{REGFLAG_DELAY, 10, {}},
 113
 114 //-------------------- panel setting --------------------//
 115         {0x00, 1, {0x80}},
 116         //{REGFLAG_DELAY, 10, {}},
 117         {0xc0, 9, {0x00,0x64,0x00,0x10,0x10,0x00,0x64,0x10,0x10}},
 118         //{REGFLAG_DELAY, 10, {}},
 119
 120         {0x00, 1, {0x90}},
 121         //{REGFLAG_DELAY, 10, {}},
 122         {0xc0, 6, {0x00,0x5c,0x00,0x01,0x00,0x04}},
 123         //{REGFLAG_DELAY, 10, {}},
 124
 125         {0x00, 1, {0xa4}},
 126         //{REGFLAG_DELAY, 10, {}},
 127         {0xc0, 1, {0x22}},
 128         //{REGFLAG_DELAY, 10, {}},
 129
 130         {0x00, 1, {0xb3}},
 131         //{REGFLAG_DELAY, 10, {}},
 132         {0xc0,2,{0x00,0x50}},
 133         //{REGFLAG_DELAY, 10, {}},
 134
 135         {0x00, 1, {0x81}},
 136         //{REGFLAG_DELAY, 10, {}},
 137         {0xc1,1,{0x55}},
 138         //{REGFLAG_DELAY, 10, {}},
 139
 140         {0x00, 1, {0x90}},
 141         //{REGFLAG_DELAY, 10, {}},
 142         {0xc4, 1, {0x49}},
 143         //{REGFLAG_DELAY, 10, {}},
 144
 145         {0x00, 1, {0xb9}},
 146         //{REGFLAG_DELAY, 10, {}},
 147         {0xb0, 1, {0x51}},
 148         //{REGFLAG_DELAY, 10, {}},
 149
 150         {0x00,1,{0xa0}},             //dcdc setting
 151         //{REGFLAG_DELAY, 10, {}},
 152         {0xc4, 14, {0x05,0x10,0x06,0x02,0x05,0x15,0x10,0x05,0x10,0x07,0x02,0x05,0x15,0x10}},
 153         //{REGFLAG_DELAY, 10, {}},
 154
 155         {0x00, 1, {0xb0}},
 156         //{REGFLAG_DELAY, 10, {}},
 157         {0xc4, 2, {0x00,0x00}},
 158         //{REGFLAG_DELAY, 10, {}},
 159
 160         {0x00,1,{0x91}},             //VGH=15V, VGL=-10V, pump ratio:VGH=6x, VGL=-5x
 161         //{REGFLAG_DELAY, 10, {}},
 162         {0xc5,2,{0x46,0x40}},
 163         //{REGFLAG_DELAY, 10, {}},
 164
 165         {0x00,1,{0x00}},             //GVDD=4.87V, NGVDD=-4.87V
 166         //{REGFLAG_DELAY, 10, {}},
 167         {0xd8,2,{0xbc,0xbc}},
 168         //{REGFLAG_DELAY, 10, {}},
 169
 170         {0x00,1,{0x00}},             //VCOMDC=-0.9
 171         //{REGFLAG_DELAY, 10, {}},
 172         {0xd9,1,{0x54}},
 173         //{REGFLAG_DELAY, 10, {}},
 174
 175         {0x00,1,{0x81}},             //source bias 0.75uA
 176         {0xc4,1,{0x82}},
 177         //{REGFLAG_DELAY, 10, {}},
 178
 179         {0x00,1,{0xb0}},             //VDD_18V=1.6V, LVDSVDD=1.55V        --huxh------------------
 180         {0xc5,2,{0x04,0x38}},
 181         //{REGFLAG_DELAY, 10, {}},
 182
 183         {0x00,1,{0xbb}},             //LVD voltage level setting
 184         {0xc5,1,{0x80}},
 185         //{REGFLAG_DELAY, 10, {}},
 186
 187         {0x00,1,{0x82}},                // chopper 0: frame 2: line 4: disable
 188         {0xC4,1,{0x02}},
 189         //{REGFLAG_DELAY, 10, {}},
 190
 191         {0x00,1,{0xc6}},                // debounce
 192         {0xB0,1,{0x03}},
 193         //{REGFLAG_DELAY, 10, {}},
 194
 195 //-------------------- control setting --------------------//
 196         {0x00,1,{0x00}},             //ID1
 197         {0xd0,1,{0x40}},
 198         //{REGFLAG_DELAY, 10, {}},
 199
 200         {0x00,1,{0x00}},             //ID2, ID3
 201         {0xd1,2,{0x00,0x00}},
 202         //{REGFLAG_DELAY, 10, {}},
 203
 204 //-------------------- panel timing state control --------------------//
 205         {0x00,1,{0x80}},             //panel timing state control
 206         //{REGFLAG_DELAY, 10, {}},
 207         {0xcb,11,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}},
 208         //{REGFLAG_DELAY, 10, {}},
 209
 210         {0x00,1,{0x90}},             //panel timing state control
 211         //{REGFLAG_DELAY, 10, {}},
 212         {0xcb,15,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}},
 213         //{REGFLAG_DELAY, 10, {}},
 214
 215         {0x00,1,{0xa0}},             //panel timing state control
 216         //{REGFLAG_DELAY, 10, {}},
 217         {0xcb,15,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}},
 218         //{REGFLAG_DELAY, 10, {}},
 219
 220         {0x00,1,{0xb0}},             //panel timing state control
 221         ///{REGFLAG_DELAY, 10, {}},
 222         {0xcb,15,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}},
 223         //{REGFLAG_DELAY, 10, {}},
 224
 225         {0x00,1,{0xc0}},             //panel timing state control
 226         //{REGFLAG_DELAY, 10, {}},
 227         {0xcb,15,{0x05,0x05,0x05,0x05,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}},
 228         //{REGFLAG_DELAY, 10, {}},
 229
 230         {0x00,1,{0xd0}},             //panel timing state control
 231         //{REGFLAG_DELAY, 10, {}},
 232         {0xcb,15,{0xff,0xff,0xff,0x00,0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x00,0x00,0x00}},
 233         //{REGFLAG_DELAY, 10, {}},
 234
 235         {0x00,1,{0xe0}},             //panel timing state control
 236         //{REGFLAG_DELAY, 10, {}},
 237         {0xcb,14,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0xff,0xff,0x00,0x05,0x05,0x05}},
 238         //{REGFLAG_DELAY, 10, {}},
 239
 240         {0x00,1,{0xf0}},             //panel timing state control
 241         //{REGFLAG_DELAY, 10, {}},
 242         {0xcb,11,{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff}},
 243         //{REGFLAG_DELAY, 10, {}},
 244
 245 //-------------------- panel pad mapping control --------------------//
 246         {0x00,1,{0x80}},             //panel pad mapping control
 247         //{REGFLAG_DELAY, 10, {}},
 248         {0xcc,15,{0x02,0x0a,0x0c,0x0e,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}},
 249         //{REGFLAG_DELAY, 10, {}},
 250
 251         {0x00,1,{0x90}},             //panel pad mapping control
 252         //{REGFLAG_DELAY, 10, {}},
 253         {0xcc,15,{0x00,0x00,0x00,0x00,0x2e,0x2d,0x06,0x01,0x09,0x0b,0x0d,0x0f,0x00,0x00,0x00}},
 254         //{REGFLAG_DELAY, 10, {}},
 255
 256         {0x00,1,{0xa0}},             //panel pad mapping control
 257         //{REGFLAG_DELAY, 10, {}},
 258         {0xcc,14,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2e,0x2d,0x05}},
 259         //{REGFLAG_DELAY, 10, {}},
 260
 261         {0x00,1,{0xb0}},             //panel pad mapping control
 262         //{REGFLAG_DELAY, 10, {}},
 263         {0xcc,15,{0x05,0x0f,0x0d,0x0b,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}},
 264         //{REGFLAG_DELAY, 10, {}},
 265
 266         {0x00,1,{0xc0}},             //panel pad mapping control
 267         //{REGFLAG_DELAY, 10, {}},
 268         {0xcc,15,{0x00,0x00,0x00,0x00,0x2d,0x2e,0x01,0x06,0x10,0x0e,0x0c,0x0a,0x00,0x00,0x00}},
 269         //{REGFLAG_DELAY, 10, {}},
 270
 271         {0x00,1,{0xd0}},             //panel pad mapping control
 272         //{REGFLAG_DELAY, 10, {}},
 273         {0xcc,14,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x2d,0x2e,0x02}},
 274         //{REGFLAG_DELAY, 10, {}},
 275
 276 //-------------------- panel timing setting --------------------//
 277         {0x00,1,{0x80}},             //panel VST setting
 278         //{REGFLAG_DELAY, 10, {}},
 279         {0xce,12,{0x87,0x03,0x10,0x86,0x03,0x10,0x00,0x00,0x00,0x00,0x00,0x00}},
 280         //{REGFLAG_DELAY, 10, {}},
 281
 282         {0x00,1,{0x90}},             //panel VEND setting
 283         //{REGFLAG_DELAY, 10, {}},
 284         {0xce,14,{0x35,0x01,0x10,0x35,0x02,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}},
 285         //{REGFLAG_DELAY, 10, {}},
 286
 287         {0x00,1,{0xa0}},             //panel CLKA1/2 setting
 288         //{REGFLAG_DELAY, 10, {}},
 289         {0xce,14,{0x38,0x03,0x04,0xf8,0x00,0x10,0x00,0x38,0x02,0x04,0xf9,0x00,0x10,0x00}},
 290         //{REGFLAG_DELAY, 10, {}},
 291
 292         {0x00,1,{0xb0}},             //panel CLKA3/4 setting
 293         //{REGFLAG_DELAY, 10, {}},
 294         {0xce,14,{0x38,0x01,0x04,0xfa,0x00,0x10,0x00,0x38,0x00,0x04,0xfb,0x00,0x10,0x00}},
 295         //{REGFLAG_DELAY, 10, {}},
 296
 297         {0x00,1,{0xc0}},             //panel CLKb1/2 setting
 298         //{REGFLAG_DELAY, 10, {}},
 299         {0xce,14,{0x30,0x00,0x04,0xfc,0x00,0x10,0x00,0x30,0x01,0x04,0xfd,0x00,0x10,0x00}},
 300         //{REGFLAG_DELAY, 10, {}},
 301
 302         {0x00,1,{0xd0}},             //panel CLKb3/4 setting
 303         //{REGFLAG_DELAY, 10, {}},
 304         {0xce,14,{0x30,0x02,0x04,0xfe,0x00,0x10,0x00,0x30,0x03,0x04,0xff,0x00,0x10,0x00}},
 305         //{REGFLAG_DELAY, 10, {}},
 306
 307         {0x00,1,{0x80}},             //panel CLKc1/2 setting
 308         //{REGFLAG_DELAY, 10, {}},
 309         {0xcf,14,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}},
 310         //{REGFLAG_DELAY, 10, {}},
 311
 312         {0x00,1,{0x90}},             //panel CLKc3/4 setting
 313         //{REGFLAG_DELAY, 10, {}},
 314         {0xcf,14,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}},
 315         //{REGFLAG_DELAY, 10, {}},
 316
 317         {0x00,1,{0xa0}},             //panel CLKd1/2 setting
 318         //{REGFLAG_DELAY, 10, {}},
 319         {0xcf,14,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}},
 320         //{REGFLAG_DELAY, 10, {}},
 321
 322         {0x00,1,{0xb0}},             //panel CLKd3/4 setting
 323         //{REGFLAG_DELAY, 10, {}},
 324         {0xcf,14,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}},
 325         //{REGFLAG_DELAY, 10, {}},
 326
 327         {0x00,1,{0xc0}},             //panel ECLK setting
 328         //{REGFLAG_DELAY, 10, {}},
 329         {0xcf,11,{0x01,0x01,0x20,0x20,0x00,0x00,0x01,0x81,0x00,0x03,0x08}}, //gate pre. ena.
 330         //{REGFLAG_DELAY, 10, {}},
 331
 332         {0x00,1,{0xb5}},             //TCON_GOA_OUT Setting
 333         //{REGFLAG_DELAY, 10, {}},
 334         {0xc5,6,{0x3f,0xff,0xff,0x3f,0xff,0xff}},
 335         //{REGFLAG_DELAY, 10, {}},
 336 //-------------------- for ,{ower IC --------------------//
 337         {0x00,1,{0x90}},             //Mode-3
 338         //{REGFLAG_DELAY, 10, {}},
 339         {0xf5,4,{0x02,0x11,0x02,0x11}},
 340         //{REGFLAG_DELAY, 10, {}},
 341
 342         {0x00, 1, {0x90}},
 343         //{REGFLAG_DELAY, 10, {}},
 344         {0xc5, 1, {0x50}},
 345         //{REGFLAG_DELAY, 10, {}},
 346
 347         {0x00, 1, {0x94}},
 348         //{REGFLAG_DELAY, 10, {}},
 349         {0xc5, 1, {0x66}},
 350         //{REGFLAG_DELAY, 10, {}},
 351
 352 //------------------VGLO1/O2 disable----------------
 353         {0x00, 1, {0xb2}},
 354         //{REGFLAG_DELAY, 10, {}},
 355         {0xf5,2,{0x00,0x00}},
 356         //{REGFLAG_DELAY, 10, {}},
 357
 358         {0x00,1,{0xb4}},             //VGLO1_S
 359         //{REGFLAG_DELAY, 10, {}},
 360         {0xf5,2,{0x00,0x00}},
 361         //{REGFLAG_DELAY, 10, {}},
 362
 363         {0x00,1,{0xb6}},             //VGLO2
 364         //{REGFLAG_DELAY, 10, {}},
 365         {0xf5,2,{0x00,0x00}},
 366         //{REGFLAG_DELAY, 10, {}},
 367
 368         {0x00,1,{0xb8}},             //VGLO2_S
 369         ///{REGFLAG_DELAY, 10, {}},
 370         {0xf5,2,{0x00,0x00}},
 371         //{REGFLAG_DELAY, 10, {}},
 372
 373         {0x00,1,{0x94}},                //VCL on
 374         //{REGFLAG_DELAY, 10, {}},
 375         {0xF5,1,{0x02}},
 376         //{REGFLAG_DELAY, 10, {}},
 377
 378         {0x00,1,{0xBA}},                //VS,{ on
 379         //{REGFLAG_DELAY, 10, {}},
 380         {0xF5,1,{0x03}},
 381         //{REGFLAG_DELAY, 10, {}},
 382
 383         {0x00,1,{0xb4}},             //VGLO1/2 ,{ull low setting
 384         //{REGFLAG_DELAY, 10, {}},
 385         {0xc5,1,{0xc0}},                //d[7] vglo1 d[6] vglo2 => 0: pull vss, 1: pull vgl
 386         //{REGFLAG_DELAY, 10, {}},
 387
 388         {0x00,1,{0xb2}},             //C31 cap. not remove
 389         //{REGFLAG_DELAY, 10, {}},
 390         {0xc5,1,{0x40}},
 391         //{REGFLAG_DELAY, 10, {}},
 392
 393
 394         {0x00,1,{0xA0}},
 395         //{REGFLAG_DELAY, 10, {}},
 396         {0xC1,1,{0x02}},  // Disable time-out function       -----------huxh---------------------------------------------
 397        // {REGFLAG_DELAY, 10, {}},
 398
 399 //-------------------- Gamma --------------------//
 400         {0x00,1,{0x00}},
 401         //{REGFLAG_DELAY, 10, {}},
 402         {0xE1,16,{0x00,0x15,0x1B,0x0D,0x06,0x0E,0x09,0x09,0x04,0x07,0x0C,0x08,0x0F,0x0F,0x09,0x00}},
 403         //{REGFLAG_DELAY, 10, {}},
 404
 405         {0x00,1,{0x00}},
 406         //{REGFLAG_DELAY, 10, {}},
 407         {0xE2,16,{0x00,0x15,0x1B,0x0D,0x06,0x0E,0x09,0x09,0x04,0x07,0x0C,0x08,0x0F,0x0F,0x09,0x00}},
 408         //{REGFLAG_DELAY, 10, {}},
 409
 410
 411         {0x00,1,{0x00}},             //Orise mode disable
 412         //{REGFLAG_DELAY, 10, {}},
 413         {0xff,3,{0xff,0xff,0xff}},
 414         //{REGFLAG_DELAY, 10, {}},
 415 };
 416
 417 static struct LCM_setting_table lcm_set_window[] = {
 418         {0x2A,  4,      {0x00, 0x00, (FRAME_WIDTH>>8), (FRAME_WIDTH&0xFF)}},
 419         {0x2B,  4,      {0x00, 0x00, (FRAME_HEIGHT>>8), (FRAME_HEIGHT&0xFF)}},
 420         {REGFLAG_END_OF_TABLE, 0x00, {}}
 421 };
 422
 423
 424 static struct LCM_setting_table lcm_sleep_out_setting[] = {
 425     // Sleep Out
 426         {0x11, 0, {0x00}},
 427     {REGFLAG_DELAY, 120, {}},
 428
 429     // Display ON
 430         {0x29, 0, {0x00}},
 431 //      {REGFLAG_DELAY, 20, {}},
 432
 433         {REGFLAG_END_OF_TABLE, 0x00, {}}
 434 };
 435
 436
 437 static struct LCM_setting_table lcm_sleep_in_setting[] = {
 438         // Display off sequence
 439         {0x28, 0, {0x00}},
 440
 441     // Sleep Mode On
 442         {0x10, 0, {0x00}},
 443
 444         {REGFLAG_END_OF_TABLE, 0x00, {}}
 445 };
 446 static void lcm_init_registers()
 447 {
 448         unsigned int data_array[16];
 449
 450         lcm_debug("liyibo : %s %d\n", __func__,__LINE__);
 451
 452         data_array[0] = 0x00042902;
 453         data_array[1] = 0x018312FF;
 454         dsi_set_cmdq(&data_array, 2, 1);//EXTC = 1
 455
 456         data_array[0] = 0x80002300;
 457         dsi_set_cmdq(&data_array, 1, 1);        //Orise mode enable
 458
 459         data_array[0] = 0x00032902;
 460         data_array[1] = 0x008312FF;
 461         dsi_set_cmdq(&data_array, 2, 1);
 462
 463         /*===================panel setting====================*/
 464         data_array[0] = 0x80002300;
 465         dsi_set_cmdq(&data_array, 1, 1);        //TCON Setting
 466
 467         data_array[0] = 0x000A2902;
 468         data_array[1] = 0x006400C0;
 469         data_array[2] = 0x6400110F;
 470         data_array[3] = 0x0000110F;
 471         dsi_set_cmdq(&data_array, 4, 1);
 472
 473         data_array[0] = 0x90002300;
 474         dsi_set_cmdq(&data_array, 1, 1);        //Panel Timing Setting
 475
 476         data_array[0] = 0x00072902;
 477         data_array[1] = 0x005C00C0;
 478         data_array[2] = 0x00040001;
 479         dsi_set_cmdq(&data_array, 3, 1);
 480
 481         data_array[0] = 0xA4002300;
 482         dsi_set_cmdq(&data_array, 1, 1);        //Source pre.
 483
 484         data_array[0] = 0x1CC02300;
 485         dsi_set_cmdq(&data_array, 1, 1);
 486
 487         data_array[0] = 0xB3002300;
 488         dsi_set_cmdq(&data_array, 1, 1);        //Interval Scan Frame: 0 frame, column inversion
 489
 490         data_array[0] = 0x00032902;
 491         data_array[1] = 0x005000C0;
 492         dsi_set_cmdq(&data_array, 2, 1);
 493
 494         data_array[0] = 0x81002300;
 495         dsi_set_cmdq(&data_array, 1, 1);        //frame rate: 60Hz
 496
 497         data_array[0] = 0x55C12300;
 498         dsi_set_cmdq(&data_array, 1, 1);
 499
 500         data_array[0] = 0x81002300;                             //Source bias 0.75uA
 501         dsi_set_cmdq(&data_array, 1, 1);
 502
 503         data_array[0] = 0x82C42300;
 504         dsi_set_cmdq(&data_array, 1, 1);
 505
 506         data_array[0] = 0x90002300;                             //clock delay for data latch
 507         dsi_set_cmdq(&data_array, 1, 1);
 508
 509         data_array[0] = 0x49C42300;
 510         dsi_set_cmdq(&data_array, 1, 1);
 511
 512         /*================Power setting===============*/
 513         data_array[0] = 0xA0002300;
 514         dsi_set_cmdq(&data_array, 1, 1);
 515
 516         data_array[0] = 0x000F2902;     //DCDC setting
 517         data_array[1] = 0x061005C4;
 518         data_array[2] = 0x10150502;
 519         data_array[3] = 0x02071005;
 520         data_array[4] = 0x00101505;
 521         dsi_set_cmdq(&data_array, 5, 1);
 522
 523         data_array[0] = 0xB0002300;
 524         dsi_set_cmdq(&data_array, 1, 1);
 525
 526         data_array[0] = 0x00032902;     //Clamp coltage setting
 527         data_array[1] = 0x000000C4;
 528         dsi_set_cmdq(&data_array, 2, 1);
 529
 530         data_array[0] = 0x91002300;
 531         dsi_set_cmdq(&data_array, 1, 1);
 532
 533         data_array[0] = 0x00032902;     //VGH=12v, VGL=-12v, pump ratio: VGH=6x, VGL=-5x
 534         data_array[1] = 0x005019c5;
 535         dsi_set_cmdq(&data_array, 2, 1);
 536
 537         data_array[0] = 0x00002300;
 538         dsi_set_cmdq(&data_array, 1, 1);
 539
 540         data_array[0] = 0x00032902;     //GVDD=4.87v, NGVDD = -4.87V
 541         data_array[1] = 0x00bcbcd8;
 542         dsi_set_cmdq(&data_array, 2, 1);
 543
 544         data_array[0] = 0x00002300;
 545         dsi_set_cmdq(&data_array, 1, 1);
 546
 547         data_array[0] = 0xd9652300;             //VCOMDC=-1.1
 548         dsi_set_cmdq(&data_array, 1, 1);
 549
 550         data_array[0] = 0xB0002300;
 551         dsi_set_cmdq(&data_array, 1, 1);
 552
 553         data_array[0] = 0x00032902;     //VDD_18v=1.6v, LVDSVDD=1.55v
 554         data_array[1] = 0x00b804c5;
 555         dsi_set_cmdq(&data_array, 2, 1);
 556
 557         data_array[0] = 0xBB002300;
 558         dsi_set_cmdq(&data_array, 1, 1);
 559
 560         data_array[0] = 0x80c52300;     //LVD voltage level setting
 561         dsi_set_cmdq(&data_array, 1, 1);
 562
 563         /*=========================Control setting======================*/
 564         data_array[0] = 0x00002300;
 565         dsi_set_cmdq(&data_array, 1, 1);
 566
 567         data_array[0] = 0x40d02300;             //ID1
 568         dsi_set_cmdq(&data_array, 1, 1);
 569
 570         data_array[0] = 0x00002300;
 571         dsi_set_cmdq(&data_array, 1, 1);
 572
 573         data_array[0] = 0x00032902;     //ID2, ID3
 574         data_array[1] = 0x000000d1;
 575         dsi_set_cmdq(&data_array, 2, 1);
 576
 577         /*=========================Panel Timming State Control================*/
 578         data_array[0] = 0x80002300;
 579         dsi_set_cmdq(&data_array, 1, 1);
 580
 581         data_array[0] = 0x000C2902;     //Panel timing state control
 582         data_array[1] = 0x000000cb;
 583         data_array[2] = 0x00000000;
 584         data_array[3] = 0x00000000;
 585         dsi_set_cmdq(&data_array, 4, 1);
 586
 587         data_array[0] = 0x90002300;
 588         dsi_set_cmdq(&data_array, 1, 1);
 589
 590         data_array[0] = 0x00102902;     //Panel timing state control
 591         data_array[1] = 0x000000cb;
 592         data_array[2] = 0x00000000;
 593         data_array[3] = 0x00000000;
 594         data_array[4] = 0x00000000;
 595         dsi_set_cmdq(&data_array, 5, 1);
 596
 597         data_array[0] = 0xa0002300;
 598         dsi_set_cmdq(&data_array, 1, 1);
 599
 600         data_array[0] = 0x00102902;     //Panel timing state control
 601         data_array[1] = 0x000000cb;
 602         data_array[2] = 0x00000000;
 603         data_array[3] = 0x00000000;
 604         data_array[4] = 0x00000000;
 605         dsi_set_cmdq(&data_array, 5, 1);
 606
 607         data_array[0] = 0xb0002300;
 608         dsi_set_cmdq(&data_array, 1, 1);
 609
 610         data_array[0] = 0x00102902;     //Panel timing state control
 611         data_array[1] = 0x000000cb;
 612         data_array[2] = 0x00000000;
 613         data_array[3] = 0x00000000;
 614         data_array[4] = 0x00000000;
 615         dsi_set_cmdq(&data_array, 5, 1);
 616
 617         data_array[0] = 0xc0002300;
 618         dsi_set_cmdq(&data_array, 1, 1);
 619
 620         data_array[0] = 0x00102902;     //Panel timing state control
 621         data_array[1] = 0x050505cb;
 622         data_array[2] = 0x00050505;
 623         data_array[3] = 0x00000000;
 624         data_array[4] = 0x00000000;
 625         dsi_set_cmdq(&data_array, 5, 1);
 626
 627         data_array[0] = 0xd0002300;
 628         dsi_set_cmdq(&data_array, 1, 1);
 629
 630         data_array[0] = 0x00102902;     //Panel timing state control
 631         data_array[1] = 0x000000cb;
 632         data_array[2] = 0x05050000;
 633         data_array[3] = 0x05050505;
 634         data_array[4] = 0x00000505;
 635         dsi_set_cmdq(&data_array, 5, 1);
 636
 637         data_array[0] = 0xe0002300;
 638         dsi_set_cmdq(&data_array, 1, 1);
 639
 640         data_array[0] = 0x000F2902;     //Panel timing state control
 641         data_array[1] = 0x000000cb;
 642         data_array[2] = 0x00000000;
 643         data_array[3] = 0x00000000;
 644         data_array[4] = 0x00050500;
 645         dsi_set_cmdq(&data_array, 5, 1);
 646
 647         data_array[0] = 0xf0002300;
 648         dsi_set_cmdq(&data_array, 1, 1);
 649
 650         data_array[0] = 0x000c2902;     //Panel timing state control
 651         data_array[1] = 0xffffffcb;
 652         data_array[2] = 0xffffffff;
 653         data_array[3] = 0xffffffff;
 654         dsi_set_cmdq(&data_array, 4, 1);
 655
 656         /*===============Panel pad mapping control===============*/
 657         data_array[0] = 0x80002300;
 658         dsi_set_cmdq(&data_array, 1, 1);
 659
 660         data_array[0] = 0x00102902;     //Panel pad mapping control
 661         data_array[1] = 0x0e0c0acc;
 662         data_array[2] = 0x00040210;
 663         data_array[3] = 0x00000000;
 664         data_array[4] = 0x00000000;
 665         dsi_set_cmdq(&data_array, 5, 1);
 666
 667         data_array[0] = 0x90002300;
 668         dsi_set_cmdq(&data_array, 1, 1);
 669
 670         data_array[0] = 0x00102902;     //Panel pad mapping control
 671         data_array[1] = 0x000000cc;
 672         data_array[2] = 0x2d2e0000;
 673         data_array[3] = 0x0f0d0b09;
 674         data_array[4] = 0x00000301;
 675         dsi_set_cmdq(&data_array, 5, 1);
 676
 677         data_array[0] = 0xa0002300;
 678         dsi_set_cmdq(&data_array, 1, 1);
 679
 680         data_array[0] = 0x000f2902;     //Panel pad mapping control
 681         data_array[1] = 0x000000cc;
 682         data_array[2] = 0x00040210;
 683         data_array[3] = 0x00000000;
 684         data_array[4] = 0x002d2e00;
 685         dsi_set_cmdq(&data_array, 5, 1);
 686
 687         data_array[0] = 0xb0002300;
 688         dsi_set_cmdq(&data_array, 1, 1);
 689
 690         data_array[0] = 0x00102902;     //Panel pad mapping control
 691         data_array[1] = 0x0b0d0fcc;
 692         data_array[2] = 0x00010309;
 693         data_array[3] = 0x00000000;
 694         data_array[4] = 0x00000000;
 695         dsi_set_cmdq(&data_array, 5, 1);
 696
 697         data_array[0] = 0xc0002300;
 698         dsi_set_cmdq(&data_array, 1, 1);
 699
 700         data_array[0] = 0x00102902;     //Panel pad mapping control
 701         data_array[1] = 0x000000cc;
 702         data_array[2] = 0x2e2d0000;
 703         data_array[3] = 0x0a0c0e10;
 704         data_array[4] = 0x00000204;
 705         dsi_set_cmdq(&data_array, 5, 1);
 706
 707         data_array[0] = 0xd0002300;
 708         dsi_set_cmdq(&data_array, 1, 1);
 709
 710         data_array[0] = 0x000f2902;     //Panel pad mapping control
 711         data_array[1] = 0x000000cc;
 712         data_array[2] = 0x00000000;
 713         data_array[3] = 0x00000000;
 714         data_array[4] = 0x002e2d00;
 715         dsi_set_cmdq(&data_array, 5, 1);
 716
 717         /*===============Panel Timing Setting====================*/
 718         data_array[0] = 0x80002300;
 719         dsi_set_cmdq(&data_array, 1, 1);
 720
 721         data_array[0] = 0x000d2902;     //Panel VST Setting
 722         data_array[1] = 0x18038fce;
 723         data_array[2] = 0x8d18038e;
 724         data_array[3] = 0x038c1803;
 725         data_array[4] = 0x00000018;
 726         dsi_set_cmdq(&data_array, 5, 1);
 727
 728         data_array[0] = 0x90002300;
 729         dsi_set_cmdq(&data_array, 1, 1);
 730
 731         data_array[0] = 0x000f2902;     //Panel vend setting
 732         data_array[1] = 0x000000ce;
 733         data_array[2] = 0x00000000;
 734         data_array[3] = 0x00000000;
 735         data_array[4] = 0x00000000;
 736         dsi_set_cmdq(&data_array, 5, 1);
 737
 738         data_array[0] = 0xa0002300;
 739         dsi_set_cmdq(&data_array, 1, 1);
 740
 741         data_array[0] = 0x000f2902;     //Panel clka1/2 setting
 742         data_array[1] = 0x050b38ce;
 743         data_array[2] = 0x00000000;
 744         data_array[3] = 0x01050a38;
 745         data_array[4] = 0x00000000;
 746         dsi_set_cmdq(&data_array, 5, 1);
 747
 748         data_array[0] = 0xb0002300;
 749         dsi_set_cmdq(&data_array, 1, 1);
 750
 751         data_array[0] = 0x000f2902;     //Panel clka3/4 setting
 752         data_array[1] = 0x050938ce;
 753         data_array[2] = 0x00000002;
 754         data_array[3] = 0x03050838;
 755         data_array[4] = 0x00000000;
 756         dsi_set_cmdq(&data_array, 5, 1);
 757
 758         data_array[0] = 0xc0002300;
 759         dsi_set_cmdq(&data_array, 1, 1);
 760
 761         data_array[0] = 0x000f2902;     //Panel clkb1/2 setting
 762         data_array[1] = 0x050738ce;
 763         data_array[2] = 0x00000004;
 764         data_array[3] = 0x05050638;
 765         data_array[4] = 0x00000000;
 766         dsi_set_cmdq(&data_array, 5, 1);
 767
 768         data_array[0] = 0xd0002300;
 769         dsi_set_cmdq(&data_array, 1, 1);
 770
 771         data_array[0] = 0x000f2902;     //Panel clkb3/4 setting
 772         data_array[1] = 0x050538ce;
 773         data_array[2] = 0x00000006;
 774         data_array[3] = 0x07050438;
 775         data_array[4] = 0x00000000;
 776         dsi_set_cmdq(&data_array, 5, 1);
 777
 778         data_array[0] = 0x80002300;
 779         dsi_set_cmdq(&data_array, 1, 1);
 780
 781         data_array[0] = 0x000f2902;     //Panel clkc1/2 setting
 782         data_array[1] = 0x000000cf;
 783         data_array[2] = 0x00000000;
 784         data_array[3] = 0x00000000;
 785         data_array[4] = 0x00000000;
 786         dsi_set_cmdq(&data_array, 5, 1);
 787
 788         data_array[0] = 0x90002300;
 789         dsi_set_cmdq(&data_array, 1, 1);
 790
 791         data_array[0] = 0x000f2902;     //Panel clkc3/4 setting
 792         data_array[1] = 0x000000cf;
 793         data_array[2] = 0x00000000;
 794         data_array[3] = 0x00000000;
 795         data_array[4] = 0x00000000;
 796         dsi_set_cmdq(&data_array, 5, 1);
 797
 798         data_array[0] = 0xa0002300;
 799         dsi_set_cmdq(&data_array, 1, 1);
 800
 801         data_array[0] = 0x000f2902;     //Panel clkd1/2 setting
 802         data_array[1] = 0x000000cf;
 803         data_array[2] = 0x00000000;
 804         data_array[3] = 0x00000000;
 805         data_array[4] = 0x00000000;
 806         dsi_set_cmdq(&data_array, 5, 1);
 807
 808         data_array[0] = 0xb0002300;
 809         dsi_set_cmdq(&data_array, 1, 1);
 810
 811         data_array[0] = 0x000f2902;     //Panel clkd3/4 setting
 812         data_array[1] = 0x000000cf;
 813         data_array[2] = 0x00000000;
 814         data_array[3] = 0x00000000;
 815         data_array[4] = 0x00000000;
 816         dsi_set_cmdq(&data_array, 5, 1);
 817
 818         data_array[0] = 0xc0002300;
 819         dsi_set_cmdq(&data_array, 1, 1);
 820
 821         data_array[0] = 0x000c2902;     //gate pre. ena
 822         data_array[1] = 0x200101cf;
 823         data_array[2] = 0x01000020;
 824         data_array[3] = 0x08030081;
 825         dsi_set_cmdq(&data_array, 4, 1);
 826
 827         data_array[0] = 0xb5002300;
 828         dsi_set_cmdq(&data_array, 1, 1);
 829
 830         data_array[0] = 0x00072902;     //normal output with VGH/VGL
 831         data_array[1] = 0xfff133c5;
 832         data_array[2] = 0x00fff133;
 833         dsi_set_cmdq(&data_array, 3, 1);
 834
 835         data_array[0] = 0x90002300;
 836         dsi_set_cmdq(&data_array, 1, 1);
 837
 838         data_array[0] = 0x00052902;     //mode-3
 839         data_array[1] = 0x021102f5;
 840         data_array[2] = 0x00000011;
 841         dsi_set_cmdq(&data_array, 3, 1);
 842
 843         data_array[0] = 0x90002300;
 844         dsi_set_cmdq(&data_array, 1, 1);
 845
 846         data_array[0] = 0x50c52300;     //2xVPNL, 1.5*=00, 2*=50, 3*=A0
 847         dsi_set_cmdq(&data_array, 1, 1);
 848
 849         data_array[0] = 0x94002300;
 850         dsi_set_cmdq(&data_array, 1, 1);
 851
 852         data_array[0] = 0x66c52300;     //Frequency
 853         dsi_set_cmdq(&data_array, 1, 1);
 854
 855         /*===============VGL01/02 disable================*/
 856         data_array[0] = 0xb2002300;
 857         dsi_set_cmdq(&data_array, 1, 1);
 858
 859         data_array[0] = 0x00032902;     //VGL01
 860         data_array[1] = 0x000000f5;
 861         dsi_set_cmdq(&data_array, 2, 1);
 862
 863         data_array[0] = 0xb4002300;
 864         dsi_set_cmdq(&data_array, 1, 1);
 865
 866         data_array[0] = 0x00032902;     //VGL01_S
 867         data_array[1] = 0x000000f5;
 868         dsi_set_cmdq(&data_array, 2, 1);
 869
 870         data_array[0] = 0xb6002300;
 871         dsi_set_cmdq(&data_array, 1, 1);
 872
 873         data_array[0] = 0x00032902;     //VGL02
 874         data_array[1] = 0x000000f5;
 875         dsi_set_cmdq(&data_array, 2, 1);
 876
 877         data_array[0] = 0xb8002300;
 878         dsi_set_cmdq(&data_array, 1, 1);
 879
 880         data_array[0] = 0x00032902;     //VGL02_S
 881         data_array[1] = 0x000000f5;
 882         dsi_set_cmdq(&data_array, 2, 1);
 883
 884         data_array[0] = 0xb4002300;
 885         dsi_set_cmdq(&data_array, 1, 1);
 886
 887         data_array[0] = 0xC0C52300;
 888         dsi_set_cmdq(&data_array, 1, 1);
 889
 890         /*===================Gamma====================*/
 891         data_array[0] = 0x00002300;
 892         dsi_set_cmdq(&data_array, 1, 1);
 893
 894         data_array[0] = 0x00112902;
 895         data_array[1] = 0x231d0ae1;
 896         data_array[2] = 0x0a0f040d;
 897         data_array[3] = 0x0a060309;
 898         data_array[4] = 0x0d110e05;
 899         data_array[5] = 0x00000001;
 900         dsi_set_cmdq(&data_array, 6 ,1);
 901
 902         data_array[0] = 0x00002300;
 903         dsi_set_cmdq(&data_array, 1, 1);
 904
 905         data_array[0] = 0x00112902;
 906         data_array[1] = 0x221d0ae2;
 907         data_array[2] = 0x0b0e040e;
 908         data_array[3] = 0x0906020a;
 909         data_array[4] = 0x0d110e05;
 910         data_array[5] = 0x00000001;
 911         dsi_set_cmdq(&data_array, 6 ,1);
 912
 913         data_array[0] = 0x00002300;
 914         dsi_set_cmdq(&data_array, 1, 1);
 915
 916         data_array[0] = 0x00042902;
 917         data_array[1] = 0x000000ff;
 918         dsi_set_cmdq(&data_array, 2 ,1);
 919 }
 920 static void push_table(struct LCM_setting_table *table, unsigned int count, unsigned char force_update)
 921 {
 922         unsigned int i;
 923         lcm_debug("liyibo : %s %d\n", __func__,__LINE__);
 924     for(i = 0; i < count; i++) {
 925
 926         unsigned cmd;
 927         cmd = table[i].cmd;
 928
 929         switch (cmd) {
 930
 931             case REGFLAG_DELAY :
 932                 MDELAY(table[i].count);
 933                 break;
 934
 935             case REGFLAG_END_OF_TABLE :
 936                 break;
 937
 938             default:
 939                                 dsi_set_cmdq_V2(cmd, table[i].count, table[i].para_list, force_update);
 940         }
 941     }
 942
 943 }
 944
 945
 946 // ---------------------------------------------------------------------------
 947 //  LCM Driver Implementations
 948 // ---------------------------------------------------------------------------
 949
 950 static void lcm_set_util_funcs(const LCM_UTIL_FUNCS *util)
 951 {
 952                 lcm_debug("liyibo : %s %d\n", __func__,__LINE__);
 953     memcpy(&lcm_util, util, sizeof(LCM_UTIL_FUNCS));
 954 }
 955
 956
 957 static void lcm_get_params(LCM_PARAMS *params)
 958 {
 959                 lcm_debug("liyibo : %s %d\n", __func__,__LINE__);
 960                 memset(params, 0, sizeof(LCM_PARAMS));
 961
 962                 params->type   = LCM_TYPE_DSI;
 963
 964                 params->width  = FRAME_WIDTH;
 965                 params->height = FRAME_HEIGHT;
 966
 967                 // enable tearing-free
 968                 params->dbi.te_mode                             = LCM_DBI_TE_MODE_VSYNC_ONLY;
 969                 params->dbi.te_edge_polarity            = LCM_POLARITY_RISING;
 970
 971 #if (LCM_DSI_CMD_MODE)
 972                 params->dsi.mode   = CMD_MODE;
 973 #else
 974                 params->dsi.mode   = BURST_VDO_MODE;
 975 #endif
 976
 977                 // DSI
 978                 /* Command mode setting */
 979                 params->dsi.LANE_NUM                            = LCM_FOUR_LANE;
 980                 //The following defined the fomat for data coming from LCD engine.
 981                 params->dsi.data_format.color_order = LCM_COLOR_ORDER_RGB;
 982                 params->dsi.data_format.trans_seq   = LCM_DSI_TRANS_SEQ_MSB_FIRST;
 983                 params->dsi.data_format.padding     = LCM_DSI_PADDING_ON_LSB;
 984                 params->dsi.data_format.format      = LCM_DSI_FORMAT_RGB888;
 985
 986                 // Highly depends on LCD driver capability.
 987                 // Not support in MT6573
 988                 params->dsi.packet_size=256;
 989
 990                 // Video mode setting
 991                 params->dsi.intermediat_buffer_num = 0;
 992
 993                 params->dsi.PS=LCM_PACKED_PS_24BIT_RGB888;
 994
 995                 params->dsi.vertical_sync_active                                = 4;//2;
 996                 params->dsi.vertical_backporch                                  = 16;//14;
 997                 params->dsi.vertical_frontporch                                 = 16;
 998                 params->dsi.vertical_active_line                                = FRAME_HEIGHT;
 999
1000                 params->dsi.horizontal_sync_active                              = 6;//2;
1001                 params->dsi.horizontal_backporch                                = 44;//44;//42;
1002                 params->dsi.horizontal_frontporch                               = 44;
1003                 params->dsi.horizontal_active_pixel                             = FRAME_WIDTH;
1004
1005     params->dsi.PLL_CLOCK = 215;//156;
1006                 // Bit rate calculation
1007                 params->dsi.pll_div1=0;         // fref=26MHz, fvco=fref*(div1+1)       (div1=0~63, fvco=500MHZ~1GHz)
1008                 params->dsi.pll_div2=1;                 // div2=0~15: fout=fvo/(2*div2)
1009                 params->dsi.fbk_div =11;    //fref=26MHz, fvco=fref*(fbk_div+1)*2/(div1_real*div2_real)
1010
1011 }
1012
1013 static unsigned int lcm_compare_id(void)
1014 {
1015                 unsigned int id = 0;
1016                 unsigned char buffer[2];
1017                 unsigned int array[16];
1018                         lcm_debug("liyibo : %s %d\n", __func__,__LINE__);
1019                         SET_RESET_PIN(1);  //NOTE:should reset LCM firstly
1020                         SET_RESET_PIN(0);
1021                         MDELAY(1);
1022                         SET_RESET_PIN(1);
1023                         MDELAY(150);
1024
1025         //      push_table(lcm_compare_id_setting, sizeof(lcm_compare_id_setting) / sizeof(struct LCM_setting_table), 1);
1026
1027                 array[0] = 0x00023700;// read id return two byte,version and id
1028                 dsi_set_cmdq(array, 1, 1);
1029                 read_reg_v2(0xDA, buffer, 1);
1030
1031                 id = buffer[0]; //we only need ID
1032       #ifdef BUILD_UBOOT
1033                 printf("%s,  id otm1283A= 0x%08x\n", __func__, id);
1034           #endif
1035                 return (LCM_ID_OTM1283 == id)?1:0;
1036
1037
1038 }
1039
1040
1041 static void lcm_init(void)
1042 {
1043         unsigned int data_array[16];
1044                 lcm_debug("liyibo : %s %d\n", __func__,__LINE__);
1045         SET_RESET_PIN(1);
1046     SET_RESET_PIN(0);
1047         MDELAY(1);//50
1048     SET_RESET_PIN(1);
1049         MDELAY(10);//100
1050
1051         //lcm_init_registers();
1052         //data_array[0] = 0x00352500;
1053         //dsi_set_cmdq(&data_array, 1, 1);
1054         push_table(lcm_initialization_setting,sizeof(lcm_initialization_setting)/sizeof(lcm_initialization_setting[0]),1);
1055         push_table(lcm_sleep_out_setting, sizeof(lcm_sleep_out_setting) / sizeof(struct LCM_setting_table), 1);
1056 }
1057
1058
1059 static void lcm_suspend(void)
1060 {
1061                 lcm_debug("liyibo : %s %d\n", __func__,__LINE__);
1062         SET_RESET_PIN(0);
1063         MDELAY(1);
1064         SET_RESET_PIN(1);
1065
1066         push_table(lcm_sleep_in_setting, sizeof(lcm_sleep_in_setting) / sizeof(struct LCM_setting_table), 1);
1067
1068         SET_GPIO_OUT(GPIO_LCM_PWR_EN,0);//Disable LCM Power
1069 }
1070
1071
1072
1073 static void lcm_resume(void)
1074 {
1075         lcm_debug("liyibo : %s %d\n", __func__,__LINE__);
1076         SET_GPIO_OUT(GPIO_LCM_PWR_EN,1);  //Enable LCM Power
1077         lcm_init();
1078 //      push_table(lcm_sleep_out_setting, sizeof(lcm_sleep_out_setting) / sizeof(struct LCM_setting_table), 1);
1079 }
1080
1081
1082 static void lcm_update(unsigned int x, unsigned int y,
1083                        unsigned int width, unsigned int height)
1084 {
1085                 lcm_debug("liyibo : %s %d\n", __func__,__LINE__);
1086         unsigned int x0 = x;
1087         unsigned int y0 = y;
1088         unsigned int x1 = x0 + width - 1;
1089         unsigned int y1 = y0 + height - 1;
1090
1091         unsigned char x0_MSB = ((x0>>8)&0xFF);
1092         unsigned char x0_LSB = (x0&0xFF);
1093         unsigned char x1_MSB = ((x1>>8)&0xFF);
1094         unsigned char x1_LSB = (x1&0xFF);
1095         unsigned char y0_MSB = ((y0>>8)&0xFF);
1096         unsigned char y0_LSB = (y0&0xFF);
1097         unsigned char y1_MSB = ((y1>>8)&0xFF);
1098         unsigned char y1_LSB = (y1&0xFF);
1099
1100         unsigned int data_array[16];
1101
1102         data_array[0]= 0x00053902;
1103         data_array[1]= (x1_MSB<<24)|(x0_LSB<<16)|(x0_MSB<<8)|0x2a;
1104         data_array[2]= (x1_LSB);
1105         data_array[3]= 0x00000000;
1106         data_array[4]= 0x00053902;
1107         data_array[5]= (y1_MSB<<24)|(y0_LSB<<16)|(y0_MSB<<8)|0x2b;
1108         data_array[6]= (y1_LSB);
1109         data_array[7]= 0x00000000;
1110         data_array[8]= 0x002c3909;
1111
1112         dsi_set_cmdq(&data_array, 9, 0);
1113
1114 }
1115
1116
1117
1118
1119
1120
1121
1122 LCM_DRIVER otm1283a_6589_hd_dsi =
1123 {
1124     .name                       = "otm1283a_6589_dsi",
1125         .set_util_funcs = lcm_set_util_funcs,
1126         .get_params     = lcm_get_params,
1127         .init           = lcm_init,
1128         .suspend        = lcm_suspend,
1129         .resume         = lcm_resume,
1130         .compare_id     = lcm_compare_id,
1131 #if (LCM_DSI_CMD_MODE)
1132         .set_backlight  = lcm_setbacklight,
1133     .update         = lcm_update,
1134 #endif
1135 };