drivers/misc/mediatek/lcm/EJ101IA/EJ101IA.c

   1 #ifndef BUILD_LK
   2 #include <linux/string.h>
   3 #endif
   4 #ifdef BUILD_LK
   5 #include <platform/mt_gpio.h>
   6 #include <platform/mt_pmic.h>
   7 #include <platform/mt_i2c.h>
   8 #include <platform/upmu_common.h>
   9 #include <debug.h>
  10 #elif (defined BUILD_UBOOT)
  11 #include <asm/arch/mt6577_gpio.h>
  12 #else
  13 #include <mach/mt_gpio.h>
  14 #include <linux/xlog.h>
  15 #include "mt8193_iic.h"
  16 #include <mach/mt_pm_ldo.h>
  17 #include <mach/upmu_common.h>
  18 #endif
  19 #include "lcm_drv.h"
  20 #include "mt8193_lvds.h"
  21 //#include <mach/upmu_common.h>
  22
  23 // ---------------------------------------------------------------------------
  24 //  Local Constants
  25 // ---------------------------------------------------------------------------
  26
  27 #define FRAME_WIDTH  (1280)
  28 #define FRAME_HEIGHT (800)
  29
  30
  31 #define GPIO_SHIFT_EN        GPIO117
  32 #define GPIO_LCD_RST_EN      GPIO119
  33 #define GPIO_LCD_STB_EN      GPIO118
  34
  35
  36 #define HSYNC_PULSE_WIDTH 80
  37 #define HSYNC_BACK_PORCH  50
  38 #define HSYNC_FRONT_PORCH 30
  39 #define VSYNC_PULSE_WIDTH 7
  40 #define VSYNC_BACK_PORCH  10
  41 #define VSYNC_FRONT_PORCH 6
  42
  43 #define LCD_DATA_FORMAT LCD_DATA_FORMAT_VESA8BIT
  44
  45 #define V_TOTAL (FRAME_HEIGHT + VSYNC_PULSE_WIDTH + VSYNC_BACK_PORCH + VSYNC_FRONT_PORCH)
  46 #define H_TOTAL (FRAME_WIDTH + HSYNC_PULSE_WIDTH + HSYNC_BACK_PORCH + HSYNC_FRONT_PORCH)
  47
  48 #define H_START (HSYNC_PULSE_WIDTH + HSYNC_BACK_PORCH)
  49 #define H_END (H_START + FRAME_WIDTH - 1)
  50
  51 #define V_START (VSYNC_PULSE_WIDTH + VSYNC_BACK_PORCH)
  52 #define V_END (V_START + FRAME_HEIGHT - 1)
  53
  54 #define V_DELAY  0x0002  //Fixed Value
  55 #define H_DELAY  (FRAME_WIDTH + HSYNC_PULSE_WIDTH + HSYNC_BACK_PORCH + HSYNC_FRONT_PORCH - V_DELAY)
  56
  57 #ifdef BUILD_LK
  58 #define MT8193_REG_WRITE(add, data) mt8193_reg_i2c_write(add, data)
  59 #define MT8193_REG_READ(add) mt8193_reg_i2c_read(add)
  60 #elif (defined BUILD_UBOOT)
  61     // do nothing in uboot
  62 #else
  63 extern int mt8193_i2c_write(u16 addr, u32 data);
  64 extern int mt8193_i2c_read(u16 addr, u32 *data);
  65
  66 #define MT8193_REG_WRITE(add, data) mt8193_i2c_write(add, data)
  67 #define MT8193_REG_READ(add) lcm_mt8193_i2c_read(add)
  68 #endif
  69 // ---------------------------------------------------------------------------
  70 //  Local Variables
  71 // ---------------------------------------------------------------------------
  72
  73 static LCM_UTIL_FUNCS lcm_util = {0};
  74
  75 #define SET_RESET_PIN(v)    (mt_set_reset_pin((v)))
  76
  77 #define UDELAY(n) (lcm_util.udelay(n))
  78 #define MDELAY(n) (lcm_util.mdelay(n))
  79
  80
  81 // ---------------------------------------------------------------------------
  82 //  Local Functions
  83 // ---------------------------------------------------------------------------
  84
  85 static __inline void send_ctrl_cmd(unsigned int cmd)
  86 {
  87
  88 }
  89
  90 static __inline void send_data_cmd(unsigned int data)
  91 {
  92
  93 }
  94
  95 static __inline void set_lcm_register(unsigned int regIndex,
  96                                       unsigned int regData)
  97 {
  98
  99 }
 100
 101 static void lcm_set_gpio_output(unsigned int GPIO, unsigned int output)
 102 {
 103     mt_set_gpio_mode(GPIO, GPIO_MODE_00);
 104     mt_set_gpio_dir(GPIO, GPIO_DIR_OUT);
 105     mt_set_gpio_out(GPIO, (output>0)? GPIO_OUT_ONE: GPIO_OUT_ZERO);
 106 }
 107 // ---------------------------------------------------------------------------
 108 //  LCM Driver Implementations
 109 // ---------------------------------------------------------------------------
 110
 111 static void lcm_set_util_funcs(const LCM_UTIL_FUNCS *util)
 112 {
 113     memcpy(&lcm_util, util, sizeof(LCM_UTIL_FUNCS));
 114 }
 115
 116 #ifdef BUILD_LK
 117 #define I2C_CH                I2C0
 118 #define MT8193_I2C_ADDR       0x3A
 119
 120 int mt8193_reg_i2c_write(u16 addr, u32 data)
 121 {
 122     u8 buffer[8];
 123     u8 lens;
 124         U32 ret_code = 0;
 125
 126     if(((addr >> 8) & 0xFF) >= 0x80) // 8 bit : fast mode
 127     {
 128         buffer[0] = (addr >> 8) & 0xFF;
 129         buffer[1] = (data >> 24) & 0xFF;
 130         buffer[2] = (data >> 16) & 0xFF;
 131         buffer[3] = (data >> 8) & 0xFF;
 132         buffer[4] = data & 0xFF;
 133         lens = 5;
 134     }
 135     else // 16 bit : noraml mode
 136     {
 137         buffer[0] = (addr >> 8) & 0xFF;
 138         buffer[1] = addr & 0xFF;
 139         buffer[2] = (data >> 24) & 0xFF;
 140         buffer[3] = (data >> 16) & 0xFF;
 141         buffer[4] = (data >> 8) & 0xFF;
 142         buffer[5] = data & 0xFF;
 143         lens = 6;
 144     }
 145
 146     ret_code = mt_i2c_write(I2C_CH, MT8193_I2C_ADDR, buffer, lens, 0); // 0:I2C_PATH_NORMAL
 147     if (ret_code != 0)
 148     {
 149         printf("[LK/LCM] mt8193_reg_i2c_write reg[0x%X] fail, Error code [0x%X] \n", addr, ret_code);
 150         return ret_code;
 151     }
 152     printf("[LK/LCM] mt8193_reg_i2c_write reg[0x%X] = 0x%X\n", addr, data);
 153         return 0;
 154 }
 155
 156
 157
 158 u32 mt8193_reg_i2c_read(u16 addr)
 159 {
 160
 161     u8 buffer[8] = {0};
 162     u8 lens;
 163     u32 ret_code = 0;
 164     u32 data;
 165
 166     if(((addr >> 8) & 0xFF) >= 0x80) // 8 bit : fast mode
 167     {
 168         buffer[0] = (addr >> 8) & 0xFF;
 169         lens = 1;
 170     }
 171     else // 16 bit : noraml mode
 172     {
 173         buffer[0] = ( addr >> 8 ) & 0xFF;
 174         buffer[1] = addr & 0xFF;
 175         lens = 2;
 176     }
 177
 178     ret_code = mt_i2c_write(I2C_CH, MT8193_I2C_ADDR, buffer, lens, 0);    // set register command
 179     if (ret_code != 0)
 180         return ret_code;
 181
 182     lens = 4;
 183     ret_code = mt_i2c_read(I2C_CH, MT8193_I2C_ADDR, buffer, lens, 0);
 184     if (ret_code != 0)
 185     {
 186         printf("[LK/LCM] mt8193_reg_i2c_read reg[0x%X] fail, Error code [0x%X] \n", addr, ret_code);
 187         return ret_code;
 188     }
 189
 190     data = (buffer[3] << 24) | (buffer[2] << 16) | (buffer[1] << 8) | (buffer[0]); //LSB fisrt
 191     printf("[LK/LCM] mt8193_reg_i2c_read reg[0x%X] = 0x%X\n", addr, data);
 192
 193     return data;
 194
 195 }
 196 #elif (defined BUILD_UBOOT)
 197     // do nothing in uboot
 198 #else
 199 u32 lcm_mt8193_i2c_read(u16 addr)
 200 {
 201    u32 u4Reg = 0;
 202    u32 ret_code = 0;
 203
 204    ret_code = mt8193_i2c_read(addr, &u4Reg);
 205    if (ret_code != 0)
 206    {
 207            return ret_code;
 208    }
 209
 210    return u4Reg;
 211 }
 212 #endif
 213
 214 static void lcm_mt8193_set_ckgen(void)
 215 {
 216         u32 u4Reg = 0;
 217
 218         u4Reg = MT8193_REG_READ(REG_PLL_GPANACFG0);
 219         u4Reg&=(~(0x7c000000));  //clear bit 26~30
 220         u4Reg |= (RG_PLL1_FBDIV | RG_PLL1_PREDIV | RG_PLL1_RST_DLY | RG_PLL1_LF | RG_PLL1_MONCKEN | RG_PLL1_VODEN | RG_NFIPLL_EN);
 221         MT8193_REG_WRITE(REG_PLL_GPANACFG0, u4Reg);
 222
 223         u4Reg = MT8193_REG_READ(RG_LVDSWRAP_CTRL1);
 224         u4Reg&=(~(0x0000000f));  //clear bit 0~3
 225         u4Reg |= (RG_DCXO_POR_MON_EN | RG_PLL1_DIV);
 226         MT8193_REG_WRITE(RG_LVDSWRAP_CTRL1, u4Reg);
 227         UDELAY(200);
 228
 229     MT8193_REG_WRITE(REG_LVDS_ANACFG2, (RG_VPLL_BC | RG_VPLL_BIC | RG_VPLL_BIR | RG_VPLL_BP | RG_VPLL_BR));
 230
 231         u4Reg = 0;
 232         u4Reg |= (RG_VPLL_DIV | RG_VPLL_DPIX_CKSEL | RG_LVDS_DELAY | RG_VPLL_MKVCO |RG_VPLL_POSTDIV_EN);
 233         MT8193_REG_WRITE(REG_LVDS_ANACFG3, u4Reg);
 234         UDELAY(200);
 235         u4Reg &= (~(RG_VPLL_POSTDIV_EN));
 236         MT8193_REG_WRITE(REG_LVDS_ANACFG3, u4Reg);
 237 }
 238
 239 static void lcm_mt8193_set_lvds_analog(void)
 240 {
 241     MT8193_REG_WRITE(REG_LVDS_ANACFG4, (RG_BYPASS | RG_LVDS_BYPASS));
 242     MT8193_REG_WRITE(REG_LVDS_ANACFG0, (RG_LVDS_ATERM_EN | RG_LVDS_APSRC | RG_LVDS_ANSRC | RG_LVDS_ATVCM | RG_LVDS_ATVO));
 243     MT8193_REG_WRITE(REG_LVDS_ANACFG1, 0x00000000);
 244         MDELAY(10);
 245 }
 246
 247 static void lcm_mt8193_ckgen_power_on(void)
 248 {
 249     u32 u4Reg = 0;
 250
 251         u4Reg = MT8193_REG_READ(REG_PLL_GPANACFG0);
 252         u4Reg |= RG_PLL1_EN;
 253         MT8193_REG_WRITE(REG_PLL_GPANACFG0, u4Reg);
 254         UDELAY(200);
 255
 256         u4Reg = MT8193_REG_READ(REG_LVDS_ANACFG2);
 257         u4Reg &= (~(RG_VPLL_BG_PD | RG_VPLL_BIAS_PD));
 258         MT8193_REG_WRITE(REG_LVDS_ANACFG2, u4Reg);
 259     UDELAY(200);
 260
 261         u4Reg = MT8193_REG_READ(REG_LVDS_ANACFG4);
 262         u4Reg &= (~(RG_VPLL_PD));
 263         MT8193_REG_WRITE(REG_LVDS_ANACFG4, u4Reg);
 264     UDELAY(200);
 265         u4Reg &= (~(RG_VPLL_RST));
 266         MT8193_REG_WRITE(REG_LVDS_ANACFG4, u4Reg);
 267         UDELAY(200);
 268 }
 269
 270 static void lcm_mt8193_ckgen_power_off(void)
 271 {
 272     u32 u4Reg = 0;
 273
 274         u4Reg = MT8193_REG_READ(REG_LVDS_ANACFG4);
 275         u4Reg |= (RG_VPLL_RST);
 276         MT8193_REG_WRITE(REG_LVDS_ANACFG4, u4Reg);
 277         UDELAY(200);
 278         u4Reg |= (RG_VPLL_PD);
 279         MT8193_REG_WRITE(REG_LVDS_ANACFG4, u4Reg);
 280         UDELAY(200);
 281
 282         u4Reg = MT8193_REG_READ(REG_LVDS_ANACFG2);
 283         u4Reg |= (RG_VPLL_BG_PD | RG_VPLL_BIAS_PD);
 284         MT8193_REG_WRITE(REG_LVDS_ANACFG2, u4Reg);
 285         UDELAY(200);
 286
 287         u4Reg = MT8193_REG_READ(REG_PLL_GPANACFG0);
 288         u4Reg &= (~(RG_PLL1_EN));
 289         MT8193_REG_WRITE(REG_PLL_GPANACFG0, u4Reg);
 290         UDELAY(200);
 291 }
 292
 293 static void lcm_mt8193_lvds_analog_power_on(void)
 294 {
 295         u32 u4Reg = 0;
 296
 297         u4Reg = MT8193_REG_READ(REG_LVDS_ANACFG0);
 298         u4Reg &= (~(RG_LVDS_APD | RG_LVDS_BIASA_PD));
 299         MT8193_REG_WRITE(REG_LVDS_ANACFG0, u4Reg);
 300         UDELAY(200);
 301 }
 302
 303 static void lcm_mt8193_lvds_analog_power_off(void)
 304 {
 305         u32 u4Reg = 0;
 306
 307         u4Reg = MT8193_REG_READ(REG_LVDS_ANACFG0);
 308         u4Reg |= (RG_LVDS_APD | RG_LVDS_BIASA_PD);
 309         MT8193_REG_WRITE(REG_LVDS_ANACFG0, u4Reg);
 310         UDELAY(200);
 311 }
 312
 313 static void lcm_mt8193_set_lvds_digital(void)
 314 {
 315     MT8193_REG_WRITE(LVDS_CLK_CTRL, (RG_TEST_CK_EN | RG_RX_CK_EN | RG_TX_CK_EN));
 316         MT8193_REG_WRITE(LVDS_CH_SWAP, RG_SWAP_SEL);
 317         MT8193_REG_WRITE(LVDS_CLK_RESET, (RG_CTSCLK_RESET_B | RG_PCLK_RESET_B));
 318 }
 319
 320 static void lcm_mt8193_set_dgi0(void)
 321 {
 322         MT8193_REG_WRITE(DGI0_DATA_OUT_CTRL, DATA_OUT_SWAP);
 323         MT8193_REG_WRITE(DGI0_TG_CTRL00, PRGS_OUT);
 324         MT8193_REG_WRITE(DGI0_TG_CTRL02, ((V_TOTAL<<16) | H_TOTAL));
 325         MT8193_REG_WRITE(DGI0_TG_CTRL03, ((VSYNC_PULSE_WIDTH<<16) | HSYNC_PULSE_WIDTH));
 326         MT8193_REG_WRITE(DGI0_TG_CTRL05, ((H_START<<16) | H_END));
 327         MT8193_REG_WRITE(DGI0_TG_CTRL06, ((V_START<<16) | V_END));
 328         MT8193_REG_WRITE(DGI0_TG_CTRL07, ((V_START<<16) | V_END));
 329         MT8193_REG_WRITE(DGI0_TG_CTRL01, ((V_DELAY<<16) | H_DELAY));
 330         MT8193_REG_WRITE(DGI0_TTL_ANAIF_CTRL, TTL_CLK_INV_ENABLE);
 331         MT8193_REG_WRITE(DGI0_TTL_ANAIF_CTRL1, PAD_TTL_EN_PP);
 332 }
 333
 334 static void lcm_mt8193_anaif_clock_enable(void)
 335 {
 336     MT8193_REG_WRITE(DGI0_ANAIF_CTRL0, DGI0_PAD_CLK_ENABLE);
 337 }
 338
 339 static void lcm_mt8193_anaif_clock_disable(void)
 340 {
 341     MT8193_REG_WRITE(DGI0_ANAIF_CTRL0, DGI0_PAD_CLK_DISABLE);
 342 }
 343
 344 static void lcm_mt8193_dgi0_clock_enable(void)
 345 {
 346     MT8193_REG_WRITE(DGI0_CLK_RST_CTRL, (DGI0_CLK_OUT_ENABLE | DGI0_CLK_IN_INV_ENABLE | DGI0_CLK_IN_ENABLE));
 347 }
 348
 349 static void lcm_mt8193_dgi0_clock_disable(void)
 350 {
 351     MT8193_REG_WRITE(DGI0_CLK_RST_CTRL, DGI0_CLK_OUT_DISABLE);
 352 }
 353
 354 static void lcm_mt8193_dgi0_fifo_write_disable(void)
 355 {
 356         MT8193_REG_WRITE(DGI0_DEC_CTRL, 0x0);
 357 }
 358
 359 static void lcm_mt8193_dgi0_fifo_write_enable(void)
 360 {
 361     MT8193_REG_WRITE(DGI0_DEC_CTRL, FIFO_WRITE_EN);
 362 }
 363
 364 static void lcm_mt8193_sw_reset(void)
 365 {
 366     MT8193_REG_WRITE(DGI0_FIFO_CTRL, (SW_RST | FIFO_RESET_ON | RD_START));
 367         UDELAY(200);
 368         MT8193_REG_WRITE(DGI0_FIFO_CTRL, (FIFO_RESET_ON | RD_START));
 369 }
 370
 371 static void lcm_mt8193_lvds_power_off(void)
 372 {
 373     MT8193_REG_WRITE(REG_LVDS_PWR_CTRL, 0x00000006);
 374         UDELAY(200);
 375         MT8193_REG_WRITE(REG_LVDS_PWR_CTRL, 0x00000007);
 376         UDELAY(200);
 377     MT8193_REG_WRITE(REG_LVDS_PWR_RST_B, 0x00000000);
 378         UDELAY(200);
 379         MT8193_REG_WRITE(REG_LVDS_PWR_CTRL, 0x00000005);
 380         MDELAY(5);
 381 }
 382
 383 static void lcm_mt8193_lvds_power_on(void)
 384 {
 385     MT8193_REG_WRITE(REG_LVDS_PWR_CTRL, 0x00000007);
 386         UDELAY(200);
 387         MT8193_REG_WRITE(REG_LVDS_PWR_RST_B, 0x00000001);
 388         UDELAY(200);
 389     MT8193_REG_WRITE(REG_LVDS_PWR_CTRL, 0x00000006);
 390         UDELAY(200);
 391         MT8193_REG_WRITE(REG_LVDS_PWR_CTRL, 0x00000002);
 392         MDELAY(5);
 393 }
 394
 395 static void lcm_mt8193_lvds_top_clock_disable(void)
 396 {
 397         MT8193_REG_WRITE(LVDS_CLK_CTRL, 0x0);
 398 }
 399
 400 static void lcm_mt8193_lvds_top_clock_enable(void)
 401 {
 402     MT8193_REG_WRITE(LVDS_CLK_CTRL, (RG_TEST_CK_EN | RG_RX_CK_EN | RG_TX_CK_EN));
 403 }
 404
 405 static void lcm_mt8193_lvds_out_disable(void)
 406 {
 407     MT8193_REG_WRITE(LVDS_OUTPUT_CTRL, 0x0);
 408 }
 409
 410 static void lcm_mt8193_lvds_out_enable(void)
 411 {
 412         MT8193_REG_WRITE(LVDS_OUTPUT_CTRL, (RG_LVDSRX_FIFO_EN | RG_SYNC_TRIG_MODE | RG_OUT_FIFO_EN | RG_LVDS_E));
 413 }
 414
 415 static void lcm_mt8193_enable_output(void)
 416 {
 417         lcm_mt8193_lvds_power_on();
 418         lcm_mt8193_anaif_clock_enable();
 419         lcm_mt8193_set_ckgen();
 420         lcm_mt8193_ckgen_power_on();
 421         lcm_mt8193_dgi0_clock_enable();
 422         lcm_mt8193_dgi0_fifo_write_disable();
 423         lcm_mt8193_set_dgi0();
 424         lcm_mt8193_dgi0_fifo_write_enable();
 425         lcm_mt8193_lvds_top_clock_enable();
 426         lcm_mt8193_lvds_out_disable();
 427         lcm_mt8193_set_lvds_digital();
 428         lcm_mt8193_lvds_analog_power_on();
 429         lcm_mt8193_set_lvds_analog();
 430         MDELAY(1);
 431         lcm_mt8193_lvds_out_enable();
 432         lcm_mt8193_sw_reset();
 433 }
 434
 435 static void lcm_mt8193_disable_output(void)
 436 {
 437         lcm_mt8193_lvds_analog_power_off();
 438         lcm_mt8193_lvds_out_disable();
 439         lcm_mt8193_lvds_top_clock_disable();
 440         lcm_mt8193_dgi0_fifo_write_disable();
 441     lcm_mt8193_dgi0_clock_disable();
 442         lcm_mt8193_ckgen_power_off();
 443     lcm_mt8193_anaif_clock_disable();
 444     lcm_mt8193_lvds_power_off();
 445 }
 446
 447 static void lcm_get_params(LCM_PARAMS *params)
 448 {
 449     memset(params, 0, sizeof(LCM_PARAMS));
 450
 451     params->type   = LCM_TYPE_DPI;
 452     params->ctrl   = LCM_CTRL_SERIAL_DBI;
 453     params->width  = FRAME_WIDTH;
 454     params->height = FRAME_HEIGHT;
 455     params->io_select_mode = 0;
 456
 457 // div0_real = div0==0 ? 1:
 458 //          div0==1 ? 2: 4;
 459 // div1_real = div1==0 ? 1:
 460 //          div1==1 ? 2: 4;
 461 // freq = 26*mipi_pll_clk_ref/2^24/div0_real/div1_real/8
 462
 463     /* RGB interface configurations */
 464     params->dpi.mipi_pll_clk_ref  = 774333046;
 465     params->dpi.mipi_pll_clk_div1 = 0;  // div0=0,1,2,3;div0_real=1,2,4,4
 466     params->dpi.mipi_pll_clk_div2 = 0;  // div1=0,1,2,3;div1_real=1,2,4,4
 467     params->dpi.dpi_clk_div       = 4;           //{4,2}, pll/4=51.025M
 468     params->dpi.dpi_clk_duty      = 2;
 469
 470     params->dpi.clk_pol           = LCM_POLARITY_RISING;
 471     params->dpi.de_pol            = LCM_POLARITY_RISING;
 472     params->dpi.vsync_pol         = LCM_POLARITY_FALLING;
 473     params->dpi.hsync_pol         = LCM_POLARITY_FALLING;
 474
 475     params->dpi.hsync_pulse_width = HSYNC_PULSE_WIDTH;
 476     params->dpi.hsync_back_porch  = HSYNC_BACK_PORCH;
 477     params->dpi.hsync_front_porch = HSYNC_FRONT_PORCH;
 478     params->dpi.vsync_pulse_width = VSYNC_PULSE_WIDTH;
 479     params->dpi.vsync_back_porch  = VSYNC_BACK_PORCH;
 480     params->dpi.vsync_front_porch = VSYNC_FRONT_PORCH;
 481
 482     params->dpi.i2x_en = 1;
 483
 484     params->dpi.format            = LCM_DPI_FORMAT_RGB888;   // format is 24 bit
 485     params->dpi.rgb_order         = LCM_COLOR_ORDER_RGB;
 486     params->dpi.is_serial_output  = 0;
 487
 488     params->dpi.intermediat_buffer_num = 0;
 489
 490     params->dpi.io_driving_current = LCM_DRIVING_CURRENT_2MA;
 491 }
 492
 493
 494 static void lcm_init(void)
 495 {
 496 #ifdef BUILD_LK
 497         printf("[LK/LCM] lcm_init()  \n");
 498
 499
 500         lcm_mt8193_enable_output();
 501
 502     //VGP6 3.3V
 503     upmu_set_rg_vgp1_vosel(0x7);
 504     upmu_set_rg_vgp1_en(0x1);
 505
 506     MDELAY(20);
 507
 508
 509
 510     lcm_set_gpio_output(GPIO_LCD_STB_EN, 1);
 511
 512     lcm_set_gpio_output(GPIO_LCD_RST_EN, 1);
 513         MDELAY(20);
 514     lcm_set_gpio_output(GPIO_LCD_RST_EN, 0);
 515     MDELAY(5);
 516     lcm_set_gpio_output(GPIO_LCD_RST_EN, 1);
 517         MDELAY(20);
 518
 519 #elif (defined BUILD_UBOOT)
 520     // do nothing in uboot
 521 #else
 522     printk("[LCM] lcm_init() enter\n");
 523
 524 #endif
 525 }
 526
 527
 528 static void lcm_suspend(void)
 529 {
 530 #ifdef BUILD_LK
 531         printf("[LK/LCM] MT8193 EJ101IA lcm_suspend() enter\n");
 532
 533     lcm_mt8193_disable_output();
 534
 535     lcm_set_gpio_output(GPIO_LCD_STB_EN, 0);
 536     MDELAY(20);
 537
 538     lcm_set_gpio_output(GPIO_LCD_RST_EN, 0);
 539     MDELAY(20);
 540     lcm_set_gpio_output(GPIO_SHIFT_EN, 0);
 541     MDELAY(20);
 542
 543
 544     //VGP1 3.3V
 545     upmu_set_rg_vgp1_vosel(0);
 546     upmu_set_rg_vgp1_en(0);
 547
 548 #elif (defined BUILD_UBOOT)
 549                 // do nothing in uboot
 550 #else
 551         printk("[LCM] MT8193 EJ101IA lcm_suspend() enter\n");
 552
 553     lcm_mt8193_disable_output();
 554
 555     lcm_set_gpio_output(GPIO_LCD_STB_EN, 0);
 556     MDELAY(5);
 557     lcm_set_gpio_output(GPIO_LCD_RST_EN, 0);
 558     MDELAY(5);
 559     lcm_set_gpio_output(GPIO_SHIFT_EN, 0);
 560     MDELAY(20);
 561
 562     upmu_set_rg_vgp1_en(0);
 563     upmu_set_rg_vgp1_vosel(0);
 564
 565     MDELAY(50);
 566
 567 #endif
 568 }
 569
 570
 571 static void lcm_resume(void)
 572 {
 573 #ifdef BUILD_LK
 574     u32 u4Reg = 0;
 575
 576         printf("[LK/LCM] lcm_resume() enter\n");
 577
 578
 579         u4Reg = MT8193_REG_READ(REG_LVDS_PWR_RST_B);
 580         if(1)
 581         {
 582           lcm_mt8193_enable_output();
 583
 584
 585       upmu_set_rg_vgp1_vosel(0x7);
 586       upmu_set_rg_vgp1_en(0x1);
 587
 588
 589     lcm_set_gpio_output(GPIO_SHIFT_EN, 1);
 590
 591       lcm_set_gpio_output(GPIO_LCD_STB_EN, 1);
 592     MDELAY(20);
 593     lcm_set_gpio_output(GPIO_LCD_RST_EN, 1);
 594     MDELAY(20);
 595
 596
 597
 598     }
 599 #elif (defined BUILD_UBOOT)
 600                 // do nothing in uboot
 601 #else
 602         printk("[LCM] MT8193 EJ101IA lcm_resume() enter\n");
 603
 604         lcm_mt8193_enable_output();
 605
 606       upmu_set_rg_vgp1_en(0x1);
 607       upmu_set_rg_vgp1_vosel(0x7);
 608
 609     lcm_set_gpio_output(GPIO_SHIFT_EN, 1);
 610     lcm_set_gpio_output(GPIO_LCD_STB_EN, 1);
 611     MDELAY(5);
 612     lcm_set_gpio_output(GPIO_LCD_RST_EN, 1);
 613     MDELAY(20);
 614     lcm_set_gpio_output(GPIO_LCD_RST_EN, 0);
 615     MDELAY(5);
 616
 617     lcm_set_gpio_output(GPIO_LCD_RST_EN, 1);
 618     MDELAY(180);
 619
 620 #endif
 621 }
 622
 623 static unsigned int lcm_check_status(void)
 624 {
 625         return 0;
 626 }
 627
 628 static void lcm_update(unsigned int x, unsigned int y,
 629                        unsigned int width, unsigned int height)
 630 {
 631
 632 }
 633
 634
 635 LCM_DRIVER ej101ia_lcm_drv =
 636 {
 637     .name               = "EJ101IA",
 638         .set_util_funcs = lcm_set_util_funcs,
 639         .get_params     = lcm_get_params,
 640         .init           = lcm_init,
 641         .suspend        = lcm_suspend,
 642         .resume         = lcm_resume,
 643         .check_status   = lcm_check_status,
 644         .update         = lcm_update,
 645 };
 646