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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / i2c / mt8127 / i2c.c
1 #include <linux/kernel.h>
2 #include <linux/module.h>
3 #include <linux/slab.h>
4 #include <linux/i2c.h>
5 #include <linux/init.h>
6 #include <linux/interrupt.h>
7 #include <linux/sched.h>
8 #include <linux/delay.h>
9 #include <linux/errno.h>
10 #include <linux/err.h>
11 #include <linux/device.h>
12 #include <linux/platform_device.h>
13 #include <linux/wait.h>
14 #include <linux/mm.h>
15 #include <linux/dma-mapping.h>
16 #include <asm/scatterlist.h>
17 #include <linux/scatterlist.h>
18 #include <asm/io.h>
19 //#include <mach/dma.h>
20 #include <asm/system.h>
21 #include <mach/mt_reg_base.h>
22 #include <mach/mt_gpio.h>
23 #include <mach/mt_clkmgr.h>
24 #include <mt_i2c.h>
25 #include <mach/sync_write.h>
26 #include "mach/memory.h"
27 #include "cust_gpio_usage.h"
28
29 //define ONLY_KERNEL
30 /******************************internal API********************************************************/
31 inline void i2c_writel(mt_i2c * i2c, U8 offset, U16 value)
32 {
33 //__raw_writew(value, (i2c->base) + (offset));
34 mt65xx_reg_sync_writel(value, (i2c->base) + (offset));
35 }
36
37 inline U32 i2c_readl(mt_i2c * i2c, U8 offset)
38 {
39 return __raw_readl((void*)((i2c->base) + (offset)));
40 }
41 /***********************************declare API**************************/
42 static void mt_i2c_clock_enable(mt_i2c *i2c);
43 static void mt_i2c_clock_disable(mt_i2c *i2c);
44
45 /***********************************I2C common Param **************************/
46 volatile U32 I2C_TIMING_REG_BACKUP[7]={0};
47 volatile U32 I2C_HIGHSP_REG_BACKUP[7]={0};
48 /***********************************I2C Param only used in kernel*****************/
49 /*this field is only for 3d camera*/
50 #ifdef I2C_DRIVER_IN_KERNEL
51 static struct i2c_msg g_msg[2];
52 static mt_i2c *g_i2c[2];
53 #define I2C_DRV_NAME "mt-i2c"
54 #endif
55 /***********************************i2c debug********************************************************/
56 //#define I2C_DEBUG_FS
57 #ifdef I2C_DEBUG_FS
58 #define PORT_COUNT 7
59 #define MESSAGE_COUNT 16
60 #define I2C_T_DMA 1
61 #define I2C_T_TRANSFERFLOW 2
62 #define I2C_T_SPEED 3
63 /*7 ports,16 types of message*/
64 U8 i2c_port[ PORT_COUNT ][ MESSAGE_COUNT ];
65 #if 0
66 #define I2CINFO( type, format, arg...) do { \
67 if ( type < MESSAGE_COUNT && type >= 0 ) { \
68 if ( i2c_port[i2c->id][0] != 0 && ( i2c_port[i2c->id][type] != 0 || i2c_port[i2c->id][MESSAGE_COUNT - 1] != 0) ) { \
69 I2CLOG( format, ## arg); \
70 } \
71 } \
72 } while (0)
73 #endif
74 #define I2CINFO( type, format, arg...) do { \
75 I2CLOG( format, ## arg); \
76 } while (0)
77
78 #ifdef I2C_DRIVER_IN_KERNEL
79 static ssize_t show_config(struct device *dev, struct device_attribute *attr, char *buff)
80 {
81 S32 i = 0;
82 S32 j = 0;
83 char *buf = buff;
84 for ( i =0; i < PORT_COUNT; i++){
85 for ( j=0;j < MESSAGE_COUNT; j++) i2c_port[i][j] += '0';
86 strncpy(buf, (char *)i2c_port[i], MESSAGE_COUNT);
87 buf += MESSAGE_COUNT;
88 *buf = '\n';
89 buf++;
90 for ( j=0;j < MESSAGE_COUNT; j++) i2c_port[i][j] -= '0';
91 }
92 return (buf - buff);
93 }
94
95 static ssize_t set_config(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
96 {
97 S32 port,type,status;
98
99 if ( sscanf(buf, "%d %d %d", &port, &type, &status) ) {
100 if ( port >= PORT_COUNT || port < 0 || type >= MESSAGE_COUNT || type < 0 ) {
101 /*Invalid param*/
102 I2CERR("i2c debug system: Parameter overflowed!\n");
103 } else {
104 if ( status != 0 )
105 i2c_port[port][type] = 1;
106 else
107 i2c_port[port][type] = 0;
108
109 I2CLOG("port:%d type:%d status:%s\ni2c debug system: Parameter accepted!\n", port, type, status?"on":"off");
110 }
111 } else {
112 /*parameter invalid*/
113 I2CERR("i2c debug system: Parameter invalid!\n");
114 }
115 return count;
116 }
117
118 static DEVICE_ATTR(debug, S_IRUGO|S_IWUGO, show_config, set_config);
119 #endif
120 #else
121 #define I2CINFO(type, format, arg...)
122 #endif
123 /***********************************common API********************************************************/
124 /*Set i2c port speed*/
125 static S32 i2c_set_speed(mt_i2c *i2c)
126 {
127 S32 ret = 0;
128 static S32 mode = 0;
129 static U32 khz = 0;
130 static U8 last_id = 0;
131 //U32 base = i2c->base;
132 U16 step_cnt_div = 0;
133 U16 sample_cnt_div = 0;
134 U32 tmp, sclk, hclk = i2c->clk;
135 U16 max_step_cnt_div = 0;
136 U32 diff, min_diff = i2c->clk;
137 U16 sample_div = MAX_SAMPLE_CNT_DIV;
138 U16 step_div = 0;
139 //I2CFUC();
140 //I2CLOG("i2c_set_speed=================\n");
141 //compare the current speed with the latest mode
142 if((mode == i2c->mode) && (khz == i2c->speed)){
143 if(i2c->id == last_id){//same controller
144 I2CINFO( I2C_T_SPEED, " same controller still set sclk to %ldkhz\n", i2c->speed);
145 } else {//diff controller
146 I2CINFO( I2C_T_SPEED, " diff controller also set sclk to %ldkhz\n", i2c->speed);
147 i2c->timing_reg = I2C_TIMING_REG_BACKUP[i2c->id] = I2C_TIMING_REG_BACKUP[last_id];
148 i2c->high_speed_reg = I2C_HIGHSP_REG_BACKUP[i2c->id] = I2C_HIGHSP_REG_BACKUP[last_id];
149 }
150 ret = 0;
151 goto end;
152 }
153 mode=i2c->mode;
154 khz = i2c->speed;
155
156 max_step_cnt_div = (mode == HS_MODE) ? MAX_HS_STEP_CNT_DIV : MAX_STEP_CNT_DIV;
157 step_div = max_step_cnt_div;
158
159 if((mode == FS_MODE && khz > MAX_FS_MODE_SPEED) || (mode == HS_MODE && khz > MAX_HS_MODE_SPEED)){
160 I2CERR(" the speed is too fast for this mode.\n");
161 I2C_BUG_ON((mode == FS_MODE && khz > MAX_FS_MODE_SPEED) || (mode == HS_MODE && khz > MAX_HS_MODE_SPEED));
162 ret = -EINVAL_I2C;
163 goto end;
164 }
165 // I2CERR("first:khz=%d,mode=%d sclk=%d,min_diff=%d,max_step_cnt_div=%d\n",khz,mode,sclk,min_diff,max_step_cnt_div);
166 /*Find the best combination*/
167 for (sample_cnt_div = 1; sample_cnt_div <= MAX_SAMPLE_CNT_DIV; sample_cnt_div++) {
168 for (step_cnt_div = 1; step_cnt_div <= max_step_cnt_div; step_cnt_div++) {
169 sclk = (hclk >> 1) / (sample_cnt_div * step_cnt_div);
170 if (sclk > khz)
171 continue;
172 diff = khz - sclk;
173 if (diff < min_diff) {
174 min_diff = diff;
175 sample_div = sample_cnt_div;
176 step_div = step_cnt_div;
177 }
178 }
179 }
180 sample_cnt_div = sample_div;
181 step_cnt_div = step_div;
182 sclk = hclk / (2 * sample_cnt_div * step_cnt_div);
183 //I2CERR("second:sclk=%d khz=%d,i2c->speed=%d hclk=%d sample_cnt_div=%d,step_cnt_div=%d.\n",sclk,khz,i2c->speed,hclk,sample_cnt_div,step_cnt_div);
184 if (sclk > khz) {
185 I2CERR("%s mode: unsupported speed (%ldkhz)\n",(mode == HS_MODE) ? "HS" : "ST/FT", (long int)khz);
186 I2CLOG("i2c->clk=%d,sclk=%d khz=%d,i2c->speed=%d hclk=%d sample_cnt_div=%d,step_cnt_div=%d.\n",i2c->clk,sclk,khz,i2c->speed,hclk,sample_cnt_div,step_cnt_div);
187 I2C_BUG_ON(sclk > khz);
188 ret = -ENOTSUPP_I2C;
189 goto end;
190 }
191
192 step_cnt_div--;
193 sample_cnt_div--;
194
195 //spin_lock(&i2c->lock);
196
197 if (mode == HS_MODE) {
198
199 /*Set the hignspeed timing control register*/
200 tmp = i2c_readl(i2c, OFFSET_TIMING) & ~((0x7 << 8) | (0x3f << 0));
201 tmp = (0 & 0x7) << 8 | (16 & 0x3f) << 0 | tmp;
202 i2c->timing_reg=tmp;
203 //i2c_writel(i2c, OFFSET_TIMING, tmp);
204 I2C_TIMING_REG_BACKUP[i2c->id]=tmp;
205
206 /*Set the hign speed mode register*/
207 tmp = i2c_readl(i2c, OFFSET_HS) & ~((0x7 << 12) | (0x7 << 8));
208 tmp = (sample_cnt_div & 0x7) << 12 | (step_cnt_div & 0x7) << 8 | tmp;
209 /*Enable the hign speed transaction*/
210 tmp |= 0x0001;
211 i2c->high_speed_reg=tmp;
212 I2C_HIGHSP_REG_BACKUP[i2c->id]=tmp;
213 //i2c_writel(i2c, OFFSET_HS, tmp);
214 }
215 else {
216 /*Set non-highspeed timing*/
217 tmp = i2c_readl(i2c, OFFSET_TIMING) & ~((0x7 << 8) | (0x3f << 0));
218 tmp = (sample_cnt_div & 0x7) << 8 | (step_cnt_div & 0x3f) << 0 | tmp;
219 i2c->timing_reg=tmp;
220 I2C_TIMING_REG_BACKUP[i2c->id]=tmp;
221 //i2c_writel(i2c, OFFSET_TIMING, tmp);
222 /*Disable the high speed transaction*/
223 //I2CERR("NOT HS_MODE============================1\n");
224 tmp = i2c_readl(i2c, OFFSET_HS) & ~(0x0001);
225 //I2CERR("NOT HS_MODE============================2\n");
226 i2c->high_speed_reg=tmp;
227 I2C_HIGHSP_REG_BACKUP[i2c->id]=tmp;
228 //i2c_writel(i2c, OFFSET_HS, tmp);
229 //I2CERR("NOT HS_MODE============================3\n");
230 }
231 //spin_unlock(&i2c->lock);
232 I2CINFO( I2C_T_SPEED, " set sclk to %ldkhz(orig:%ldkhz), sample=%d,step=%d\n", sclk, khz, sample_cnt_div, step_cnt_div);
233 end:
234 last_id = i2c->id;
235 return ret;
236 }
237
238 void _i2c_dump_info(mt_i2c *i2c)
239 {
240 //I2CFUC();
241 I2CLOG("I2C structure:\n"
242 I2CTAG"Clk=%d,Id=%d,Speed mode=%x,St_rs=%x,Dma_en=%x,Op=%x,Poll_en=%x,Irq_stat=%x\n"
243 I2CTAG"Trans_len=%x,Trans_num=%x,Trans_auxlen=%x,Data_size=%x,speed=%d\n"
244 I2CTAG"Trans_stop=%u,Trans_comp=%u,Trans_error=%u\n",
245 i2c->clk,i2c->id,i2c->mode,i2c->st_rs,i2c->dma_en,i2c->op,i2c->poll_en,i2c->irq_stat,\
246 i2c->trans_data.trans_len,i2c->trans_data.trans_num,i2c->trans_data.trans_auxlen,i2c->trans_data.data_size,i2c->speed,\
247 atomic_read(&i2c->trans_stop),atomic_read(&i2c->trans_comp),atomic_read(&i2c->trans_err));
248
249 I2CLOG("base address 0x%x\n",i2c->base);
250 I2CLOG("I2C register:\n"
251 I2CTAG"SLAVE_ADDR=%x,INTR_MASK=%x,INTR_STAT=%x,CONTROL=%x,TRANSFER_LEN=%x\n"
252 I2CTAG"TRANSAC_LEN=%x,DELAY_LEN=%x,TIMING=%x,START=%x,FIFO_STAT=%x\n"
253 I2CTAG"IO_CONFIG=%x,HS=%x,DCM_EN=%x,DEBUGSTAT=%x,EXT_CONF=%x\n",
254 (i2c_readl(i2c, OFFSET_SLAVE_ADDR)),
255 (i2c_readl(i2c, OFFSET_INTR_MASK)),
256 (i2c_readl(i2c, OFFSET_INTR_STAT)),
257 (i2c_readl(i2c, OFFSET_CONTROL)),
258 (i2c_readl(i2c, OFFSET_TRANSFER_LEN)),
259 (i2c_readl(i2c, OFFSET_TRANSAC_LEN)),
260 (i2c_readl(i2c, OFFSET_DELAY_LEN)),
261 (i2c_readl(i2c, OFFSET_TIMING)),
262 (i2c_readl(i2c, OFFSET_START)),
263 (i2c_readl(i2c, OFFSET_FIFO_STAT)),
264 (i2c_readl(i2c, OFFSET_IO_CONFIG)),
265 (i2c_readl(i2c, OFFSET_HS)),
266 (i2c_readl(i2c, OFFSET_DCM_EN)),
267 (i2c_readl(i2c, OFFSET_DEBUGSTAT)),
268 (i2c_readl(i2c, OFFSET_EXT_CONF)));
269 /*
270 I2CERR("DMA register:\nINT_FLAG %x\nCON %x\nTX_MEM_ADDR %x\nRX_MEM_ADDR %x\nTX_LEN %x\nRX_LEN %x\nINT_EN %x\nEN %x\nINT_BUF_SIZE %x\n",
271 (__raw_readl(i2c->pdmabase+OFFSET_INT_FLAG)),
272 (__raw_readl(i2c->pdmabase+OFFSET_CON)),
273 (__raw_readl(i2c->pdmabase+OFFSET_TX_MEM_ADDR)),
274 (__raw_readl(i2c->pdmabase+OFFSET_RX_MEM_ADDR)),
275 (__raw_readl(i2c->pdmabase+OFFSET_TX_LEN)),
276 (__raw_readl(i2c->pdmabase+OFFSET_RX_LEN)),
277 (__raw_readl(i2c->pdmabase+OFFSET_INT_EN)),
278 (__raw_readl(i2c->pdmabase+OFFSET_EN)),
279 (__raw_readl(i2c->pdmabase+OFFSET_INT_BUF_SIZE)));
280 */
281 /*clock*/
282 I2CLOG("Clock stat(0x10003018) is 0x%08x, %s\n",__raw_readl((void*)0xF0003018), (__raw_readl((void*)0xF0003018)>>21) & (1 << i2c->id)?"disable":"enable");
283
284 I2CLOG("mt_get_gpio_in I2C0_SDA=%d,I2C0_SCA=%d,I2C1_SDA=%d,I2C1_SCA=%d",\
285 mt_get_gpio_in(GPIO_I2C0_SDA_PIN),mt_get_gpio_in(GPIO_I2C0_SCA_PIN),mt_get_gpio_in(GPIO_I2C1_SDA_PIN),mt_get_gpio_in(GPIO_I2C1_SCA_PIN));
286 return;
287 }
288 static S32 _i2c_deal_result(mt_i2c *i2c)
289 {
290 #ifdef I2C_DRIVER_IN_KERNEL
291 long tmo = i2c->adap.timeout;
292 #else
293 long tmo = 1;
294 #endif
295 U16 data_size = 0;
296 U8 *ptr = i2c->msg_buf;
297 S32 ret = i2c->msg_len;
298 long tmo_poll = 0xffff;
299 //I2CFUC();
300 //addr_reg = i2c->read_flag ? ((i2c->addr << 1) | 0x1) : ((i2c->addr << 1) & ~0x1);
301
302 if(i2c->poll_en)
303 { /*master read && poll mode*/
304 for (;;)
305 { /*check the interrupt status register*/
306 i2c->irq_stat = i2c_readl(i2c, OFFSET_INTR_STAT);
307 //I2CLOG("irq_stat = 0x%x\n", i2c->irq_stat);
308 if(i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP))
309 {
310 atomic_set(&i2c->trans_stop, 1);
311 spin_lock(&i2c->lock);
312 /*Clear interrupt status,write 1 clear*/
313 i2c_writel(i2c, OFFSET_INTR_STAT, (I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP));
314 spin_unlock(&i2c->lock);
315 break;
316 }
317 tmo_poll --;
318 if(tmo_poll == 0) {
319 tmo = 0;
320 break;
321 }
322 }
323 } else { /*Interrupt mode,wait for interrupt wake up*/
324 tmo = wait_event_timeout(i2c->wait,atomic_read(&i2c->trans_stop), tmo);
325 }
326
327 /*Save status register status to i2c struct*/
328 #ifdef I2C_DRIVER_IN_KERNEL
329 if (i2c->irq_stat & I2C_TRANSAC_COMP) {
330 atomic_set(&i2c->trans_err, 0);
331 atomic_set(&i2c->trans_comp, 1);
332 }
333 atomic_set(&i2c->trans_err, i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR));
334 #endif
335
336 /*Check the transfer status*/
337 if (!(tmo == 0 || atomic_read(&i2c->trans_err)) )
338 {
339 /*Transfer success ,we need to get data from fifo*/
340 if((!i2c->dma_en) && (i2c->op == I2C_MASTER_RD || i2c->op == I2C_MASTER_WRRD) )
341 { /*only read mode or write_read mode and fifo mode need to get data*/
342 data_size = (i2c_readl(i2c, OFFSET_FIFO_STAT) >> 4) & 0x000F;
343 BUG_ON(data_size > i2c->msg_len);
344 //I2CLOG("data_size=%d\n",data_size);
345 while (data_size--)
346 {
347 *ptr = i2c_readl(i2c, OFFSET_DATA_PORT);
348 //I2CLOG("addr %x read byte = 0x%x\n", i2c->addr, *ptr);
349 ptr++;
350 }
351 }
352 #ifdef I2C_DEBUG_FS
353 _i2c_dump_info(i2c);
354 #endif
355 }else
356 {
357 /*Timeout or ACKERR*/
358 if ( tmo == 0 ){
359 I2CERR("id=%d,addr: %x, transfer timeout\n",i2c->id, i2c->addr);
360 ret = -ETIMEDOUT_I2C;
361 } else
362 {
363 I2CERR("id=%d,addr: %x, transfer error\n",i2c->id,i2c->addr);
364 ret = -EREMOTEIO_I2C;
365 }
366 if (i2c->irq_stat & I2C_HS_NACKERR)
367 I2CERR("I2C_HS_NACKERR\n");
368 if (i2c->irq_stat & I2C_ACKERR)
369 I2CERR("I2C_ACKERR\n");
370 if (i2c->filter_msg==FALSE) //TEST
371 {
372 _i2c_dump_info(i2c);
373 }
374
375 spin_lock(&i2c->lock);
376 /*Reset i2c port*/
377 i2c_writel(i2c, OFFSET_SOFTRESET, 0x0001);
378 /*Set slave address*/
379 i2c_writel( i2c, OFFSET_SLAVE_ADDR, 0x0000 );
380 /*Clear interrupt status*/
381 i2c_writel(i2c, OFFSET_INTR_STAT, (I2C_HS_NACKERR|I2C_ACKERR|I2C_TRANSAC_COMP));
382 /*Clear fifo address*/
383 i2c_writel(i2c, OFFSET_FIFO_ADDR_CLR, 0x0001);
384
385 spin_unlock(&i2c->lock);
386 }
387 return ret;
388 }
389
390
391 static void _i2c_write_reg(mt_i2c *i2c)
392 {
393 U8 *ptr = i2c->msg_buf;
394 U32 data_size=i2c->trans_data.data_size;
395 U32 addr_reg=0;
396 //I2CFUC();
397
398 i2c_writel(i2c, OFFSET_CONTROL, i2c->control_reg);
399
400 /*set start condition */
401 if(i2c->speed <= 100){
402 i2c_writel(i2c,OFFSET_EXT_CONF, 0x8001);
403 } else {
404 i2c_writel(i2c,OFFSET_EXT_CONF, 0x1800);
405 }
406 //set timing reg
407 i2c_writel(i2c, OFFSET_TIMING, i2c->timing_reg);
408 i2c_writel(i2c, OFFSET_HS, i2c->high_speed_reg);
409
410 if(0 == i2c->delay_len)
411 i2c->delay_len = 2;
412 if(~i2c->control_reg & I2C_CONTROL_RS){ // bit is set to 1, i.e.,use repeated stop
413 i2c_writel(i2c, OFFSET_DELAY_LEN, i2c->delay_len);
414 }
415
416 /*Set ioconfig*/
417 if (i2c->pushpull) {
418 i2c_writel(i2c, OFFSET_IO_CONFIG, 0x0000);
419 } else {
420 i2c_writel(i2c, OFFSET_IO_CONFIG, 0x0003);
421 }
422
423 /*Set slave address*/
424
425 addr_reg = i2c->read_flag ? ((i2c->addr << 1) | 0x1) : ((i2c->addr << 1) & ~0x1);
426 i2c_writel(i2c, OFFSET_SLAVE_ADDR, addr_reg);
427 /*Clear interrupt status*/
428 i2c_writel(i2c, OFFSET_INTR_STAT, (I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP));
429 /*Clear fifo address*/
430 i2c_writel(i2c, OFFSET_FIFO_ADDR_CLR, 0x0001);
431 /*Setup the interrupt mask flag*/
432 if(i2c->poll_en)
433 i2c_writel(i2c, OFFSET_INTR_MASK, i2c_readl(i2c, OFFSET_INTR_MASK) & ~(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP)); /*Disable interrupt*/
434 else
435 i2c_writel(i2c, OFFSET_INTR_MASK, i2c_readl(i2c, OFFSET_INTR_MASK) | (I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP)); /*Enable interrupt*/
436 /*Set transfer len */
437 i2c_writel(i2c, OFFSET_TRANSFER_LEN, ((i2c->trans_data.trans_auxlen & 0x1F) << 8) | (i2c->trans_data.trans_len & 0xFF));
438 /*Set transaction len*/
439 i2c_writel(i2c, OFFSET_TRANSAC_LEN, i2c->trans_data.trans_num & 0xFF);
440
441 /*Prepare buffer data to start transfer*/
442
443 if(i2c->dma_en)
444 {
445 if (I2C_MASTER_RD == i2c->op) {
446 mt65xx_reg_sync_writel(0x0000, i2c->pdmabase + OFFSET_INT_FLAG);
447 mt65xx_reg_sync_writel(0x0001, i2c->pdmabase + OFFSET_CON);
448 mt65xx_reg_sync_writel((U32)i2c->msg_buf, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
449 mt65xx_reg_sync_writel(i2c->trans_data.data_size, i2c->pdmabase + OFFSET_RX_LEN);
450 } else if (I2C_MASTER_WR == i2c->op) {
451 mt65xx_reg_sync_writel(0x0000, i2c->pdmabase + OFFSET_INT_FLAG);
452 mt65xx_reg_sync_writel(0x0000, i2c->pdmabase + OFFSET_CON);
453 mt65xx_reg_sync_writel((U32)i2c->msg_buf, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
454 mt65xx_reg_sync_writel(i2c->trans_data.data_size, i2c->pdmabase + OFFSET_TX_LEN);
455 } else {
456 mt65xx_reg_sync_writel(0x0000, i2c->pdmabase + OFFSET_INT_FLAG);
457 mt65xx_reg_sync_writel(0x0000, i2c->pdmabase + OFFSET_CON);
458 mt65xx_reg_sync_writel((U32)i2c->msg_buf, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
459 mt65xx_reg_sync_writel((U32)i2c->msg_buf, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
460 mt65xx_reg_sync_writel(i2c->trans_data.trans_len, i2c->pdmabase + OFFSET_TX_LEN);
461 mt65xx_reg_sync_writel(i2c->trans_data.trans_auxlen, i2c->pdmabase + OFFSET_RX_LEN);
462 }
463 I2C_MB();
464 mt65xx_reg_sync_writel(0x0001, i2c->pdmabase + OFFSET_EN);
465
466 I2CINFO( I2C_T_DMA, "addr %.2x dma %.2X byte\n", i2c->addr, i2c->trans_data.data_size);
467 I2CINFO( I2C_T_DMA, "DMA Register:INT_FLAG:0x%x,CON:0x%x,TX_MEM_ADDR:0x%x, \
468 RX_MEM_ADDR:0x%x,TX_LEN:0x%x,RX_LEN:0x%x,EN:0x%x\n",\
469 readl(i2c->pdmabase + OFFSET_INT_FLAG),\
470 readl(i2c->pdmabase + OFFSET_CON),\
471 readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR),\
472 readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR),\
473 readl(i2c->pdmabase + OFFSET_TX_LEN),\
474 readl(i2c->pdmabase + OFFSET_RX_LEN),\
475 readl(i2c->pdmabase + OFFSET_EN));
476
477 }
478 else
479 {
480 /*Set fifo mode data*/
481 if (I2C_MASTER_RD == i2c->op)
482 {
483 /*do not need set fifo data*/
484 }else
485 { /*both write && write_read mode*/
486 while (data_size--)
487 {
488 i2c_writel(i2c, OFFSET_DATA_PORT, *ptr);
489 //dev_info(i2c->dev, "addr %.2x write byte = 0x%.2X\n", addr, *ptr);
490 ptr++;
491 }
492 }
493 }
494 /*Set trans_data*/
495 i2c->trans_data.data_size = data_size;
496
497 i2c_writel(i2c,OFFSET_DCM_EN, 0x0);//disable dcm, since default/reset is 1
498 }
499 static S32 _i2c_get_transfer_len(mt_i2c *i2c)
500 {
501 S32 ret = I2C_OK;
502 u16 trans_num = 0;
503 u16 data_size = 0;
504 u16 trans_len = 0;
505 u16 trans_auxlen = 0;
506 //I2CFUC();
507 /*Get Transfer len and transaux len*/
508 if(FALSE == i2c->dma_en)
509 { /*non-DMA mode*/
510 if(I2C_MASTER_WRRD != i2c->op)
511 {
512 trans_len = (i2c->msg_len) & 0xFF;
513 trans_num = (i2c->msg_len >> 8) & 0xFF;
514 if(0 == trans_num)
515 trans_num = 1;
516 trans_auxlen = 0;
517 data_size = trans_len*trans_num;
518
519 if(!trans_len || !trans_num || trans_len*trans_num > 8)
520 {
521 I2CERR(" non-WRRD transfer length is not right. trans_len=%x, tans_num=%x, trans_auxlen=%x\n", trans_len, trans_num, trans_auxlen);
522 I2C_BUG_ON(!trans_len || !trans_num || trans_len*trans_num > 8);
523 ret = -EINVAL_I2C;
524 }
525 } else
526 {
527 trans_len = (i2c->msg_len) & 0xFF;
528 trans_auxlen = (i2c->msg_len >> 8) & 0xFF;
529 trans_num = 2;
530 data_size = trans_len;
531 if(!trans_len || !trans_auxlen || trans_len > 8 || trans_auxlen > 8)
532 {
533 I2CERR(" WRRD transfer length is not right. trans_len=%x, tans_num=%x, trans_auxlen=%x\n", trans_len, trans_num, trans_auxlen);
534 I2C_BUG_ON(!trans_len || !trans_auxlen || trans_len > 8 || trans_auxlen > 8);
535 ret = -EINVAL_I2C;
536 }
537 }
538 }
539 else
540 { /*DMA mode*/
541 if(I2C_MASTER_WRRD != i2c->op)
542 {
543 trans_len = (i2c->msg_len) & 0xFF;
544 trans_num = (i2c->msg_len >> 8) & 0xFF;
545 if(0 == trans_num)
546 trans_num = 1;
547 trans_auxlen = 0;
548 data_size = trans_len*trans_num;
549
550 if(!trans_len || !trans_num || trans_len > 255 || trans_num > 255)
551 {
552 I2CERR(" DMA non-WRRD transfer length is not right. trans_len=%x, tans_num=%x, trans_auxlen=%x\n", trans_len, trans_num, trans_auxlen);
553 I2C_BUG_ON(!trans_len || !trans_num || trans_len > 255 || trans_num > 255);
554 ret = -EINVAL_I2C;
555 }
556 I2CINFO(I2C_T_DMA, "DMA non-WRRD mode!trans_len=%x, tans_num=%x, trans_auxlen=%x\n",trans_len, trans_num, trans_auxlen);
557 } else
558 {
559 trans_len = (i2c->msg_len) & 0xFF;
560 trans_auxlen = (i2c->msg_len >> 8) & 0xFF;
561 trans_num = 2;
562 data_size = trans_len;
563 if(!trans_len || !trans_auxlen || trans_len > 255 || trans_auxlen > 31)
564 {
565 I2CERR(" DMA WRRD transfer length is not right. trans_len=%x, tans_num=%x, trans_auxlen=%x\n", trans_len, trans_num, trans_auxlen);
566 I2C_BUG_ON(!trans_len || !trans_auxlen || trans_len > 255 || trans_auxlen > 31);
567 ret = -EINVAL_I2C;
568 }
569 I2CINFO(I2C_T_DMA, "DMA WRRD mode!trans_len=%x, tans_num=%x, trans_auxlen=%x\n",trans_len, trans_num, trans_auxlen);
570 }
571 }
572
573 i2c->trans_data.trans_num = trans_num;
574 i2c->trans_data.trans_len = trans_len;
575 i2c->trans_data.data_size = data_size;
576 i2c->trans_data.trans_auxlen = trans_auxlen;
577
578 return ret;
579 }
580 static S32 _i2c_transfer_interface(mt_i2c *i2c)
581 {
582 S32 return_value=0;
583 S32 ret=0;
584 U8 *ptr = i2c->msg_buf;
585 //I2CFUC();
586
587 if(i2c->dma_en)
588 {
589 I2CINFO( I2C_T_DMA, "DMA Transfer mode!\n");
590 if (i2c->pdmabase == 0) {
591 I2CERR(" I2C%d doesnot support DMA mode!\n",i2c->id);
592 I2C_BUG_ON(i2c->pdmabase == NULL);
593 ret = -EINVAL_I2C;
594 goto err;
595 }
596 if((U32)ptr > DMA_ADDRESS_HIGH){
597 I2CERR(" DMA mode should use physical buffer address!\n");
598 I2C_BUG_ON((U32)ptr > DMA_ADDRESS_HIGH);
599 ret = -EINVAL_I2C;
600 goto err;
601 }
602 }
603 #ifdef I2C_DRIVER_IN_KERNEL
604 atomic_set(&i2c->trans_stop, 0);
605 atomic_set(&i2c->trans_comp, 0);
606 atomic_set(&i2c->trans_err, 0);
607 #endif
608 i2c->irq_stat = 0;
609
610 return_value=_i2c_get_transfer_len(i2c);
611 if ( return_value < 0 ){
612 I2CERR("_i2c_get_transfer_len fail,return_value=%d\n",return_value);
613 ret =-EINVAL_I2C;
614 goto err;
615 }
616 //get clock
617 #ifdef CONFIG_MT_I2C_FPGA_ENABLE
618 i2c->clk = I2C_CLK_RATE;
619 #else
620 i2c->clk = mt_get_bus_freq()/16;
621 #endif
622
623 return_value=i2c_set_speed(i2c);
624 if ( return_value < 0 ){
625 I2CERR("i2c_set_speed fail,return_value=%d\n",return_value);
626 ret =-EINVAL_I2C;
627 goto err;
628 }
629 /*Set Control Register*/
630 i2c->control_reg = I2C_CONTROL_ACKERR_DET_EN | I2C_CONTROL_CLK_EXT_EN;
631 if(i2c->dma_en) {
632 i2c->control_reg |= I2C_CONTROL_DMA_EN;
633 }
634 if(I2C_MASTER_WRRD == i2c->op)
635 i2c->control_reg |= I2C_CONTROL_DIR_CHANGE;
636
637 if(HS_MODE == i2c->mode || (i2c->trans_data.trans_num > 1 && I2C_TRANS_REPEATED_START == i2c->st_rs)) {
638 i2c->control_reg |= I2C_CONTROL_RS;
639 }
640
641 spin_lock(&i2c->lock);
642 _i2c_write_reg(i2c);
643
644 /*All register must be prepared before setting the start bit [SMP]*/
645 I2C_MB();
646 #ifdef I2C_DRIVER_IN_KERNEL
647 /*This is only for 3D CAMERA*/
648 if (i2c->i2c_3dcamera_flag)
649 {
650 spin_unlock(&i2c->lock);
651 if (g_i2c[0] == NULL)
652 g_i2c[0] = i2c;
653 else
654 g_i2c[1] = i2c;
655
656 goto end;
657 }
658 #endif
659 I2CINFO( I2C_T_TRANSFERFLOW, "Before start .....\n");
660 #ifdef I2C_DEBUG_FS
661 I2CLOG("mt_get_gpio_in I2C0_SDA=%d,I2C0_SCA=%d,I2C1_SDA=%d,I2C1_SCA=%d",\
662 mt_get_gpio_in(GPIO_I2C0_SDA_PIN),mt_get_gpio_in(GPIO_I2C0_SCA_PIN),mt_get_gpio_in(GPIO_I2C1_SDA_PIN),mt_get_gpio_in(GPIO_I2C1_SCA_PIN));
663 #endif
664
665 /*Start the transfer*/
666 i2c_writel(i2c, OFFSET_START, 0x0001);
667 spin_unlock(&i2c->lock);
668 ret = _i2c_deal_result(i2c);
669 I2CINFO(I2C_T_TRANSFERFLOW, "After i2c transfer .....\n");
670 err:
671 end:
672 return ret;
673 }
674 /*=========API in kernel=====================================================================*/
675 static void _i2c_translate_msg(mt_i2c *i2c,struct i2c_msg *msg)
676 {
677 /*-------------compatible with 77/75 driver------*/
678 if(msg->addr & 0xFF00){
679 msg->ext_flag |= msg->addr & 0xFF00;
680 }
681 I2CINFO( I2C_T_TRANSFERFLOW, "Before i2c transfer .....\n");
682
683 i2c->msg_buf = msg->buf;
684 i2c->msg_len = msg->len;
685 if(msg->ext_flag & I2C_RS_FLAG)
686 i2c->st_rs = I2C_TRANS_REPEATED_START;
687 else
688 i2c->st_rs = I2C_TRANS_STOP;
689
690 if(msg->ext_flag & I2C_DMA_FLAG)
691 i2c->dma_en = TRUE;
692 else
693 i2c->dma_en = FALSE;
694
695 if (msg->ext_flag & I2C_WR_FLAG)
696 i2c->op = I2C_MASTER_WRRD;
697 else
698 {
699 if(msg->flags & I2C_M_RD)
700 i2c->op = I2C_MASTER_RD;
701 else
702 i2c->op = I2C_MASTER_WR;
703 }
704 if(msg->ext_flag & I2C_POLLING_FLAG)
705 i2c->poll_en = TRUE;
706 else
707 i2c->poll_en = FALSE;
708 if(msg->ext_flag & I2C_A_FILTER_MSG)
709 i2c->filter_msg = TRUE;
710 else
711 i2c->filter_msg = FALSE;
712 i2c->delay_len = (msg->timing & 0xff0000) >> 16;
713
714 ///*Set device speed,set it before set_control register
715 if(0 == (msg->timing & 0xFFFF)){
716 i2c->mode = ST_MODE;
717 i2c->speed = MAX_ST_MODE_SPEED;
718 }
719 else
720 {
721 if (msg->ext_flag & I2C_HS_FLAG)
722 i2c->mode = HS_MODE;
723 else
724 i2c->mode = FS_MODE;
725
726 i2c->speed= msg->timing & 0xFFFF;
727 }
728
729 /*Set ioconfig*/
730 if (msg->ext_flag & I2C_PUSHPULL_FLAG)
731 i2c->pushpull=TRUE;
732 else
733 i2c->pushpull=FALSE;
734
735 if (msg->ext_flag & I2C_3DCAMERA_FLAG)
736 i2c->i2c_3dcamera_flag=TRUE;
737 else
738 i2c->i2c_3dcamera_flag=FALSE;
739
740 }
741
742 static S32 mt_i2c_start_xfer(mt_i2c *i2c, struct i2c_msg *msg)
743 {
744 S32 return_value = 0;
745 S32 ret = msg->len;
746 //start=========================Check param valid=====================================//
747 //I2CLOG(" mt_i2c_start_xfer.\n");
748 //get the read/write flag
749 i2c->read_flag=(msg->flags & I2C_M_RD);
750 i2c->addr=msg->addr;
751 if(i2c->addr == 0){
752 I2CERR(" addr is invalid.\n");
753 I2C_BUG_ON(i2c->addr == NULL);
754 ret = -EINVAL_I2C;
755 goto err;
756 }
757
758 if(msg->buf == NULL){
759 I2CERR(" data buffer is NULL.\n");
760 I2C_BUG_ON(msg->buf == NULL);
761 ret = -EINVAL_I2C;
762 goto err;
763 }
764 if (g_i2c[0] == i2c || g_i2c[1] == i2c) {
765 I2CERR("mt-i2c%d: Current I2C Adapter is busy.\n", i2c->id);
766 ret = -EINVAL_I2C;
767 goto err;
768 }
769 //start=========================translate msg to mt_i2c===============================//
770 _i2c_translate_msg(i2c,msg);
771 /*This is only for 3D CAMERA*//*Save address infomation for 3d camera*/
772 #ifdef I2C_DRIVER_IN_KERNEL
773 if (i2c->i2c_3dcamera_flag)
774 {
775 if (g_msg[0].buf == NULL)
776 memcpy((void *)&g_msg[0], msg, sizeof(struct i2c_msg));
777 else
778 memcpy((void *)&g_msg[1], msg, sizeof(struct i2c_msg));
779 }
780 #endif
781 //end=========================translate msg to mt_i2c===============================//
782 mt_i2c_clock_enable(i2c);
783 return_value =_i2c_transfer_interface(i2c);
784 if (!(msg->ext_flag & I2C_3DCAMERA_FLAG))
785 mt_i2c_clock_disable(i2c);
786 if ( return_value < 0 )
787 {
788 ret =-EINVAL_I2C;
789 goto err;
790 }
791 err:
792 return ret;
793 }
794
795 static S32 mt_i2c_do_transfer(mt_i2c *i2c, struct i2c_msg *msgs, S32 num)
796 {
797 S32 ret = 0;
798 S32 left_num = num;
799
800 while (left_num--) {
801 ret = mt_i2c_start_xfer(i2c, msgs++);
802 if ( ret < 0 ){
803 if ( ret != -EINVAL_I2C ) /*We never try again when the param is invalid*/
804 return -EAGAIN;
805 else
806 return -EINVAL_I2C;
807 }
808 }
809 /*the return value is number of executed messages*/
810 return num;
811 }
812
813 static S32 mt_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msgs[], S32 num)
814 {
815 S32 ret = 0;
816 S32 retry;
817 mt_i2c *i2c = i2c_get_adapdata(adap);
818
819 for (retry = 0; retry < adap->retries; retry++)
820 {
821 ret = mt_i2c_do_transfer(i2c, msgs, num);
822 if (ret != -EAGAIN) {
823 break;
824 }
825 if ( retry < adap->retries - 1 )
826 udelay(100);
827 }
828
829 if (ret != -EAGAIN)
830 return ret;
831 else
832 return -EREMOTEIO;
833 }
834 #ifdef I2C_DRIVER_IN_KERNEL
835 static S32 _i2c_deal_result_3dcamera(mt_i2c *i2c, struct i2c_msg *msg)
836 {
837 U16 addr = msg->addr;
838 U16 read = (msg->flags & I2C_M_RD);
839 i2c->msg_buf=msg->buf;
840 i2c->msg_len=msg->len;
841 i2c->addr = read ? ((addr << 1) | 0x1) : ((addr << 1) & ~0x1);
842 return _i2c_deal_result(i2c);
843 }
844 #endif
845
846 static void mt_i2c_clock_enable(mt_i2c *i2c)
847 {
848 #if (!defined(CONFIG_MT_I2C_FPGA_ENABLE))
849 if (i2c->dma_en){
850 I2CINFO( I2C_T_TRANSFERFLOW, "Before dma clock enable .....\n");
851 enable_clock(MT_CG_PERI_AP_DMA, "i2c");
852 }
853 I2CINFO( I2C_T_TRANSFERFLOW, "Before i2c clock enable .....\n");
854 enable_clock(i2c->pdn, "i2c");
855 I2CINFO( I2C_T_TRANSFERFLOW, "clock enable done.....\n");
856 #endif
857 return;
858 }
859 static void mt_i2c_clock_disable(mt_i2c *i2c)
860 {
861 #if (!defined(CONFIG_MT_I2C_FPGA_ENABLE))
862 if (i2c->dma_en){
863 I2CINFO( I2C_T_TRANSFERFLOW, "Before dma clock disable .....\n");
864 disable_clock(MT_CG_PERI_AP_DMA, "i2c");
865 }
866 I2CINFO( I2C_T_TRANSFERFLOW, "Before i2c clock disable .....\n");
867 disable_clock(i2c->pdn, "i2c");
868 I2CINFO( I2C_T_TRANSFERFLOW, "clock disable done .....\n");
869 #endif
870 return;
871 }
872 /*
873 static void mt_i2c_post_isr(mt_i2c *i2c)
874 {
875 if (i2c->irq_stat & I2C_TRANSAC_COMP) {
876 atomic_set(&i2c->trans_err, 0);
877 atomic_set(&i2c->trans_comp, 1);
878 }
879
880 if (i2c->irq_stat & I2C_HS_NACKERR) {
881 if (i2c->filter_msg==FALSE)
882 I2CERR("I2C_HS_NACKERR\n");
883 }
884
885 if (i2c->irq_stat & I2C_ACKERR) {
886 if (i2c->filter_msg==FALSE)
887 I2CERR("I2C_ACKERR\n");
888 }
889 atomic_set(&i2c->trans_err, i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR));
890 }*/
891
892 /*interrupt handler function*/
893 static irqreturn_t mt_i2c_irq(S32 irqno, void *dev_id)
894 {
895 mt_i2c *i2c = (mt_i2c *)dev_id;
896 //U32 base = i2c->base;
897
898 I2CINFO( I2C_T_TRANSFERFLOW, "i2c interrupt coming.....\n");
899 //I2CLOG("mt_i2c_irq\n");
900 /*Clear interrupt mask*/
901 i2c_writel(i2c,OFFSET_INTR_MASK,i2c_readl(i2c,OFFSET_INTR_MASK) & ~(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP));
902 /*Save interrupt status*/
903 i2c->irq_stat = i2c_readl(i2c, OFFSET_INTR_STAT);
904 /*Clear interrupt status,write 1 clear*/
905 i2c_writel(i2c,OFFSET_INTR_STAT, (I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP));
906 //dev_info(i2c->dev, "I2C interrupt status 0x%04X\n", i2c->irq_stat);
907
908 /*Wake up process*/
909 atomic_set(&i2c->trans_stop, 1);
910 wake_up(&i2c->wait);
911 return IRQ_HANDLED;
912 }
913
914 /*This function is only for 3d camera*/
915
916 S32 mt_wait4_i2c_complete(void)
917 {
918 mt_i2c *i2c0 = g_i2c[0];
919 mt_i2c *i2c1 = g_i2c[1];
920 S32 result0, result1;
921 S32 ret = 0;
922
923 if ((i2c0 == NULL) ||(i2c1 == NULL)) {
924 /*What's wrong?*/
925 ret = -EINVAL_I2C;
926 goto end;
927 }
928
929 result0 = _i2c_deal_result_3dcamera(i2c0, &g_msg[0]);
930 result1 = _i2c_deal_result_3dcamera(i2c1, &g_msg[1]);
931
932 if (result0 < 0 || result1 < 0) {
933 ret = -EINVAL_I2C;
934 }
935 if(NULL != i2c0) mt_i2c_clock_disable(i2c0);
936 if(NULL != i2c1) mt_i2c_clock_disable(i2c1);
937
938 end:
939 g_i2c[0] = NULL;
940 g_i2c[1] = NULL;
941
942 g_msg[0].buf = NULL;
943 g_msg[1].buf = NULL;
944
945 return ret;
946 }
947
948 static U32 mt_i2c_functionality(struct i2c_adapter *adap)
949 {
950 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
951 }
952 static struct i2c_algorithm mt_i2c_algorithm = {
953 .master_xfer = mt_i2c_transfer,
954 .smbus_xfer = NULL,
955 .functionality = mt_i2c_functionality,
956 };
957 static inline void mt_i2c_init_hw(mt_i2c *i2c)
958 {
959 i2c_writel(i2c,OFFSET_SOFTRESET, 0x0001);
960 i2c_writel(i2c,OFFSET_DCM_EN, 0x0);
961 }
962
963 static void mt_i2c_free(mt_i2c *i2c)
964 {
965 if (!i2c)
966 return;
967
968 free_irq(i2c->irqnr, i2c);
969 i2c_del_adapter(&i2c->adap);
970 kfree(i2c);
971 }
972
973 static S32 mt_i2c_probe(struct platform_device *pdev)
974 {
975 S32 ret, irq;
976 mt_i2c *i2c = NULL;
977 struct resource *res;
978
979 /* Request platform_device IO resource*/
980 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
981 irq = platform_get_irq(pdev, 0);
982 if (res == NULL || irq < 0)
983 return -ENODEV;
984
985 /* Request IO memory */
986 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
987 return -ENOMEM;
988 }
989
990 if (NULL == (i2c = kzalloc(sizeof(mt_i2c), GFP_KERNEL)))
991 return -ENOMEM;
992
993 /* initialize mt_i2c structure */
994 i2c->id = pdev->id;
995 i2c->base = IO_PHYS_TO_VIRT(res->start);
996 //i2c->base = 0x11011000;
997 i2c->irqnr = irq;
998 #if (defined(CONFIG_MT_I2C_FPGA_ENABLE))
999 i2c->clk = I2C_CLK_RATE;
1000 #else
1001 i2c->clk = mt_get_bus_freq();// is not ready
1002
1003 switch(i2c->id){
1004 case 0:
1005 i2c->pdn = MT_CG_PERI_I2C0;
1006 break;
1007 case 1:
1008 i2c->pdn = MT_CG_PERI_I2C1;
1009 break;
1010 case 2:
1011 i2c->pdn = MT_CG_PERI_I2C2;
1012 break;
1013 default:
1014 dev_err(&pdev->dev, "Error id %d\n", i2c->id);
1015 break;
1016 }
1017 #endif
1018 i2c->dev = &i2c->adap.dev;
1019
1020 i2c->adap.dev.parent = &pdev->dev;
1021 i2c->adap.nr = i2c->id;
1022 i2c->adap.owner = THIS_MODULE;
1023 i2c->adap.algo = &mt_i2c_algorithm;
1024 i2c->adap.algo_data = NULL;
1025 i2c->adap.timeout = 2 * HZ; /*2s*/
1026 i2c->adap.retries = 1; /*DO NOT TRY*/
1027
1028 snprintf(i2c->adap.name, sizeof(i2c->adap.name), I2C_DRV_NAME);
1029
1030 i2c->pdmabase = AP_DMA_BASE + 0x200 + (0x80*(i2c->id));
1031
1032 spin_lock_init(&i2c->lock);
1033 init_waitqueue_head(&i2c->wait);
1034
1035 ret = request_irq(irq, mt_i2c_irq, IRQF_TRIGGER_LOW, I2C_DRV_NAME, i2c);
1036
1037 if (ret){
1038 dev_err(&pdev->dev, "Can Not request I2C IRQ %d\n", irq);
1039 goto free;
1040 }
1041
1042 mt_i2c_init_hw(i2c);
1043 i2c_set_adapdata(&i2c->adap, i2c);
1044 ret = i2c_add_numbered_adapter(&i2c->adap);
1045 if (ret){
1046 dev_err(&pdev->dev, "failed to add i2c bus to i2c core\n");
1047 goto free;
1048 }
1049 platform_set_drvdata(pdev, i2c);
1050
1051 #ifdef I2C_DEBUG_FS
1052 ret = device_create_file(i2c->dev, &dev_attr_debug);
1053 if ( ret ){
1054 /*Do nothing*/
1055 }
1056 #endif
1057
1058 return ret;
1059
1060 free:
1061 mt_i2c_free(i2c);
1062 return ret;
1063 }
1064
1065
1066 static S32 mt_i2c_remove(struct platform_device *pdev)
1067 {
1068 mt_i2c *i2c = platform_get_drvdata(pdev);
1069 if (i2c) {
1070 platform_set_drvdata(pdev, NULL);
1071 mt_i2c_free(i2c);
1072 }
1073 return 0;
1074 }
1075
1076 #ifdef CONFIG_PM
1077 static S32 mt_i2c_suspend(struct platform_device *pdev, pm_message_t state)
1078 {
1079 // struct mt_i2c *i2c = platform_get_drvdata(pdev);
1080 //dev_dbg(i2c->dev,"[I2C %d] Suspend!\n", i2c->id);
1081 return 0;
1082 }
1083
1084 static S32 mt_i2c_resume(struct platform_device *pdev)
1085 {
1086 // struct mt_i2c *i2c = platform_get_drvdata(pdev);
1087 // dev_dbg(i2c->dev,"[I2C %d] Resume!\n", i2c->id);
1088 return 0;
1089 }
1090 #else
1091 #define mt_i2c_suspend NULL
1092 #define mt_i2c_resume NULL
1093 #endif
1094
1095 static struct platform_driver mt_i2c_driver = {
1096 .probe = mt_i2c_probe,
1097 .remove = mt_i2c_remove,
1098 .suspend = mt_i2c_suspend,
1099 .resume = mt_i2c_resume,
1100 .driver = {
1101 .name = I2C_DRV_NAME,
1102 .owner = THIS_MODULE,
1103 },
1104 };
1105
1106 static S32 __init mt_i2c_init(void)
1107 {
1108 return platform_driver_register(&mt_i2c_driver);
1109 }
1110
1111 static void __exit mt_i2c_exit(void)
1112 {
1113 platform_driver_unregister(&mt_i2c_driver);
1114 }
1115
1116 module_init(mt_i2c_init);
1117 module_exit(mt_i2c_exit);
1118
1119 MODULE_LICENSE("GPL");
1120 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
1121 MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
kernel source for telekom puls (alcatel/mediatek)