drivers/misc/mediatek/hdmi/mt8193/mt8193edid.h

   1 #ifndef __mt8193edid_h__
   2 #define __mt8193edid_h__
   3 #ifdef CONFIG_MTK_MT8193_HDMI_SUPPORT
   4
   5
   6
   7 typedef enum {
   8         AVD_BITS_NONE = 0,
   9         AVD_LPCM = 1,
  10         AVD_AC3,
  11         AVD_MPEG1_AUD,
  12         AVD_MP3,
  13         AVD_MPEG2_AUD,
  14         AVD_AAC,
  15         AVD_DTS,
  16         AVD_ATRAC,
  17         AVD_DSD,
  18         AVD_DOLBY_PLUS,
  19         AVD_DTS_HD,
  20         AVD_MAT_MLP,
  21         AVD_DST,
  22         AVD_WMA,
  23         AVD_CDDA,
  24         AVD_SACD_PCM,
  25         AVD_HDCD = 0xfe,
  26         AVD_BITS_OTHERS = 0xff
  27 } AUDIO_BITSTREAM_TYPE_T;
  28
  29 typedef enum {
  30         EXTERNAL_EDID = 0,
  31         INTERNAL_EDID,
  32         NO_EDID
  33 } GET_EDID_T;
  34 #define SINK_480P      (1 << 0)
  35 #define SINK_720P60    (1 << 1)
  36 #define SINK_1080I60   (1 << 2)
  37 #define SINK_1080P60   (1 << 3)
  38 #define SINK_480P_1440 (1 << 4)
  39 #define SINK_480P_2880 (1 << 5)
  40 #define SINK_480I      (1 << 6)
  41 #define SINK_480I_1440 (1 << 7)
  42 #define SINK_480I_2880 (1 << 8)
  43 #define SINK_1080P30   (1 << 9)
  44 #define SINK_576P      (1 << 10)
  45 #define SINK_720P50    (1 << 11)
  46 #define SINK_1080I50   (1 << 12)
  47 #define SINK_1080P50   (1 << 13)
  48 #define SINK_576P_1440 (1 << 14)
  49 #define SINK_576P_2880 (1 << 15)
  50 #define SINK_576I      (1 << 16)
  51 #define SINK_576I_1440 (1 << 17)
  52 #define SINK_576I_2880 (1 << 18)
  53 #define SINK_1080P25   (1 << 19)
  54 #define SINK_1080P24   (1 << 20)
  55 #define SINK_1080P23976   (1 << 21)
  56 #define SINK_1080P2997   (1 << 22)
  57
  58 /* This HDMI_SINK_VIDEO_COLORIMETRY_T will define what kind of YCBCR */
  59 /* can be supported by sink. */
  60 /* And each bit also defines the colorimetry data block of EDID. */
  61 #define SINK_YCBCR_444 (1<<0)
  62 #define SINK_YCBCR_422 (1<<1)
  63 #define SINK_XV_YCC709 (1<<2)
  64 #define SINK_XV_YCC601 (1<<3)
  65 #define SINK_METADATA0 (1<<4)
  66 #define SINK_METADATA1 (1<<5)
  67 #define SINK_METADATA2 (1<<6)
  68 #define SINK_RGB       (1<<7)
  69
  70
  71 /* HDMI_SINK_VCDB_T Each bit defines the VIDEO Capability Data Block of EDID. */
  72 #define SINK_CE_ALWAYS_OVERSCANNED                  (1<<0)
  73 #define SINK_CE_ALWAYS_UNDERSCANNED                 (1<<1)
  74 #define SINK_CE_BOTH_OVER_AND_UNDER_SCAN            (1<<2)
  75 #define SINK_IT_ALWAYS_OVERSCANNED                  (1<<3)
  76 #define SINK_IT_ALWAYS_UNDERSCANNED                 (1<<4)
  77 #define SINK_IT_BOTH_OVER_AND_UNDER_SCAN            (1<<5)
  78 #define SINK_PT_ALWAYS_OVERSCANNED                  (1<<6)
  79 #define SINK_PT_ALWAYS_UNDERSCANNED                 (1<<7)
  80 #define SINK_PT_BOTH_OVER_AND_UNDER_SCAN            (1<<8)
  81 #define SINK_RGB_SELECTABLE                         (1<<9)
  82
  83
  84 /* HDMI_SINK_AUDIO_DECODER_T define what kind of audio decoder */
  85 /* can be supported by sink. */
  86 #define   HDMI_SINK_AUDIO_DEC_LPCM        (1<<0)
  87 #define   HDMI_SINK_AUDIO_DEC_AC3         (1<<1)
  88 #define   HDMI_SINK_AUDIO_DEC_MPEG1       (1<<2)
  89 #define   HDMI_SINK_AUDIO_DEC_MP3         (1<<3)
  90 #define   HDMI_SINK_AUDIO_DEC_MPEG2       (1<<4)
  91 #define   HDMI_SINK_AUDIO_DEC_AAC         (1<<5)
  92 #define   HDMI_SINK_AUDIO_DEC_DTS         (1<<6)
  93 #define   HDMI_SINK_AUDIO_DEC_ATRAC       (1<<7)
  94 #define   HDMI_SINK_AUDIO_DEC_DSD         (1<<8)
  95 #define   HDMI_SINK_AUDIO_DEC_DOLBY_PLUS   (1<<9)
  96 #define   HDMI_SINK_AUDIO_DEC_DTS_HD      (1<<10)
  97 #define   HDMI_SINK_AUDIO_DEC_MAT_MLP     (1<<11)
  98 #define   HDMI_SINK_AUDIO_DEC_DST         (1<<12)
  99 #define   HDMI_SINK_AUDIO_DEC_WMA         (1<<13)
 100
 101
 102 /* Sink audio channel ability for a fixed Fs */
 103 #define SINK_AUDIO_2CH   (1<<0)
 104 #define SINK_AUDIO_3CH   (1<<1)
 105 #define SINK_AUDIO_4CH   (1<<2)
 106 #define SINK_AUDIO_5CH   (1<<3)
 107 #define SINK_AUDIO_6CH   (1<<4)
 108 #define SINK_AUDIO_7CH   (1<<5)
 109 #define SINK_AUDIO_8CH   (1<<6)
 110
 111 /* Sink supported sampling rate for a fixed channel number */
 112 #define SINK_AUDIO_32k (1<<0)
 113 #define SINK_AUDIO_44k (1<<1)
 114 #define SINK_AUDIO_48k (1<<2)
 115 #define SINK_AUDIO_88k (1<<3)
 116 #define SINK_AUDIO_96k (1<<4)
 117 #define SINK_AUDIO_176k (1<<5)
 118 #define SINK_AUDIO_192k (1<<6)
 119
 120 /* The following definition is for Sink speaker allocation data block . */
 121 #define SINK_AUDIO_FL_FR   (1<<0)
 122 #define SINK_AUDIO_LFE     (1<<1)
 123 #define SINK_AUDIO_FC      (1<<2)
 124 #define SINK_AUDIO_RL_RR   (1<<3)
 125 #define SINK_AUDIO_RC      (1<<4)
 126 #define SINK_AUDIO_FLC_FRC (1<<5)
 127 #define SINK_AUDIO_RLC_RRC (1<<6)
 128
 129 /* The following definition is */
 130 /* For EDID Audio Support, //HDMI_EDID_CHKSUM_AND_AUDIO_SUP_T */
 131 #define SINK_BASIC_AUDIO_NO_SUP    (1<<0)
 132 #define SINK_SAD_NO_EXIST          (1<<1)       /* short audio descriptor */
 133 #define SINK_BASE_BLK_CHKSUM_ERR   (1<<2)
 134 #define SINK_EXT_BLK_CHKSUM_ERR    (1<<3)
 135
 136
 137 /* The following definition is for the output channel of */
 138 /* audio decoder AUDIO_DEC_OUTPUT_CHANNEL_T */
 139 #define AUDIO_DEC_FL   (1<<0)
 140 #define AUDIO_DEC_FR   (1<<1)
 141 #define AUDIO_DEC_LFE  (1<<2)
 142 #define AUDIO_DEC_FC   (1<<3)
 143 #define AUDIO_DEC_RL   (1<<4)
 144 #define AUDIO_DEC_RR   (1<<5)
 145 #define AUDIO_DEC_RC   (1<<6)
 146 #define AUDIO_DEC_FLC  (1<<7)
 147 #define AUDIO_DEC_FRC  (1<<8)
 148
 149 /* (5) Define the EDID relative information */
 150 /* (5.1) Define one EDID block length */
 151 #define EDID_BLOCK_LEN      128
 152 /* (5.2) Define EDID header length */
 153 #define EDID_HEADER_LEN     8
 154 /* (5.3) Define the address for EDID info. (ref. EDID Recommended Practive for EIA/CEA-861) */
 155 /* Base Block 0 */
 156 #define EDID_ADDR_HEADER                      0x00
 157 #define EDID_ADDR_VERSION                     0x12
 158 #define EDID_ADDR_REVISION                    0x13
 159 #define EDID_IMAGE_HORIZONTAL_SIZE            0x15
 160 #define EDID_IMAGE_VERTICAL_SIZE              0x16
 161 #define EDID_ADDR_FEATURE_SUPPORT             0x18
 162 #define EDID_ADDR_TIMING_DSPR_1               0x36
 163 #define EDID_ADDR_TIMING_DSPR_2               0x48
 164 #define EDID_ADDR_MONITOR_DSPR_1              0x5A
 165 #define EDID_ADDR_MONITOR_DSPR_2              0x6C
 166 #define EDID_ADDR_EXT_BLOCK_FLAG              0x7E
 167 #define EDID_ADDR_EXTEND_BYTE3                0x03      /* EDID address: 0x83 */
 168                                                    /* for ID receiver if RGB, YCbCr 4:2:2 or 4:4:4 */
 169 /* Extension Block 1: */
 170 #define EXTEDID_ADDR_TAG                      0x00
 171 #define EXTEDID_ADDR_REVISION                 0x01
 172 #define EXTEDID_ADDR_OFST_TIME_DSPR           0x02
 173
 174 /* (5.4) Define the ID for descriptor block type */
 175 /* Notice: reference Table 11 ~ 14 of "EDID Recommended Practive for EIA/CEA-861" */
 176 #define DETAIL_TIMING_DESCRIPTOR              -1
 177 #define UNKNOWN_DESCRIPTOR                    -255
 178 #define MONITOR_NAME_DESCRIPTOR               0xFC
 179 #define MONITOR_RANGE_LIMITS_DESCRIPTOR       0xFD
 180
 181
 182 /* (5.5) Define the offset address of info. within detail timing descriptor block */
 183 #define OFST_PXL_CLK_LO       0
 184 #define OFST_PXL_CLK_HI       1
 185 #define OFST_H_ACTIVE_LO      2
 186 #define OFST_H_BLANKING_LO    3
 187 #define OFST_H_ACT_BLA_HI     4
 188 #define OFST_V_ACTIVE_LO      5
 189 #define OFST_V_BLANKING_LO    6
 190 #define OFST_V_ACTIVE_HI      7
 191 #define OFST_FLAGS            17
 192
 193 /* (5.6) Define the ID for EDID extension type */
 194 #define LCD_TIMING                  0x1
 195 #define CEA_TIMING_EXTENSION        0x01
 196 #define EDID_20_EXTENSION           0x20
 197 #define COLOR_INFO_TYPE0            0x30
 198 #define DVI_FEATURE_DATA            0x40
 199 #define TOUCH_SCREEN_MAP            0x50
 200 #define BLOCK_MAP                   0xF0
 201 #define EXTENSION_DEFINITION        0xFF
 202
 203 /* (5.7) Define EDID VSDB header length */
 204 #define EDID_VSDB_LEN               0x03
 205 typedef enum {
 206         HDMI_SINK_NO_DEEP_COLOR = 0,
 207         HDMI_SINK_DEEP_COLOR_10_BIT = (1 << 0),
 208         HDMI_SINK_DEEP_COLOR_12_BIT = (1 << 1),
 209         HDMI_SINK_DEEP_COLOR_16_BIT = (1 << 2)
 210 } HDMI_SINK_DEEP_COLOR_T;
 211
 212 typedef struct _HDMI_SINK_AV_CAP_T {
 213         u32 ui4_sink_cea_ntsc_resolution;       /* use HDMI_SINK_VIDEO_RES_T */
 214         u32 ui4_sink_cea_pal_resolution;        /* use HDMI_SINK_VIDEO_RES_T */
 215         u32 ui4_sink_dtd_ntsc_resolution;       /* use HDMI_SINK_VIDEO_RES_T */
 216         u32 ui4_sink_dtd_pal_resolution;        /* use HDMI_SINK_VIDEO_RES_T */
 217         u32 ui4_sink_1st_dtd_ntsc_resolution;   /* use HDMI_SINK_VIDEO_RES_T */
 218         u32 ui4_sink_1st_dtd_pal_resolution;    /* use HDMI_SINK_VIDEO_RES_T */
 219         u32 ui4_sink_native_ntsc_resolution;    /* use HDMI_SINK_VIDEO_RES_T */
 220         u32 ui4_sink_native_pal_resolution;     /* use HDMI_SINK_VIDEO_RES_T */
 221         u16 ui2_sink_colorimetry;       /* use HDMI_SINK_VIDEO_COLORIMETRY_T */
 222         u16 ui2_sink_vcdb_data; /* use HDMI_SINK_VCDB_T */
 223         u16 ui2_sink_aud_dec;   /* HDMI_SINK_AUDIO_DECODER_T */
 224         u8 ui1_sink_dsd_ch_num;
 225         u8 ui1_sink_pcm_ch_sampling[7]; /* n: channel number index, value: each bit means sampling rate for this channel number (SINK_AUDIO_32k..) */
 226         u8 ui1_sink_pcm_bit_size[7];    /* //n: channel number index, value: each bit means bit size for this channel number */
 227         u8 ui1_sink_dst_ch_sampling[7]; /* n: channel number index, value: each bit means sampling rate for this channel number (SINK_AUDIO_32k..) */
 228         u8 ui1_sink_dsd_ch_sampling[7]; /* n: channel number index, value: each bit means sampling rate for this channel number (SINK_AUDIO_32k..) */
 229         u16 ui1_sink_max_tmds_clock;
 230         u8 ui1_sink_spk_allocation;
 231         u8 ui1_sink_content_cnc;
 232         u8 ui1_sink_p_latency_present;
 233         u8 ui1_sink_i_latency_present;
 234         u8 ui1_sink_p_audio_latency;
 235         u8 ui1_sink_p_video_latency;
 236         u8 ui1_sink_i_audio_latency;
 237         u8 ui1_sink_i_video_latency;
 238         u8 e_sink_rgb_color_bit;
 239         u8 e_sink_ycbcr_color_bit;
 240         u8 u1_sink_support_ai;  /* kenny add 2010/4/25 */
 241         u8 u1_sink_max_tmds;    /* kenny add 2010/4/25 */
 242         u16 ui2_edid_chksum_and_audio_sup;      /* HDMI_EDID_CHKSUM_AND_AUDIO_SUP_T */
 243         u16 ui2_sink_cec_address;
 244         u8 b_sink_edid_ready;
 245         u8 b_sink_support_hdmi_mode;
 246         u8 ui1_ExtEdid_Revision;
 247         u8 ui1_Edid_Version;
 248         u8 ui1_Edid_Revision;
 249         u8 ui1_sink_support_ai;
 250         u8 ui1_Display_Horizontal_Size;
 251         u8 ui1_Display_Vertical_Size;
 252         u8 b_sink_hdmi_video_present;
 253         u8 ui1_CNC;
 254         u8 b_sink_3D_present;
 255         u32 ui4_sink_cea_3D_resolution;
 256 } HDMI_SINK_AV_CAP_T;
 257
 258 typedef struct _HDMI_EDID_INFO_T {
 259         u32 ui4_ntsc_resolution;        /* use EDID_VIDEO_RES_T, there are many resolution */
 260         u32 ui4_pal_resolution; /* use EDID_VIDEO_RES_T */
 261         u32 ui4_sink_native_ntsc_resolution;    /* use EDID_VIDEO_RES_T, only one NTSC resolution, Zero means none native NTSC resolution is avaiable */
 262         u32 ui4_sink_native_pal_resolution;     /* use EDID_VIDEO_RES_T, only one resolution, Zero means none native PAL resolution is avaiable */
 263         u32 ui4_sink_cea_ntsc_resolution;       /* use EDID_VIDEO_RES_T */
 264         u32 ui4_sink_cea_pal_resolution;        /* use EDID_VIDEO_RES_T */
 265         u32 ui4_sink_dtd_ntsc_resolution;       /* use EDID_VIDEO_RES_T */
 266         u32 ui4_sink_dtd_pal_resolution;        /* use EDID_VIDEO_RES_T */
 267         u32 ui4_sink_1st_dtd_ntsc_resolution;   /* use EDID_VIDEO_RES_T */
 268         u32 ui4_sink_1st_dtd_pal_resolution;    /* use EDID_VIDEO_RES_T */
 269         u16 ui2_sink_colorimetry;       /* use EDID_VIDEO_COLORIMETRY_T */
 270         u8 ui1_sink_rgb_color_bit;      /* color bit for RGB */
 271         u8 ui1_sink_ycbcr_color_bit;    /* color bit for YCbCr */
 272         u16 ui2_sink_aud_dec;   /* use EDID_AUDIO_DECODER_T */
 273         u8 ui1_sink_is_plug_in; /* 1: Plug in 0:Plug Out */
 274         u32 ui4_hdmi_pcm_ch_type;       /* use EDID_A_FMT_CH_TYPE */
 275         u32 ui4_hdmi_pcm_ch3ch4ch5ch7_type;     /* use EDID_A_FMT_CH_TYPE1 */
 276         u32 ui4_dac_pcm_ch_type;        /* use EDID_A_FMT_CH_TYPE */
 277         u8 ui1_sink_i_latency_present;
 278         u8 ui1_sink_p_audio_latency;
 279         u8 ui1_sink_p_video_latency;
 280         u8 ui1_sink_i_audio_latency;
 281         u8 ui1_sink_i_video_latency;
 282         u8 ui1ExtEdid_Revision;
 283         u8 ui1Edid_Version;
 284         u8 ui1Edid_Revision;
 285         u8 ui1_Display_Horizontal_Size;
 286         u8 ui1_Display_Vertical_Size;
 287         u32 ui4_ID_Serial_Number;
 288         u32 ui4_sink_cea_3D_resolution;
 289         u8 ui1_sink_support_ai; /* 0: not support AI, 1:support AI */
 290         u16 ui2_sink_cec_address;
 291         u16 ui1_sink_max_tmds_clock;
 292         u16 ui2_sink_3D_structure;
 293         u32 ui4_sink_cea_FP_SUP_3D_resolution;
 294         u32 ui4_sink_cea_TOB_SUP_3D_resolution;
 295         u32 ui4_sink_cea_SBS_SUP_3D_resolution;
 296         u16 ui2_sink_ID_manufacturer_name;      /* (08H~09H) */
 297         u16 ui2_sink_ID_product_code;   /* (0aH~0bH) */
 298         u32 ui4_sink_ID_serial_number;  /* (0cH~0fH) */
 299         u8 ui1_sink_week_of_manufacture;        /* (10H) */
 300         u8 ui1_sink_year_of_manufacture;        /* (11H)  base on year 1990 */
 301 } HDMI_EDID_INFO_T;
 302
 303
 304 extern void mt8193_checkedid(u8 i1noedid);
 305 extern u8 mt8193_fgreadedid(u8 i1noedid);
 306 extern void vShowEdidInformation(void);
 307 extern void vShowEdidRawData(void);
 308 extern void vClearEdidInfo(void);
 309 extern void mt8193_AppGetEdidInfo(HDMI_EDID_INFO_T *pv_get_info);
 310 extern u8 vCheckPcmBitSize(u8 ui1ChNumInx);
 311 extern u8 mt8193_Check_EdidHeader(void);
 312 #endif
 313 #endif