drivers/misc/mediatek/hdmi/mt8193/mt8193ddc.h

   1 #ifndef __mt8193ddc_h__
   2 #define __mt8193ddc_h__
   3 #ifdef CONFIG_MTK_MT8193_HDMI_SUPPORT
   4
   5
   6 #define EDID_BLOCK_LEN      128
   7 #define EDID_SIZE 512
   8
   9 #define SIF1_CLOK 260           /* 27M/432 = 62.5Khz */
  10
  11
  12 #define EDID_ID     0x50        /* 0xA0 */
  13 #define EDID_ID1    0x51        /* 0xA2 */
  14
  15 #define EDID_ADDR_HEADER                      0x00
  16 #define EDID_ADDR_VERSION                     0x12
  17 #define EDID_ADDR_REVISION                    0x13
  18 #define EDID_IMAGE_HORIZONTAL_SIZE            0x15
  19 #define EDID_IMAGE_VERTICAL_SIZE              0x16
  20 #define EDID_ADDR_FEATURE_SUPPORT             0x18
  21 #define EDID_ADDR_TIMING_DSPR_1               0x36
  22 #define EDID_ADDR_TIMING_DSPR_2               0x48
  23 #define EDID_ADDR_MONITOR_DSPR_1              0x5A
  24 #define EDID_ADDR_MONITOR_DSPR_2              0x6C
  25 #define EDID_ADDR_EXT_BLOCK_FLAG              0x7E
  26 #define EDID_ADDR_EXTEND_BYTE3                0x03      /* EDID address: 0x83 */
  27                                                    /* for ID receiver if RGB, YCbCr 4:2:2 or 4:4:4 */
  28 /* Extension Block 1: */
  29 #define EXTEDID_ADDR_TAG                      0x00
  30 #define EXTEDID_ADDR_REVISION                 0x01
  31 #define EXTEDID_ADDR_OFST_TIME_DSPR           0x02
  32
  33
  34 /* ddcci master */
  35 #define DDC_DDCMCTL0           ((UINT32)0x0)
  36 #define DDCM_ODRAIN          ((UINT32)0x1<<31)
  37 #define DDCM_CLK_DIV_OFFSET  ((UINT32)16)
  38 #define DDCM_CLK_DIV_MASK    ((UINT32)0xFFF<<16)
  39 #define DDCM_CS_STATUS       ((UINT32)0x1<<4)
  40 #define DDCM_SCL_STATE       ((UINT32)0x1<<3)
  41 #define DDCM_SDA_STATE       ((UINT32)0x1<<2)
  42 #define DDCM_SM0EN           ((UINT32)0x1<<1)
  43 #define DDCM_SCL_STRECH      ((UINT32)0x1<<0)
  44
  45 #define DDC_DDCMCTL1           ((UINT32)0x4)
  46 #define DDCM_ACK_OFFSET      ((UINT32)16)
  47 #define DDCM_ACK_MASK        ((UINT32)0xFF<<16)
  48 #define DDCM_PGLEN_OFFSET    ((UINT32)8)
  49 #define DDCM_PGLEN_MASK      ((UINT32)0x7<<8)
  50 #define DDCM_SIF_MODE_OFFSET ((UINT32)4)
  51 #define DDCM_SIF_MODE_MASK   ((UINT32)0x7<<4)
  52 #define DDCM_START            ((UINT32)0x1)
  53 #define DDCM_WRITE_DATA       ((UINT32)0x2)
  54 #define DDCM_STOP             ((UINT32)0x3)
  55 #define DDCM_READ_DATA_NO_ACK ((UINT32)0x4)
  56 #define DDCM_READ_DATA_ACK    ((UINT32)0x5)
  57 #define DDCM_TRI             ((UINT32)0x1<<0)
  58
  59 #define DDC_DDCMD0             ((UINT32)0x8)
  60 #define DDCM_DATA3           ((UINT32)0xFF<<24)
  61 #define DDCM_DATA2           ((UINT32)0xFF<<16)
  62 #define DDCM_DATA1           ((UINT32)0xFF<<8)
  63 #define DDCM_DATA0           ((UINT32)0xFF<<0)
  64
  65 #define DDC_DDCMD1             ((UINT32)0xC)
  66 #define DDCM_DATA7           ((UINT32)0xFF<<24)
  67 #define DDCM_DATA6           ((UINT32)0xFF<<16)
  68 #define DDCM_DATA5           ((UINT32)0xFF<<8)
  69 #define DDCM_DATA4           ((UINT32)0xFF<<0)
  70
  71
  72 typedef enum {
  73         SIF_8_BIT,              /* /< [8 bits data address.] */
  74         SIF_16_BIT,             /* /< [16 bits data address.] */
  75 } SIF_BIT_T;
  76
  77 typedef enum {
  78         SIF_NORMAL,             /* /< [Normal, always select this.] */
  79         SIF_OTHER,              /* /< [Other.] */
  80 } SIF_TYPE_T;
  81   /* / [Sif control mode select.] */
  82 typedef struct _SIF_MODE_T {
  83         SIF_BIT_T eBit;         /* /< [The data address type. ] */
  84         SIF_TYPE_T eType;       /* /< [The control mode.] */
  85 } SIF_MODE_T;
  86
  87 extern u8 fgDDCDataRead(u8 bDevice, u8 bData_Addr, u8 bDataCount, u8 *prData);
  88 extern u8 fgDDCDataWrite(u8 bDevice, u8 bData_Addr, u8 bDataCount, u8 *prData);
  89
  90 #endif
  91 #endif