drivers/misc/mediatek/hdmi/ch7035/ch703xdriver.h

   1 /* Description: ch7033-35 interface */
   2
   3
   4 #ifndef _CH703x_LIB_H_
   5 #define _CH703x_LIB_H_
   6
   7 /* --------------- TIMING INFORMATION ----------------------- */
   8 typedef struct {
   9         uint32 ht;              /* horizontal tatal pixels */
  10         uint32 ha;              /* horizontal active pixels */
  11         uint32 ho;              /* horizontal offset (back porch) */
  12         uint32 hw;              /* horizontal sync pulse width */
  13         uint32 vt;              /* vertical total lines */
  14         uint32 va;              /* vertical active lines */
  15         uint32 vo;              /* vertical offset (back porch) */
  16         uint32 vw;              /* vertical sync pulse width */
  17 } CH703x_TIMING, *PCH703x_TIMING;
  18
  19 /* --------------- INPUT INFORMATION ----------------------- */
  20 /* pixel format for input */
  21 #define PIXEL_FMT_RGB888        0       /* RGB 888 format (24-bit) */
  22 #define PIXEL_FMT_RGB666        1       /* RGB 666 format (18-bit) */
  23 #define PIXEL_FMT_RGB565        2       /* RGB 565 format (16-bit) */
  24 #define PIXEL_FMT_RGB555        3       /* RGB 555 format (16-bit) */
  25 #define PIXEL_FMT_RGBDVO        4       /* RGB DVO */
  26 #define PIXEL_FMT_YUV422_8      5       /* YCbCr 4:2:2 8-bit */
  27 #define PIXEL_FMT_YUV422_10     6       /* YCbCr 4:2:2 10-bit */
  28 #define PIXEL_FMT_YUV444        7       /* YCbCr 4:4:4 8-bit */
  29 #define PIXEL_FMT_RGB666_C      9       /* consecutive RGB666 */
  30 #define PIXEL_FMT_RGB565_C      10      /* consecutive RGB565 */
  31 #define PIXEL_FMT_RGB555_C      11      /* consecutive RGB555 */
  32
  33 /* polarity and invert */
  34 #define POL_HIGH                        1
  35 #define POL_LOW                         0
  36 #define POL_INVERT                      1
  37 #define POL_NO_INV                      0
  38
  39 /* audio input type */
  40 #define AUDIO_I2S                       1
  41 #define AUDIO_SPDIF                     0
  42
  43 #define SPDIF_MOD_DIFF          0
  44 #define SPDIF_MOD_CMOS          1
  45
  46 /* I2S audio format */
  47 #define I2S_FMT_STD                     0
  48 #define I2S_FMT_RTJ                     1       /* right justified */
  49 #define I2S_FMT_LTJ                     2       /* left justified */
  50
  51 #define I2S_LEN_16B                     0       /* 16 - bit */
  52 #define I2S_LEN_20B                     1       /* 20 - bit */
  53 #define I2S_LEN_24B                     2       /* 24 - bit */
  54
  55 typedef enum {
  56         IF_PRO = 0,             /* progressive video interface */
  57         IF_INT,                 /* interlace video interface */
  58         IF_CPU,                 /* video interface like CPU data interface */
  59 } IF_TYPE;
  60
  61 /* Multi 2x format: */
  62 #define M2X_SEQ_NO_INV          0
  63 #define M2X_SEQ_INVERT          1
  64 #define M2X_ALIGH_LBIT          0
  65 #define M2X_ALIGH_HBIT          1
  66 typedef struct {
  67         /* for 2x multi: */
  68         uint8 halfword_swap;    /* halfword swap: refer to "SWP_PAPB" in datasheet */
  69         uint8 halfword_align;   /* halfword align select: refer to "AH_LB" in datasheet */
  70         uint8 yc_swap;          /* indicate Y and C swap (only for BT656 input) */
  71         uint8 reserved;
  72 } M2X_FMT, *PM2X_FMT;
  73
  74 /* Multi 3x format; */
  75 #define M3X_ALIGH_LBIT          0
  76 #define M3X_ALIGH_MBIT          1
  77 #define M3X_ALIGH_HBIT          2
  78 typedef struct {
  79         /* for 3x multi: */
  80         uint8 byte_align;       /* byte align: refer to "POS3X" in datasheet */
  81         uint8 reserved[3];
  82 } M3X_FMT, *PM3X_FMT;
  83
  84 #define MULTI_1X                0
  85 #define MULTI_2X                1
  86 #define MULTI_3X                2
  87
  88 /* input pixel format byte swap, byte_swap */
  89 #define BYTE_SWAP_RGB   0
  90 #define BYTE_SWAP_RBG   1
  91 #define BYTE_SWAP_GRB   2
  92 #define BYTE_SWAP_GBR   3
  93 #define BYTE_SWAP_BRG   4
  94 #define BYTE_SWAP_BGR   5
  95
  96 typedef struct {
  97         uint8 format;           /* input data format, refer to IDF in datasheet */
  98         uint8 bit_swap;         /* select bit swap for each byte, refer to REVERSE in datasheet */
  99         uint8 byte_swap;        /* R-G-B or Y-Pb-Pr swap, refer to SWAP in datasheet */
 100         uint8 byte_align;       /* MSB align or LSB align, refer to HIGH in datasheet */
 101         uint8 multiplexed;      /* indicate if data is multiplexed: refer to MULTI in datasheet */
 102         uint8 embedded_sync;    /* indicate if embedded sync is used */
 103         uint8 reserved[2];
 104         M2X_FMT m2x_fmt;        /* multiplexed 2x data properties */
 105         M3X_FMT m3x_fmt;        /* multiplexed 3x data properties */
 106 } PIXEL_FMT, *PPIXEL_FMT;
 107
 108 typedef struct {
 109         IF_TYPE if_type;        /* interface type */
 110         CH703x_TIMING timing;
 111         uint32 pclk_khz;        /* pixel clock frequecy */
 112         PIXEL_FMT pixel_fmt;
 113         uint8 hs_pol;           /* horizontal sync polarity */
 114         uint8 vs_pol;           /* vertical sync polarity */
 115         uint8 de_pol;           /* data enable  polarity */
 116         /* audio related: */
 117         uint8 audio_type;       /* 0: spdif - 1: i2s */
 118         uint8 spdif_mode;       /* 0: differential mode - 1: cmos mode */
 119         uint8 i2s_pol;
 120         uint8 i2s_len;
 121         uint8 i2s_fmt;
 122         /* if using crystal: */
 123         uint8 crystal_used;     /* 0: no crystal - 1: using crystal */
 124         uint8 reserved[3];
 125         uint32 crystal_khz;
 126 } CH703x_INPUT_INFO, *PCH703x_INPUT_INFO;
 127
 128 /* --------------- OUTPUT INFORMATION ----------------------- */
 129 /* channel bit define: */
 130 #define LVDS_DATA0_SEL                  0
 131 #define LVDS_DATA1_SEL                  1
 132 #define LVDS_DATA2_SEL                  2
 133 #define LVDS_DATA3_SEL                  3
 134 #define LVDS_CLOCK_SEL                  4
 135
 136 #define LVDS_CHANNEL_SWAP_DEF   0
 137 #define LVDS_CHANNEL_SWAP_OP1   1
 138
 139 #define LVDS_SPWG_T1_MIN                1
 140 #define LVDS_SPWG_T1_MAX                50
 141 #define LVDS_SPWG_T2_MIN                200
 142 #define LVDS_SPWG_T2_MAX                1023
 143 #define LVDS_SPWG_T3_MIN                200
 144 #define LVDS_SPWG_T3_MAX                1023
 145 #define LVDS_SPWG_T4_MIN                1
 146 #define LVDS_SPWG_T4_MAX                50
 147 #define LVDS_SPWG_T5_MIN                200
 148 #define LVDS_SPWG_T5_MAX                1023
 149
 150 /* value of pwm_freq, Hz */
 151 #define IDX_PWM_FREQ_100Hz              100
 152 #define IDX_PWM_FREQ_200Hz              200
 153 #define IDX_PWM_FREQ_2KHz               2000
 154 #define IDX_PWM_FREQ_4KHz               4000
 155 #define IDX_PWM_FREQ_16KHz              16000
 156 #define IDX_PWM_FREQ_32KHz              32000
 157 #define IDX_PWM_FREQ_64KHz              64000
 158 #define IDX_PWM_FREQ_128KHz             128000
 159
 160 typedef struct {
 161         uint8 bypass;           /* indicate if bypass function enabled */
 162         uint8 channel_swap;     /* refer to spec: HD_LV_SEQ */
 163         uint8 channel_pol;      /* channel polarity */
 164         uint8 hs_pol;           /* hsync polarity */
 165         uint8 vs_pol;           /* vsync polarity */
 166         uint8 de_pol;           /* de polarity */
 167         /* externed at 2011.05.25 */
 168         uint8 pwm_duty;         /* pwm duty-cycle       0~255 */
 169         uint8 pwm_inv;          /* pwm inverter  POL_INVERT or POL_NO_INV */
 170         uint32 pwm_freq;        /* pwm frequency, which should be 100Hz, 200Hz, 2kHz, 4KHz, 16Khz, 32KHZ, 64KHz, 128KHz */
 171         uint32 spwg_t1;         /* power sequency of T1 */
 172         uint32 spwg_t2;         /* power sequency of T2 */
 173         uint32 spwg_t3;         /* power sequency of T3 */
 174         uint32 spwg_t4;         /* power sequency of T4 */
 175         uint32 spwg_t5;         /* power sequency of T5 */
 176 } LVDS_FMT, *PLVDS_FMT;
 177
 178 /* aspect ratio, These do not match the EDID encoding */
 179 #define AS_RATIO_NA                     0       /* support */
 180 #define AS_RATIO_4_3            1       /* support */
 181 #define AS_RATIO_16_9           2       /* support */
 182 #define AS_RATIO_16_10          3       /* not support */
 183 #define AS_RATIO_5_4            4       /* not support */
 184
 185 /* hdmi channel swap selection, description "channel_swap" in HDMI_FMT below: */
 186 /* here only define default macro, for other condition, use number directly... */
 187 #define HDMI_CHANNEL_SWAP_DEF   0
 188
 189 typedef struct {
 190         uint8 bypass;           /* indicate if bypass mode enabled */
 191         uint8 is_dvi_mode;      /* indicate if DVI mode required */
 192         uint8 format_index;     /* VIC index */
 193         uint8 aspect_ratio;     /* 1: 4:3 - 2: 16:9 */
 194         uint8 channel_swap;     /* refer to "HD_LV_SEQ" in datasheet. */
 195         uint8 data_pol_invert;  /* if invert the polarity of input of HDMI module, refer to HD_LV_POL in spec. */
 196         uint8 hs_pol;           /* HDMI output horizontal sync polarity */
 197         uint8 vs_pol;           /* HDMI output vertical sync polarity */
 198 } HDMI_FMT, *PHDMI_FMT;
 199
 200 /* vga channel swap selection, descript "channel_swap" in VGA_FMT below: */
 201 /* here only define default macro, for other condition, use number directly... */
 202 #define VGA_CHANNEL_SWAP_DEF    0
 203
 204 /* vga sync swap selection, descript "sync_swap" in VGA_FMT below: */
 205 /* here only define default macro, for other condition, use number directly... */
 206 #define VGA_SYNC_SWAP_DEF               0
 207
 208 #define VGA_CSYNC_XOR                   0
 209 #define VGA_CSYNC_OR                    1
 210 #define VGA_CSYNC_AND                   2
 211
 212 typedef struct {
 213         uint8 bypass;           /* indicate if bypass function enabled */
 214         uint8 channel_swap;     /* R G B swap control, refer to "DACSP" in datasheet */
 215         uint8 sync_swap;        /* sync swap control, refer to "SYNCS" in datasheet */
 216         uint8 csync_type;       /* CSync type */
 217         uint8 hs_pol;           /* horizontal sync polarity */
 218         uint8 vs_pol;           /* vetical sync polairy */
 219         uint8 de_pol;           /* Data enable signal polarity */
 220         uint8 reserved;
 221 } VGA_FMT, *PVGA_FMT;
 222
 223 /* hdtv channel swap selection, descript "channel_swap" in HDTV_FMT below: */
 224 /* here only define default macro, for other condition, use number directly... */
 225 #define HDTV_CHANNEL_SWAP_DEF   0
 226
 227 typedef struct {
 228         uint8 bypass;           /* indicate if bypass function enabled */
 229         uint8 format_index;     /* refer to datasheet */
 230         uint8 channel_swap;     /* Y Pb Pr channel swap, refer to "DACSP" in datasheet */
 231         uint8 reserved;
 232 } HDTV_FMT, *PHDTV_FMT;
 233
 234 /* channel bits, output channel */
 235 #define CHANNEL_LVDS            0x01
 236 #define CHANNEL_HDMI            0x02
 237 #define CHANNEL_VGA                     0x04
 238 #define CHANNEL_HDTV            0x08
 239 #define CHANNEL_VGA1            0x10
 240 /* channel bits, input channel */
 241 #define CHANNEL_INPUTLOST       0x20
 242
 243 #define ROTATE_NO                       0
 244 #define ROTATE_90                       1
 245 #define ROTATE_180                      2
 246 #define ROTATE_270                      3
 247
 248 #define DOWN_SCALING_MAX        80      /* -+wyc, [0..80]. 0=100%, no down scaling; 80=down scale to 20% in size */
 249
 250 typedef struct {
 251         CH703x_TIMING timing;   /* Timing */
 252         uint32 uclk_khz;        /* output clock frequency */
 253         uint8 channel;          /* combined channel bits */
 254         uint8 reserved1[3];
 255         LVDS_FMT lvds_fmt;      /* LVDS special format if output to LVDS */
 256         HDMI_FMT hdmi_fmt;      /* HDMI special format if output to LVDS */
 257         VGA_FMT vga_fmt;        /* VGA special format if output to LVDS */
 258         HDTV_FMT hdtv_fmt;      /* HDTV special format  if output to LVDS */
 259
 260         /* features */
 261         uint8 ds_percent_h;     /* down scaling percent for horizontal direction */
 262         uint8 ds_percent_v;     /* down scaling percent for vertical direction */
 263         uint8 rotate;           /* Rotation control */
 264         uint8 h_flip;           /* Horizontal flip control */
 265         uint8 v_flip;           /* Vertical flip control */
 266         uint8 reserved2[3];
 267 } CH703x_OUTPUT_INFO, *PCH703x_OUTPUT_INFO;
 268
 269 /* get which panel's EDID, currently only support reading EDID from HDMI or VGA */
 270 #define  GET_VGA_EDID           0x80
 271 #define  GET_HDMI_EDID          0x00
 272 #define  GET_EDID_MASK          0x80
 273
 274 /* --------------- DEVICE INFORMATION ----------------------- */
 275 typedef enum {
 276         DEV_CH7033E = 0,
 277         DEV_CH7034E,
 278         DEV_CH7035E,
 279
 280         DEV_CH7033F,
 281         DEV_CH7034F,
 282         DEV_CH7035F,
 283
 284         DEV_UNKNOW,             /* always be the last */
 285 } CH703x_DEV_TYPE;
 286
 287 typedef struct _FW703X_CFG {
 288         unsigned char size;     /* total size <=16 bytes, currently 7 bytes */
 289         unsigned char ver_major;        /* MCU firmware version */
 290         unsigned char ver_minor;
 291         unsigned char did;      /* device id */
 292         unsigned char rid;      /* revision id */
 293         unsigned char capbility;        /* Firmware capability; */
 294         unsigned char reserved;
 295         unsigned char reserve2;
 296 } FW703X_CFG;
 297
 298 /* ------------------ Interface -------------------------------- */
 299
 300 #ifdef __cplusplus
 301 extern "C" {
 302 #endif
 303
 304 /* open I2C device before calling any of the following functions */
 305
 306 /* Enter: */
 307 /* 0..DEV_UNKNOW-1:        check whether the specified device present */
 308 /* DEV_UNKNOW:    check which device present */
 309 /* Return: */
 310 /* 0..DEV_UNKNOW-1:        the device present */
 311 /* DEV_UNKNOW:    not found device present */
 312         CH703x_DEV_TYPE ch_check_chip(CH703x_DEV_TYPE chip);
 313
 314 /* start firmware before calling any other functions */
 315         int32 ch_start_firmware(CH703x_DEV_TYPE chip);
 316
 317 /* get MCU information */
 318         int32 ch_getMcuVersion(CH703x_DEV_TYPE chip, FW703X_CFG * cfg);
 319
 320 /* load the firmware of ch703x */
 321         int32 ch_load_firmware(CH703x_DEV_TYPE chip, uint8 *fw, uint16 size);
 322
 323 /* set ch703x working mode */
 324 /* this function also sets these features: scaling down, rotation or flip */
 325         int32 ch_set_mode(CH703x_DEV_TYPE chip, CH703x_INPUT_INFO * in, CH703x_OUTPUT_INFO * out);
 326
 327 /* force ch703x to output color bar(generated by itself) instead of the input. */
 328 /* ch_set_mode() should be successfully called before calling this function. */
 329 /* test only. */
 330         int32 ch_set_test_mode(CH703x_DEV_TYPE chip);
 331
 332 /* get edid from VGA pannel or HDMI pannel */
 333 /* Enter: */
 334 /* buf:  buffer to store EDID, >= 256 bytes, 512 bytes recommended. */
 335 /* len:  buffer length */
 336 /* whichEDID: GET_VGA_EDID or GET_HDMI_EDID */
 337         int32 ch_get_edid(CH703x_DEV_TYPE chip, uint8 *buf, uint16 len, uint8 whichEDID);
 338
 339 #define VGA_HOTPLUG_DELAY               50      /* unit ms */
 340 /* For output channel, currently only support HDMI and VGA hotplg detecting, */
 341 /* could not detect HDTV, VGA1, LVDS hotplug. */
 342 /* For input channel, currently support input channel lost detecting. */
 343 /* There is a delay when hardware detecting VGA connection, VGA_HOTPLUG_DELAY */
 344 /* is workable. If you periodically detect hotplug, you can specify the delay */
 345 /* to 0. It is not effective for firmware detecting. */
 346 /* Return: */
 347 /* channel bits to indicate which outputs are connected and */
 348 /* whether input lost. */
 349         uint8 ch_check_connection(CH703x_DEV_TYPE chip, int delay);
 350         int32 ch_set_plug_out_power(CH703x_DEV_TYPE chip, uint8 enable);
 351 /* Enter */
 352 /* channel_bits: combined output channel bits */
 353 /* 1: power on  this output channel */
 354 /* 0: power off this output channel */
 355         int32 ch_set_channel_power(CH703x_DEV_TYPE chip, uint8 channel_bits);
 356
 357 /* Enter: */
 358 /* channel_bits: combined output channel bits */
 359 /* 0x00:  force chip to enter standby state to save power. */
 360 /* other: wake up chip and power on the specified output channel, */
 361 /* then you must call ch_set_mode to setup chip again */
 362         int32 ch_set_chip_power(CH703x_DEV_TYPE chip, uint8 channel_bits);
 363
 364 /* dither: 0 - disable; 1 - enable */
 365         int32 ch_set_dither(CH703x_DEV_TYPE chip, uint8 dither);
 366
 367 /* Enter: */
 368 /* pwm_duty:       same as pwm_duty in LVDS_FMT, 0~255 */
 369 /* Return:  old setting */
 370         uint8 ch_set_lvds_brightness(CH703x_DEV_TYPE chip, uint8 pwm_duty);
 371
 372 #define MCUAUTO_SETMODE         0x40
 373 /* currently you can only enable/disable MCU auto set display mode function. */
 374 /* auto ouput channel hotplug and input channel lost detection are always */
 375 /* enabled. If you enable MCU auto function, when output channel hotplug, */
 376 /* MCU will automatically close/display to this output channel. */
 377 /* Enter: */
 378 /* mcuAutoBits:    combined bits to enable MCU auto functions */
 379 /* Return:      old setting */
 380         uint8 ch_enable_MCU_AutoFunc(CH703x_DEV_TYPE chip, uint8 mcuAutoBits);
 381
 382 /* -------- lvds_bypass_mode, add on 2011-11-11 ---------- */
 383
 384 /* Enter: */
 385 /* current:  bit 7,    0 - enable, 1 - disable */
 386 /* bi7 2..0, 0 ~ 7 set current to */
 387 /* 0 - 2.45mA,  1 - 2.8mA,  2 - 3.15mA,  3 - 3.5mA(default) */
 388 /* 4 - 3.85mA,  5 - 4.2mA,  6 - 4.55mA,  7 - 4.9mA */
 389 /* Note: */
 390 /* only set this when the output is lvds bypass mode */
 391 /* some settings may cause panel fail to power on */
 392 /* Return:  old setting */
 393 /* uint8 ch_set_lvds_current(CH703x_DEV_TYPE chip, uint8 current); */
 394
 395 /* Enter: */
 396 /* bOn:    0 - Off; 1 - On */
 397 /* Return:  old setting */
 398         uint8 ch_set_lvds_common_voltage(CH703x_DEV_TYPE chip, uint8 bOn);
 399
 400 /* MTK-Add */
 401         void ch_dump_reg(void);
 402         void ch_read_reg(unsigned char u8Reg);
 403         void ch_write_reg(unsigned char u8Reg, unsigned char u8Data);
 404         void hw_set_HPD_MAX(uint8 addr);
 405         void hw_set_inv_clk(uint8 inv);
 406         void hw_set_suspend(void);
 407         void hw_set_resume(void);
 408
 409 #ifdef __cplusplus
 410 }
 411 #endif
 412 #endif