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mali mess
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / gpu / mt8127 / mali / mali / common / mali_l2_cache.c
1 /*
2 * This confidential and proprietary software may be used only as
3 * authorised by a licensing agreement from ARM Limited
4 * (C) COPYRIGHT 2008-2015 ARM Limited
5 * ALL RIGHTS RESERVED
6 * The entire notice above must be reproduced on all authorised
7 * copies and copies may only be made to the extent permitted
8 * by a licensing agreement from ARM Limited.
9 */
10 #include "mali_kernel_common.h"
11 #include "mali_osk.h"
12 #include "mali_l2_cache.h"
13 #include "mali_hw_core.h"
14 #include "mali_scheduler.h"
15 #include "mali_pm.h"
16 #include "mali_pm_domain.h"
17
18 /**
19 * Size of the Mali L2 cache registers in bytes
20 */
21 #define MALI400_L2_CACHE_REGISTERS_SIZE 0x30
22
23 /**
24 * Mali L2 cache register numbers
25 * Used in the register read/write routines.
26 * See the hardware documentation for more information about each register
27 */
28 typedef enum mali_l2_cache_register {
29 MALI400_L2_CACHE_REGISTER_SIZE = 0x0004,
30 MALI400_L2_CACHE_REGISTER_STATUS = 0x0008,
31 /*unused = 0x000C */
32 MALI400_L2_CACHE_REGISTER_COMMAND = 0x0010,
33 MALI400_L2_CACHE_REGISTER_CLEAR_PAGE = 0x0014,
34 MALI400_L2_CACHE_REGISTER_MAX_READS = 0x0018,
35 MALI400_L2_CACHE_REGISTER_ENABLE = 0x001C,
36 MALI400_L2_CACHE_REGISTER_PERFCNT_SRC0 = 0x0020,
37 MALI400_L2_CACHE_REGISTER_PERFCNT_VAL0 = 0x0024,
38 MALI400_L2_CACHE_REGISTER_PERFCNT_SRC1 = 0x0028,
39 MALI400_L2_CACHE_REGISTER_PERFCNT_VAL1 = 0x002C,
40 } mali_l2_cache_register;
41
42 /**
43 * Mali L2 cache commands
44 * These are the commands that can be sent to the Mali L2 cache unit
45 */
46 typedef enum mali_l2_cache_command {
47 MALI400_L2_CACHE_COMMAND_CLEAR_ALL = 0x01,
48 } mali_l2_cache_command;
49
50 /**
51 * Mali L2 cache commands
52 * These are the commands that can be sent to the Mali L2 cache unit
53 */
54 typedef enum mali_l2_cache_enable {
55 MALI400_L2_CACHE_ENABLE_DEFAULT = 0x0, /* Default */
56 MALI400_L2_CACHE_ENABLE_ACCESS = 0x01,
57 MALI400_L2_CACHE_ENABLE_READ_ALLOCATE = 0x02,
58 } mali_l2_cache_enable;
59
60 /**
61 * Mali L2 cache status bits
62 */
63 typedef enum mali_l2_cache_status {
64 MALI400_L2_CACHE_STATUS_COMMAND_BUSY = 0x01,
65 MALI400_L2_CACHE_STATUS_DATA_BUSY = 0x02,
66 } mali_l2_cache_status;
67
68 #define MALI400_L2_MAX_READS_NOT_SET -1
69
70 static struct mali_l2_cache_core *
71 mali_global_l2s[MALI_MAX_NUMBER_OF_L2_CACHE_CORES] = { NULL, };
72 static u32 mali_global_num_l2s = 0;
73
74 int mali_l2_max_reads = MALI400_L2_MAX_READS_NOT_SET;
75
76
77 /* Local helper functions */
78
79 static void mali_l2_cache_reset(struct mali_l2_cache_core *cache);
80
81 static _mali_osk_errcode_t mali_l2_cache_send_command(
82 struct mali_l2_cache_core *cache, u32 reg, u32 val);
83
84 static void mali_l2_cache_lock(struct mali_l2_cache_core *cache)
85 {
86 MALI_DEBUG_ASSERT_POINTER(cache);
87 _mali_osk_spinlock_irq_lock(cache->lock);
88 }
89
90 static void mali_l2_cache_unlock(struct mali_l2_cache_core *cache)
91 {
92 MALI_DEBUG_ASSERT_POINTER(cache);
93 _mali_osk_spinlock_irq_unlock(cache->lock);
94 }
95
96 /* Implementation of the L2 cache interface */
97
98 struct mali_l2_cache_core *mali_l2_cache_create(
99 _mali_osk_resource_t *resource, u32 domain_index)
100 {
101 struct mali_l2_cache_core *cache = NULL;
102 #if defined(DEBUG)
103 u32 cache_size;
104 #endif
105
106 MALI_DEBUG_PRINT(4, ("Mali L2 cache: Creating Mali L2 cache: %s\n",
107 resource->description));
108
109 if (mali_global_num_l2s >= MALI_MAX_NUMBER_OF_L2_CACHE_CORES) {
110 MALI_PRINT_ERROR(("Mali L2 cache: Too many L2 caches\n"));
111 return NULL;
112 }
113
114 cache = _mali_osk_malloc(sizeof(struct mali_l2_cache_core));
115 if (NULL == cache) {
116 MALI_PRINT_ERROR(("Mali L2 cache: Failed to allocate memory for L2 cache core\n"));
117 return NULL;
118 }
119
120 cache->core_id = mali_global_num_l2s;
121 cache->counter_src0 = MALI_HW_CORE_NO_COUNTER;
122 cache->counter_src1 = MALI_HW_CORE_NO_COUNTER;
123 cache->counter_value0_base = 0;
124 cache->counter_value1_base = 0;
125 cache->pm_domain = NULL;
126 cache->power_is_on = MALI_FALSE;
127 cache->last_invalidated_id = 0;
128
129 if (_MALI_OSK_ERR_OK != mali_hw_core_create(&cache->hw_core,
130 resource, MALI400_L2_CACHE_REGISTERS_SIZE)) {
131 _mali_osk_free(cache);
132 return NULL;
133 }
134
135 #if defined(DEBUG)
136 cache_size = mali_hw_core_register_read(&cache->hw_core,
137 MALI400_L2_CACHE_REGISTER_SIZE);
138 MALI_DEBUG_PRINT(2, ("Mali L2 cache: Created %s: % 3uK, %u-way, % 2ubyte cache line, % 3ubit external bus\n",
139 resource->description,
140 1 << (((cache_size >> 16) & 0xff) - 10),
141 1 << ((cache_size >> 8) & 0xff),
142 1 << (cache_size & 0xff),
143 1 << ((cache_size >> 24) & 0xff)));
144 #endif
145
146 cache->lock = _mali_osk_spinlock_irq_init(_MALI_OSK_LOCKFLAG_ORDERED,
147 _MALI_OSK_LOCK_ORDER_L2);
148 if (NULL == cache->lock) {
149 MALI_PRINT_ERROR(("Mali L2 cache: Failed to create counter lock for L2 cache core %s\n",
150 cache->hw_core.description));
151 mali_hw_core_delete(&cache->hw_core);
152 _mali_osk_free(cache);
153 return NULL;
154 }
155
156 /* register with correct power domain */
157 cache->pm_domain = mali_pm_register_l2_cache(
158 domain_index, cache);
159
160 mali_global_l2s[mali_global_num_l2s] = cache;
161 mali_global_num_l2s++;
162
163 return cache;
164 }
165
166 void mali_l2_cache_delete(struct mali_l2_cache_core *cache)
167 {
168 u32 i;
169 for (i = 0; i < mali_global_num_l2s; i++) {
170 if (mali_global_l2s[i] != cache) {
171 continue;
172 }
173
174 mali_global_l2s[i] = NULL;
175 mali_global_num_l2s--;
176
177 if (i == mali_global_num_l2s) {
178 /* Removed last element, nothing more to do */
179 break;
180 }
181
182 /*
183 * We removed a l2 cache from the middle of the array,
184 * so move the last l2 cache to current position
185 */
186 mali_global_l2s[i] = mali_global_l2s[mali_global_num_l2s];
187 mali_global_l2s[mali_global_num_l2s] = NULL;
188
189 /* All good */
190 break;
191 }
192
193 _mali_osk_spinlock_irq_term(cache->lock);
194 mali_hw_core_delete(&cache->hw_core);
195 _mali_osk_free(cache);
196 }
197
198 void mali_l2_cache_power_up(struct mali_l2_cache_core *cache)
199 {
200 MALI_DEBUG_ASSERT_POINTER(cache);
201
202 mali_l2_cache_lock(cache);
203
204 mali_l2_cache_reset(cache);
205
206 MALI_DEBUG_ASSERT(MALI_FALSE == cache->power_is_on);
207 cache->power_is_on = MALI_TRUE;
208
209 mali_l2_cache_unlock(cache);
210 }
211
212 void mali_l2_cache_power_down(struct mali_l2_cache_core *cache)
213 {
214 MALI_DEBUG_ASSERT_POINTER(cache);
215
216 mali_l2_cache_lock(cache);
217
218 MALI_DEBUG_ASSERT(MALI_TRUE == cache->power_is_on);
219
220 /*
221 * The HW counters will start from zero again when we resume,
222 * but we should report counters as always increasing.
223 * Take a copy of the HW values now in order to add this to
224 * the values we report after being powered up.
225 *
226 * The physical power off of the L2 cache might be outside our
227 * own control (e.g. runtime PM). That is why we must manually
228 * set set the counter value to zero as well.
229 */
230
231 if (cache->counter_src0 != MALI_HW_CORE_NO_COUNTER) {
232 cache->counter_value0_base += mali_hw_core_register_read(
233 &cache->hw_core,
234 MALI400_L2_CACHE_REGISTER_PERFCNT_VAL0);
235 mali_hw_core_register_write(&cache->hw_core,
236 MALI400_L2_CACHE_REGISTER_PERFCNT_VAL0, 0);
237 }
238
239 if (cache->counter_src1 != MALI_HW_CORE_NO_COUNTER) {
240 cache->counter_value1_base += mali_hw_core_register_read(
241 &cache->hw_core,
242 MALI400_L2_CACHE_REGISTER_PERFCNT_VAL1);
243 mali_hw_core_register_write(&cache->hw_core,
244 MALI400_L2_CACHE_REGISTER_PERFCNT_VAL1, 0);
245 }
246
247
248 cache->power_is_on = MALI_FALSE;
249
250 mali_l2_cache_unlock(cache);
251 }
252
253 void mali_l2_cache_core_set_counter_src(
254 struct mali_l2_cache_core *cache, u32 source_id, u32 counter)
255 {
256 u32 reg_offset_src;
257 u32 reg_offset_val;
258
259 MALI_DEBUG_ASSERT_POINTER(cache);
260 MALI_DEBUG_ASSERT(source_id >= 0 && source_id <= 1);
261
262 mali_l2_cache_lock(cache);
263
264 if (0 == source_id) {
265 /* start counting from 0 */
266 cache->counter_value0_base = 0;
267 cache->counter_src0 = counter;
268 reg_offset_src = MALI400_L2_CACHE_REGISTER_PERFCNT_SRC0;
269 reg_offset_val = MALI400_L2_CACHE_REGISTER_PERFCNT_VAL0;
270 } else {
271 /* start counting from 0 */
272 cache->counter_value1_base = 0;
273 cache->counter_src1 = counter;
274 reg_offset_src = MALI400_L2_CACHE_REGISTER_PERFCNT_SRC1;
275 reg_offset_val = MALI400_L2_CACHE_REGISTER_PERFCNT_VAL1;
276 }
277
278 if (cache->power_is_on) {
279 u32 hw_src;
280
281 if (MALI_HW_CORE_NO_COUNTER != counter) {
282 hw_src = counter;
283 } else {
284 hw_src = 0; /* disable value for HW */
285 }
286
287 /* Set counter src */
288 mali_hw_core_register_write(&cache->hw_core,
289 reg_offset_src, hw_src);
290
291 /* Make sure the HW starts counting from 0 again */
292 mali_hw_core_register_write(&cache->hw_core,
293 reg_offset_val, 0);
294 }
295
296 mali_l2_cache_unlock(cache);
297 }
298
299 void mali_l2_cache_core_get_counter_values(
300 struct mali_l2_cache_core *cache,
301 u32 *src0, u32 *value0, u32 *src1, u32 *value1)
302 {
303 MALI_DEBUG_ASSERT_POINTER(cache);
304 MALI_DEBUG_ASSERT(NULL != src0);
305 MALI_DEBUG_ASSERT(NULL != value0);
306 MALI_DEBUG_ASSERT(NULL != src1);
307 MALI_DEBUG_ASSERT(NULL != value1);
308
309 mali_l2_cache_lock(cache);
310
311 *src0 = cache->counter_src0;
312 *src1 = cache->counter_src1;
313
314 if (cache->counter_src0 != MALI_HW_CORE_NO_COUNTER) {
315 if (MALI_TRUE == cache->power_is_on) {
316 *value0 = mali_hw_core_register_read(&cache->hw_core,
317 MALI400_L2_CACHE_REGISTER_PERFCNT_VAL0);
318 } else {
319 *value0 = 0;
320 }
321
322 /* Add base offset value (in case we have been power off) */
323 *value0 += cache->counter_value0_base;
324 }
325
326 if (cache->counter_src1 != MALI_HW_CORE_NO_COUNTER) {
327 if (MALI_TRUE == cache->power_is_on) {
328 *value1 = mali_hw_core_register_read(&cache->hw_core,
329 MALI400_L2_CACHE_REGISTER_PERFCNT_VAL1);
330 } else {
331 *value1 = 0;
332 }
333
334 /* Add base offset value (in case we have been power off) */
335 *value1 += cache->counter_value1_base;
336 }
337
338 mali_l2_cache_unlock(cache);
339 }
340
341 struct mali_l2_cache_core *mali_l2_cache_core_get_glob_l2_core(u32 index)
342 {
343 if (mali_global_num_l2s > index) {
344 return mali_global_l2s[index];
345 }
346
347 return NULL;
348 }
349
350 u32 mali_l2_cache_core_get_glob_num_l2_cores(void)
351 {
352 return mali_global_num_l2s;
353 }
354
355 void mali_l2_cache_invalidate(struct mali_l2_cache_core *cache)
356 {
357 MALI_DEBUG_ASSERT_POINTER(cache);
358
359 if (NULL == cache) {
360 return;
361 }
362
363 mali_l2_cache_lock(cache);
364
365 cache->last_invalidated_id = mali_scheduler_get_new_cache_order();
366 mali_l2_cache_send_command(cache, MALI400_L2_CACHE_REGISTER_COMMAND,
367 MALI400_L2_CACHE_COMMAND_CLEAR_ALL);
368
369 mali_l2_cache_unlock(cache);
370 }
371
372 void mali_l2_cache_invalidate_conditional(
373 struct mali_l2_cache_core *cache, u32 id)
374 {
375 MALI_DEBUG_ASSERT_POINTER(cache);
376
377 if (NULL == cache) {
378 return;
379 }
380
381 /*
382 * If the last cache invalidation was done by a job with a higher id we
383 * don't have to flush. Since user space will store jobs w/ their
384 * corresponding memory in sequence (first job #0, then job #1, ...),
385 * we don't have to flush for job n-1 if job n has already invalidated
386 * the cache since we know for sure that job n-1's memory was already
387 * written when job n was started.
388 */
389
390 mali_l2_cache_lock(cache);
391
392 if (((s32)id) > ((s32)cache->last_invalidated_id)) {
393 /* Set latest invalidated id to current "point in time" */
394 cache->last_invalidated_id =
395 mali_scheduler_get_new_cache_order();
396 mali_l2_cache_send_command(cache,
397 MALI400_L2_CACHE_REGISTER_COMMAND,
398 MALI400_L2_CACHE_COMMAND_CLEAR_ALL);
399 }
400
401 mali_l2_cache_unlock(cache);
402 }
403
404 void mali_l2_cache_invalidate_all(void)
405 {
406 u32 i;
407 for (i = 0; i < mali_global_num_l2s; i++) {
408 struct mali_l2_cache_core *cache = mali_global_l2s[i];
409 _mali_osk_errcode_t ret;
410
411 MALI_DEBUG_ASSERT_POINTER(cache);
412
413 mali_l2_cache_lock(cache);
414
415 if (MALI_TRUE != cache->power_is_on) {
416 mali_l2_cache_unlock(cache);
417 continue;
418 }
419
420 cache->last_invalidated_id =
421 mali_scheduler_get_new_cache_order();
422
423 ret = mali_l2_cache_send_command(cache,
424 MALI400_L2_CACHE_REGISTER_COMMAND,
425 MALI400_L2_CACHE_COMMAND_CLEAR_ALL);
426 if (_MALI_OSK_ERR_OK != ret) {
427 MALI_PRINT_ERROR(("Failed to invalidate cache\n"));
428 }
429
430 mali_l2_cache_unlock(cache);
431 }
432 }
433
434 void mali_l2_cache_invalidate_all_pages(u32 *pages, u32 num_pages)
435 {
436 u32 i;
437 for (i = 0; i < mali_global_num_l2s; i++) {
438 struct mali_l2_cache_core *cache = mali_global_l2s[i];
439 u32 j;
440
441 MALI_DEBUG_ASSERT_POINTER(cache);
442
443 mali_l2_cache_lock(cache);
444
445 if (MALI_TRUE != cache->power_is_on) {
446 mali_l2_cache_unlock(cache);
447 continue;
448 }
449
450 for (j = 0; j < num_pages; j++) {
451 _mali_osk_errcode_t ret;
452
453 ret = mali_l2_cache_send_command(cache,
454 MALI400_L2_CACHE_REGISTER_CLEAR_PAGE,
455 pages[j]);
456 if (_MALI_OSK_ERR_OK != ret) {
457 MALI_PRINT_ERROR(("Failed to invalidate cache (page)\n"));
458 }
459 }
460
461 mali_l2_cache_unlock(cache);
462 }
463 }
464
465 /* -------- local helper functions below -------- */
466
467 static void mali_l2_cache_reset(struct mali_l2_cache_core *cache)
468 {
469 MALI_DEBUG_ASSERT_POINTER(cache);
470 MALI_DEBUG_ASSERT_LOCK_HELD(cache->lock);
471
472 /* Invalidate cache (just to keep it in a known state at startup) */
473 mali_l2_cache_send_command(cache, MALI400_L2_CACHE_REGISTER_COMMAND,
474 MALI400_L2_CACHE_COMMAND_CLEAR_ALL);
475
476 /* Enable cache */
477 mali_hw_core_register_write(&cache->hw_core,
478 MALI400_L2_CACHE_REGISTER_ENABLE,
479 (u32)MALI400_L2_CACHE_ENABLE_ACCESS |
480 (u32)MALI400_L2_CACHE_ENABLE_READ_ALLOCATE);
481
482 if (MALI400_L2_MAX_READS_NOT_SET != mali_l2_max_reads) {
483 mali_hw_core_register_write(&cache->hw_core,
484 MALI400_L2_CACHE_REGISTER_MAX_READS,
485 (u32)mali_l2_max_reads);
486 }
487
488 /* Restart any performance counters (if enabled) */
489 if (cache->counter_src0 != MALI_HW_CORE_NO_COUNTER) {
490
491 mali_hw_core_register_write(&cache->hw_core,
492 MALI400_L2_CACHE_REGISTER_PERFCNT_SRC0,
493 cache->counter_src0);
494 }
495
496 if (cache->counter_src1 != MALI_HW_CORE_NO_COUNTER) {
497 mali_hw_core_register_write(&cache->hw_core,
498 MALI400_L2_CACHE_REGISTER_PERFCNT_SRC1,
499 cache->counter_src1);
500 }
501 }
502
503 static _mali_osk_errcode_t mali_l2_cache_send_command(
504 struct mali_l2_cache_core *cache, u32 reg, u32 val)
505 {
506 int i = 0;
507 const int loop_count = 100000;
508
509 MALI_DEBUG_ASSERT_POINTER(cache);
510 MALI_DEBUG_ASSERT_LOCK_HELD(cache->lock);
511
512 /*
513 * First, wait for L2 cache command handler to go idle.
514 * (Commands received while processing another command will be ignored)
515 */
516 for (i = 0; i < loop_count; i++) {
517 if (!(mali_hw_core_register_read(&cache->hw_core,
518 MALI400_L2_CACHE_REGISTER_STATUS) &
519 (u32)MALI400_L2_CACHE_STATUS_COMMAND_BUSY)) {
520 break;
521 }
522 }
523
524 if (i == loop_count) {
525 MALI_DEBUG_PRINT(1, ("Mali L2 cache: aborting wait for command interface to go idle\n"));
526 return _MALI_OSK_ERR_FAULT;
527 }
528
529 /* then issue the command */
530 mali_hw_core_register_write(&cache->hw_core, reg, val);
531
532 return _MALI_OSK_ERR_OK;
533 }
kernel source for telekom puls (alcatel/mediatek)