drivers/misc/mediatek/connectivity/conn_soc/common/include/wmt_plat.h

   1 /*
   2 * Copyright (C) 2011-2014 MediaTek Inc.
   3 *
   4 * This program is free software: you can redistribute it and/or modify it under the terms of the
   5 * GNU General Public License version 2 as published by the Free Software Foundation.
   6 *
   7 * This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
   8 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
   9 * See the GNU General Public License for more details.
  10 *
  11 * You should have received a copy of the GNU General Public License along with this program.
  12 * If not, see <http://www.gnu.org/licenses/>.
  13 */
  14
  15 /*! \file
  16     \brief  Declaration of library functions
  17
  18     Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
  19 */
  20
  21
  22
  23 #ifndef _WMT_PLAT_H_
  24 #define _WMT_PLAT_H_
  25 #include "osal_typedef.h"
  26 #include "stp_exp.h"
  27 #include <mach/mtk_wcn_cmb_stub.h>
  28
  29 //#include "mtk_wcn_consys_hw.h"
  30
  31
  32 /*******************************************************************************
  33 *                         C O M P I L E R   F L A G S
  34 ********************************************************************************
  35 */
  36
  37 /*******************************************************************************
  38 *                                 M A C R O S
  39 ********************************************************************************
  40 */
  41
  42
  43 #if 1 /* moved from wmt_exp.h */
  44 #ifndef DFT_TAG
  45 #define DFT_TAG         "[WMT-DFT]"
  46 #endif
  47
  48 #define WMT_PLAT_LOG_LOUD                 4
  49 #define WMT_PLAT_LOG_DBG                  3
  50 #define WMT_PLAT_LOG_INFO                 2
  51 #define WMT_PLAT_LOG_WARN                 1
  52 #define WMT_PLAT_LOG_ERR                  0
  53
  54 extern UINT32 wmtPlatLogLvl;
  55
  56 #define WMT_PLAT_LOUD_FUNC(fmt, arg...)    if(wmtPlatLogLvl >= WMT_PLAT_LOG_LOUD) { printk(KERN_DEBUG DFT_TAG "[L]%s:"  fmt, __FUNCTION__ ,##arg);}
  57 #define WMT_PLAT_INFO_FUNC(fmt, arg...)    if(wmtPlatLogLvl >= WMT_PLAT_LOG_INFO) { printk(KERN_ERR DFT_TAG "[I]%s:"  fmt, __FUNCTION__ ,##arg);}
  58 #define WMT_PLAT_WARN_FUNC(fmt, arg...)    if(wmtPlatLogLvl >= WMT_PLAT_LOG_WARN) { printk(KERN_WARNING DFT_TAG "[W]%s:"  fmt, __FUNCTION__ ,##arg);}
  59 #define WMT_PLAT_ERR_FUNC(fmt, arg...)     if(wmtPlatLogLvl >= WMT_PLAT_LOG_ERR)  { printk(KERN_ERR DFT_TAG "[E]%s(%d):"  fmt, __FUNCTION__ , __LINE__, ##arg);}
  60 #define WMT_PLAT_DBG_FUNC(fmt, arg...)     if(wmtPlatLogLvl >= WMT_PLAT_LOG_DBG)  { printk(KERN_DEBUG DFT_TAG "[D]%s:"  fmt, __FUNCTION__ ,##arg);}
  61
  62 #endif
  63
  64
  65 #define CFG_WMT_PS_SUPPORT 1 /* moved from wmt_exp.h */
  66 #define CFG_WMT_DUMP_INT_STATUS 0
  67 #define CONSYS_ENALBE_SET_JTAG 1
  68 #define CONSYS_WMT_REG_SUSPEND_CB_ENABLE 0
  69
  70 /*******************************************************************************
  71 *                              C O N S T A N T S
  72 ********************************************************************************
  73 */
  74
  75 /*******************************************************************************
  76 *                             D A T A   T Y P E S
  77 ********************************************************************************
  78 */
  79
  80 typedef enum _ENUM_FUNC_STATE_{
  81     FUNC_ON = 0,
  82     FUNC_OFF = 1,
  83     FUNC_RST = 2,
  84     FUNC_STAT = 3,
  85     FUNC_CTRL_MAX,
  86 } ENUM_FUNC_STATE, *P_ENUM_FUNC_STATE;
  87
  88 typedef enum _ENUM_PIN_ID_{
  89     PIN_BGF_EINT = 0,
  90     PIN_I2S_GRP = 1,
  91     PIN_GPS_SYNC = 2,
  92     PIN_GPS_LNA = 3,
  93 #if CFG_WMT_LTE_COEX_HANDLING
  94     PIN_TDM_REQ = 4,
  95 #endif
  96     PIN_ID_MAX
  97 } ENUM_PIN_ID, *P_ENUM_PIN_ID;
  98
  99 typedef enum _ENUM_PIN_STATE_{
 100     PIN_STA_INIT = 0,
 101     PIN_STA_OUT_L = 1,
 102     PIN_STA_OUT_H = 2,
 103     PIN_STA_IN_L = 3,
 104     PIN_STA_MUX = 4,
 105     PIN_STA_EINT_EN = 5,
 106     PIN_STA_EINT_DIS = 6,
 107     PIN_STA_DEINIT = 7,
 108     PIN_STA_SHOW = 8,
 109     PIN_STA_MAX
 110 } ENUM_PIN_STATE, *P_ENUM_PIN_STATE;
 111
 112 typedef enum _CMB_IF_TYPE_{
 113     CMB_IF_UART = 0,
 114     CMB_IF_WIFI_SDIO = 1,
 115     CMB_IF_BGF_SDIO = 2,
 116     CMB_IF_BGWF_SDIO = 3,
 117     CMB_IF_TYPE_MAX
 118 } CMB_IF_TYPE, *P_CMB_IF_TYPE;
 119
 120 typedef INT32 (*fp_set_pin)(ENUM_PIN_STATE);
 121
 122 typedef enum _ENUM_WL_OP_{
 123     WL_OP_GET = 0,
 124     WL_OP_PUT = 1,
 125     WL_OP_MAX
 126 } ENUM_WL_OP, *P_ENUM_WL_OP;
 127
 128 typedef enum _ENUM_PALDO_TYPE_{
 129         BT_PALDO = 0,
 130         WIFI_PALDO = 1,
 131         FM_PALDO = 2,
 132         GPS_PALDO = 3,
 133         PMIC_CHIPID_PALDO = 4,
 134         WIFI_5G_PALDO = 5,
 135         PALDO_TYPE_MAX
 136 }ENUM_PALDO_TYPE,*P_ENUM_PALDO_TYPE;
 137
 138 typedef enum _ENUM_PALDO_OP_{
 139         PALDO_OFF = 0,
 140         PALDO_ON = 1,
 141         PALDO_OP_MAX
 142 }ENUM_PALDO_OP,*P_ENUM_PALDO_OP;
 143
 144 typedef enum _ENUM_HOST_DUMP_STATE_T{
 145         STP_HOST_DUMP_NOT_START = 0,
 146         STP_HOST_DUMP_GET = 1,
 147         STP_HOST_DUMP_GET_DONE = 2,
 148         STP_HOST_DUMP_END = 3,
 149         STP_HOST_DUMP_MAX
 150 }ENUM_HOST_DUMP_STATE,*P_ENUM_HOST_DUMP_STATE_T;
 151
 152 typedef enum _ENUM_FORCE_TRG_ASSERT_T{
 153         STP_FORCE_TRG_ASSERT_EMI = 0,
 154         STP_FORCE_TRG_ASSERT_DEBUG_PIN = 1,
 155         STP_FORCE_TRG_ASSERT_MAX = 2
 156 }ENUM_FORCE_TRG_ASSERT_T,*P_ENUM_FORCE_TRG_ASSERT_T;
 157
 158 typedef enum _ENUM_CHIP_DUMP_STATE_T{
 159         STP_CHIP_DUMP_NOT_START = 0,
 160         STP_CHIP_DUMP_PUT = 1,
 161         STP_CHIP_DUMP_PUT_DONE = 2,
 162         STP_CHIP_DUMP_END = 3,
 163         STP_CHIP_DUMP_MAX
 164 }ENUM_CHIP_DUMP_STATE,*P_ENUM_CHIP_DUMP_STATE_T;
 165
 166 typedef struct _EMI_CTRL_STATE_OFFSET_{
 167         UINT32 emi_apmem_ctrl_state;
 168         UINT32 emi_apmem_ctrl_host_sync_state;
 169         UINT32 emi_apmem_ctrl_host_sync_num;
 170         UINT32 emi_apmem_ctrl_chip_sync_state;
 171         UINT32 emi_apmem_ctrl_chip_sync_num;
 172         UINT32 emi_apmem_ctrl_chip_sync_addr;
 173         UINT32 emi_apmem_ctrl_chip_sync_len;
 174         UINT32 emi_apmem_ctrl_chip_print_buff_start;
 175         UINT32 emi_apmem_ctrl_chip_print_buff_len;
 176         UINT32 emi_apmem_ctrl_chip_print_buff_idx;
 177         UINT32 emi_apmem_ctrl_chip_int_status;
 178         UINT32 emi_apmem_ctrl_chip_paded_dump_end;
 179         UINT32 emi_apmem_ctrl_host_outband_assert_w1;
 180 }EMI_CTRL_STATE_OFFSET, *P_EMI_CTRL_STATE_OFFSET;
 181
 182 typedef struct _BGF_IRQ_BALANCE_{
 183         UINT32 counter;
 184         unsigned long flags;
 185         spinlock_t lock;
 186 }BGF_IRQ_BALANCE,*P_BGF_IRQ_BALANCE;
 187
 188 typedef struct _CONSYS_EMI_ADDR_INFO_{
 189         UINT32 emi_phy_addr;
 190         UINT32 paged_trace_off;
 191         UINT32 paged_dump_off;
 192         UINT32 full_dump_off;
 193         P_EMI_CTRL_STATE_OFFSET p_emi_ctrl_state_offset;
 194 }CONSYS_EMI_ADDR_INFO,*P_CONSYS_EMI_ADDR_INFO;
 195
 196 typedef struct _GPIO_TDM_REQ_INFO_{
 197         UINT32 ant_sel_index;
 198         UINT32 gpio_number;
 199         UINT32 cr_address;
 200 }GPIO_TDM_REQ_INFO,*P_GPIO_TDM_REQ_INFO;
 201
 202 typedef VOID (*irq_cb)(VOID);
 203 typedef INT32 (*device_audio_if_cb) (CMB_STUB_AIF_X aif, MTK_WCN_BOOL share);
 204 typedef VOID (*func_ctrl_cb)(UINT32 on,UINT32 type);
 205 typedef long (*thermal_query_ctrl_cb)(VOID);
 206 typedef INT32 (*deep_idle_ctrl_cb)(UINT32);
 207
 208 /*******************************************************************************
 209 *                    E X T E R N A L   R E F E R E N C E S
 210 ********************************************************************************
 211 */
 212
 213 /*******************************************************************************
 214 *                            P U B L I C   D A T A
 215 ********************************************************************************
 216 */
 217 extern UINT32 gWmtDbgLvl;
 218
 219
 220 /*******************************************************************************
 221 *                           P R I V A T E   D A T A
 222 ********************************************************************************
 223 */
 224
 225 /*******************************************************************************
 226 *                  F U N C T I O N   D E C L A R A T I O N S
 227 ********************************************************************************
 228 */
 229
 230 INT32
 231 wmt_plat_init (UINT32 co_clock_en);
 232
 233 INT32
 234 wmt_plat_deinit (VOID);
 235
 236
 237 INT32
 238 wmt_plat_pwr_ctrl (
 239     ENUM_FUNC_STATE state
 240     );
 241
 242
 243 INT32
 244 wmt_plat_gpio_ctrl (
 245     ENUM_PIN_ID id,
 246     ENUM_PIN_STATE state
 247     );
 248
 249 INT32
 250 wmt_plat_eirq_ctrl (
 251     ENUM_PIN_ID id,
 252     ENUM_PIN_STATE state
 253     );
 254
 255
 256 INT32
 257 wmt_plat_wake_lock_ctrl(
 258     ENUM_WL_OP opId
 259     );
 260
 261
 262 INT32
 263 wmt_plat_audio_ctrl (
 264     CMB_STUB_AIF_X state,
 265     CMB_STUB_AIF_CTRL ctrl
 266     );
 267
 268 VOID wmt_plat_irq_cb_reg (irq_cb bgf_irq_cb);
 269 VOID wmt_plat_aif_cb_reg (device_audio_if_cb aif_ctrl_cb);
 270 VOID wmt_plat_func_ctrl_cb_reg(func_ctrl_cb subsys_func_ctrl);
 271 VOID wmt_plat_thermal_ctrl_cb_reg(thermal_query_ctrl_cb thermal_query_ctrl);
 272 VOID wmt_plat_deep_idle_ctrl_cb_reg(deep_idle_ctrl_cb deep_idle_ctrl);
 273
 274 INT32 wmt_plat_soc_paldo_ctrl(ENUM_PALDO_TYPE ePt,ENUM_PALDO_OP ePo);
 275 UINT8 *wmt_plat_get_emi_virt_add(UINT32 offset);
 276 #if CONSYS_ENALBE_SET_JTAG
 277 UINT32 wmt_plat_jtag_flag_ctrl(UINT32 en);
 278 #endif
 279 #if CONSYS_WMT_REG_SUSPEND_CB_ENABLE
 280 UINT32 wmt_plat_soc_osc_en_ctrl(UINT32 en);
 281 #endif
 282 #if CFG_WMT_DUMP_INT_STATUS
 283 VOID wmt_plat_BGF_irq_dump_status(VOID);
 284 #endif
 285 P_CONSYS_EMI_ADDR_INFO wmt_plat_get_emi_phy_add(VOID);
 286 UINT32 wmt_plat_read_cpupcr(VOID);
 287 UINT32 wmt_plat_read_dmaregs(UINT32);
 288 INT32 wmt_plat_set_host_dump_state(ENUM_HOST_DUMP_STATE state);
 289 UINT32 wmt_plat_force_trigger_assert(ENUM_FORCE_TRG_ASSERT_T type);
 290 INT32 wmt_plat_update_host_sync_num(VOID);
 291 INT32 wmt_plat_get_dump_info(UINT32 offset);
 292 UINT32 wmt_plat_get_soc_chipid(VOID);
 293 #if CFG_WMT_LTE_COEX_HANDLING
 294 INT32 wmt_plat_get_tdm_antsel_index(VOID);
 295 #endif
 296 /*******************************************************************************
 297 *                              F U N C T I O N S
 298 ********************************************************************************
 299 */
 300
 301 #endif /* _WMT_PLAT_H_ */
 302