drivers/misc/mediatek/connectivity/combo/drv_wlan/mt6628/wlan/include/nic/mt5931_reg.h

   1 /*
   2 ** $Id: //Department/DaVinci/BRANCHES/MT662X_593X_WIFI_DRIVER_V2_3/include/nic/mt5931_reg.h#1 $
   3 */
   4
   5 /*! \file   "mt5931_reg.h"
   6     \brief  The common register definition of mt5931
   7
   8     N/A
   9 */
  10
  11
  12
  13 /*
  14 ** $Log: mt5931_reg.h $
  15  *
  16  * 02 25 2011 cp.wu
  17  * [WCXRP00000496] [MT5931][Driver] Apply host-triggered chip reset before initializing firmware download procedures
  18  * apply host-triggered chip reset mechanism before initializing firmware download procedures.
  19  *
  20  * 02 18 2011 terry.wu
  21  * [WCXRP00000412] [MT6620 Wi-Fi][FW/Driver] Dump firmware assert info at android kernel log
  22  * Add WHISR_D2H_SW_ASSERT_INFO_INT to MT5931_reg.
  23  *
  24  * 10 07 2010 cp.wu
  25  * [WCXRP00000083] [MT5931][Driver][FW] Add necessary logic for MT5931 first connection
  26  * add firmware download for MT5931.
  27  *
  28 */
  29
  30 #ifndef _MT5931_REG_H
  31 #define _MT5931_REG_H
  32
  33 /*******************************************************************************
  34 *                         C O M P I L E R   F L A G S
  35 ********************************************************************************
  36 */
  37
  38 /*******************************************************************************
  39 *                    E X T E R N A L   R E F E R E N C E S
  40 ********************************************************************************
  41 */
  42
  43 /*******************************************************************************
  44 *                              C O N S T A N T S
  45 ********************************************************************************
  46 */
  47
  48 /*******************************************************************************
  49 *                             D A T A   T Y P E S
  50 ********************************************************************************
  51 */
  52
  53
  54 /*******************************************************************************
  55 *                            P U B L I C   D A T A
  56 ********************************************************************************
  57 */
  58
  59 /*******************************************************************************
  60 *                           P R I V A T E   D A T A
  61 ********************************************************************************
  62 */
  63
  64 /*******************************************************************************
  65 *                                 M A C R O S
  66 ********************************************************************************
  67 */
  68
  69 /*******************************************************************************
  70 *                   F U N C T I O N   D E C L A R A T I O N S
  71 ********************************************************************************
  72 */
  73
  74 /*******************************************************************************
  75 *                              F U N C T I O N S
  76 ********************************************************************************
  77 */
  78
  79 /* 1 MT5931 MCR Definition */
  80
  81 /* 2 Host Interface */
  82
  83 /* 4 CHIP ID Register */
  84 #define MCR_WCIR                            0x0000
  85
  86 /* 4 HIF Low Power Control  Register */
  87 #define MCR_WHLPCR                          0x0004
  88
  89 /* 4 Control  Status Register */
  90 #define MCR_WSDIOCSR                        0x0008
  91 #define MCR_WSPICSR                         0x0008
  92
  93 /* 4 HIF Control Register */
  94 #define MCR_WHCR                            0x000C
  95
  96 /* 4 HIF Interrupt Status  Register */
  97 #define MCR_WHISR                           0x0010
  98
  99 /* 4 HIF Interrupt Enable  Register */
 100 #define MCR_WHIER                           0x0014
 101
 102 /* 4 Abnormal Status Register */
 103 #define MCR_WASR                            0x0018
 104
 105 /* 4 WLAN Software Interrupt Control Register */
 106 #define MCR_WSICR                           0x001C
 107
 108 /* 4 WLAN TX Status Register */
 109 #define MCR_WTSR0                           0x0020
 110
 111 /* 4 WLAN TX Status Register */
 112 #define MCR_WTSR1                           0x0024
 113
 114 /* 4 WLAN TX Data Register 0 */
 115 #define MCR_WTDR0                           0x0028
 116
 117 /* 4 WLAN TX Data Register 1 */
 118 #define MCR_WTDR1                           0x002C
 119
 120 /* 4 WLAN RX Data Register 0 */
 121 #define MCR_WRDR0                           0x0030
 122
 123 /* 4 WLAN RX Data Register 1 */
 124 #define MCR_WRDR1                           0x0034
 125
 126 /* 4 Host to Device Send Mailbox 0 Register */
 127 #define MCR_H2DSM0R                         0x0038
 128
 129 /* 4 Host to Device Send Mailbox 1 Register */
 130 #define MCR_H2DSM1R                         0x003c
 131
 132 /* 4 Device to Host Receive Mailbox 0 Register */
 133 #define MCR_D2HRM0R                         0x0040
 134
 135 /* 4 Device to Host Receive Mailbox 1 Register */
 136 #define MCR_D2HRM1R                         0x0044
 137
 138 /* 4 Device to Host Receive Mailbox 2 Register */
 139 #define MCR_D2HRM2R                         0x0048
 140
 141 /* 4 WLAN RX Packet Length Register */
 142 #define MCR_WRPLR                           0x0050
 143
 144 /* 4 EHPI Transaction Count Register */
 145 #define MCR_EHTCR                           0x0054
 146
 147 /* 4 Firmware Download Data Register */
 148 #define MCR_FWDLDR                          0x0080
 149
 150 /* 4 Firmware Download Destination Starting Address Register */
 151 #define MCR_FWDLDSAR                        0x0084
 152
 153 /* 4 Firmware Download Status Register */
 154 #define MCR_FWDLSR                          0x0088
 155
 156 /* 4 WLAN MCU Control & Status Register */
 157 #define MCR_WMCSR                           0x008c
 158
 159 /* 4 WLAN Firmware Download Configuration */
 160 #define MCR_FWCFG                           0x0090
 161
 162
 163 /* #if CFG_SDIO_INTR_ENHANCE */
 164 typedef struct _ENHANCE_MODE_DATA_STRUCT_T {
 165         UINT_32 u4WHISR;
 166         union {
 167                 struct {
 168                         UINT_8 ucTQ0Cnt;
 169                         UINT_8 ucTQ1Cnt;
 170                         UINT_8 ucTQ2Cnt;
 171                         UINT_8 ucTQ3Cnt;
 172                         UINT_8 ucTQ4Cnt;
 173                         UINT_8 ucTQ5Cnt;
 174                         UINT_16 u2Rsrv;
 175                 } u;
 176                 UINT_32 au4WTSR[2];
 177         } rTxInfo;
 178         union {
 179                 struct {
 180                         UINT_16 u2NumValidRx0Len;
 181                         UINT_16 u2NumValidRx1Len;
 182                         UINT_16 au2Rx0Len[16];
 183                         UINT_16 au2Rx1Len[16];
 184                 } u;
 185                 UINT_32 au4RxStatusRaw[17];
 186         } rRxInfo;
 187         UINT_32 u4RcvMailbox0;
 188         UINT_32 u4RcvMailbox1;
 189 } ENHANCE_MODE_DATA_STRUCT_T, *P_ENHANCE_MODE_DATA_STRUCT_T;
 190 /* #endif /* ENHANCE_MODE_DATA_STRUCT_T */ */
 191
 192
 193 /* 2 Definition in each register */
 194 /* 3 WCIR 0x0000 */
 195 #define WCIR_WLAN_READY                  BIT(21)
 196 #define WCIR_POR_INDICATOR               BIT(20)
 197 #define WCIR_REVISION_ID                 BITS(16, 19)
 198 #define WCIR_CHIP_ID                     BITS(0, 15)
 199
 200 #define MTK_CHIP_REV                     0x00005931
 201 #define MTK_CHIP_MP_REVERSION_ID         0x0
 202
 203 /* 3 WHLPCR 0x0004 */
 204 #define WHLPCR_FW_OWN_REQ_CLR            BIT(9)
 205 #define WHLPCR_FW_OWN_REQ_SET            BIT(8)
 206 #define WHLPCR_IS_DRIVER_OWN             BIT(8)
 207 #define WHLPCR_INT_EN_CLR                BIT(1)
 208 #define WHLPCR_INT_EN_SET                BIT(0)
 209
 210 /* 3 WSDIOCSR 0x0008 */
 211 #define WSDIOCSR_SDIO_RE_INIT_EN         BIT(0)
 212
 213 /* 3 WSPICSR 0x0008 */
 214 #define WCSR_SPI_MODE_SEL                BITS(3, 4)
 215 #define WCSR_SPI_ENDIAN_BIG              BIT(2)
 216 #define WCSR_SPI_INT_OUT_MODE            BIT(1)
 217 #define WCSR_SPI_DATA_OUT_MODE           BIT(0)
 218
 219 /* 3 WHCR 0x000C */
 220 #define WHCR_RX_ENHANCE_MODE_EN         BIT(16)
 221 #define WHCR_MAX_HIF_RX_LEN_NUM         BITS(4, 7)
 222 #define WHCR_W_MAILBOX_RD_CLR_EN        BIT(2)
 223 #define WHCR_W_INT_CLR_CTRL             BIT(1)
 224 #define WHCR_MCU_DBG_EN                 BIT(0)
 225 #define WHCR_OFFSET_MAX_HIF_RX_LEN_NUM  4
 226
 227 /* 3 WHISR 0x0010 */
 228 #define WHISR_D2H_SW_INT                BITS(8, 31)
 229 #define WHISR_D2H_SW_ASSERT_INFO_INT    BIT(31)
 230 #define WHISR_FW_OWN_BACK_INT           BIT(4)
 231 #define WHISR_ABNORMAL_INT              BIT(3)
 232 #define WHISR_RX1_DONE_INT              BIT(2)
 233 #define WHISR_RX0_DONE_INT              BIT(1)
 234 #define WHISR_TX_DONE_INT               BIT(0)
 235
 236
 237 /* 3 WHIER 0x0014 */
 238 #define WHIER_D2H_SW_INT                BITS(8, 31)
 239 #define WHIER_FW_OWN_BACK_INT_EN        BIT(4)
 240 #define WHIER_ABNORMAL_INT_EN           BIT(3)
 241 #define WHIER_RX1_DONE_INT_EN           BIT(2)
 242 #define WHIER_RX0_DONE_INT_EN           BIT(1)
 243 #define WHIER_TX_DONE_INT_EN            BIT(0)
 244 #define WHIER_DEFAULT                   (WHIER_RX0_DONE_INT_EN    | \
 245                                          WHIER_RX1_DONE_INT_EN    | \
 246                                          WHIER_TX_DONE_INT_EN     | \
 247                                          WHIER_ABNORMAL_INT_EN    | \
 248                                          WHIER_D2H_SW_INT           \
 249                                          )
 250
 251
 252 /* 3 WASR 0x0018 */
 253 #define WASR_FW_OWN_INVALID_ACCESS      BIT(4)
 254 #define WASR_RX1_UNDER_FLOW             BIT(3)
 255 #define WASR_RX0_UNDER_FLOW             BIT(2)
 256 #define WASR_TX1_OVER_FLOW              BIT(1)
 257 #define WASR_TX0_OVER_FLOW              BIT(0)
 258
 259
 260 /* 3 WSICR 0x001C */
 261 #define WSICR_H2D_SW_INT_SET            BITS(16, 31)
 262
 263
 264 /* 3 WRPLR 0x0050 */
 265 #define WRPLR_RX1_PACKET_LENGTH         BITS(16, 31)
 266 #define WRPLR_RX0_PACKET_LENGTH         BITS(0, 15)
 267
 268
 269 /* 3 FWDLSR 0x0088 */
 270 #define FWDLSR_FWDL_RDY                 BIT(8)
 271 #define FWDLSR_FWDL_MODE                BIT(0)
 272
 273
 274 /* 3 WMCSR 0x008c */
 275 #define WMCSR_CHIP_RST                  BIT(15) /* write */
 276 #define WMCSR_DL_OK                     BIT(15) /* read */
 277 #define WMCSR_DL_FAIL                   BIT(14)
 278 #define WMCSR_PLLRDY                    BIT(13)
 279 #define WMCSR_WF_ON                     BIT(12)
 280 #define WMCSR_INI_RDY                   BIT(11)
 281 #define WMCSR_WF_EN                     BIT(6)
 282 #define WMCSR_SW_EN                     BIT(5)
 283 #define WMCSR_SPLLEN                    BIT(4)
 284 #define WMCSR_SPWREN                    BIT(3)
 285 #define WMCSR_HSTOPIL                   BIT(2)
 286 #define WMCSR_FWDLRST                   BIT(1)
 287 #define WMCSR_FWDLEN                    BIT(0)
 288
 289
 290 /* 3 FWCFG 0x0090 */
 291 #define FWCFG_KSEL                      BITS(14, 15)
 292 #define FWCFG_FLEN                      BITS(0, 13)
 293
 294
 295 #endif                          /* _MT5931_REG_H */