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[SCSI] fcoe: fix fcoe module ref counting
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / mfd / wm8350-core.c
1 /*
2 * wm8350-core.c -- Device access for Wolfson WM8350
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Liam Girdwood, Mark Brown
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/bug.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/interrupt.h>
23 #include <linux/workqueue.h>
24
25 #include <linux/mfd/wm8350/core.h>
26 #include <linux/mfd/wm8350/audio.h>
27 #include <linux/mfd/wm8350/comparator.h>
28 #include <linux/mfd/wm8350/gpio.h>
29 #include <linux/mfd/wm8350/pmic.h>
30 #include <linux/mfd/wm8350/rtc.h>
31 #include <linux/mfd/wm8350/supply.h>
32 #include <linux/mfd/wm8350/wdt.h>
33
34 #define WM8350_UNLOCK_KEY 0x0013
35 #define WM8350_LOCK_KEY 0x0000
36
37 #define WM8350_CLOCK_CONTROL_1 0x28
38 #define WM8350_AIF_TEST 0x74
39
40 /* debug */
41 #define WM8350_BUS_DEBUG 0
42 #if WM8350_BUS_DEBUG
43 #define dump(regs, src) do { \
44 int i_; \
45 u16 *src_ = src; \
46 printk(KERN_DEBUG); \
47 for (i_ = 0; i_ < regs; i_++) \
48 printk(" 0x%4.4x", *src_++); \
49 printk("\n"); \
50 } while (0);
51 #else
52 #define dump(bytes, src)
53 #endif
54
55 #define WM8350_LOCK_DEBUG 0
56 #if WM8350_LOCK_DEBUG
57 #define ldbg(format, arg...) printk(format, ## arg)
58 #else
59 #define ldbg(format, arg...)
60 #endif
61
62 /*
63 * WM8350 Device IO
64 */
65 static DEFINE_MUTEX(io_mutex);
66 static DEFINE_MUTEX(reg_lock_mutex);
67
68 /* Perform a physical read from the device.
69 */
70 static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
71 u16 *dest)
72 {
73 int i, ret;
74 int bytes = num_regs * 2;
75
76 dev_dbg(wm8350->dev, "volatile read\n");
77 ret = wm8350->read_dev(wm8350, reg, bytes, (char *)dest);
78
79 for (i = reg; i < reg + num_regs; i++) {
80 /* Cache is CPU endian */
81 dest[i - reg] = be16_to_cpu(dest[i - reg]);
82
83 /* Mask out non-readable bits */
84 dest[i - reg] &= wm8350_reg_io_map[i].readable;
85 }
86
87 dump(num_regs, dest);
88
89 return ret;
90 }
91
92 static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
93 {
94 int i;
95 int end = reg + num_regs;
96 int ret = 0;
97 int bytes = num_regs * 2;
98
99 if (wm8350->read_dev == NULL)
100 return -ENODEV;
101
102 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
103 dev_err(wm8350->dev, "invalid reg %x\n",
104 reg + num_regs - 1);
105 return -EINVAL;
106 }
107
108 dev_dbg(wm8350->dev,
109 "%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
110
111 #if WM8350_BUS_DEBUG
112 /* we can _safely_ read any register, but warn if read not supported */
113 for (i = reg; i < end; i++) {
114 if (!wm8350_reg_io_map[i].readable)
115 dev_warn(wm8350->dev,
116 "reg R%d is not readable\n", i);
117 }
118 #endif
119
120 /* if any volatile registers are required, then read back all */
121 for (i = reg; i < end; i++)
122 if (wm8350_reg_io_map[i].vol)
123 return wm8350_phys_read(wm8350, reg, num_regs, dest);
124
125 /* no volatiles, then cache is good */
126 dev_dbg(wm8350->dev, "cache read\n");
127 memcpy(dest, &wm8350->reg_cache[reg], bytes);
128 dump(num_regs, dest);
129 return ret;
130 }
131
132 static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
133 {
134 if (reg == WM8350_SECURITY ||
135 wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
136 return 0;
137
138 if ((reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
139 reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
140 (reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
141 reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
142 return 1;
143 return 0;
144 }
145
146 static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
147 {
148 int i;
149 int end = reg + num_regs;
150 int bytes = num_regs * 2;
151
152 if (wm8350->write_dev == NULL)
153 return -ENODEV;
154
155 if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
156 dev_err(wm8350->dev, "invalid reg %x\n",
157 reg + num_regs - 1);
158 return -EINVAL;
159 }
160
161 /* it's generally not a good idea to write to RO or locked registers */
162 for (i = reg; i < end; i++) {
163 if (!wm8350_reg_io_map[i].writable) {
164 dev_err(wm8350->dev,
165 "attempted write to read only reg R%d\n", i);
166 return -EINVAL;
167 }
168
169 if (is_reg_locked(wm8350, i)) {
170 dev_err(wm8350->dev,
171 "attempted write to locked reg R%d\n", i);
172 return -EINVAL;
173 }
174
175 src[i - reg] &= wm8350_reg_io_map[i].writable;
176
177 wm8350->reg_cache[i] =
178 (wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
179 | src[i - reg];
180
181 src[i - reg] = cpu_to_be16(src[i - reg]);
182 }
183
184 /* Actually write it out */
185 return wm8350->write_dev(wm8350, reg, bytes, (char *)src);
186 }
187
188 /*
189 * Safe read, modify, write methods
190 */
191 int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
192 {
193 u16 data;
194 int err;
195
196 mutex_lock(&io_mutex);
197 err = wm8350_read(wm8350, reg, 1, &data);
198 if (err) {
199 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
200 goto out;
201 }
202
203 data &= ~mask;
204 err = wm8350_write(wm8350, reg, 1, &data);
205 if (err)
206 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
207 out:
208 mutex_unlock(&io_mutex);
209 return err;
210 }
211 EXPORT_SYMBOL_GPL(wm8350_clear_bits);
212
213 int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
214 {
215 u16 data;
216 int err;
217
218 mutex_lock(&io_mutex);
219 err = wm8350_read(wm8350, reg, 1, &data);
220 if (err) {
221 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
222 goto out;
223 }
224
225 data |= mask;
226 err = wm8350_write(wm8350, reg, 1, &data);
227 if (err)
228 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
229 out:
230 mutex_unlock(&io_mutex);
231 return err;
232 }
233 EXPORT_SYMBOL_GPL(wm8350_set_bits);
234
235 u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
236 {
237 u16 data;
238 int err;
239
240 mutex_lock(&io_mutex);
241 err = wm8350_read(wm8350, reg, 1, &data);
242 if (err)
243 dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
244
245 mutex_unlock(&io_mutex);
246 return data;
247 }
248 EXPORT_SYMBOL_GPL(wm8350_reg_read);
249
250 int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
251 {
252 int ret;
253 u16 data = val;
254
255 mutex_lock(&io_mutex);
256 ret = wm8350_write(wm8350, reg, 1, &data);
257 if (ret)
258 dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
259 mutex_unlock(&io_mutex);
260 return ret;
261 }
262 EXPORT_SYMBOL_GPL(wm8350_reg_write);
263
264 int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
265 u16 *dest)
266 {
267 int err = 0;
268
269 mutex_lock(&io_mutex);
270 err = wm8350_read(wm8350, start_reg, regs, dest);
271 if (err)
272 dev_err(wm8350->dev, "block read starting from R%d failed\n",
273 start_reg);
274 mutex_unlock(&io_mutex);
275 return err;
276 }
277 EXPORT_SYMBOL_GPL(wm8350_block_read);
278
279 int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
280 u16 *src)
281 {
282 int ret = 0;
283
284 mutex_lock(&io_mutex);
285 ret = wm8350_write(wm8350, start_reg, regs, src);
286 if (ret)
287 dev_err(wm8350->dev, "block write starting at R%d failed\n",
288 start_reg);
289 mutex_unlock(&io_mutex);
290 return ret;
291 }
292 EXPORT_SYMBOL_GPL(wm8350_block_write);
293
294 /**
295 * wm8350_reg_lock()
296 *
297 * The WM8350 has a hardware lock which can be used to prevent writes to
298 * some registers (generally those which can cause particularly serious
299 * problems if misused). This function enables that lock.
300 */
301 int wm8350_reg_lock(struct wm8350 *wm8350)
302 {
303 u16 key = WM8350_LOCK_KEY;
304 int ret;
305
306 ldbg(__func__);
307 mutex_lock(&io_mutex);
308 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
309 if (ret)
310 dev_err(wm8350->dev, "lock failed\n");
311 mutex_unlock(&io_mutex);
312 return ret;
313 }
314 EXPORT_SYMBOL_GPL(wm8350_reg_lock);
315
316 /**
317 * wm8350_reg_unlock()
318 *
319 * The WM8350 has a hardware lock which can be used to prevent writes to
320 * some registers (generally those which can cause particularly serious
321 * problems if misused). This function disables that lock so updates
322 * can be performed. For maximum safety this should be done only when
323 * required.
324 */
325 int wm8350_reg_unlock(struct wm8350 *wm8350)
326 {
327 u16 key = WM8350_UNLOCK_KEY;
328 int ret;
329
330 ldbg(__func__);
331 mutex_lock(&io_mutex);
332 ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
333 if (ret)
334 dev_err(wm8350->dev, "unlock failed\n");
335 mutex_unlock(&io_mutex);
336 return ret;
337 }
338 EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
339
340 int wm8350_read_auxadc(struct wm8350 *wm8350, int channel, int scale, int vref)
341 {
342 u16 reg, result = 0;
343
344 if (channel < WM8350_AUXADC_AUX1 || channel > WM8350_AUXADC_TEMP)
345 return -EINVAL;
346 if (channel >= WM8350_AUXADC_USB && channel <= WM8350_AUXADC_TEMP
347 && (scale != 0 || vref != 0))
348 return -EINVAL;
349
350 mutex_lock(&wm8350->auxadc_mutex);
351
352 /* Turn on the ADC */
353 reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
354 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5, reg | WM8350_AUXADC_ENA);
355
356 if (scale || vref) {
357 reg = scale << 13;
358 reg |= vref << 12;
359 wm8350_reg_write(wm8350, WM8350_AUX1_READBACK + channel, reg);
360 }
361
362 reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
363 reg |= 1 << channel | WM8350_AUXADC_POLL;
364 wm8350_reg_write(wm8350, WM8350_DIGITISER_CONTROL_1, reg);
365
366 /* We ignore the result of the completion and just check for a
367 * conversion result, allowing us to soldier on if the IRQ
368 * infrastructure is not set up for the chip. */
369 wait_for_completion_timeout(&wm8350->auxadc_done, msecs_to_jiffies(5));
370
371 reg = wm8350_reg_read(wm8350, WM8350_DIGITISER_CONTROL_1);
372 if (reg & WM8350_AUXADC_POLL)
373 dev_err(wm8350->dev, "adc chn %d read timeout\n", channel);
374 else
375 result = wm8350_reg_read(wm8350,
376 WM8350_AUX1_READBACK + channel);
377
378 /* Turn off the ADC */
379 reg = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_5);
380 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_5,
381 reg & ~WM8350_AUXADC_ENA);
382
383 mutex_unlock(&wm8350->auxadc_mutex);
384
385 return result & WM8350_AUXADC_DATA1_MASK;
386 }
387 EXPORT_SYMBOL_GPL(wm8350_read_auxadc);
388
389 static irqreturn_t wm8350_auxadc_irq(int irq, void *irq_data)
390 {
391 struct wm8350 *wm8350 = irq_data;
392
393 complete(&wm8350->auxadc_done);
394
395 return IRQ_HANDLED;
396 }
397
398 /*
399 * Cache is always host endian.
400 */
401 static int wm8350_create_cache(struct wm8350 *wm8350, int type, int mode)
402 {
403 int i, ret = 0;
404 u16 value;
405 const u16 *reg_map;
406
407 switch (type) {
408 case 0:
409 switch (mode) {
410 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
411 case 0:
412 reg_map = wm8350_mode0_defaults;
413 break;
414 #endif
415 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
416 case 1:
417 reg_map = wm8350_mode1_defaults;
418 break;
419 #endif
420 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
421 case 2:
422 reg_map = wm8350_mode2_defaults;
423 break;
424 #endif
425 #ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
426 case 3:
427 reg_map = wm8350_mode3_defaults;
428 break;
429 #endif
430 default:
431 dev_err(wm8350->dev,
432 "WM8350 configuration mode %d not supported\n",
433 mode);
434 return -EINVAL;
435 }
436 break;
437
438 case 1:
439 switch (mode) {
440 #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_0
441 case 0:
442 reg_map = wm8351_mode0_defaults;
443 break;
444 #endif
445 #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_1
446 case 1:
447 reg_map = wm8351_mode1_defaults;
448 break;
449 #endif
450 #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_2
451 case 2:
452 reg_map = wm8351_mode2_defaults;
453 break;
454 #endif
455 #ifdef CONFIG_MFD_WM8351_CONFIG_MODE_3
456 case 3:
457 reg_map = wm8351_mode3_defaults;
458 break;
459 #endif
460 default:
461 dev_err(wm8350->dev,
462 "WM8351 configuration mode %d not supported\n",
463 mode);
464 return -EINVAL;
465 }
466 break;
467
468 case 2:
469 switch (mode) {
470 #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_0
471 case 0:
472 reg_map = wm8352_mode0_defaults;
473 break;
474 #endif
475 #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_1
476 case 1:
477 reg_map = wm8352_mode1_defaults;
478 break;
479 #endif
480 #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_2
481 case 2:
482 reg_map = wm8352_mode2_defaults;
483 break;
484 #endif
485 #ifdef CONFIG_MFD_WM8352_CONFIG_MODE_3
486 case 3:
487 reg_map = wm8352_mode3_defaults;
488 break;
489 #endif
490 default:
491 dev_err(wm8350->dev,
492 "WM8352 configuration mode %d not supported\n",
493 mode);
494 return -EINVAL;
495 }
496 break;
497
498 default:
499 dev_err(wm8350->dev,
500 "WM835x configuration mode %d not supported\n",
501 mode);
502 return -EINVAL;
503 }
504
505 wm8350->reg_cache =
506 kmalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
507 if (wm8350->reg_cache == NULL)
508 return -ENOMEM;
509
510 /* Read the initial cache state back from the device - this is
511 * a PMIC so the device many not be in a virgin state and we
512 * can't rely on the silicon values.
513 */
514 ret = wm8350->read_dev(wm8350, 0,
515 sizeof(u16) * (WM8350_MAX_REGISTER + 1),
516 wm8350->reg_cache);
517 if (ret < 0) {
518 dev_err(wm8350->dev,
519 "failed to read initial cache values\n");
520 goto out;
521 }
522
523 /* Mask out uncacheable/unreadable bits and the audio. */
524 for (i = 0; i < WM8350_MAX_REGISTER; i++) {
525 if (wm8350_reg_io_map[i].readable &&
526 (i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
527 value = be16_to_cpu(wm8350->reg_cache[i]);
528 value &= wm8350_reg_io_map[i].readable;
529 wm8350->reg_cache[i] = value;
530 } else
531 wm8350->reg_cache[i] = reg_map[i];
532 }
533
534 out:
535 return ret;
536 }
537
538 /*
539 * Register a client device. This is non-fatal since there is no need to
540 * fail the entire device init due to a single platform device failing.
541 */
542 static void wm8350_client_dev_register(struct wm8350 *wm8350,
543 const char *name,
544 struct platform_device **pdev)
545 {
546 int ret;
547
548 *pdev = platform_device_alloc(name, -1);
549 if (*pdev == NULL) {
550 dev_err(wm8350->dev, "Failed to allocate %s\n", name);
551 return;
552 }
553
554 (*pdev)->dev.parent = wm8350->dev;
555 platform_set_drvdata(*pdev, wm8350);
556 ret = platform_device_add(*pdev);
557 if (ret != 0) {
558 dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
559 platform_device_put(*pdev);
560 *pdev = NULL;
561 }
562 }
563
564 int wm8350_device_init(struct wm8350 *wm8350, int irq,
565 struct wm8350_platform_data *pdata)
566 {
567 int ret;
568 u16 id1, id2, mask_rev;
569 u16 cust_id, mode, chip_rev;
570
571 /* get WM8350 revision and config mode */
572 ret = wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1);
573 if (ret != 0) {
574 dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
575 goto err;
576 }
577
578 ret = wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2);
579 if (ret != 0) {
580 dev_err(wm8350->dev, "Failed to read ID: %d\n", ret);
581 goto err;
582 }
583
584 ret = wm8350->read_dev(wm8350, WM8350_REVISION, sizeof(mask_rev),
585 &mask_rev);
586 if (ret != 0) {
587 dev_err(wm8350->dev, "Failed to read revision: %d\n", ret);
588 goto err;
589 }
590
591 id1 = be16_to_cpu(id1);
592 id2 = be16_to_cpu(id2);
593 mask_rev = be16_to_cpu(mask_rev);
594
595 if (id1 != 0x6143) {
596 dev_err(wm8350->dev,
597 "Device with ID %x is not a WM8350\n", id1);
598 ret = -ENODEV;
599 goto err;
600 }
601
602 mode = id2 & WM8350_CONF_STS_MASK >> 10;
603 cust_id = id2 & WM8350_CUST_ID_MASK;
604 chip_rev = (id2 & WM8350_CHIP_REV_MASK) >> 12;
605 dev_info(wm8350->dev,
606 "CONF_STS %d, CUST_ID %d, MASK_REV %d, CHIP_REV %d\n",
607 mode, cust_id, mask_rev, chip_rev);
608
609 if (cust_id != 0) {
610 dev_err(wm8350->dev, "Unsupported CUST_ID\n");
611 ret = -ENODEV;
612 goto err;
613 }
614
615 switch (mask_rev) {
616 case 0:
617 wm8350->pmic.max_dcdc = WM8350_DCDC_6;
618 wm8350->pmic.max_isink = WM8350_ISINK_B;
619
620 switch (chip_rev) {
621 case WM8350_REV_E:
622 dev_info(wm8350->dev, "WM8350 Rev E\n");
623 break;
624 case WM8350_REV_F:
625 dev_info(wm8350->dev, "WM8350 Rev F\n");
626 break;
627 case WM8350_REV_G:
628 dev_info(wm8350->dev, "WM8350 Rev G\n");
629 wm8350->power.rev_g_coeff = 1;
630 break;
631 case WM8350_REV_H:
632 dev_info(wm8350->dev, "WM8350 Rev H\n");
633 wm8350->power.rev_g_coeff = 1;
634 break;
635 default:
636 /* For safety we refuse to run on unknown hardware */
637 dev_err(wm8350->dev, "Unknown WM8350 CHIP_REV\n");
638 ret = -ENODEV;
639 goto err;
640 }
641 break;
642
643 case 1:
644 wm8350->pmic.max_dcdc = WM8350_DCDC_4;
645 wm8350->pmic.max_isink = WM8350_ISINK_A;
646
647 switch (chip_rev) {
648 case 0:
649 dev_info(wm8350->dev, "WM8351 Rev A\n");
650 wm8350->power.rev_g_coeff = 1;
651 break;
652
653 case 1:
654 dev_info(wm8350->dev, "WM8351 Rev B\n");
655 wm8350->power.rev_g_coeff = 1;
656 break;
657
658 default:
659 dev_err(wm8350->dev, "Unknown WM8351 CHIP_REV\n");
660 ret = -ENODEV;
661 goto err;
662 }
663 break;
664
665 case 2:
666 wm8350->pmic.max_dcdc = WM8350_DCDC_6;
667 wm8350->pmic.max_isink = WM8350_ISINK_B;
668
669 switch (chip_rev) {
670 case 0:
671 dev_info(wm8350->dev, "WM8352 Rev A\n");
672 wm8350->power.rev_g_coeff = 1;
673 break;
674
675 default:
676 dev_err(wm8350->dev, "Unknown WM8352 CHIP_REV\n");
677 ret = -ENODEV;
678 goto err;
679 }
680 break;
681
682 default:
683 dev_err(wm8350->dev, "Unknown MASK_REV\n");
684 ret = -ENODEV;
685 goto err;
686 }
687
688 ret = wm8350_create_cache(wm8350, mask_rev, mode);
689 if (ret < 0) {
690 dev_err(wm8350->dev, "Failed to create register cache\n");
691 return ret;
692 }
693
694 mutex_init(&wm8350->auxadc_mutex);
695 init_completion(&wm8350->auxadc_done);
696
697 ret = wm8350_irq_init(wm8350, irq, pdata);
698 if (ret < 0)
699 goto err;
700
701 if (wm8350->irq_base) {
702 ret = request_threaded_irq(wm8350->irq_base +
703 WM8350_IRQ_AUXADC_DATARDY,
704 NULL, wm8350_auxadc_irq, 0,
705 "auxadc", wm8350);
706 if (ret < 0)
707 dev_warn(wm8350->dev,
708 "Failed to request AUXADC IRQ: %d\n", ret);
709 }
710
711 if (pdata && pdata->init) {
712 ret = pdata->init(wm8350);
713 if (ret != 0) {
714 dev_err(wm8350->dev, "Platform init() failed: %d\n",
715 ret);
716 goto err_irq;
717 }
718 }
719
720 wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
721
722 wm8350_client_dev_register(wm8350, "wm8350-codec",
723 &(wm8350->codec.pdev));
724 wm8350_client_dev_register(wm8350, "wm8350-gpio",
725 &(wm8350->gpio.pdev));
726 wm8350_client_dev_register(wm8350, "wm8350-hwmon",
727 &(wm8350->hwmon.pdev));
728 wm8350_client_dev_register(wm8350, "wm8350-power",
729 &(wm8350->power.pdev));
730 wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
731 wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
732
733 return 0;
734
735 err_irq:
736 wm8350_irq_exit(wm8350);
737 err:
738 kfree(wm8350->reg_cache);
739 return ret;
740 }
741 EXPORT_SYMBOL_GPL(wm8350_device_init);
742
743 void wm8350_device_exit(struct wm8350 *wm8350)
744 {
745 int i;
746
747 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.led); i++)
748 platform_device_unregister(wm8350->pmic.led[i].pdev);
749
750 for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++)
751 platform_device_unregister(wm8350->pmic.pdev[i]);
752
753 platform_device_unregister(wm8350->wdt.pdev);
754 platform_device_unregister(wm8350->rtc.pdev);
755 platform_device_unregister(wm8350->power.pdev);
756 platform_device_unregister(wm8350->hwmon.pdev);
757 platform_device_unregister(wm8350->gpio.pdev);
758 platform_device_unregister(wm8350->codec.pdev);
759
760 if (wm8350->irq_base)
761 free_irq(wm8350->irq_base + WM8350_IRQ_AUXADC_DATARDY, wm8350);
762
763 wm8350_irq_exit(wm8350);
764
765 kfree(wm8350->reg_cache);
766 }
767 EXPORT_SYMBOL_GPL(wm8350_device_exit);
768
769 MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver");
770 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)