3 * Support for the mpeg transport stream transfers
4 * PCI function #2 of the cx2388x.
6 * (c) 2004 Jelle Foks <jelle@foks.8m.com>
7 * (c) 2004 Chris Pascoe <c.pascoe@itee.uq.edu.au>
8 * (c) 2004 Gerd Knorr <kraxel@bytesex.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/device.h>
29 #include <linux/interrupt.h>
30 #include <asm/delay.h>
34 /* ------------------------------------------------------------------ */
36 MODULE_DESCRIPTION("mpeg driver for cx2388x based TV cards");
37 MODULE_AUTHOR("Jelle Foks <jelle@foks.8m.com>");
38 MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
39 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
40 MODULE_LICENSE("GPL");
42 static unsigned int debug
= 0;
43 module_param(debug
,int,0644);
44 MODULE_PARM_DESC(debug
,"enable debug messages [mpeg]");
46 #define dprintk(level,fmt, arg...) if (debug >= level) \
47 printk(KERN_DEBUG "%s/2: " fmt, dev->core->name , ## arg)
49 /* ------------------------------------------------------------------ */
51 static int cx8802_start_dma(struct cx8802_dev
*dev
,
52 struct cx88_dmaqueue
*q
,
53 struct cx88_buffer
*buf
)
55 struct cx88_core
*core
= dev
->core
;
57 dprintk(0, "cx8802_start_dma w: %d, h: %d, f: %d\n", dev
->width
, dev
->height
, buf
->vb
.field
);
59 /* setup fifo + format */
60 cx88_sram_channel_setup(core
, &cx88_sram_channels
[SRAM_CH28
],
61 dev
->ts_packet_size
, buf
->risc
.dma
);
63 /* write TS length to chip */
64 cx_write(MO_TS_LNGTH
, buf
->vb
.width
);
66 /* FIXME: this needs a review.
67 * also: move to cx88-blackbird + cx88-dvb source files? */
69 if (cx88_boards
[core
->board
].dvb
) {
70 /* negedge driven & software reset */
71 cx_write(TS_GEN_CNTRL
, 0x0040 | dev
->ts_gen_cntrl
);
73 cx_write(MO_PINMUX_IO
, 0x00);
74 cx_write(TS_HW_SOP_CNTRL
,0x47<<16|188<<4|0x01);
75 switch (core
->board
) {
76 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q
:
77 case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T
:
78 case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD
:
79 cx_write(TS_SOP_STAT
, 1<<13);
81 case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1
:
82 case CX88_BOARD_HAUPPAUGE_NOVASE2_S1
:
83 cx_write(MO_PINMUX_IO
, 0x88); /* Enable MPEG parallel IO and video signal pins */
87 cx_write(TS_SOP_STAT
, 0x00);
90 cx_write(TS_GEN_CNTRL
, dev
->ts_gen_cntrl
);
94 if (cx88_boards
[core
->board
].blackbird
) {
95 cx_write(MO_PINMUX_IO
, 0x88); /* enable MPEG parallel IO */
97 cx_write(TS_GEN_CNTRL
, 0x46); /* punctured clock TS & posedge driven & software reset */
100 cx_write(TS_HW_SOP_CNTRL
, 0x408); /* mpeg start byte */
101 cx_write(TS_VALERR_CNTRL
, 0x2000);
103 cx_write(TS_GEN_CNTRL
, 0x06); /* punctured clock TS & posedge driven */
108 cx_write(MO_TS_GPCNTRL
, GP_COUNT_CONTROL_RESET
);
112 dprintk( 0, "setting the interrupt mask\n" );
113 cx_set(MO_PCI_INTMSK
, core
->pci_irqmask
| 0x04);
114 cx_set(MO_TS_INTMSK
, 0x1f0011);
117 cx_set(MO_DEV_CNTRL2
, (1<<5));
118 cx_set(MO_TS_DMACNTRL
, 0x11);
122 static int cx8802_stop_dma(struct cx8802_dev
*dev
)
124 struct cx88_core
*core
= dev
->core
;
125 dprintk( 0, "cx8802_stop_dma\n" );
128 cx_clear(MO_TS_DMACNTRL
, 0x11);
131 cx_clear(MO_PCI_INTMSK
, 0x000004);
132 cx_clear(MO_TS_INTMSK
, 0x1f0011);
134 /* Reset the controller */
135 cx_write(TS_GEN_CNTRL
, 0xcd);
139 static int cx8802_restart_queue(struct cx8802_dev
*dev
,
140 struct cx88_dmaqueue
*q
)
142 struct cx88_buffer
*buf
;
143 struct list_head
*item
;
145 dprintk( 0, "cx8802_restart_queue\n" );
146 if (list_empty(&q
->active
))
148 dprintk( 0, "cx8802_restart_queue: queue is empty\n" );
152 buf
= list_entry(q
->active
.next
, struct cx88_buffer
, vb
.queue
);
153 dprintk(2,"restart_queue [%p/%d]: restart dma\n",
155 cx8802_start_dma(dev
, q
, buf
);
156 list_for_each(item
,&q
->active
) {
157 buf
= list_entry(item
, struct cx88_buffer
, vb
.queue
);
158 buf
->count
= q
->count
++;
160 mod_timer(&q
->timeout
, jiffies
+BUFFER_TIMEOUT
);
164 /* ------------------------------------------------------------------ */
166 int cx8802_buf_prepare(struct cx8802_dev
*dev
, struct cx88_buffer
*buf
,
167 enum v4l2_field field
)
169 int size
= dev
->ts_packet_size
* dev
->ts_packet_count
;
172 dprintk(1, "%s: %p\n", __FUNCTION__
, buf
);
173 if (0 != buf
->vb
.baddr
&& buf
->vb
.bsize
< size
)
176 if (STATE_NEEDS_INIT
== buf
->vb
.state
) {
177 buf
->vb
.width
= dev
->ts_packet_size
;
178 buf
->vb
.height
= dev
->ts_packet_count
;
180 buf
->vb
.field
= field
/*V4L2_FIELD_TOP*/;
182 if (0 != (rc
= videobuf_iolock(dev
->pci
,&buf
->vb
,NULL
)))
184 cx88_risc_databuffer(dev
->pci
, &buf
->risc
,
186 buf
->vb
.width
, buf
->vb
.height
);
188 buf
->vb
.state
= STATE_PREPARED
;
192 cx88_free_buffer(dev
->pci
,buf
);
196 void cx8802_buf_queue(struct cx8802_dev
*dev
, struct cx88_buffer
*buf
)
198 struct cx88_buffer
*prev
;
199 struct cx88_dmaqueue
*q
= &dev
->mpegq
;
201 dprintk( 1, "cx8802_buf_queue\n" );
202 /* add jump to stopper */
203 buf
->risc
.jmp
[0] = cpu_to_le32(RISC_JUMP
| RISC_IRQ1
| RISC_CNT_INC
);
204 buf
->risc
.jmp
[1] = cpu_to_le32(q
->stopper
.dma
);
206 if (list_empty(&q
->active
)) {
207 dprintk( 0, "queue is empty - first active\n" );
208 list_add_tail(&buf
->vb
.queue
,&q
->active
);
209 cx8802_start_dma(dev
, q
, buf
);
210 buf
->vb
.state
= STATE_ACTIVE
;
211 buf
->count
= q
->count
++;
212 mod_timer(&q
->timeout
, jiffies
+BUFFER_TIMEOUT
);
213 dprintk(0,"[%p/%d] %s - first active\n",
214 buf
, buf
->vb
.i
, __FUNCTION__
);
217 dprintk( 1, "queue is not empty - append to active\n" );
218 prev
= list_entry(q
->active
.prev
, struct cx88_buffer
, vb
.queue
);
219 list_add_tail(&buf
->vb
.queue
,&q
->active
);
220 buf
->vb
.state
= STATE_ACTIVE
;
221 buf
->count
= q
->count
++;
222 prev
->risc
.jmp
[1] = cpu_to_le32(buf
->risc
.dma
);
223 dprintk( 1, "[%p/%d] %s - append to active\n",
224 buf
, buf
->vb
.i
, __FUNCTION__
);
228 /* ----------------------------------------------------------- */
230 static void do_cancel_buffers(struct cx8802_dev
*dev
, char *reason
, int restart
)
232 struct cx88_dmaqueue
*q
= &dev
->mpegq
;
233 struct cx88_buffer
*buf
;
236 spin_lock_irqsave(&dev
->slock
,flags
);
237 while (!list_empty(&q
->active
)) {
238 buf
= list_entry(q
->active
.next
, struct cx88_buffer
, vb
.queue
);
239 list_del(&buf
->vb
.queue
);
240 buf
->vb
.state
= STATE_ERROR
;
241 wake_up(&buf
->vb
.done
);
242 dprintk(1,"[%p/%d] %s - dma=0x%08lx\n",
243 buf
, buf
->vb
.i
, reason
, (unsigned long)buf
->risc
.dma
);
247 dprintk(0, "restarting queue\n" );
248 cx8802_restart_queue(dev
,q
);
250 spin_unlock_irqrestore(&dev
->slock
,flags
);
253 void cx8802_cancel_buffers(struct cx8802_dev
*dev
)
255 struct cx88_dmaqueue
*q
= &dev
->mpegq
;
257 dprintk( 1, "cx8802_cancel_buffers" );
258 del_timer_sync(&q
->timeout
);
259 cx8802_stop_dma(dev
);
260 do_cancel_buffers(dev
,"cancel",0);
263 static void cx8802_timeout(unsigned long data
)
265 struct cx8802_dev
*dev
= (struct cx8802_dev
*)data
;
267 dprintk(0, "%s\n",__FUNCTION__
);
270 cx88_sram_channel_dump(dev
->core
, &cx88_sram_channels
[SRAM_CH28
]);
271 cx8802_stop_dma(dev
);
272 do_cancel_buffers(dev
,"timeout",1);
275 static char *cx88_mpeg_irqs
[32] = {
276 "ts_risci1", NULL
, NULL
, NULL
,
277 "ts_risci2", NULL
, NULL
, NULL
,
278 "ts_oflow", NULL
, NULL
, NULL
,
279 "ts_sync", NULL
, NULL
, NULL
,
280 "opc_err", "par_err", "rip_err", "pci_abort",
284 static void cx8802_mpeg_irq(struct cx8802_dev
*dev
)
286 struct cx88_core
*core
= dev
->core
;
287 u32 status
, mask
, count
;
289 dprintk( 1, "cx8802_mpeg_irq\n" );
290 status
= cx_read(MO_TS_INTSTAT
);
291 mask
= cx_read(MO_TS_INTMSK
);
292 if (0 == (status
& mask
))
295 cx_write(MO_TS_INTSTAT
, status
);
297 if (debug
|| (status
& mask
& ~0xff))
298 cx88_print_irqbits(core
->name
, "irq mpeg ",
299 cx88_mpeg_irqs
, status
, mask
);
301 /* risc op code error */
302 if (status
& (1 << 16)) {
303 printk(KERN_WARNING
"%s: mpeg risc op code error\n",core
->name
);
304 cx_clear(MO_TS_DMACNTRL
, 0x11);
305 cx88_sram_channel_dump(dev
->core
, &cx88_sram_channels
[SRAM_CH28
]);
310 dprintk( 1, "wake up\n" );
311 spin_lock(&dev
->slock
);
312 count
= cx_read(MO_TS_GPCNT
);
313 cx88_wakeup(dev
->core
, &dev
->mpegq
, count
);
314 spin_unlock(&dev
->slock
);
319 spin_lock(&dev
->slock
);
320 cx8802_restart_queue(dev
,&dev
->mpegq
);
321 spin_unlock(&dev
->slock
);
324 /* other general errors */
325 if (status
& 0x1f0100) {
326 dprintk( 0, "general errors: 0x%08x\n", status
& 0x1f0100 );
327 spin_lock(&dev
->slock
);
328 cx8802_stop_dma(dev
);
329 cx8802_restart_queue(dev
,&dev
->mpegq
);
330 spin_unlock(&dev
->slock
);
334 #define MAX_IRQ_LOOP 10
336 static irqreturn_t
cx8802_irq(int irq
, void *dev_id
, struct pt_regs
*regs
)
338 struct cx8802_dev
*dev
= dev_id
;
339 struct cx88_core
*core
= dev
->core
;
341 int loop
, handled
= 0;
343 for (loop
= 0; loop
< MAX_IRQ_LOOP
; loop
++) {
344 status
= cx_read(MO_PCI_INTSTAT
) & (core
->pci_irqmask
| 0x04);
347 dprintk( 1, "cx8802_irq\n" );
348 dprintk( 1, " loop: %d/%d\n", loop
, MAX_IRQ_LOOP
);
349 dprintk( 1, " status: %d\n", status
);
351 cx_write(MO_PCI_INTSTAT
, status
);
353 if (status
& core
->pci_irqmask
)
354 cx88_core_irq(core
,status
);
356 cx8802_mpeg_irq(dev
);
358 if (MAX_IRQ_LOOP
== loop
) {
359 dprintk( 0, "clearing mask\n" );
360 printk(KERN_WARNING
"%s/0: irq loop -- clearing mask\n",
362 cx_write(MO_PCI_INTMSK
,0);
366 return IRQ_RETVAL(handled
);
369 /* ----------------------------------------------------------- */
372 int cx8802_init_common(struct cx8802_dev
*dev
)
374 struct cx88_core
*core
= dev
->core
;
378 if (pci_enable_device(dev
->pci
))
380 pci_set_master(dev
->pci
);
381 if (!pci_dma_supported(dev
->pci
,0xffffffff)) {
382 printk("%s/2: Oops: no 32bit PCI DMA ???\n",dev
->core
->name
);
386 pci_read_config_byte(dev
->pci
, PCI_CLASS_REVISION
, &dev
->pci_rev
);
387 pci_read_config_byte(dev
->pci
, PCI_LATENCY_TIMER
, &dev
->pci_lat
);
388 printk(KERN_INFO
"%s/2: found at %s, rev: %d, irq: %d, "
389 "latency: %d, mmio: 0x%lx\n", dev
->core
->name
,
390 pci_name(dev
->pci
), dev
->pci_rev
, dev
->pci
->irq
,
391 dev
->pci_lat
,pci_resource_start(dev
->pci
,0));
393 /* initialize driver struct */
394 spin_lock_init(&dev
->slock
);
397 INIT_LIST_HEAD(&dev
->mpegq
.active
);
398 INIT_LIST_HEAD(&dev
->mpegq
.queued
);
399 dev
->mpegq
.timeout
.function
= cx8802_timeout
;
400 dev
->mpegq
.timeout
.data
= (unsigned long)dev
;
401 init_timer(&dev
->mpegq
.timeout
);
402 cx88_risc_stopper(dev
->pci
,&dev
->mpegq
.stopper
,
403 MO_TS_DMACNTRL
,0x11,0x00);
406 err
= request_irq(dev
->pci
->irq
, cx8802_irq
,
407 SA_SHIRQ
| SA_INTERRUPT
, dev
->core
->name
, dev
);
409 printk(KERN_ERR
"%s: can't get IRQ %d\n",
410 dev
->core
->name
, dev
->pci
->irq
);
413 cx_set(MO_PCI_INTMSK
, core
->pci_irqmask
);
415 /* everything worked */
416 pci_set_drvdata(dev
->pci
,dev
);
420 void cx8802_fini_common(struct cx8802_dev
*dev
)
422 dprintk( 2, "cx8802_fini_common\n" );
423 cx8802_stop_dma(dev
);
424 pci_disable_device(dev
->pci
);
426 /* unregister stuff */
427 free_irq(dev
->pci
->irq
, dev
);
428 pci_set_drvdata(dev
->pci
, NULL
);
431 btcx_riscmem_free(dev
->pci
,&dev
->mpegq
.stopper
);
434 /* ----------------------------------------------------------- */
436 int cx8802_suspend_common(struct pci_dev
*pci_dev
, pm_message_t state
)
438 struct cx8802_dev
*dev
= pci_get_drvdata(pci_dev
);
439 struct cx88_core
*core
= dev
->core
;
442 spin_lock(&dev
->slock
);
443 if (!list_empty(&dev
->mpegq
.active
)) {
444 dprintk( 2, "suspend\n" );
445 printk("%s: suspend mpeg\n", core
->name
);
446 cx8802_stop_dma(dev
);
447 del_timer(&dev
->mpegq
.timeout
);
449 spin_unlock(&dev
->slock
);
451 /* FIXME -- shutdown device */
452 cx88_shutdown(dev
->core
);
454 pci_save_state(pci_dev
);
455 if (0 != pci_set_power_state(pci_dev
, pci_choose_state(pci_dev
, state
))) {
456 pci_disable_device(pci_dev
);
457 dev
->state
.disabled
= 1;
462 int cx8802_resume_common(struct pci_dev
*pci_dev
)
464 struct cx8802_dev
*dev
= pci_get_drvdata(pci_dev
);
465 struct cx88_core
*core
= dev
->core
;
468 if (dev
->state
.disabled
) {
469 err
=pci_enable_device(pci_dev
);
471 printk(KERN_ERR
"%s: can't enable device\n",
475 dev
->state
.disabled
= 0;
477 err
=pci_set_power_state(pci_dev
, PCI_D0
);
479 printk(KERN_ERR
"%s: can't enable device\n",
481 pci_disable_device(pci_dev
);
482 dev
->state
.disabled
= 1;
486 pci_restore_state(pci_dev
);
488 /* FIXME: re-initialize hardware */
489 cx88_reset(dev
->core
);
491 /* restart video+vbi capture */
492 spin_lock(&dev
->slock
);
493 if (!list_empty(&dev
->mpegq
.active
)) {
494 printk("%s: resume mpeg\n", core
->name
);
495 cx8802_restart_queue(dev
,&dev
->mpegq
);
497 spin_unlock(&dev
->slock
);
502 /* ----------------------------------------------------------- */
504 EXPORT_SYMBOL(cx8802_buf_prepare
);
505 EXPORT_SYMBOL(cx8802_buf_queue
);
506 EXPORT_SYMBOL(cx8802_cancel_buffers
);
508 EXPORT_SYMBOL(cx8802_init_common
);
509 EXPORT_SYMBOL(cx8802_fini_common
);
511 EXPORT_SYMBOL(cx8802_suspend_common
);
512 EXPORT_SYMBOL(cx8802_resume_common
);
514 /* ----------------------------------------------------------- */
519 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off