drivers/media/video/cx18/cx18-irq.c

   1 /*
   2  *  cx18 interrupt handling
   3  *
   4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  19  *  02111-1307  USA
  20  */
  21
  22 #include "cx18-driver.h"
  23 #include "cx18-io.h"
  24 #include "cx18-firmware.h"
  25 #include "cx18-fileops.h"
  26 #include "cx18-queue.h"
  27 #include "cx18-irq.h"
  28 #include "cx18-ioctl.h"
  29 #include "cx18-mailbox.h"
  30 #include "cx18-vbi.h"
  31 #include "cx18-scb.h"
  32
  33 #define DMA_MAGIC_COOKIE 0x000001fe
  34
  35 static void epu_dma_done(struct cx18 *cx, struct cx18_mailbox *mb)
  36 {
  37         u32 handle = mb->args[0];
  38         struct cx18_stream *s = NULL;
  39         struct cx18_buffer *buf;
  40         u32 off;
  41         int i;
  42         int id;
  43
  44         for (i = 0; i < CX18_MAX_STREAMS; i++) {
  45                 s = &cx->streams[i];
  46                 if ((handle == s->handle) && (s->dvb.enabled))
  47                         break;
  48                 if (s->v4l2dev && handle == s->handle)
  49                         break;
  50         }
  51         if (i == CX18_MAX_STREAMS) {
  52                 CX18_WARN("Got DMA done notification for unknown/inactive"
  53                           " handle %d\n", handle);
  54                 mb->error = CXERR_NOT_OPEN;
  55                 mb->cmd = 0;
  56                 cx18_mb_ack(cx, mb);
  57                 return;
  58         }
  59
  60         off = mb->args[1];
  61         if (mb->args[2] != 1)
  62                 CX18_WARN("Ack struct = %d for %s\n",
  63                         mb->args[2], s->name);
  64         id = cx18_read_enc(cx, off);
  65         buf = cx18_queue_get_buf_irq(s, id, cx18_read_enc(cx, off + 4));
  66         CX18_DEBUG_HI_DMA("DMA DONE for %s (buffer %d)\n", s->name, id);
  67         if (buf) {
  68                 cx18_buf_sync_for_cpu(s, buf);
  69                 if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) {
  70                         /* process the buffer here */
  71                         CX18_DEBUG_HI_DMA("TS recv and sent bytesused=%d\n",
  72                                         buf->bytesused);
  73
  74                         dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
  75                                         buf->bytesused);
  76
  77                         cx18_buf_sync_for_device(s, buf);
  78                         cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle,
  79                             (void __iomem *)&cx->scb->cpu_mdl[buf->id] - cx->enc_mem,
  80                             1, buf->id, s->buf_size);
  81                 } else
  82                         set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags);
  83         } else {
  84                 CX18_WARN("Could not find buf %d for stream %s\n",
  85                                 cx18_read_enc(cx, off), s->name);
  86         }
  87         mb->error = 0;
  88         mb->cmd = 0;
  89         cx18_mb_ack(cx, mb);
  90         wake_up(&cx->dma_waitq);
  91         if (s->id != -1)
  92                 wake_up(&s->waitq);
  93 }
  94
  95 static void epu_debug(struct cx18 *cx, struct cx18_mailbox *mb)
  96 {
  97         char str[256] = { 0 };
  98         char *p;
  99
 100         if (mb->args[1]) {
 101                 cx18_setup_page(cx, mb->args[1]);
 102                 cx18_memcpy_fromio(cx, str, cx->enc_mem + mb->args[1], 252);
 103                 str[252] = 0;
 104         }
 105         cx18_mb_ack(cx, mb);
 106         CX18_DEBUG_INFO("%x %s\n", mb->args[0], str);
 107         p = strchr(str, '.');
 108         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags) && p && p > str)
 109                 CX18_INFO("FW version: %s\n", p - 1);
 110 }
 111
 112 static void hpu_cmd(struct cx18 *cx, u32 sw1)
 113 {
 114         struct cx18_mailbox mb;
 115
 116         if (sw1 & IRQ_CPU_TO_EPU) {
 117                 cx18_memcpy_fromio(cx, &mb, &cx->scb->cpu2epu_mb, sizeof(mb));
 118                 mb.error = 0;
 119
 120                 switch (mb.cmd) {
 121                 case CX18_EPU_DMA_DONE:
 122                         epu_dma_done(cx, &mb);
 123                         break;
 124                 case CX18_EPU_DEBUG:
 125                         epu_debug(cx, &mb);
 126                         break;
 127                 default:
 128                         CX18_WARN("Unexpected mailbox command %08x\n", mb.cmd);
 129                         break;
 130                 }
 131         }
 132         if (sw1 & (IRQ_APU_TO_EPU | IRQ_HPU_TO_EPU))
 133                 CX18_WARN("Unexpected interrupt %08x\n", sw1);
 134 }
 135
 136 irqreturn_t cx18_irq_handler(int irq, void *dev_id)
 137 {
 138         struct cx18 *cx = (struct cx18 *)dev_id;
 139         u32 sw1, sw1_mask;
 140         u32 sw2, sw2_mask;
 141         u32 hw2, hw2_mask;
 142
 143         spin_lock(&cx->dma_reg_lock);
 144
 145         hw2_mask = cx18_read_reg(cx, HW2_INT_MASK5_PCI);
 146         hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & hw2_mask;
 147         sw2_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU_ACK;
 148         sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & sw2_mask;
 149         sw1_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | IRQ_EPU_TO_HPU;
 150         sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & sw1_mask;
 151
 152         cx18_write_reg(cx, sw2&sw2_mask, SW2_INT_STATUS);
 153         cx18_write_reg(cx, sw1&sw1_mask, SW1_INT_STATUS);
 154         cx18_write_reg(cx, hw2&hw2_mask, HW2_INT_CLR_STATUS);
 155
 156         if (sw1 || sw2 || hw2)
 157                 CX18_DEBUG_HI_IRQ("SW1: %x  SW2: %x  HW2: %x\n", sw1, sw2, hw2);
 158
 159         /* To do: interrupt-based I2C handling
 160         if (hw2 & 0x00c00000) {
 161         }
 162         */
 163
 164         if (sw2) {
 165                 if (sw2 & (cx18_readl(cx, &cx->scb->cpu2hpu_irq_ack) |
 166                            cx18_readl(cx, &cx->scb->cpu2epu_irq_ack)))
 167                         wake_up(&cx->mb_cpu_waitq);
 168                 if (sw2 & (cx18_readl(cx, &cx->scb->apu2hpu_irq_ack) |
 169                            cx18_readl(cx, &cx->scb->apu2epu_irq_ack)))
 170                         wake_up(&cx->mb_apu_waitq);
 171                 if (sw2 & cx18_readl(cx, &cx->scb->epu2hpu_irq_ack))
 172                         wake_up(&cx->mb_epu_waitq);
 173                 if (sw2 & cx18_readl(cx, &cx->scb->hpu2epu_irq_ack))
 174                         wake_up(&cx->mb_hpu_waitq);
 175         }
 176
 177         if (sw1)
 178                 hpu_cmd(cx, sw1);
 179         spin_unlock(&cx->dma_reg_lock);
 180
 181         return (hw2 | sw1 | sw2) ? IRQ_HANDLED : IRQ_NONE;
 182 }