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ARM: at91: fix board-rm9200-dt after sys_timer conversion
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / media / platform / s5p-mfc / s5p_mfc.c
1 /*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
24 #include <media/videobuf2-core.h>
25 #include "s5p_mfc_common.h"
26 #include "s5p_mfc_ctrl.h"
27 #include "s5p_mfc_debug.h"
28 #include "s5p_mfc_dec.h"
29 #include "s5p_mfc_enc.h"
30 #include "s5p_mfc_intr.h"
31 #include "s5p_mfc_opr.h"
32 #include "s5p_mfc_cmd.h"
33 #include "s5p_mfc_pm.h"
34
35 #define S5P_MFC_NAME "s5p-mfc"
36 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
37 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
38
39 int debug;
40 module_param(debug, int, S_IRUGO | S_IWUSR);
41 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
42
43 /* Helper functions for interrupt processing */
44
45 /* Remove from hw execution round robin */
46 void clear_work_bit(struct s5p_mfc_ctx *ctx)
47 {
48 struct s5p_mfc_dev *dev = ctx->dev;
49
50 spin_lock(&dev->condlock);
51 __clear_bit(ctx->num, &dev->ctx_work_bits);
52 spin_unlock(&dev->condlock);
53 }
54
55 /* Add to hw execution round robin */
56 void set_work_bit(struct s5p_mfc_ctx *ctx)
57 {
58 struct s5p_mfc_dev *dev = ctx->dev;
59
60 spin_lock(&dev->condlock);
61 __set_bit(ctx->num, &dev->ctx_work_bits);
62 spin_unlock(&dev->condlock);
63 }
64
65 /* Remove from hw execution round robin */
66 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
67 {
68 struct s5p_mfc_dev *dev = ctx->dev;
69 unsigned long flags;
70
71 spin_lock_irqsave(&dev->condlock, flags);
72 __clear_bit(ctx->num, &dev->ctx_work_bits);
73 spin_unlock_irqrestore(&dev->condlock, flags);
74 }
75
76 /* Add to hw execution round robin */
77 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
78 {
79 struct s5p_mfc_dev *dev = ctx->dev;
80 unsigned long flags;
81
82 spin_lock_irqsave(&dev->condlock, flags);
83 __set_bit(ctx->num, &dev->ctx_work_bits);
84 spin_unlock_irqrestore(&dev->condlock, flags);
85 }
86
87 /* Wake up context wait_queue */
88 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
89 unsigned int err)
90 {
91 ctx->int_cond = 1;
92 ctx->int_type = reason;
93 ctx->int_err = err;
94 wake_up(&ctx->queue);
95 }
96
97 /* Wake up device wait_queue */
98 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
99 unsigned int err)
100 {
101 dev->int_cond = 1;
102 dev->int_type = reason;
103 dev->int_err = err;
104 wake_up(&dev->queue);
105 }
106
107 static void s5p_mfc_watchdog(unsigned long arg)
108 {
109 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
110
111 if (test_bit(0, &dev->hw_lock))
112 atomic_inc(&dev->watchdog_cnt);
113 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
114 /* This means that hw is busy and no interrupts were
115 * generated by hw for the Nth time of running this
116 * watchdog timer. This usually means a serious hw
117 * error. Now it is time to kill all instances and
118 * reset the MFC. */
119 mfc_err("Time out during waiting for HW\n");
120 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
121 }
122 dev->watchdog_timer.expires = jiffies +
123 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
124 add_timer(&dev->watchdog_timer);
125 }
126
127 static void s5p_mfc_watchdog_worker(struct work_struct *work)
128 {
129 struct s5p_mfc_dev *dev;
130 struct s5p_mfc_ctx *ctx;
131 unsigned long flags;
132 int mutex_locked;
133 int i, ret;
134
135 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
136
137 mfc_err("Driver timeout error handling\n");
138 /* Lock the mutex that protects open and release.
139 * This is necessary as they may load and unload firmware. */
140 mutex_locked = mutex_trylock(&dev->mfc_mutex);
141 if (!mutex_locked)
142 mfc_err("Error: some instance may be closing/opening\n");
143 spin_lock_irqsave(&dev->irqlock, flags);
144
145 s5p_mfc_clock_off();
146
147 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
148 ctx = dev->ctx[i];
149 if (!ctx)
150 continue;
151 ctx->state = MFCINST_ERROR;
152 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
153 &ctx->vq_dst);
154 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
155 &ctx->vq_src);
156 clear_work_bit(ctx);
157 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
158 }
159 clear_bit(0, &dev->hw_lock);
160 spin_unlock_irqrestore(&dev->irqlock, flags);
161 /* Double check if there is at least one instance running.
162 * If no instance is in memory than no firmware should be present */
163 if (dev->num_inst > 0) {
164 ret = s5p_mfc_reload_firmware(dev);
165 if (ret) {
166 mfc_err("Failed to reload FW\n");
167 goto unlock;
168 }
169 s5p_mfc_clock_on();
170 ret = s5p_mfc_init_hw(dev);
171 if (ret)
172 mfc_err("Failed to reinit FW\n");
173 }
174 unlock:
175 if (mutex_locked)
176 mutex_unlock(&dev->mfc_mutex);
177 }
178
179 static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file)
180 {
181 struct video_device *vdev = video_devdata(file);
182
183 if (!vdev) {
184 mfc_err("failed to get video_device");
185 return MFCNODE_INVALID;
186 }
187 if (vdev->index == 0)
188 return MFCNODE_DECODER;
189 else if (vdev->index == 1)
190 return MFCNODE_ENCODER;
191 return MFCNODE_INVALID;
192 }
193
194 static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
195 {
196 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
197 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
198 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
199 }
200
201 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
202 {
203 struct s5p_mfc_buf *dst_buf;
204 struct s5p_mfc_dev *dev = ctx->dev;
205
206 ctx->state = MFCINST_FINISHED;
207 ctx->sequence++;
208 while (!list_empty(&ctx->dst_queue)) {
209 dst_buf = list_entry(ctx->dst_queue.next,
210 struct s5p_mfc_buf, list);
211 mfc_debug(2, "Cleaning up buffer: %d\n",
212 dst_buf->b->v4l2_buf.index);
213 vb2_set_plane_payload(dst_buf->b, 0, 0);
214 vb2_set_plane_payload(dst_buf->b, 1, 0);
215 list_del(&dst_buf->list);
216 ctx->dst_queue_cnt--;
217 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
218
219 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
220 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
221 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
222 else
223 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
224
225 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
226 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
227 }
228 }
229
230 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
231 {
232 struct s5p_mfc_dev *dev = ctx->dev;
233 struct s5p_mfc_buf *dst_buf, *src_buf;
234 size_t dec_y_addr;
235 unsigned int frame_type;
236
237 dec_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
238 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
239
240 /* Copy timestamp / timecode from decoded src to dst and set
241 appropraite flags */
242 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
243 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
244 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
245 memcpy(&dst_buf->b->v4l2_buf.timecode,
246 &src_buf->b->v4l2_buf.timecode,
247 sizeof(struct v4l2_timecode));
248 memcpy(&dst_buf->b->v4l2_buf.timestamp,
249 &src_buf->b->v4l2_buf.timestamp,
250 sizeof(struct timeval));
251 switch (frame_type) {
252 case S5P_FIMV_DECODE_FRAME_I_FRAME:
253 dst_buf->b->v4l2_buf.flags |=
254 V4L2_BUF_FLAG_KEYFRAME;
255 break;
256 case S5P_FIMV_DECODE_FRAME_P_FRAME:
257 dst_buf->b->v4l2_buf.flags |=
258 V4L2_BUF_FLAG_PFRAME;
259 break;
260 case S5P_FIMV_DECODE_FRAME_B_FRAME:
261 dst_buf->b->v4l2_buf.flags |=
262 V4L2_BUF_FLAG_BFRAME;
263 break;
264 }
265 break;
266 }
267 }
268 }
269
270 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
271 {
272 struct s5p_mfc_dev *dev = ctx->dev;
273 struct s5p_mfc_buf *dst_buf;
274 size_t dspl_y_addr;
275 unsigned int frame_type;
276 unsigned int index;
277
278 dspl_y_addr = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
279 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
280
281 /* If frame is same as previous then skip and do not dequeue */
282 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
283 if (!ctx->after_packed_pb)
284 ctx->sequence++;
285 ctx->after_packed_pb = 0;
286 return;
287 }
288 ctx->sequence++;
289 /* The MFC returns address of the buffer, now we have to
290 * check which videobuf does it correspond to */
291 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
292 /* Check if this is the buffer we're looking for */
293 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
294 list_del(&dst_buf->list);
295 ctx->dst_queue_cnt--;
296 dst_buf->b->v4l2_buf.sequence = ctx->sequence;
297 if (s5p_mfc_hw_call(dev->mfc_ops,
298 get_pic_type_top, ctx) ==
299 s5p_mfc_hw_call(dev->mfc_ops,
300 get_pic_type_bot, ctx))
301 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
302 else
303 dst_buf->b->v4l2_buf.field =
304 V4L2_FIELD_INTERLACED;
305 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
306 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
307 clear_bit(dst_buf->b->v4l2_buf.index,
308 &ctx->dec_dst_flag);
309
310 vb2_buffer_done(dst_buf->b,
311 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
312
313 index = dst_buf->b->v4l2_buf.index;
314 break;
315 }
316 }
317 }
318
319 /* Handle frame decoding interrupt */
320 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
321 unsigned int reason, unsigned int err)
322 {
323 struct s5p_mfc_dev *dev = ctx->dev;
324 unsigned int dst_frame_status;
325 struct s5p_mfc_buf *src_buf;
326 unsigned long flags;
327 unsigned int res_change;
328
329 unsigned int index;
330
331 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
332 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
333 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
334 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
335 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
336 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
337 if (ctx->state == MFCINST_RES_CHANGE_INIT)
338 ctx->state = MFCINST_RES_CHANGE_FLUSH;
339 if (res_change == S5P_FIMV_RES_INCREASE ||
340 res_change == S5P_FIMV_RES_DECREASE) {
341 ctx->state = MFCINST_RES_CHANGE_INIT;
342 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
343 wake_up_ctx(ctx, reason, err);
344 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
345 BUG();
346 s5p_mfc_clock_off();
347 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
348 return;
349 }
350 if (ctx->dpb_flush_flag)
351 ctx->dpb_flush_flag = 0;
352
353 spin_lock_irqsave(&dev->irqlock, flags);
354 /* All frames remaining in the buffer have been extracted */
355 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
356 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
357 s5p_mfc_handle_frame_all_extracted(ctx);
358 ctx->state = MFCINST_RES_CHANGE_END;
359 goto leave_handle_frame;
360 } else {
361 s5p_mfc_handle_frame_all_extracted(ctx);
362 }
363 }
364
365 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY ||
366 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY)
367 s5p_mfc_handle_frame_copy_time(ctx);
368
369 /* A frame has been decoded and is in the buffer */
370 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
371 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
372 s5p_mfc_handle_frame_new(ctx, err);
373 } else {
374 mfc_debug(2, "No frame decode\n");
375 }
376 /* Mark source buffer as complete */
377 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
378 && !list_empty(&ctx->src_queue)) {
379 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
380 list);
381 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
382 get_consumed_stream, dev);
383 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
384 ctx->consumed_stream + STUFF_BYTE <
385 src_buf->b->v4l2_planes[0].bytesused) {
386 /* Run MFC again on the same buffer */
387 mfc_debug(2, "Running again the same buffer\n");
388 ctx->after_packed_pb = 1;
389 } else {
390 index = src_buf->b->v4l2_buf.index;
391 mfc_debug(2, "MFC needs next buffer\n");
392 ctx->consumed_stream = 0;
393 list_del(&src_buf->list);
394 ctx->src_queue_cnt--;
395 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
396 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
397 else
398 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
399 }
400 }
401 leave_handle_frame:
402 spin_unlock_irqrestore(&dev->irqlock, flags);
403 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
404 || ctx->dst_queue_cnt < ctx->dpb_count)
405 clear_work_bit(ctx);
406 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
407 wake_up_ctx(ctx, reason, err);
408 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
409 BUG();
410 s5p_mfc_clock_off();
411 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
412 }
413
414 /* Error handling for interrupt */
415 static void s5p_mfc_handle_error(struct s5p_mfc_ctx *ctx,
416 unsigned int reason, unsigned int err)
417 {
418 struct s5p_mfc_dev *dev;
419 unsigned long flags;
420
421 /* If no context is available then all necessary
422 * processing has been done. */
423 if (ctx == NULL)
424 return;
425
426 dev = ctx->dev;
427 mfc_err("Interrupt Error: %08x\n", err);
428 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
429 wake_up_dev(dev, reason, err);
430
431 /* Error recovery is dependent on the state of context */
432 switch (ctx->state) {
433 case MFCINST_INIT:
434 /* This error had to happen while acquireing instance */
435 case MFCINST_GOT_INST:
436 /* This error had to happen while parsing the header */
437 case MFCINST_HEAD_PARSED:
438 /* This error had to happen while setting dst buffers */
439 case MFCINST_RETURN_INST:
440 /* This error had to happen while releasing instance */
441 clear_work_bit(ctx);
442 wake_up_ctx(ctx, reason, err);
443 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
444 BUG();
445 s5p_mfc_clock_off();
446 ctx->state = MFCINST_ERROR;
447 break;
448 case MFCINST_FINISHING:
449 case MFCINST_FINISHED:
450 case MFCINST_RUNNING:
451 /* It is higly probable that an error occured
452 * while decoding a frame */
453 clear_work_bit(ctx);
454 ctx->state = MFCINST_ERROR;
455 /* Mark all dst buffers as having an error */
456 spin_lock_irqsave(&dev->irqlock, flags);
457 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue,
458 &ctx->vq_dst);
459 /* Mark all src buffers as having an error */
460 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
461 &ctx->vq_src);
462 spin_unlock_irqrestore(&dev->irqlock, flags);
463 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
464 BUG();
465 s5p_mfc_clock_off();
466 break;
467 default:
468 mfc_err("Encountered an error interrupt which had not been handled\n");
469 break;
470 }
471 return;
472 }
473
474 /* Header parsing interrupt handling */
475 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
476 unsigned int reason, unsigned int err)
477 {
478 struct s5p_mfc_dev *dev;
479
480 if (ctx == NULL)
481 return;
482 dev = ctx->dev;
483 if (ctx->c_ops->post_seq_start) {
484 if (ctx->c_ops->post_seq_start(ctx))
485 mfc_err("post_seq_start() failed\n");
486 } else {
487 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
488 dev);
489 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
490 dev);
491
492 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
493
494 ctx->dpb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
495 dev);
496 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
497 dev);
498 if (ctx->img_width == 0 || ctx->img_height == 0)
499 ctx->state = MFCINST_ERROR;
500 else
501 ctx->state = MFCINST_HEAD_PARSED;
502
503 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
504 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
505 !list_empty(&ctx->src_queue)) {
506 struct s5p_mfc_buf *src_buf;
507 src_buf = list_entry(ctx->src_queue.next,
508 struct s5p_mfc_buf, list);
509 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
510 dev) <
511 src_buf->b->v4l2_planes[0].bytesused)
512 ctx->head_processed = 0;
513 else
514 ctx->head_processed = 1;
515 } else {
516 ctx->head_processed = 1;
517 }
518 }
519 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
520 clear_work_bit(ctx);
521 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
522 BUG();
523 s5p_mfc_clock_off();
524 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
525 wake_up_ctx(ctx, reason, err);
526 }
527
528 /* Header parsing interrupt handling */
529 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
530 unsigned int reason, unsigned int err)
531 {
532 struct s5p_mfc_buf *src_buf;
533 struct s5p_mfc_dev *dev;
534 unsigned long flags;
535
536 if (ctx == NULL)
537 return;
538 dev = ctx->dev;
539 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
540 ctx->int_type = reason;
541 ctx->int_err = err;
542 ctx->int_cond = 1;
543 clear_work_bit(ctx);
544 if (err == 0) {
545 ctx->state = MFCINST_RUNNING;
546 if (!ctx->dpb_flush_flag && ctx->head_processed) {
547 spin_lock_irqsave(&dev->irqlock, flags);
548 if (!list_empty(&ctx->src_queue)) {
549 src_buf = list_entry(ctx->src_queue.next,
550 struct s5p_mfc_buf, list);
551 list_del(&src_buf->list);
552 ctx->src_queue_cnt--;
553 vb2_buffer_done(src_buf->b,
554 VB2_BUF_STATE_DONE);
555 }
556 spin_unlock_irqrestore(&dev->irqlock, flags);
557 } else {
558 ctx->dpb_flush_flag = 0;
559 }
560 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
561 BUG();
562
563 s5p_mfc_clock_off();
564
565 wake_up(&ctx->queue);
566 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
567 } else {
568 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
569 BUG();
570
571 s5p_mfc_clock_off();
572
573 wake_up(&ctx->queue);
574 }
575 }
576
577 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
578 unsigned int reason, unsigned int err)
579 {
580 struct s5p_mfc_dev *dev = ctx->dev;
581 struct s5p_mfc_buf *mb_entry;
582
583 mfc_debug(2, "Stream completed");
584
585 s5p_mfc_clear_int_flags(dev);
586 ctx->int_type = reason;
587 ctx->int_err = err;
588 ctx->state = MFCINST_FINISHED;
589
590 spin_lock(&dev->irqlock);
591 if (!list_empty(&ctx->dst_queue)) {
592 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
593 list);
594 list_del(&mb_entry->list);
595 ctx->dst_queue_cnt--;
596 vb2_set_plane_payload(mb_entry->b, 0, 0);
597 vb2_buffer_done(mb_entry->b, VB2_BUF_STATE_DONE);
598 }
599 spin_unlock(&dev->irqlock);
600
601 clear_work_bit(ctx);
602
603 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
604 WARN_ON(1);
605
606 s5p_mfc_clock_off();
607 wake_up(&ctx->queue);
608 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
609 }
610
611 /* Interrupt processing */
612 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
613 {
614 struct s5p_mfc_dev *dev = priv;
615 struct s5p_mfc_ctx *ctx;
616 unsigned int reason;
617 unsigned int err;
618
619 mfc_debug_enter();
620 /* Reset the timeout watchdog */
621 atomic_set(&dev->watchdog_cnt, 0);
622 ctx = dev->ctx[dev->curr_ctx];
623 /* Get the reason of interrupt and the error code */
624 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
625 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
626 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
627 switch (reason) {
628 case S5P_MFC_R2H_CMD_ERR_RET:
629 /* An error has occured */
630 if (ctx->state == MFCINST_RUNNING &&
631 s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
632 dev->warn_start)
633 s5p_mfc_handle_frame(ctx, reason, err);
634 else
635 s5p_mfc_handle_error(ctx, reason, err);
636 clear_bit(0, &dev->enter_suspend);
637 break;
638
639 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
640 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
641 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
642 if (ctx->c_ops->post_frame_start) {
643 if (ctx->c_ops->post_frame_start(ctx))
644 mfc_err("post_frame_start() failed\n");
645 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
646 wake_up_ctx(ctx, reason, err);
647 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
648 BUG();
649 s5p_mfc_clock_off();
650 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
651 } else {
652 s5p_mfc_handle_frame(ctx, reason, err);
653 }
654 break;
655
656 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
657 s5p_mfc_handle_seq_done(ctx, reason, err);
658 break;
659
660 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
661 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
662 ctx->state = MFCINST_GOT_INST;
663 clear_work_bit(ctx);
664 wake_up(&ctx->queue);
665 goto irq_cleanup_hw;
666
667 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
668 clear_work_bit(ctx);
669 ctx->state = MFCINST_FREE;
670 wake_up(&ctx->queue);
671 goto irq_cleanup_hw;
672
673 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
674 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
675 case S5P_MFC_R2H_CMD_SLEEP_RET:
676 case S5P_MFC_R2H_CMD_WAKEUP_RET:
677 if (ctx)
678 clear_work_bit(ctx);
679 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
680 wake_up_dev(dev, reason, err);
681 clear_bit(0, &dev->hw_lock);
682 clear_bit(0, &dev->enter_suspend);
683 break;
684
685 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
686 s5p_mfc_handle_init_buffers(ctx, reason, err);
687 break;
688
689 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
690 s5p_mfc_handle_stream_complete(ctx, reason, err);
691 break;
692
693 default:
694 mfc_debug(2, "Unknown int reason\n");
695 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
696 }
697 mfc_debug_leave();
698 return IRQ_HANDLED;
699 irq_cleanup_hw:
700 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
701 ctx->int_type = reason;
702 ctx->int_err = err;
703 ctx->int_cond = 1;
704 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
705 mfc_err("Failed to unlock hw\n");
706
707 s5p_mfc_clock_off();
708
709 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
710 mfc_debug(2, "Exit via irq_cleanup_hw\n");
711 return IRQ_HANDLED;
712 }
713
714 /* Open an MFC node */
715 static int s5p_mfc_open(struct file *file)
716 {
717 struct s5p_mfc_dev *dev = video_drvdata(file);
718 struct s5p_mfc_ctx *ctx = NULL;
719 struct vb2_queue *q;
720 int ret = 0;
721
722 mfc_debug_enter();
723 if (mutex_lock_interruptible(&dev->mfc_mutex))
724 return -ERESTARTSYS;
725 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
726 /* Allocate memory for context */
727 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
728 if (!ctx) {
729 mfc_err("Not enough memory\n");
730 ret = -ENOMEM;
731 goto err_alloc;
732 }
733 v4l2_fh_init(&ctx->fh, video_devdata(file));
734 file->private_data = &ctx->fh;
735 v4l2_fh_add(&ctx->fh);
736 ctx->dev = dev;
737 INIT_LIST_HEAD(&ctx->src_queue);
738 INIT_LIST_HEAD(&ctx->dst_queue);
739 ctx->src_queue_cnt = 0;
740 ctx->dst_queue_cnt = 0;
741 /* Get context number */
742 ctx->num = 0;
743 while (dev->ctx[ctx->num]) {
744 ctx->num++;
745 if (ctx->num >= MFC_NUM_CONTEXTS) {
746 mfc_err("Too many open contexts\n");
747 ret = -EBUSY;
748 goto err_no_ctx;
749 }
750 }
751 /* Mark context as idle */
752 clear_work_bit_irqsave(ctx);
753 dev->ctx[ctx->num] = ctx;
754 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
755 ctx->type = MFCINST_DECODER;
756 ctx->c_ops = get_dec_codec_ops();
757 s5p_mfc_dec_init(ctx);
758 /* Setup ctrl handler */
759 ret = s5p_mfc_dec_ctrls_setup(ctx);
760 if (ret) {
761 mfc_err("Failed to setup mfc controls\n");
762 goto err_ctrls_setup;
763 }
764 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
765 ctx->type = MFCINST_ENCODER;
766 ctx->c_ops = get_enc_codec_ops();
767 /* only for encoder */
768 INIT_LIST_HEAD(&ctx->ref_queue);
769 ctx->ref_queue_cnt = 0;
770 s5p_mfc_enc_init(ctx);
771 /* Setup ctrl handler */
772 ret = s5p_mfc_enc_ctrls_setup(ctx);
773 if (ret) {
774 mfc_err("Failed to setup mfc controls\n");
775 goto err_ctrls_setup;
776 }
777 } else {
778 ret = -ENOENT;
779 goto err_bad_node;
780 }
781 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
782 ctx->inst_no = -1;
783 /* Load firmware if this is the first instance */
784 if (dev->num_inst == 1) {
785 dev->watchdog_timer.expires = jiffies +
786 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
787 add_timer(&dev->watchdog_timer);
788 ret = s5p_mfc_power_on();
789 if (ret < 0) {
790 mfc_err("power on failed\n");
791 goto err_pwr_enable;
792 }
793 s5p_mfc_clock_on();
794 ret = s5p_mfc_alloc_and_load_firmware(dev);
795 if (ret)
796 goto err_alloc_fw;
797 /* Init the FW */
798 ret = s5p_mfc_init_hw(dev);
799 if (ret)
800 goto err_init_hw;
801 s5p_mfc_clock_off();
802 }
803 /* Init videobuf2 queue for CAPTURE */
804 q = &ctx->vq_dst;
805 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
806 q->drv_priv = &ctx->fh;
807 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
808 q->io_modes = VB2_MMAP;
809 q->ops = get_dec_queue_ops();
810 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
811 q->io_modes = VB2_MMAP | VB2_USERPTR;
812 q->ops = get_enc_queue_ops();
813 } else {
814 ret = -ENOENT;
815 goto err_queue_init;
816 }
817 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
818 ret = vb2_queue_init(q);
819 if (ret) {
820 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
821 goto err_queue_init;
822 }
823 /* Init videobuf2 queue for OUTPUT */
824 q = &ctx->vq_src;
825 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
826 q->io_modes = VB2_MMAP;
827 q->drv_priv = &ctx->fh;
828 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
829 q->io_modes = VB2_MMAP;
830 q->ops = get_dec_queue_ops();
831 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
832 q->io_modes = VB2_MMAP | VB2_USERPTR;
833 q->ops = get_enc_queue_ops();
834 } else {
835 ret = -ENOENT;
836 goto err_queue_init;
837 }
838 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
839 ret = vb2_queue_init(q);
840 if (ret) {
841 mfc_err("Failed to initialize videobuf2 queue(output)\n");
842 goto err_queue_init;
843 }
844 init_waitqueue_head(&ctx->queue);
845 mutex_unlock(&dev->mfc_mutex);
846 mfc_debug_leave();
847 return ret;
848 /* Deinit when failure occured */
849 err_queue_init:
850 err_init_hw:
851 s5p_mfc_release_firmware(dev);
852 err_alloc_fw:
853 dev->ctx[ctx->num] = NULL;
854 del_timer_sync(&dev->watchdog_timer);
855 s5p_mfc_clock_off();
856 err_pwr_enable:
857 if (dev->num_inst == 1) {
858 if (s5p_mfc_power_off() < 0)
859 mfc_err("power off failed\n");
860 s5p_mfc_release_firmware(dev);
861 }
862 err_ctrls_setup:
863 s5p_mfc_dec_ctrls_delete(ctx);
864 err_bad_node:
865 err_no_ctx:
866 v4l2_fh_del(&ctx->fh);
867 v4l2_fh_exit(&ctx->fh);
868 kfree(ctx);
869 err_alloc:
870 dev->num_inst--;
871 mutex_unlock(&dev->mfc_mutex);
872 mfc_debug_leave();
873 return ret;
874 }
875
876 /* Release MFC context */
877 static int s5p_mfc_release(struct file *file)
878 {
879 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
880 struct s5p_mfc_dev *dev = ctx->dev;
881
882 mfc_debug_enter();
883 mutex_lock(&dev->mfc_mutex);
884 s5p_mfc_clock_on();
885 vb2_queue_release(&ctx->vq_src);
886 vb2_queue_release(&ctx->vq_dst);
887 /* Mark context as idle */
888 clear_work_bit_irqsave(ctx);
889 /* If instance was initialised then
890 * return instance and free reosurces */
891 if (ctx->inst_no != MFC_NO_INSTANCE_SET) {
892 mfc_debug(2, "Has to free instance\n");
893 ctx->state = MFCINST_RETURN_INST;
894 set_work_bit_irqsave(ctx);
895 s5p_mfc_clean_ctx_int_flags(ctx);
896 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
897 /* Wait until instance is returned or timeout occured */
898 if (s5p_mfc_wait_for_done_ctx
899 (ctx, S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) {
900 s5p_mfc_clock_off();
901 mfc_err("Err returning instance\n");
902 }
903 mfc_debug(2, "After free instance\n");
904 /* Free resources */
905 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
906 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
907 if (ctx->type == MFCINST_DECODER)
908 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer,
909 ctx);
910
911 ctx->inst_no = MFC_NO_INSTANCE_SET;
912 }
913 /* hardware locking scheme */
914 if (dev->curr_ctx == ctx->num)
915 clear_bit(0, &dev->hw_lock);
916 dev->num_inst--;
917 if (dev->num_inst == 0) {
918 mfc_debug(2, "Last instance - release firmware\n");
919 /* reset <-> F/W release */
920 s5p_mfc_reset(dev);
921 s5p_mfc_deinit_hw(dev);
922 s5p_mfc_release_firmware(dev);
923 del_timer_sync(&dev->watchdog_timer);
924 if (s5p_mfc_power_off() < 0)
925 mfc_err("Power off failed\n");
926 }
927 mfc_debug(2, "Shutting down clock\n");
928 s5p_mfc_clock_off();
929 dev->ctx[ctx->num] = NULL;
930 s5p_mfc_dec_ctrls_delete(ctx);
931 v4l2_fh_del(&ctx->fh);
932 v4l2_fh_exit(&ctx->fh);
933 kfree(ctx);
934 mfc_debug_leave();
935 mutex_unlock(&dev->mfc_mutex);
936 return 0;
937 }
938
939 /* Poll */
940 static unsigned int s5p_mfc_poll(struct file *file,
941 struct poll_table_struct *wait)
942 {
943 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
944 struct s5p_mfc_dev *dev = ctx->dev;
945 struct vb2_queue *src_q, *dst_q;
946 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
947 unsigned int rc = 0;
948 unsigned long flags;
949
950 mutex_lock(&dev->mfc_mutex);
951 src_q = &ctx->vq_src;
952 dst_q = &ctx->vq_dst;
953 /*
954 * There has to be at least one buffer queued on each queued_list, which
955 * means either in driver already or waiting for driver to claim it
956 * and start processing.
957 */
958 if ((!src_q->streaming || list_empty(&src_q->queued_list))
959 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
960 rc = POLLERR;
961 goto end;
962 }
963 mutex_unlock(&dev->mfc_mutex);
964 poll_wait(file, &ctx->fh.wait, wait);
965 poll_wait(file, &src_q->done_wq, wait);
966 poll_wait(file, &dst_q->done_wq, wait);
967 mutex_lock(&dev->mfc_mutex);
968 if (v4l2_event_pending(&ctx->fh))
969 rc |= POLLPRI;
970 spin_lock_irqsave(&src_q->done_lock, flags);
971 if (!list_empty(&src_q->done_list))
972 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
973 done_entry);
974 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
975 || src_vb->state == VB2_BUF_STATE_ERROR))
976 rc |= POLLOUT | POLLWRNORM;
977 spin_unlock_irqrestore(&src_q->done_lock, flags);
978 spin_lock_irqsave(&dst_q->done_lock, flags);
979 if (!list_empty(&dst_q->done_list))
980 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
981 done_entry);
982 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
983 || dst_vb->state == VB2_BUF_STATE_ERROR))
984 rc |= POLLIN | POLLRDNORM;
985 spin_unlock_irqrestore(&dst_q->done_lock, flags);
986 end:
987 mutex_unlock(&dev->mfc_mutex);
988 return rc;
989 }
990
991 /* Mmap */
992 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
993 {
994 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
995 struct s5p_mfc_dev *dev = ctx->dev;
996 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
997 int ret;
998
999 if (mutex_lock_interruptible(&dev->mfc_mutex))
1000 return -ERESTARTSYS;
1001 if (offset < DST_QUEUE_OFF_BASE) {
1002 mfc_debug(2, "mmaping source\n");
1003 ret = vb2_mmap(&ctx->vq_src, vma);
1004 } else { /* capture */
1005 mfc_debug(2, "mmaping destination\n");
1006 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1007 ret = vb2_mmap(&ctx->vq_dst, vma);
1008 }
1009 mutex_unlock(&dev->mfc_mutex);
1010 return ret;
1011 }
1012
1013 /* v4l2 ops */
1014 static const struct v4l2_file_operations s5p_mfc_fops = {
1015 .owner = THIS_MODULE,
1016 .open = s5p_mfc_open,
1017 .release = s5p_mfc_release,
1018 .poll = s5p_mfc_poll,
1019 .unlocked_ioctl = video_ioctl2,
1020 .mmap = s5p_mfc_mmap,
1021 };
1022
1023 static int match_child(struct device *dev, void *data)
1024 {
1025 if (!dev_name(dev))
1026 return 0;
1027 return !strcmp(dev_name(dev), (char *)data);
1028 }
1029
1030 /* MFC probe function */
1031 static int s5p_mfc_probe(struct platform_device *pdev)
1032 {
1033 struct s5p_mfc_dev *dev;
1034 struct video_device *vfd;
1035 struct resource *res;
1036 int ret;
1037
1038 pr_debug("%s++\n", __func__);
1039 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1040 if (!dev) {
1041 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
1042 return -ENOMEM;
1043 }
1044
1045 spin_lock_init(&dev->irqlock);
1046 spin_lock_init(&dev->condlock);
1047 dev->plat_dev = pdev;
1048 if (!dev->plat_dev) {
1049 dev_err(&pdev->dev, "No platform data specified\n");
1050 return -ENODEV;
1051 }
1052
1053 dev->variant = (struct s5p_mfc_variant *)
1054 platform_get_device_id(pdev)->driver_data;
1055
1056 ret = s5p_mfc_init_pm(dev);
1057 if (ret < 0) {
1058 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1059 return ret;
1060 }
1061
1062 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1063
1064 dev->regs_base = devm_request_and_ioremap(&pdev->dev, res);
1065 if (dev->regs_base == NULL) {
1066 dev_err(&pdev->dev, "Failed to obtain io memory\n");
1067 return -ENOENT;
1068 }
1069
1070 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1071 if (res == NULL) {
1072 dev_err(&pdev->dev, "failed to get irq resource\n");
1073 ret = -ENOENT;
1074 goto err_res;
1075 }
1076 dev->irq = res->start;
1077 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1078 IRQF_DISABLED, pdev->name, dev);
1079 if (ret) {
1080 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1081 goto err_res;
1082 }
1083
1084 dev->mem_dev_l = device_find_child(&dev->plat_dev->dev, "s5p-mfc-l",
1085 match_child);
1086 if (!dev->mem_dev_l) {
1087 mfc_err("Mem child (L) device get failed\n");
1088 ret = -ENODEV;
1089 goto err_res;
1090 }
1091
1092 dev->mem_dev_r = device_find_child(&dev->plat_dev->dev, "s5p-mfc-r",
1093 match_child);
1094 if (!dev->mem_dev_r) {
1095 mfc_err("Mem child (R) device get failed\n");
1096 ret = -ENODEV;
1097 goto err_res;
1098 }
1099
1100 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
1101 if (IS_ERR_OR_NULL(dev->alloc_ctx[0])) {
1102 ret = PTR_ERR(dev->alloc_ctx[0]);
1103 goto err_res;
1104 }
1105 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
1106 if (IS_ERR_OR_NULL(dev->alloc_ctx[1])) {
1107 ret = PTR_ERR(dev->alloc_ctx[1]);
1108 goto err_mem_init_ctx_1;
1109 }
1110
1111 mutex_init(&dev->mfc_mutex);
1112
1113 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1114 if (ret)
1115 goto err_v4l2_dev_reg;
1116 init_waitqueue_head(&dev->queue);
1117
1118 /* decoder */
1119 vfd = video_device_alloc();
1120 if (!vfd) {
1121 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1122 ret = -ENOMEM;
1123 goto err_dec_alloc;
1124 }
1125 vfd->fops = &s5p_mfc_fops,
1126 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1127 vfd->release = video_device_release,
1128 vfd->lock = &dev->mfc_mutex;
1129 vfd->v4l2_dev = &dev->v4l2_dev;
1130 vfd->vfl_dir = VFL_DIR_M2M;
1131 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1132 dev->vfd_dec = vfd;
1133 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1134 if (ret) {
1135 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1136 video_device_release(vfd);
1137 goto err_dec_reg;
1138 }
1139 v4l2_info(&dev->v4l2_dev,
1140 "decoder registered as /dev/video%d\n", vfd->num);
1141 video_set_drvdata(vfd, dev);
1142
1143 /* encoder */
1144 vfd = video_device_alloc();
1145 if (!vfd) {
1146 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1147 ret = -ENOMEM;
1148 goto err_enc_alloc;
1149 }
1150 vfd->fops = &s5p_mfc_fops,
1151 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1152 vfd->release = video_device_release,
1153 vfd->lock = &dev->mfc_mutex;
1154 vfd->v4l2_dev = &dev->v4l2_dev;
1155 vfd->vfl_dir = VFL_DIR_M2M;
1156 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1157 dev->vfd_enc = vfd;
1158 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1159 if (ret) {
1160 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1161 video_device_release(vfd);
1162 goto err_enc_reg;
1163 }
1164 v4l2_info(&dev->v4l2_dev,
1165 "encoder registered as /dev/video%d\n", vfd->num);
1166 video_set_drvdata(vfd, dev);
1167 platform_set_drvdata(pdev, dev);
1168
1169 dev->hw_lock = 0;
1170 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1171 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1172 atomic_set(&dev->watchdog_cnt, 0);
1173 init_timer(&dev->watchdog_timer);
1174 dev->watchdog_timer.data = (unsigned long)dev;
1175 dev->watchdog_timer.function = s5p_mfc_watchdog;
1176
1177 /* Initialize HW ops and commands based on MFC version */
1178 s5p_mfc_init_hw_ops(dev);
1179 s5p_mfc_init_hw_cmds(dev);
1180
1181 pr_debug("%s--\n", __func__);
1182 return 0;
1183
1184 /* Deinit MFC if probe had failed */
1185 err_enc_reg:
1186 video_device_release(dev->vfd_enc);
1187 err_enc_alloc:
1188 video_unregister_device(dev->vfd_dec);
1189 err_dec_reg:
1190 video_device_release(dev->vfd_dec);
1191 err_dec_alloc:
1192 v4l2_device_unregister(&dev->v4l2_dev);
1193 err_v4l2_dev_reg:
1194 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1195 err_mem_init_ctx_1:
1196 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1197 err_res:
1198 s5p_mfc_final_pm(dev);
1199
1200 pr_debug("%s-- with error\n", __func__);
1201 return ret;
1202
1203 }
1204
1205 /* Remove the driver */
1206 static int __devexit s5p_mfc_remove(struct platform_device *pdev)
1207 {
1208 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1209
1210 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1211
1212 del_timer_sync(&dev->watchdog_timer);
1213 flush_workqueue(dev->watchdog_workqueue);
1214 destroy_workqueue(dev->watchdog_workqueue);
1215
1216 video_unregister_device(dev->vfd_enc);
1217 video_unregister_device(dev->vfd_dec);
1218 v4l2_device_unregister(&dev->v4l2_dev);
1219 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1220 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1221
1222 s5p_mfc_final_pm(dev);
1223 return 0;
1224 }
1225
1226 #ifdef CONFIG_PM_SLEEP
1227
1228 static int s5p_mfc_suspend(struct device *dev)
1229 {
1230 struct platform_device *pdev = to_platform_device(dev);
1231 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1232 int ret;
1233
1234 if (m_dev->num_inst == 0)
1235 return 0;
1236
1237 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1238 mfc_err("Error: going to suspend for a second time\n");
1239 return -EIO;
1240 }
1241
1242 /* Check if we're processing then wait if it necessary. */
1243 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1244 /* Try and lock the HW */
1245 /* Wait on the interrupt waitqueue */
1246 ret = wait_event_interruptible_timeout(m_dev->queue,
1247 m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond,
1248 msecs_to_jiffies(MFC_INT_TIMEOUT));
1249
1250 if (ret == 0) {
1251 mfc_err("Waiting for hardware to finish timed out\n");
1252 return -EIO;
1253 }
1254 }
1255
1256 return s5p_mfc_sleep(m_dev);
1257 }
1258
1259 static int s5p_mfc_resume(struct device *dev)
1260 {
1261 struct platform_device *pdev = to_platform_device(dev);
1262 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1263
1264 if (m_dev->num_inst == 0)
1265 return 0;
1266 return s5p_mfc_wakeup(m_dev);
1267 }
1268 #endif
1269
1270 #ifdef CONFIG_PM_RUNTIME
1271 static int s5p_mfc_runtime_suspend(struct device *dev)
1272 {
1273 struct platform_device *pdev = to_platform_device(dev);
1274 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1275
1276 atomic_set(&m_dev->pm.power, 0);
1277 return 0;
1278 }
1279
1280 static int s5p_mfc_runtime_resume(struct device *dev)
1281 {
1282 struct platform_device *pdev = to_platform_device(dev);
1283 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1284 int pre_power;
1285
1286 if (!m_dev->alloc_ctx)
1287 return 0;
1288 pre_power = atomic_read(&m_dev->pm.power);
1289 atomic_set(&m_dev->pm.power, 1);
1290 return 0;
1291 }
1292 #endif
1293
1294 /* Power management */
1295 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1296 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1297 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1298 NULL)
1299 };
1300
1301 struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1302 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1303 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1304 .dsc = DESC_BUF_SIZE,
1305 .shm = SHARED_BUF_SIZE,
1306 };
1307
1308 struct s5p_mfc_buf_size buf_size_v5 = {
1309 .fw = MAX_FW_SIZE,
1310 .cpb = MAX_CPB_SIZE,
1311 .priv = &mfc_buf_size_v5,
1312 };
1313
1314 struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1315 .base = MFC_BASE_ALIGN_ORDER,
1316 };
1317
1318 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1319 .version = MFC_VERSION,
1320 .port_num = MFC_NUM_PORTS,
1321 .buf_size = &buf_size_v5,
1322 .buf_align = &mfc_buf_align_v5,
1323 .mclk_name = "sclk_mfc",
1324 .fw_name = "s5p-mfc.fw",
1325 };
1326
1327 struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1328 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1329 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1330 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1331 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1332 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1333 };
1334
1335 struct s5p_mfc_buf_size buf_size_v6 = {
1336 .fw = MAX_FW_SIZE_V6,
1337 .cpb = MAX_CPB_SIZE_V6,
1338 .priv = &mfc_buf_size_v6,
1339 };
1340
1341 struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1342 .base = 0,
1343 };
1344
1345 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1346 .version = MFC_VERSION_V6,
1347 .port_num = MFC_NUM_PORTS_V6,
1348 .buf_size = &buf_size_v6,
1349 .buf_align = &mfc_buf_align_v6,
1350 .mclk_name = "aclk_333",
1351 .fw_name = "s5p-mfc-v6.fw",
1352 };
1353
1354 static struct platform_device_id mfc_driver_ids[] = {
1355 {
1356 .name = "s5p-mfc",
1357 .driver_data = (unsigned long)&mfc_drvdata_v5,
1358 }, {
1359 .name = "s5p-mfc-v5",
1360 .driver_data = (unsigned long)&mfc_drvdata_v5,
1361 }, {
1362 .name = "s5p-mfc-v6",
1363 .driver_data = (unsigned long)&mfc_drvdata_v6,
1364 },
1365 {},
1366 };
1367 MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1368
1369 static struct platform_driver s5p_mfc_driver = {
1370 .probe = s5p_mfc_probe,
1371 .remove = __devexit_p(s5p_mfc_remove),
1372 .id_table = mfc_driver_ids,
1373 .driver = {
1374 .name = S5P_MFC_NAME,
1375 .owner = THIS_MODULE,
1376 .pm = &s5p_mfc_pm_ops
1377 },
1378 };
1379
1380 module_platform_driver(s5p_mfc_driver);
1381
1382 MODULE_LICENSE("GPL");
1383 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1384 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1385
kernel source for telekom puls (alcatel/mediatek)